1 /*
2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
3 * driver for Linux.
4 *
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #ifndef __T4VF_DEFS_H__
37 #define __T4VF_DEFS_H__
38
39 #include "../cxgb4/t4_regs.h"
40
41 /*
42 * The VF Register Map.
43 *
44 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
45 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
46 * the Slice to Module Map Table (see below) in the Physical Function Register
47 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
48 * and Offset registers in the PF Register Map. The MBDATA base address is
49 * quite constrained as it determines the Mailbox Data addresses for both PFs
50 * and VFs, and therefore must fit in both the VF and PF Register Maps without
51 * overlapping other registers.
52 */
53 #define T4VF_SGE_BASE_ADDR 0x0000
54 #define T4VF_MPS_BASE_ADDR 0x0100
55 #define T4VF_PL_BASE_ADDR 0x0200
56 #define T4VF_MBDATA_BASE_ADDR 0x0240
57 #define T6VF_MBDATA_BASE_ADDR 0x0280
58 #define T4VF_CIM_BASE_ADDR 0x0300
59
60 #define T4VF_REGMAP_START 0x0000
61 #define T4VF_REGMAP_SIZE 0x0400
62
63 /*
64 * There's no hardware limitation which requires that the addresses of the
65 * Mailbox Data in the fixed CIM PF map and the programmable VF map must
66 * match. However, it's a useful convention ...
67 */
68 #if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA_A
69 #error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA_A!
70 #endif
71
72 /*
73 * Virtual Function "Slice to Module Map Table" definitions.
74 *
75 * This table allows us to map subsets of the various module register sets
76 * into the T4VF Register Map. Each table entry identifies the index of the
77 * module whose registers are being mapped, the offset within the module's
78 * register set that the mapping should start at, the limit of the mapping,
79 * and the offset within the T4VF Register Map to which the module's registers
80 * are being mapped. All addresses and qualtities are in terms of 32-bit
81 * words. The "limit" value is also in terms of 32-bit words and is equal to
82 * the last address mapped in the T4VF Register Map 1 (i.e. it's a "<="
83 * relation rather than a "<").
84 */
85 #define T4VF_MOD_MAP(module, index, first, last) \
86 T4VF_MOD_MAP_##module##_INDEX = (index), \
87 T4VF_MOD_MAP_##module##_FIRST = (first), \
88 T4VF_MOD_MAP_##module##_LAST = (last), \
89 T4VF_MOD_MAP_##module##_OFFSET = ((first)/4), \
90 T4VF_MOD_MAP_##module##_BASE = \
91 (T4VF_##module##_BASE_ADDR/4 + (first)/4), \
92 T4VF_MOD_MAP_##module##_LIMIT = \
93 (T4VF_##module##_BASE_ADDR/4 + (last)/4),
94
95 #define SGE_VF_KDOORBELL 0x0
96 #define SGE_VF_GTS 0x4
97 #define MPS_VF_CTL 0x0
98 #define MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
99 #define PL_VF_WHOAMI 0x0
100 #define CIM_VF_EXT_MAILBOX_CTRL 0x0
101 #define CIM_VF_EXT_MAILBOX_STATUS 0x4
102
103 enum {
104 T4VF_MOD_MAP(SGE, 2, SGE_VF_KDOORBELL, SGE_VF_GTS)
105 T4VF_MOD_MAP(MPS, 0, MPS_VF_CTL, MPS_VF_STAT_RX_VF_ERR_FRAMES_H)
106 T4VF_MOD_MAP(PL, 3, PL_VF_WHOAMI, PL_VF_WHOAMI)
107 T4VF_MOD_MAP(CIM, 1, CIM_VF_EXT_MAILBOX_CTRL, CIM_VF_EXT_MAILBOX_STATUS)
108 };
109
110 /*
111 * There isn't a Slice to Module Map Table entry for the Mailbox Data
112 * registers, but it's convenient to use similar names as above. There are 8
113 * little-endian 64-bit Mailbox Data registers. Note that the "instances"
114 * value below is in terms of 32-bit words which matches the "word" addressing
115 * space we use above for the Slice to Module Map Space.
116 */
117 #define NUM_CIM_VF_MAILBOX_DATA_INSTANCES 16
118
119 #define T4VF_MBDATA_FIRST 0
120 #define T4VF_MBDATA_LAST ((NUM_CIM_VF_MAILBOX_DATA_INSTANCES-1)*4)
121
122 #endif /* __T4T4VF_DEFS_H__ */