drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
mbox_cmd_log_entry
is_offload
is_hashfilter
is_pci_uld
is_uld
t4_read_reg
t4_write_reg
readq
writeq
t4_read_reg64
t4_write_reg64
t4_set_hw_addr
netdev2pinfo
adap2pinfo
netdev2adap
mk_adap_vers
qtimer_val
is_bypass
is_bypass_device
is_10gbt_device
core_ticks_per_usec
us_to_core_ticks
core_ticks_to_us
dack_ticks_to_usec
t4_wr_mbox_timeout
t4_wr_mbox
t4_wr_mbox_ns
hash_mac_addr
init_rspq
t4_is_inserted_mod_type
t4_link_l1cfg
t4_link_l1cfg_ns
t4_memory_write
   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34 
  35 #ifndef __CXGB4_H__
  36 #define __CXGB4_H__
  37 
  38 #include "t4_hw.h"
  39 
  40 #include <linux/bitops.h>
  41 #include <linux/cache.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/list.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/pci.h>
  46 #include <linux/spinlock.h>
  47 #include <linux/timer.h>
  48 #include <linux/vmalloc.h>
  49 #include <linux/rhashtable.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/net_tstamp.h>
  52 #include <linux/ptp_clock_kernel.h>
  53 #include <linux/ptp_classify.h>
  54 #include <linux/crash_dump.h>
  55 #include <linux/thermal.h>
  56 #include <asm/io.h>
  57 #include "t4_chip_type.h"
  58 #include "cxgb4_uld.h"
  59 
  60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
  61 extern struct list_head adapter_list;
  62 extern struct mutex uld_mutex;
  63 
  64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
  65  * This is the same as calc_tx_descs() for a TSO packet with
  66  * nr_frags == MAX_SKB_FRAGS.
  67  */
  68 #define ETHTXQ_STOP_THRES \
  69         (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
  70 
  71 enum {
  72         MAX_NPORTS      = 4,     /* max # of ports */
  73         SERNUM_LEN      = 24,    /* Serial # length */
  74         EC_LEN          = 16,    /* E/C length */
  75         ID_LEN          = 16,    /* ID length */
  76         PN_LEN          = 16,    /* Part Number length */
  77         MACADDR_LEN     = 12,    /* MAC Address length */
  78 };
  79 
  80 enum {
  81         T4_REGMAP_SIZE = (160 * 1024),
  82         T5_REGMAP_SIZE = (332 * 1024),
  83 };
  84 
  85 enum {
  86         MEM_EDC0,
  87         MEM_EDC1,
  88         MEM_MC,
  89         MEM_MC0 = MEM_MC,
  90         MEM_MC1,
  91         MEM_HMA,
  92 };
  93 
  94 enum {
  95         MEMWIN0_APERTURE = 2048,
  96         MEMWIN0_BASE     = 0x1b800,
  97         MEMWIN1_APERTURE = 32768,
  98         MEMWIN1_BASE     = 0x28000,
  99         MEMWIN1_BASE_T5  = 0x52000,
 100         MEMWIN2_APERTURE = 65536,
 101         MEMWIN2_BASE     = 0x30000,
 102         MEMWIN2_APERTURE_T5 = 131072,
 103         MEMWIN2_BASE_T5  = 0x60000,
 104 };
 105 
 106 enum dev_master {
 107         MASTER_CANT,
 108         MASTER_MAY,
 109         MASTER_MUST
 110 };
 111 
 112 enum dev_state {
 113         DEV_STATE_UNINIT,
 114         DEV_STATE_INIT,
 115         DEV_STATE_ERR
 116 };
 117 
 118 enum cc_pause {
 119         PAUSE_RX      = 1 << 0,
 120         PAUSE_TX      = 1 << 1,
 121         PAUSE_AUTONEG = 1 << 2
 122 };
 123 
 124 enum cc_fec {
 125         FEC_AUTO      = 1 << 0,  /* IEEE 802.3 "automatic" */
 126         FEC_RS        = 1 << 1,  /* Reed-Solomon */
 127         FEC_BASER_RS  = 1 << 2   /* BaseR/Reed-Solomon */
 128 };
 129 
 130 struct port_stats {
 131         u64 tx_octets;            /* total # of octets in good frames */
 132         u64 tx_frames;            /* all good frames */
 133         u64 tx_bcast_frames;      /* all broadcast frames */
 134         u64 tx_mcast_frames;      /* all multicast frames */
 135         u64 tx_ucast_frames;      /* all unicast frames */
 136         u64 tx_error_frames;      /* all error frames */
 137 
 138         u64 tx_frames_64;         /* # of Tx frames in a particular range */
 139         u64 tx_frames_65_127;
 140         u64 tx_frames_128_255;
 141         u64 tx_frames_256_511;
 142         u64 tx_frames_512_1023;
 143         u64 tx_frames_1024_1518;
 144         u64 tx_frames_1519_max;
 145 
 146         u64 tx_drop;              /* # of dropped Tx frames */
 147         u64 tx_pause;             /* # of transmitted pause frames */
 148         u64 tx_ppp0;              /* # of transmitted PPP prio 0 frames */
 149         u64 tx_ppp1;              /* # of transmitted PPP prio 1 frames */
 150         u64 tx_ppp2;              /* # of transmitted PPP prio 2 frames */
 151         u64 tx_ppp3;              /* # of transmitted PPP prio 3 frames */
 152         u64 tx_ppp4;              /* # of transmitted PPP prio 4 frames */
 153         u64 tx_ppp5;              /* # of transmitted PPP prio 5 frames */
 154         u64 tx_ppp6;              /* # of transmitted PPP prio 6 frames */
 155         u64 tx_ppp7;              /* # of transmitted PPP prio 7 frames */
 156 
 157         u64 rx_octets;            /* total # of octets in good frames */
 158         u64 rx_frames;            /* all good frames */
 159         u64 rx_bcast_frames;      /* all broadcast frames */
 160         u64 rx_mcast_frames;      /* all multicast frames */
 161         u64 rx_ucast_frames;      /* all unicast frames */
 162         u64 rx_too_long;          /* # of frames exceeding MTU */
 163         u64 rx_jabber;            /* # of jabber frames */
 164         u64 rx_fcs_err;           /* # of received frames with bad FCS */
 165         u64 rx_len_err;           /* # of received frames with length error */
 166         u64 rx_symbol_err;        /* symbol errors */
 167         u64 rx_runt;              /* # of short frames */
 168 
 169         u64 rx_frames_64;         /* # of Rx frames in a particular range */
 170         u64 rx_frames_65_127;
 171         u64 rx_frames_128_255;
 172         u64 rx_frames_256_511;
 173         u64 rx_frames_512_1023;
 174         u64 rx_frames_1024_1518;
 175         u64 rx_frames_1519_max;
 176 
 177         u64 rx_pause;             /* # of received pause frames */
 178         u64 rx_ppp0;              /* # of received PPP prio 0 frames */
 179         u64 rx_ppp1;              /* # of received PPP prio 1 frames */
 180         u64 rx_ppp2;              /* # of received PPP prio 2 frames */
 181         u64 rx_ppp3;              /* # of received PPP prio 3 frames */
 182         u64 rx_ppp4;              /* # of received PPP prio 4 frames */
 183         u64 rx_ppp5;              /* # of received PPP prio 5 frames */
 184         u64 rx_ppp6;              /* # of received PPP prio 6 frames */
 185         u64 rx_ppp7;              /* # of received PPP prio 7 frames */
 186 
 187         u64 rx_ovflow0;           /* drops due to buffer-group 0 overflows */
 188         u64 rx_ovflow1;           /* drops due to buffer-group 1 overflows */
 189         u64 rx_ovflow2;           /* drops due to buffer-group 2 overflows */
 190         u64 rx_ovflow3;           /* drops due to buffer-group 3 overflows */
 191         u64 rx_trunc0;            /* buffer-group 0 truncated packets */
 192         u64 rx_trunc1;            /* buffer-group 1 truncated packets */
 193         u64 rx_trunc2;            /* buffer-group 2 truncated packets */
 194         u64 rx_trunc3;            /* buffer-group 3 truncated packets */
 195 };
 196 
 197 struct lb_port_stats {
 198         u64 octets;
 199         u64 frames;
 200         u64 bcast_frames;
 201         u64 mcast_frames;
 202         u64 ucast_frames;
 203         u64 error_frames;
 204 
 205         u64 frames_64;
 206         u64 frames_65_127;
 207         u64 frames_128_255;
 208         u64 frames_256_511;
 209         u64 frames_512_1023;
 210         u64 frames_1024_1518;
 211         u64 frames_1519_max;
 212 
 213         u64 drop;
 214 
 215         u64 ovflow0;
 216         u64 ovflow1;
 217         u64 ovflow2;
 218         u64 ovflow3;
 219         u64 trunc0;
 220         u64 trunc1;
 221         u64 trunc2;
 222         u64 trunc3;
 223 };
 224 
 225 struct tp_tcp_stats {
 226         u32 tcp_out_rsts;
 227         u64 tcp_in_segs;
 228         u64 tcp_out_segs;
 229         u64 tcp_retrans_segs;
 230 };
 231 
 232 struct tp_usm_stats {
 233         u32 frames;
 234         u32 drops;
 235         u64 octets;
 236 };
 237 
 238 struct tp_fcoe_stats {
 239         u32 frames_ddp;
 240         u32 frames_drop;
 241         u64 octets_ddp;
 242 };
 243 
 244 struct tp_err_stats {
 245         u32 mac_in_errs[4];
 246         u32 hdr_in_errs[4];
 247         u32 tcp_in_errs[4];
 248         u32 tnl_cong_drops[4];
 249         u32 ofld_chan_drops[4];
 250         u32 tnl_tx_drops[4];
 251         u32 ofld_vlan_drops[4];
 252         u32 tcp6_in_errs[4];
 253         u32 ofld_no_neigh;
 254         u32 ofld_cong_defer;
 255 };
 256 
 257 struct tp_cpl_stats {
 258         u32 req[4];
 259         u32 rsp[4];
 260 };
 261 
 262 struct tp_rdma_stats {
 263         u32 rqe_dfr_pkt;
 264         u32 rqe_dfr_mod;
 265 };
 266 
 267 struct sge_params {
 268         u32 hps;                        /* host page size for our PF/VF */
 269         u32 eq_qpp;                     /* egress queues/page for our PF/VF */
 270         u32 iq_qpp;                     /* egress queues/page for our PF/VF */
 271 };
 272 
 273 struct tp_params {
 274         unsigned int tre;            /* log2 of core clocks per TP tick */
 275         unsigned int la_mask;        /* what events are recorded by TP LA */
 276         unsigned short tx_modq_map;  /* TX modulation scheduler queue to */
 277                                      /* channel map */
 278 
 279         uint32_t dack_re;            /* DACK timer resolution */
 280         unsigned short tx_modq[NCHAN];  /* channel to modulation queue map */
 281 
 282         u32 vlan_pri_map;               /* cached TP_VLAN_PRI_MAP */
 283         u32 filter_mask;
 284         u32 ingress_config;             /* cached TP_INGRESS_CONFIG */
 285 
 286         /* cached TP_OUT_CONFIG compressed error vector
 287          * and passing outer header info for encapsulated packets.
 288          */
 289         int rx_pkt_encap;
 290 
 291         /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets.  This is a
 292          * subset of the set of fields which may be present in the Compressed
 293          * Filter Tuple portion of filters and TCP TCB connections.  The
 294          * fields which are present are controlled by the TP_VLAN_PRI_MAP.
 295          * Since a variable number of fields may or may not be present, their
 296          * shifted field positions within the Compressed Filter Tuple may
 297          * vary, or not even be present if the field isn't selected in
 298          * TP_VLAN_PRI_MAP.  Since some of these fields are needed in various
 299          * places we store their offsets here, or a -1 if the field isn't
 300          * present.
 301          */
 302         int fcoe_shift;
 303         int port_shift;
 304         int vnic_shift;
 305         int vlan_shift;
 306         int tos_shift;
 307         int protocol_shift;
 308         int ethertype_shift;
 309         int macmatch_shift;
 310         int matchtype_shift;
 311         int frag_shift;
 312 
 313         u64 hash_filter_mask;
 314 };
 315 
 316 struct vpd_params {
 317         unsigned int cclk;
 318         u8 ec[EC_LEN + 1];
 319         u8 sn[SERNUM_LEN + 1];
 320         u8 id[ID_LEN + 1];
 321         u8 pn[PN_LEN + 1];
 322         u8 na[MACADDR_LEN + 1];
 323 };
 324 
 325 /* Maximum resources provisioned for a PCI PF.
 326  */
 327 struct pf_resources {
 328         unsigned int nvi;               /* N virtual interfaces */
 329         unsigned int neq;               /* N egress Qs */
 330         unsigned int nethctrl;          /* N egress ETH or CTRL Qs */
 331         unsigned int niqflint;          /* N ingress Qs/w free list(s) & intr */
 332         unsigned int niq;               /* N ingress Qs */
 333         unsigned int tc;                /* PCI-E traffic class */
 334         unsigned int pmask;             /* port access rights mask */
 335         unsigned int nexactf;           /* N exact MPS filters */
 336         unsigned int r_caps;            /* read capabilities */
 337         unsigned int wx_caps;           /* write/execute capabilities */
 338 };
 339 
 340 struct pci_params {
 341         unsigned int vpd_cap_addr;
 342         unsigned char speed;
 343         unsigned char width;
 344 };
 345 
 346 struct devlog_params {
 347         u32 memtype;                    /* which memory (EDC0, EDC1, MC) */
 348         u32 start;                      /* start of log in firmware memory */
 349         u32 size;                       /* size of log */
 350 };
 351 
 352 /* Stores chip specific parameters */
 353 struct arch_specific_params {
 354         u8 nchan;
 355         u8 pm_stats_cnt;
 356         u8 cng_ch_bits_log;             /* congestion channel map bits width */
 357         u16 mps_rplc_size;
 358         u16 vfcount;
 359         u32 sge_fl_db;
 360         u16 mps_tcam_size;
 361 };
 362 
 363 struct adapter_params {
 364         struct sge_params sge;
 365         struct tp_params  tp;
 366         struct vpd_params vpd;
 367         struct pf_resources pfres;
 368         struct pci_params pci;
 369         struct devlog_params devlog;
 370         enum pcie_memwin drv_memwin;
 371 
 372         unsigned int cim_la_size;
 373 
 374         unsigned int sf_size;             /* serial flash size in bytes */
 375         unsigned int sf_nsec;             /* # of flash sectors */
 376 
 377         unsigned int fw_vers;             /* firmware version */
 378         unsigned int bs_vers;             /* bootstrap version */
 379         unsigned int tp_vers;             /* TP microcode version */
 380         unsigned int er_vers;             /* expansion ROM version */
 381         unsigned int scfg_vers;           /* Serial Configuration version */
 382         unsigned int vpd_vers;            /* VPD Version */
 383         u8 api_vers[7];
 384 
 385         unsigned short mtus[NMTUS];
 386         unsigned short a_wnd[NCCTRL_WIN];
 387         unsigned short b_wnd[NCCTRL_WIN];
 388 
 389         unsigned char nports;             /* # of ethernet ports */
 390         unsigned char portvec;
 391         enum chip_type chip;               /* chip code */
 392         struct arch_specific_params arch;  /* chip specific params */
 393         unsigned char offload;
 394         unsigned char crypto;           /* HW capability for crypto */
 395 
 396         unsigned char bypass;
 397         unsigned char hash_filter;
 398 
 399         unsigned int ofldq_wr_cred;
 400         bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
 401 
 402         unsigned int nsched_cls;          /* number of traffic classes */
 403         unsigned int max_ordird_qp;       /* Max read depth per RDMA QP */
 404         unsigned int max_ird_adapter;     /* Max read depth per adapter */
 405         bool fr_nsmr_tpte_wr_support;     /* FW support for FR_NSMR_TPTE_WR */
 406         u8 fw_caps_support;             /* 32-bit Port Capabilities */
 407         bool filter2_wr_support;        /* FW support for FILTER2_WR */
 408         unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
 409 
 410         /* MPS Buffer Group Map[per Port].  Bit i is set if buffer group i is
 411          * used by the Port
 412          */
 413         u8 mps_bg_map[MAX_NPORTS];      /* MPS Buffer Group Map */
 414         bool write_w_imm_support;       /* FW supports WRITE_WITH_IMMEDIATE */
 415         bool write_cmpl_support;        /* FW supports WRITE_CMPL */
 416 };
 417 
 418 /* State needed to monitor the forward progress of SGE Ingress DMA activities
 419  * and possible hangs.
 420  */
 421 struct sge_idma_monitor_state {
 422         unsigned int idma_1s_thresh;    /* 1s threshold in Core Clock ticks */
 423         unsigned int idma_stalled[2];   /* synthesized stalled timers in HZ */
 424         unsigned int idma_state[2];     /* IDMA Hang detect state */
 425         unsigned int idma_qid[2];       /* IDMA Hung Ingress Queue ID */
 426         unsigned int idma_warn[2];      /* time to warning in HZ */
 427 };
 428 
 429 /* Firmware Mailbox Command/Reply log.  All values are in Host-Endian format.
 430  * The access and execute times are signed in order to accommodate negative
 431  * error returns.
 432  */
 433 struct mbox_cmd {
 434         u64 cmd[MBOX_LEN / 8];          /* a Firmware Mailbox Command/Reply */
 435         u64 timestamp;                  /* OS-dependent timestamp */
 436         u32 seqno;                      /* sequence number */
 437         s16 access;                     /* time (ms) to access mailbox */
 438         s16 execute;                    /* time (ms) to execute */
 439 };
 440 
 441 struct mbox_cmd_log {
 442         unsigned int size;              /* number of entries in the log */
 443         unsigned int cursor;            /* next position in the log to write */
 444         u32 seqno;                      /* next sequence number */
 445         /* variable length mailbox command log starts here */
 446 };
 447 
 448 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
 449  * return a pointer to the specified entry.
 450  */
 451 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
 452                                                   unsigned int entry_idx)
 453 {
 454         return &((struct mbox_cmd *)&(log)[1])[entry_idx];
 455 }
 456 
 457 #include "t4fw_api.h"
 458 
 459 #define FW_VERSION(chip) ( \
 460                 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
 461                 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
 462                 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
 463                 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
 464 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
 465 
 466 struct fw_info {
 467         u8 chip;
 468         char *fs_name;
 469         char *fw_mod_name;
 470         struct fw_hdr fw_hdr;
 471 };
 472 
 473 struct trace_params {
 474         u32 data[TRACE_LEN / 4];
 475         u32 mask[TRACE_LEN / 4];
 476         unsigned short snap_len;
 477         unsigned short min_len;
 478         unsigned char skip_ofst;
 479         unsigned char skip_len;
 480         unsigned char invert;
 481         unsigned char port;
 482 };
 483 
 484 /* Firmware Port Capabilities types. */
 485 
 486 typedef u16 fw_port_cap16_t;    /* 16-bit Port Capabilities integral value */
 487 typedef u32 fw_port_cap32_t;    /* 32-bit Port Capabilities integral value */
 488 
 489 enum fw_caps {
 490         FW_CAPS_UNKNOWN = 0,    /* 0'ed out initial state */
 491         FW_CAPS16       = 1,    /* old Firmware: 16-bit Port Capabilities */
 492         FW_CAPS32       = 2,    /* new Firmware: 32-bit Port Capabilities */
 493 };
 494 
 495 struct link_config {
 496         fw_port_cap32_t pcaps;           /* link capabilities */
 497         fw_port_cap32_t def_acaps;       /* default advertised capabilities */
 498         fw_port_cap32_t acaps;           /* advertised capabilities */
 499         fw_port_cap32_t lpacaps;         /* peer advertised capabilities */
 500 
 501         fw_port_cap32_t speed_caps;      /* speed(s) user has requested */
 502         unsigned int   speed;            /* actual link speed (Mb/s) */
 503 
 504         enum cc_pause  requested_fc;     /* flow control user has requested */
 505         enum cc_pause  fc;               /* actual link flow control */
 506         enum cc_pause  advertised_fc;    /* actual advertised flow control */
 507 
 508         enum cc_fec    requested_fec;    /* Forward Error Correction: */
 509         enum cc_fec    fec;              /* requested and actual in use */
 510 
 511         unsigned char  autoneg;          /* autonegotiating? */
 512 
 513         unsigned char  link_ok;          /* link up? */
 514         unsigned char  link_down_rc;     /* link down reason */
 515 
 516         bool new_module;                 /* ->OS Transceiver Module inserted */
 517         bool redo_l1cfg;                 /* ->CC redo current "sticky" L1 CFG */
 518 };
 519 
 520 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 521 
 522 enum {
 523         MAX_ETH_QSETS = 32,           /* # of Ethernet Tx/Rx queue sets */
 524         MAX_OFLD_QSETS = 16,          /* # of offload Tx, iscsi Rx queue sets */
 525         MAX_CTRL_QUEUES = NCHAN,      /* # of control Tx queues */
 526 };
 527 
 528 enum {
 529         MAX_TXQ_ENTRIES      = 16384,
 530         MAX_CTRL_TXQ_ENTRIES = 1024,
 531         MAX_RSPQ_ENTRIES     = 16384,
 532         MAX_RX_BUFFERS       = 16384,
 533         MIN_TXQ_ENTRIES      = 32,
 534         MIN_CTRL_TXQ_ENTRIES = 32,
 535         MIN_RSPQ_ENTRIES     = 128,
 536         MIN_FL_ENTRIES       = 16
 537 };
 538 
 539 enum {
 540         MAX_TXQ_DESC_SIZE      = 64,
 541         MAX_RXQ_DESC_SIZE      = 128,
 542         MAX_FL_DESC_SIZE       = 8,
 543         MAX_CTRL_TXQ_DESC_SIZE = 64,
 544 };
 545 
 546 enum {
 547         INGQ_EXTRAS = 2,        /* firmware event queue and */
 548                                 /*   forwarded interrupts */
 549         MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
 550 };
 551 
 552 enum {
 553         PRIV_FLAG_PORT_TX_VM_BIT,
 554 };
 555 
 556 #define PRIV_FLAG_PORT_TX_VM            BIT(PRIV_FLAG_PORT_TX_VM_BIT)
 557 
 558 #define PRIV_FLAGS_ADAP                 0
 559 #define PRIV_FLAGS_PORT                 PRIV_FLAG_PORT_TX_VM
 560 
 561 struct adapter;
 562 struct sge_rspq;
 563 
 564 #include "cxgb4_dcb.h"
 565 
 566 #ifdef CONFIG_CHELSIO_T4_FCOE
 567 #include "cxgb4_fcoe.h"
 568 #endif /* CONFIG_CHELSIO_T4_FCOE */
 569 
 570 struct port_info {
 571         struct adapter *adapter;
 572         u16    viid;
 573         int    xact_addr_filt;        /* index of exact MAC address filter */
 574         u16    rss_size;              /* size of VI's RSS table slice */
 575         s8     mdio_addr;
 576         enum fw_port_type port_type;
 577         u8     mod_type;
 578         u8     port_id;
 579         u8     tx_chan;
 580         u8     lport;                 /* associated offload logical port */
 581         u8     nqsets;                /* # of qsets */
 582         u8     first_qset;            /* index of first qset */
 583         u8     rss_mode;
 584         struct link_config link_cfg;
 585         u16   *rss;
 586         struct port_stats stats_base;
 587 #ifdef CONFIG_CHELSIO_T4_DCB
 588         struct port_dcb_info dcb;     /* Data Center Bridging support */
 589 #endif
 590 #ifdef CONFIG_CHELSIO_T4_FCOE
 591         struct cxgb_fcoe fcoe;
 592 #endif /* CONFIG_CHELSIO_T4_FCOE */
 593         bool rxtstamp;  /* Enable TS */
 594         struct hwtstamp_config tstamp_config;
 595         bool ptp_enable;
 596         struct sched_table *sched_tbl;
 597         u32 eth_flags;
 598 
 599         /* viid and smt fields either returned by fw
 600          * or decoded by parsing viid by driver.
 601          */
 602         u8 vin;
 603         u8 vivld;
 604         u8 smt_idx;
 605         u8 rx_cchan;
 606 };
 607 
 608 struct dentry;
 609 struct work_struct;
 610 
 611 enum {                                 /* adapter flags */
 612         CXGB4_FULL_INIT_DONE            = (1 << 0),
 613         CXGB4_DEV_ENABLED               = (1 << 1),
 614         CXGB4_USING_MSI                 = (1 << 2),
 615         CXGB4_USING_MSIX                = (1 << 3),
 616         CXGB4_FW_OK                     = (1 << 4),
 617         CXGB4_RSS_TNLALLLOOKUP          = (1 << 5),
 618         CXGB4_USING_SOFT_PARAMS         = (1 << 6),
 619         CXGB4_MASTER_PF                 = (1 << 7),
 620         CXGB4_FW_OFLD_CONN              = (1 << 9),
 621         CXGB4_ROOT_NO_RELAXED_ORDERING  = (1 << 10),
 622         CXGB4_SHUTTING_DOWN             = (1 << 11),
 623         CXGB4_SGE_DBQ_TIMER             = (1 << 12),
 624 };
 625 
 626 enum {
 627         ULP_CRYPTO_LOOKASIDE = 1 << 0,
 628         ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
 629 };
 630 
 631 struct rx_sw_desc;
 632 
 633 struct sge_fl {                     /* SGE free-buffer queue state */
 634         unsigned int avail;         /* # of available Rx buffers */
 635         unsigned int pend_cred;     /* new buffers since last FL DB ring */
 636         unsigned int cidx;          /* consumer index */
 637         unsigned int pidx;          /* producer index */
 638         unsigned long alloc_failed; /* # of times buffer allocation failed */
 639         unsigned long large_alloc_failed;
 640         unsigned long mapping_err;  /* # of RX Buffer DMA Mapping failures */
 641         unsigned long low;          /* # of times momentarily starving */
 642         unsigned long starving;
 643         /* RO fields */
 644         unsigned int cntxt_id;      /* SGE context id for the free list */
 645         unsigned int size;          /* capacity of free list */
 646         struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
 647         __be64 *desc;               /* address of HW Rx descriptor ring */
 648         dma_addr_t addr;            /* bus address of HW ring start */
 649         void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
 650         unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
 651 };
 652 
 653 /* A packet gather list */
 654 struct pkt_gl {
 655         u64 sgetstamp;              /* SGE Time Stamp for Ingress Packet */
 656         struct page_frag frags[MAX_SKB_FRAGS];
 657         void *va;                         /* virtual address of first byte */
 658         unsigned int nfrags;              /* # of fragments */
 659         unsigned int tot_len;             /* total length of fragments */
 660 };
 661 
 662 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
 663                               const struct pkt_gl *gl);
 664 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
 665 /* LRO related declarations for ULD */
 666 struct t4_lro_mgr {
 667 #define MAX_LRO_SESSIONS                64
 668         u8 lro_session_cnt;         /* # of sessions to aggregate */
 669         unsigned long lro_pkts;     /* # of LRO super packets */
 670         unsigned long lro_merged;   /* # of wire packets merged by LRO */
 671         struct sk_buff_head lroq;   /* list of aggregated sessions */
 672 };
 673 
 674 struct sge_rspq {                   /* state for an SGE response queue */
 675         struct napi_struct napi;
 676         const __be64 *cur_desc;     /* current descriptor in queue */
 677         unsigned int cidx;          /* consumer index */
 678         u8 gen;                     /* current generation bit */
 679         u8 intr_params;             /* interrupt holdoff parameters */
 680         u8 next_intr_params;        /* holdoff params for next interrupt */
 681         u8 adaptive_rx;
 682         u8 pktcnt_idx;              /* interrupt packet threshold */
 683         u8 uld;                     /* ULD handling this queue */
 684         u8 idx;                     /* queue index within its group */
 685         int offset;                 /* offset into current Rx buffer */
 686         u16 cntxt_id;               /* SGE context id for the response q */
 687         u16 abs_id;                 /* absolute SGE id for the response q */
 688         __be64 *desc;               /* address of HW response ring */
 689         dma_addr_t phys_addr;       /* physical address of the ring */
 690         void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
 691         unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
 692         unsigned int iqe_len;       /* entry size */
 693         unsigned int size;          /* capacity of response queue */
 694         struct adapter *adap;
 695         struct net_device *netdev;  /* associated net device */
 696         rspq_handler_t handler;
 697         rspq_flush_handler_t flush_handler;
 698         struct t4_lro_mgr lro_mgr;
 699 };
 700 
 701 struct sge_eth_stats {              /* Ethernet queue statistics */
 702         unsigned long pkts;         /* # of ethernet packets */
 703         unsigned long lro_pkts;     /* # of LRO super packets */
 704         unsigned long lro_merged;   /* # of wire packets merged by LRO */
 705         unsigned long rx_cso;       /* # of Rx checksum offloads */
 706         unsigned long vlan_ex;      /* # of Rx VLAN extractions */
 707         unsigned long rx_drops;     /* # of packets dropped due to no mem */
 708         unsigned long bad_rx_pkts;  /* # of packets with err_vec!=0 */
 709 };
 710 
 711 struct sge_eth_rxq {                /* SW Ethernet Rx queue */
 712         struct sge_rspq rspq;
 713         struct sge_fl fl;
 714         struct sge_eth_stats stats;
 715 } ____cacheline_aligned_in_smp;
 716 
 717 struct sge_ofld_stats {             /* offload queue statistics */
 718         unsigned long pkts;         /* # of packets */
 719         unsigned long imm;          /* # of immediate-data packets */
 720         unsigned long an;           /* # of asynchronous notifications */
 721         unsigned long nomem;        /* # of responses deferred due to no mem */
 722 };
 723 
 724 struct sge_ofld_rxq {               /* SW offload Rx queue */
 725         struct sge_rspq rspq;
 726         struct sge_fl fl;
 727         struct sge_ofld_stats stats;
 728 } ____cacheline_aligned_in_smp;
 729 
 730 struct tx_desc {
 731         __be64 flit[8];
 732 };
 733 
 734 struct tx_sw_desc;
 735 
 736 struct sge_txq {
 737         unsigned int  in_use;       /* # of in-use Tx descriptors */
 738         unsigned int  q_type;       /* Q type Eth/Ctrl/Ofld */
 739         unsigned int  size;         /* # of descriptors */
 740         unsigned int  cidx;         /* SW consumer index */
 741         unsigned int  pidx;         /* producer index */
 742         unsigned long stops;        /* # of times q has been stopped */
 743         unsigned long restarts;     /* # of queue restarts */
 744         unsigned int  cntxt_id;     /* SGE context id for the Tx q */
 745         struct tx_desc *desc;       /* address of HW Tx descriptor ring */
 746         struct tx_sw_desc *sdesc;   /* address of SW Tx descriptor ring */
 747         struct sge_qstat *stat;     /* queue status entry */
 748         dma_addr_t    phys_addr;    /* physical address of the ring */
 749         spinlock_t db_lock;
 750         int db_disabled;
 751         unsigned short db_pidx;
 752         unsigned short db_pidx_inc;
 753         void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
 754         unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
 755 };
 756 
 757 struct sge_eth_txq {                /* state for an SGE Ethernet Tx queue */
 758         struct sge_txq q;
 759         struct netdev_queue *txq;   /* associated netdev TX queue */
 760 #ifdef CONFIG_CHELSIO_T4_DCB
 761         u8 dcb_prio;                /* DCB Priority bound to queue */
 762 #endif
 763         u8 dbqt;                    /* SGE Doorbell Queue Timer in use */
 764         unsigned int dbqtimerix;    /* SGE Doorbell Queue Timer Index */
 765         unsigned long tso;          /* # of TSO requests */
 766         unsigned long tx_cso;       /* # of Tx checksum offloads */
 767         unsigned long vlan_ins;     /* # of Tx VLAN insertions */
 768         unsigned long mapping_err;  /* # of I/O MMU packet mapping errors */
 769 } ____cacheline_aligned_in_smp;
 770 
 771 struct sge_uld_txq {               /* state for an SGE offload Tx queue */
 772         struct sge_txq q;
 773         struct adapter *adap;
 774         struct sk_buff_head sendq;  /* list of backpressured packets */
 775         struct tasklet_struct qresume_tsk; /* restarts the queue */
 776         bool service_ofldq_running; /* service_ofldq() is processing sendq */
 777         u8 full;                    /* the Tx ring is full */
 778         unsigned long mapping_err;  /* # of I/O MMU packet mapping errors */
 779 } ____cacheline_aligned_in_smp;
 780 
 781 struct sge_ctrl_txq {               /* state for an SGE control Tx queue */
 782         struct sge_txq q;
 783         struct adapter *adap;
 784         struct sk_buff_head sendq;  /* list of backpressured packets */
 785         struct tasklet_struct qresume_tsk; /* restarts the queue */
 786         u8 full;                    /* the Tx ring is full */
 787 } ____cacheline_aligned_in_smp;
 788 
 789 struct sge_uld_rxq_info {
 790         char name[IFNAMSIZ];    /* name of ULD driver */
 791         struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
 792         u16 *msix_tbl;          /* msix_tbl for uld */
 793         u16 *rspq_id;           /* response queue id's of rxq */
 794         u16 nrxq;               /* # of ingress uld queues */
 795         u16 nciq;               /* # of completion queues */
 796         u8 uld;                 /* uld type */
 797 };
 798 
 799 struct sge_uld_txq_info {
 800         struct sge_uld_txq *uldtxq; /* Txq's for ULD */
 801         atomic_t users;         /* num users */
 802         u16 ntxq;               /* # of egress uld queues */
 803 };
 804 
 805 struct sge {
 806         struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
 807         struct sge_eth_txq ptptxq;
 808         struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
 809 
 810         struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
 811         struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
 812         struct sge_uld_rxq_info **uld_rxq_info;
 813         struct sge_uld_txq_info **uld_txq_info;
 814 
 815         struct sge_rspq intrq ____cacheline_aligned_in_smp;
 816         spinlock_t intrq_lock;
 817 
 818         u16 max_ethqsets;           /* # of available Ethernet queue sets */
 819         u16 ethqsets;               /* # of active Ethernet queue sets */
 820         u16 ethtxq_rover;           /* Tx queue to clean up next */
 821         u16 ofldqsets;              /* # of active ofld queue sets */
 822         u16 nqs_per_uld;            /* # of Rx queues per ULD */
 823         u16 timer_val[SGE_NTIMERS];
 824         u8 counter_val[SGE_NCOUNTERS];
 825         u16 dbqtimer_tick;
 826         u16 dbqtimer_val[SGE_NDBQTIMERS];
 827         u32 fl_pg_order;            /* large page allocation size */
 828         u32 stat_len;               /* length of status page at ring end */
 829         u32 pktshift;               /* padding between CPL & packet data */
 830         u32 fl_align;               /* response queue message alignment */
 831         u32 fl_starve_thres;        /* Free List starvation threshold */
 832 
 833         struct sge_idma_monitor_state idma_monitor;
 834         unsigned int egr_start;
 835         unsigned int egr_sz;
 836         unsigned int ingr_start;
 837         unsigned int ingr_sz;
 838         void **egr_map;    /* qid->queue egress queue map */
 839         struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
 840         unsigned long *starving_fl;
 841         unsigned long *txq_maperr;
 842         unsigned long *blocked_fl;
 843         struct timer_list rx_timer; /* refills starving FLs */
 844         struct timer_list tx_timer; /* checks Tx queues */
 845 };
 846 
 847 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
 848 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
 849 
 850 struct l2t_data;
 851 
 852 #ifdef CONFIG_PCI_IOV
 853 
 854 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7.  However, the Serial
 855  * Configuration initialization for T5 only has SR-IOV functionality enabled
 856  * on PF0-3 in order to simplify everything.
 857  */
 858 #define NUM_OF_PF_WITH_SRIOV 4
 859 
 860 #endif
 861 
 862 struct doorbell_stats {
 863         u32 db_drop;
 864         u32 db_empty;
 865         u32 db_full;
 866 };
 867 
 868 struct hash_mac_addr {
 869         struct list_head list;
 870         u8 addr[ETH_ALEN];
 871         unsigned int iface_mac;
 872 };
 873 
 874 struct uld_msix_bmap {
 875         unsigned long *msix_bmap;
 876         unsigned int mapsize;
 877         spinlock_t lock; /* lock for acquiring bitmap */
 878 };
 879 
 880 struct uld_msix_info {
 881         unsigned short vec;
 882         char desc[IFNAMSIZ + 10];
 883         unsigned int idx;
 884         cpumask_var_t aff_mask;
 885 };
 886 
 887 struct vf_info {
 888         unsigned char vf_mac_addr[ETH_ALEN];
 889         unsigned int tx_rate;
 890         bool pf_set_mac;
 891         u16 vlan;
 892         int link_state;
 893 };
 894 
 895 enum {
 896         HMA_DMA_MAPPED_FLAG = 1
 897 };
 898 
 899 struct hma_data {
 900         unsigned char flags;
 901         struct sg_table *sgt;
 902         dma_addr_t *phy_addr;   /* physical address of the page */
 903 };
 904 
 905 struct mbox_list {
 906         struct list_head list;
 907 };
 908 
 909 #if IS_ENABLED(CONFIG_THERMAL)
 910 struct ch_thermal {
 911         struct thermal_zone_device *tzdev;
 912         int trip_temp;
 913         int trip_type;
 914 };
 915 #endif
 916 
 917 struct mps_entries_ref {
 918         struct list_head list;
 919         u8 addr[ETH_ALEN];
 920         u8 mask[ETH_ALEN];
 921         u16 idx;
 922         refcount_t refcnt;
 923 };
 924 
 925 struct adapter {
 926         void __iomem *regs;
 927         void __iomem *bar2;
 928         u32 t4_bar0;
 929         struct pci_dev *pdev;
 930         struct device *pdev_dev;
 931         const char *name;
 932         unsigned int mbox;
 933         unsigned int pf;
 934         unsigned int flags;
 935         unsigned int adap_idx;
 936         enum chip_type chip;
 937         u32 eth_flags;
 938 
 939         int msg_enable;
 940         __be16 vxlan_port;
 941         u8 vxlan_port_cnt;
 942         __be16 geneve_port;
 943         u8 geneve_port_cnt;
 944 
 945         struct adapter_params params;
 946         struct cxgb4_virt_res vres;
 947         unsigned int swintr;
 948 
 949         struct msix_info {
 950                 unsigned short vec;
 951                 char desc[IFNAMSIZ + 10];
 952                 cpumask_var_t aff_mask;
 953         } msix_info[MAX_INGQ + 1];
 954         struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
 955         struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
 956         int msi_idx;
 957 
 958         struct doorbell_stats db_stats;
 959         struct sge sge;
 960 
 961         struct net_device *port[MAX_NPORTS];
 962         u8 chan_map[NCHAN];                   /* channel -> port map */
 963 
 964         struct vf_info *vfinfo;
 965         u8 num_vfs;
 966 
 967         u32 filter_mode;
 968         unsigned int l2t_start;
 969         unsigned int l2t_end;
 970         struct l2t_data *l2t;
 971         unsigned int clipt_start;
 972         unsigned int clipt_end;
 973         struct clip_tbl *clipt;
 974         unsigned int rawf_start;
 975         unsigned int rawf_cnt;
 976         struct smt_data *smt;
 977         struct cxgb4_uld_info *uld;
 978         void *uld_handle[CXGB4_ULD_MAX];
 979         unsigned int num_uld;
 980         unsigned int num_ofld_uld;
 981         struct list_head list_node;
 982         struct list_head rcu_node;
 983         struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
 984         struct list_head mps_ref;
 985         spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
 986 
 987         void *iscsi_ppm;
 988 
 989         struct tid_info tids;
 990         void **tid_release_head;
 991         spinlock_t tid_release_lock;
 992         struct workqueue_struct *workq;
 993         struct work_struct tid_release_task;
 994         struct work_struct db_full_task;
 995         struct work_struct db_drop_task;
 996         struct work_struct fatal_err_notify_task;
 997         bool tid_release_task_busy;
 998 
 999         /* lock for mailbox cmd list */
1000         spinlock_t mbox_lock;
1001         struct mbox_list mlist;
1002 
1003         /* support for mailbox command/reply logging */
1004 #define T4_OS_LOG_MBOX_CMDS 256
1005         struct mbox_cmd_log *mbox_log;
1006 
1007         struct mutex uld_mutex;
1008 
1009         struct dentry *debugfs_root;
1010         bool use_bd;     /* Use SGE Back Door intfc for reading SGE Contexts */
1011         bool trace_rss; /* 1 implies that different RSS flit per filter is
1012                          * used per filter else if 0 default RSS flit is
1013                          * used for all 4 filters.
1014                          */
1015 
1016         struct ptp_clock *ptp_clock;
1017         struct ptp_clock_info ptp_clock_info;
1018         struct sk_buff *ptp_tx_skb;
1019         /* ptp lock */
1020         spinlock_t ptp_lock;
1021         spinlock_t stats_lock;
1022         spinlock_t win0_lock ____cacheline_aligned_in_smp;
1023 
1024         /* TC u32 offload */
1025         struct cxgb4_tc_u32_table *tc_u32;
1026         struct chcr_stats_debug chcr_stats;
1027 
1028         /* TC flower offload */
1029         bool tc_flower_initialized;
1030         struct rhashtable flower_tbl;
1031         struct rhashtable_params flower_ht_params;
1032         struct timer_list flower_stats_timer;
1033         struct work_struct flower_stats_work;
1034 
1035         /* Ethtool Dump */
1036         struct ethtool_dump eth_dump;
1037 
1038         /* HMA */
1039         struct hma_data hma;
1040 
1041         struct srq_data *srq;
1042 
1043         /* Dump buffer for collecting logs in kdump kernel */
1044         struct vmcoredd_data vmcoredd;
1045 #if IS_ENABLED(CONFIG_THERMAL)
1046         struct ch_thermal ch_thermal;
1047 #endif
1048 };
1049 
1050 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1051  * programmed with various parameters.
1052  */
1053 struct ch_sched_params {
1054         s8   type;                     /* packet or flow */
1055         union {
1056                 struct {
1057                         s8   level;    /* scheduler hierarchy level */
1058                         s8   mode;     /* per-class or per-flow */
1059                         s8   rateunit; /* bit or packet rate */
1060                         s8   ratemode; /* %port relative or kbps absolute */
1061                         s8   channel;  /* scheduler channel [0..N] */
1062                         s8   class;    /* scheduler class [0..N] */
1063                         s32  minrate;  /* minimum rate */
1064                         s32  maxrate;  /* maximum rate */
1065                         s16  weight;   /* percent weight */
1066                         s16  pktsize;  /* average packet size */
1067                 } params;
1068         } u;
1069 };
1070 
1071 enum {
1072         SCHED_CLASS_TYPE_PACKET = 0,    /* class type */
1073 };
1074 
1075 enum {
1076         SCHED_CLASS_LEVEL_CL_RL = 0,    /* class rate limiter */
1077 };
1078 
1079 enum {
1080         SCHED_CLASS_MODE_CLASS = 0,     /* per-class scheduling */
1081 };
1082 
1083 enum {
1084         SCHED_CLASS_RATEUNIT_BITS = 0,  /* bit rate scheduling */
1085 };
1086 
1087 enum {
1088         SCHED_CLASS_RATEMODE_ABS = 1,   /* Kb/s */
1089 };
1090 
1091 struct tx_sw_desc {                /* SW state per Tx descriptor */
1092         struct sk_buff *skb;
1093         struct ulptx_sgl *sgl;
1094 };
1095 
1096 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1097  * to be bound to a TX Scheduling Class.
1098  */
1099 struct ch_sched_queue {
1100         s8   queue;    /* queue index */
1101         s8   class;    /* class index */
1102 };
1103 
1104 /* Defined bit width of user definable filter tuples
1105  */
1106 #define ETHTYPE_BITWIDTH 16
1107 #define FRAG_BITWIDTH 1
1108 #define MACIDX_BITWIDTH 9
1109 #define FCOE_BITWIDTH 1
1110 #define IPORT_BITWIDTH 3
1111 #define MATCHTYPE_BITWIDTH 3
1112 #define PROTO_BITWIDTH 8
1113 #define TOS_BITWIDTH 8
1114 #define PF_BITWIDTH 8
1115 #define VF_BITWIDTH 8
1116 #define IVLAN_BITWIDTH 16
1117 #define OVLAN_BITWIDTH 16
1118 #define ENCAP_VNI_BITWIDTH 24
1119 
1120 /* Filter matching rules.  These consist of a set of ingress packet field
1121  * (value, mask) tuples.  The associated ingress packet field matches the
1122  * tuple when ((field & mask) == value).  (Thus a wildcard "don't care" field
1123  * rule can be constructed by specifying a tuple of (0, 0).)  A filter rule
1124  * matches an ingress packet when all of the individual individual field
1125  * matching rules are true.
1126  *
1127  * Partial field masks are always valid, however, while it may be easy to
1128  * understand their meanings for some fields (e.g. IP address to match a
1129  * subnet), for others making sensible partial masks is less intuitive (e.g.
1130  * MPS match type) ...
1131  *
1132  * Most of the following data structures are modeled on T4 capabilities.
1133  * Drivers for earlier chips use the subsets which make sense for those chips.
1134  * We really need to come up with a hardware-independent mechanism to
1135  * represent hardware filter capabilities ...
1136  */
1137 struct ch_filter_tuple {
1138         /* Compressed header matching field rules.  The TP_VLAN_PRI_MAP
1139          * register selects which of these fields will participate in the
1140          * filter match rules -- up to a maximum of 36 bits.  Because
1141          * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1142          * set of fields.
1143          */
1144         uint32_t ethtype:ETHTYPE_BITWIDTH;      /* Ethernet type */
1145         uint32_t frag:FRAG_BITWIDTH;            /* IP fragmentation header */
1146         uint32_t ivlan_vld:1;                   /* inner VLAN valid */
1147         uint32_t ovlan_vld:1;                   /* outer VLAN valid */
1148         uint32_t pfvf_vld:1;                    /* PF/VF valid */
1149         uint32_t encap_vld:1;                   /* Encapsulation valid */
1150         uint32_t macidx:MACIDX_BITWIDTH;        /* exact match MAC index */
1151         uint32_t fcoe:FCOE_BITWIDTH;            /* FCoE packet */
1152         uint32_t iport:IPORT_BITWIDTH;          /* ingress port */
1153         uint32_t matchtype:MATCHTYPE_BITWIDTH;  /* MPS match type */
1154         uint32_t proto:PROTO_BITWIDTH;          /* protocol type */
1155         uint32_t tos:TOS_BITWIDTH;              /* TOS/Traffic Type */
1156         uint32_t pf:PF_BITWIDTH;                /* PCI-E PF ID */
1157         uint32_t vf:VF_BITWIDTH;                /* PCI-E VF ID */
1158         uint32_t ivlan:IVLAN_BITWIDTH;          /* inner VLAN */
1159         uint32_t ovlan:OVLAN_BITWIDTH;          /* outer VLAN */
1160         uint32_t vni:ENCAP_VNI_BITWIDTH;        /* VNI of tunnel */
1161 
1162         /* Uncompressed header matching field rules.  These are always
1163          * available for field rules.
1164          */
1165         uint8_t lip[16];        /* local IP address (IPv4 in [3:0]) */
1166         uint8_t fip[16];        /* foreign IP address (IPv4 in [3:0]) */
1167         uint16_t lport;         /* local port */
1168         uint16_t fport;         /* foreign port */
1169 };
1170 
1171 /* A filter ioctl command.
1172  */
1173 struct ch_filter_specification {
1174         /* Administrative fields for filter.
1175          */
1176         uint32_t hitcnts:1;     /* count filter hits in TCB */
1177         uint32_t prio:1;        /* filter has priority over active/server */
1178 
1179         /* Fundamental filter typing.  This is the one element of filter
1180          * matching that doesn't exist as a (value, mask) tuple.
1181          */
1182         uint32_t type:1;        /* 0 => IPv4, 1 => IPv6 */
1183         u32 hash:1;             /* 0 => wild-card, 1 => exact-match */
1184 
1185         /* Packet dispatch information.  Ingress packets which match the
1186          * filter rules will be dropped, passed to the host or switched back
1187          * out as egress packets.
1188          */
1189         uint32_t action:2;      /* drop, pass, switch */
1190 
1191         uint32_t rpttid:1;      /* report TID in RSS hash field */
1192 
1193         uint32_t dirsteer:1;    /* 0 => RSS, 1 => steer to iq */
1194         uint32_t iq:10;         /* ingress queue */
1195 
1196         uint32_t maskhash:1;    /* dirsteer=0: store RSS hash in TCB */
1197         uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1198                                 /*             1 => TCB contains IQ ID */
1199 
1200         /* Switch proxy/rewrite fields.  An ingress packet which matches a
1201          * filter with "switch" set will be looped back out as an egress
1202          * packet -- potentially with some Ethernet header rewriting.
1203          */
1204         uint32_t eport:2;       /* egress port to switch packet out */
1205         uint32_t newdmac:1;     /* rewrite destination MAC address */
1206         uint32_t newsmac:1;     /* rewrite source MAC address */
1207         uint32_t newvlan:2;     /* rewrite VLAN Tag */
1208         uint32_t nat_mode:3;    /* specify NAT operation mode */
1209         uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1210         uint8_t smac[ETH_ALEN]; /* new source MAC address */
1211         uint16_t vlan;          /* VLAN Tag to insert */
1212 
1213         u8 nat_lip[16];         /* local IP to use after NAT'ing */
1214         u8 nat_fip[16];         /* foreign IP to use after NAT'ing */
1215         u16 nat_lport;          /* local port to use after NAT'ing */
1216         u16 nat_fport;          /* foreign port to use after NAT'ing */
1217 
1218         /* reservation for future additions */
1219         u8 rsvd[24];
1220 
1221         /* Filter rule value/mask pairs.
1222          */
1223         struct ch_filter_tuple val;
1224         struct ch_filter_tuple mask;
1225 };
1226 
1227 enum {
1228         FILTER_PASS = 0,        /* default */
1229         FILTER_DROP,
1230         FILTER_SWITCH
1231 };
1232 
1233 enum {
1234         VLAN_NOCHANGE = 0,      /* default */
1235         VLAN_REMOVE,
1236         VLAN_INSERT,
1237         VLAN_REWRITE
1238 };
1239 
1240 enum {
1241         NAT_MODE_NONE = 0,      /* No NAT performed */
1242         NAT_MODE_DIP,           /* NAT on Dst IP */
1243         NAT_MODE_DIP_DP,        /* NAT on Dst IP, Dst Port */
1244         NAT_MODE_DIP_DP_SIP,    /* NAT on Dst IP, Dst Port and Src IP */
1245         NAT_MODE_DIP_DP_SP,     /* NAT on Dst IP, Dst Port and Src Port */
1246         NAT_MODE_SIP_SP,        /* NAT on Src IP and Src Port */
1247         NAT_MODE_DIP_SIP_SP,    /* NAT on Dst IP, Src IP and Src Port */
1248         NAT_MODE_ALL            /* NAT on entire 4-tuple */
1249 };
1250 
1251 /* Host shadow copy of ingress filter entry.  This is in host native format
1252  * and doesn't match the ordering or bit order, etc. of the hardware of the
1253  * firmware command.  The use of bit-field structure elements is purely to
1254  * remind ourselves of the field size limitations and save memory in the case
1255  * where the filter table is large.
1256  */
1257 struct filter_entry {
1258         /* Administrative fields for filter. */
1259         u32 valid:1;            /* filter allocated and valid */
1260         u32 locked:1;           /* filter is administratively locked */
1261 
1262         u32 pending:1;          /* filter action is pending firmware reply */
1263         struct filter_ctx *ctx; /* Caller's completion hook */
1264         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
1265         struct smt_entry *smt;  /* Source Mac Table entry for smac */
1266         struct net_device *dev; /* Associated net device */
1267         u32 tid;                /* This will store the actual tid */
1268 
1269         /* The filter itself.  Most of this is a straight copy of information
1270          * provided by the extended ioctl().  Some fields are translated to
1271          * internal forms -- for instance the Ingress Queue ID passed in from
1272          * the ioctl() is translated into the Absolute Ingress Queue ID.
1273          */
1274         struct ch_filter_specification fs;
1275 };
1276 
1277 static inline int is_offload(const struct adapter *adap)
1278 {
1279         return adap->params.offload;
1280 }
1281 
1282 static inline int is_hashfilter(const struct adapter *adap)
1283 {
1284         return adap->params.hash_filter;
1285 }
1286 
1287 static inline int is_pci_uld(const struct adapter *adap)
1288 {
1289         return adap->params.crypto;
1290 }
1291 
1292 static inline int is_uld(const struct adapter *adap)
1293 {
1294         return (adap->params.offload || adap->params.crypto);
1295 }
1296 
1297 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1298 {
1299         return readl(adap->regs + reg_addr);
1300 }
1301 
1302 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1303 {
1304         writel(val, adap->regs + reg_addr);
1305 }
1306 
1307 #ifndef readq
1308 static inline u64 readq(const volatile void __iomem *addr)
1309 {
1310         return readl(addr) + ((u64)readl(addr + 4) << 32);
1311 }
1312 
1313 static inline void writeq(u64 val, volatile void __iomem *addr)
1314 {
1315         writel(val, addr);
1316         writel(val >> 32, addr + 4);
1317 }
1318 #endif
1319 
1320 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1321 {
1322         return readq(adap->regs + reg_addr);
1323 }
1324 
1325 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1326 {
1327         writeq(val, adap->regs + reg_addr);
1328 }
1329 
1330 /**
1331  * t4_set_hw_addr - store a port's MAC address in SW
1332  * @adapter: the adapter
1333  * @port_idx: the port index
1334  * @hw_addr: the Ethernet address
1335  *
1336  * Store the Ethernet address of the given port in SW.  Called by the common
1337  * code when it retrieves a port's Ethernet address from EEPROM.
1338  */
1339 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1340                                   u8 hw_addr[])
1341 {
1342         ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1343         ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1344 }
1345 
1346 /**
1347  * netdev2pinfo - return the port_info structure associated with a net_device
1348  * @dev: the netdev
1349  *
1350  * Return the struct port_info associated with a net_device
1351  */
1352 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1353 {
1354         return netdev_priv(dev);
1355 }
1356 
1357 /**
1358  * adap2pinfo - return the port_info of a port
1359  * @adap: the adapter
1360  * @idx: the port index
1361  *
1362  * Return the port_info structure for the port of the given index.
1363  */
1364 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1365 {
1366         return netdev_priv(adap->port[idx]);
1367 }
1368 
1369 /**
1370  * netdev2adap - return the adapter structure associated with a net_device
1371  * @dev: the netdev
1372  *
1373  * Return the struct adapter associated with a net_device
1374  */
1375 static inline struct adapter *netdev2adap(const struct net_device *dev)
1376 {
1377         return netdev2pinfo(dev)->adapter;
1378 }
1379 
1380 /* Return a version number to identify the type of adapter.  The scheme is:
1381  * - bits 0..9: chip version
1382  * - bits 10..15: chip revision
1383  * - bits 16..23: register dump version
1384  */
1385 static inline unsigned int mk_adap_vers(struct adapter *ap)
1386 {
1387         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1388                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1389 }
1390 
1391 /* Return a queue's interrupt hold-off time in us.  0 means no timer. */
1392 static inline unsigned int qtimer_val(const struct adapter *adap,
1393                                       const struct sge_rspq *q)
1394 {
1395         unsigned int idx = q->intr_params >> 1;
1396 
1397         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1398 }
1399 
1400 /* driver version & name used for ethtool_drvinfo */
1401 extern char cxgb4_driver_name[];
1402 extern const char cxgb4_driver_version[];
1403 
1404 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1405 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1406 
1407 void t4_free_sge_resources(struct adapter *adap);
1408 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1409 irq_handler_t t4_intr_handler(struct adapter *adap);
1410 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1411 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1412                      const struct pkt_gl *gl);
1413 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1414 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1415 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1416                      struct net_device *dev, int intr_idx,
1417                      struct sge_fl *fl, rspq_handler_t hnd,
1418                      rspq_flush_handler_t flush_handler, int cong);
1419 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1420                          struct net_device *dev, struct netdev_queue *netdevq,
1421                          unsigned int iqid, u8 dbqt);
1422 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1423                           struct net_device *dev, unsigned int iqid,
1424                           unsigned int cmplqid);
1425 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1426                         unsigned int cmplqid);
1427 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1428                          struct net_device *dev, unsigned int iqid,
1429                          unsigned int uld_type);
1430 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1431 int t4_sge_init(struct adapter *adap);
1432 void t4_sge_start(struct adapter *adap);
1433 void t4_sge_stop(struct adapter *adap);
1434 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1435                                  int maxreclaim);
1436 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1437 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1438 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1439 extern int dbfifo_int_thresh;
1440 
1441 #define for_each_port(adapter, iter) \
1442         for (iter = 0; iter < (adapter)->params.nports; ++iter)
1443 
1444 static inline int is_bypass(struct adapter *adap)
1445 {
1446         return adap->params.bypass;
1447 }
1448 
1449 static inline int is_bypass_device(int device)
1450 {
1451         /* this should be set based upon device capabilities */
1452         switch (device) {
1453         case 0x440b:
1454         case 0x440c:
1455                 return 1;
1456         default:
1457                 return 0;
1458         }
1459 }
1460 
1461 static inline int is_10gbt_device(int device)
1462 {
1463         /* this should be set based upon device capabilities */
1464         switch (device) {
1465         case 0x4409:
1466         case 0x4486:
1467                 return 1;
1468 
1469         default:
1470                 return 0;
1471         }
1472 }
1473 
1474 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1475 {
1476         return adap->params.vpd.cclk / 1000;
1477 }
1478 
1479 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1480                                             unsigned int us)
1481 {
1482         return (us * adap->params.vpd.cclk) / 1000;
1483 }
1484 
1485 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1486                                             unsigned int ticks)
1487 {
1488         /* add Core Clock / 2 to round ticks to nearest uS */
1489         return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1490                 adapter->params.vpd.cclk);
1491 }
1492 
1493 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1494                                               unsigned int ticks)
1495 {
1496         return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1497 }
1498 
1499 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1500                       u32 val);
1501 
1502 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1503                             int size, void *rpl, bool sleep_ok, int timeout);
1504 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1505                     void *rpl, bool sleep_ok);
1506 
1507 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1508                                      const void *cmd, int size, void *rpl,
1509                                      int timeout)
1510 {
1511         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1512                                        timeout);
1513 }
1514 
1515 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1516                              int size, void *rpl)
1517 {
1518         return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1519 }
1520 
1521 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1522                                 int size, void *rpl)
1523 {
1524         return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1525 }
1526 
1527 /**
1528  *      hash_mac_addr - return the hash value of a MAC address
1529  *      @addr: the 48-bit Ethernet MAC address
1530  *
1531  *      Hashes a MAC address according to the hash function used by HW inexact
1532  *      (hash) address matching.
1533  */
1534 static inline int hash_mac_addr(const u8 *addr)
1535 {
1536         u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1537         u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1538 
1539         a ^= b;
1540         a ^= (a >> 12);
1541         a ^= (a >> 6);
1542         return a & 0x3f;
1543 }
1544 
1545 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1546                                unsigned int cnt);
1547 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1548                              unsigned int us, unsigned int cnt,
1549                              unsigned int size, unsigned int iqe_size)
1550 {
1551         q->adap = adap;
1552         cxgb4_set_rspq_intr_params(q, us, cnt);
1553         q->iqe_len = iqe_size;
1554         q->size = size;
1555 }
1556 
1557 /**
1558  *     t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1559  *     @fw_mod_type: the Firmware Mofule Type
1560  *
1561  *     Return whether the Firmware Module Type represents a real Transceiver
1562  *     Module/Cable Module Type which has been inserted.
1563  */
1564 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1565 {
1566         return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1567                 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1568                 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1569                 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1570 }
1571 
1572 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1573                        unsigned int data_reg, const u32 *vals,
1574                        unsigned int nregs, unsigned int start_idx);
1575 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1576                       unsigned int data_reg, u32 *vals, unsigned int nregs,
1577                       unsigned int start_idx);
1578 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1579 
1580 struct fw_filter_wr;
1581 
1582 void t4_intr_enable(struct adapter *adapter);
1583 void t4_intr_disable(struct adapter *adapter);
1584 int t4_slow_intr_handler(struct adapter *adapter);
1585 
1586 int t4_wait_dev_ready(void __iomem *regs);
1587 
1588 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1589                               struct link_config *lc);
1590 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1591                        unsigned int port, struct link_config *lc,
1592                        u8 sleep_ok, int timeout);
1593 
1594 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1595                                 unsigned int port, struct link_config *lc)
1596 {
1597         return t4_link_l1cfg_core(adapter, mbox, port, lc,
1598                                   true, FW_CMD_MAX_TIMEOUT);
1599 }
1600 
1601 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1602                                    unsigned int port, struct link_config *lc)
1603 {
1604         return t4_link_l1cfg_core(adapter, mbox, port, lc,
1605                                   false, FW_CMD_MAX_TIMEOUT);
1606 }
1607 
1608 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1609 
1610 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1611 u32 t4_get_util_window(struct adapter *adap);
1612 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1613 
1614 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1615                       u32 *mem_base, u32 *mem_aperture);
1616 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1617 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1618                            int dir);
1619 #define T4_MEMORY_WRITE 0
1620 #define T4_MEMORY_READ  1
1621 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1622                  void *buf, int dir);
1623 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1624                                   u32 len, __be32 *buf)
1625 {
1626         return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1627 }
1628 
1629 unsigned int t4_get_regs_len(struct adapter *adapter);
1630 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1631 
1632 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1633 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1634 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1635 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1636 int t4_get_pfres(struct adapter *adapter);
1637 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1638                   unsigned int nwords, u32 *data, int byte_oriented);
1639 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1640 int t4_load_phy_fw(struct adapter *adap,
1641                    int win, spinlock_t *lock,
1642                    int (*phy_fw_version)(const u8 *, size_t),
1643                    const u8 *phy_fw_data, size_t phy_fw_size);
1644 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1645 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1646 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1647                   const u8 *fw_data, unsigned int size, int force);
1648 int t4_fl_pkt_align(struct adapter *adap);
1649 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1650 int t4_check_fw_version(struct adapter *adap);
1651 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1652 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1653 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1654 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1655 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1656 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1657 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1658 int t4_get_version_info(struct adapter *adapter);
1659 void t4_dump_version_info(struct adapter *adapter);
1660 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1661                const u8 *fw_data, unsigned int fw_size,
1662                struct fw_hdr *card_fw, enum dev_state state, int *reset);
1663 int t4_prep_adapter(struct adapter *adapter);
1664 int t4_shutdown_adapter(struct adapter *adapter);
1665 
1666 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1667 int t4_bar2_sge_qregs(struct adapter *adapter,
1668                       unsigned int qid,
1669                       enum t4_bar2_qtype qtype,
1670                       int user,
1671                       u64 *pbar2_qoffset,
1672                       unsigned int *pbar2_qid);
1673 
1674 unsigned int qtimer_val(const struct adapter *adap,
1675                         const struct sge_rspq *q);
1676 
1677 int t4_init_devlog_params(struct adapter *adapter);
1678 int t4_init_sge_params(struct adapter *adapter);
1679 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1680 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1681 int t4_init_rss_mode(struct adapter *adap, int mbox);
1682 int t4_init_portinfo(struct port_info *pi, int mbox,
1683                      int port, int pf, int vf, u8 mac[]);
1684 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1685 void t4_fatal_err(struct adapter *adapter);
1686 unsigned int t4_chip_rss_size(struct adapter *adapter);
1687 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1688                         int start, int n, const u16 *rspq, unsigned int nrspq);
1689 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1690                        unsigned int flags);
1691 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1692                      unsigned int flags, unsigned int defq);
1693 int t4_read_rss(struct adapter *adapter, u16 *entries);
1694 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1695 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1696                       bool sleep_ok);
1697 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1698                            u32 *valp, bool sleep_ok);
1699 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1700                            u32 *vfl, u32 *vfh, bool sleep_ok);
1701 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1702 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1703 
1704 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1705 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1706 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1707 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1708 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1709                     size_t n);
1710 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1711                     size_t n);
1712 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1713                 unsigned int *valp);
1714 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1715                  const unsigned int *valp);
1716 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1717 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1718                         unsigned int *pif_req_wrptr,
1719                         unsigned int *pif_rsp_wrptr);
1720 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1721 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1722 const char *t4_get_port_type_description(enum fw_port_type port_type);
1723 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1724 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1725                               struct port_stats *stats,
1726                               struct port_stats *offset);
1727 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1728 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1729 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1730 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1731                             unsigned int mask, unsigned int val);
1732 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1733 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1734                          bool sleep_ok);
1735 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1736                          bool sleep_ok);
1737 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1738                           bool sleep_ok);
1739 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1740                       bool sleep_ok);
1741 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1742                          struct tp_tcp_stats *v6, bool sleep_ok);
1743 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1744                        struct tp_fcoe_stats *st, bool sleep_ok);
1745 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1746                   const unsigned short *alpha, const unsigned short *beta);
1747 
1748 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1749 
1750 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1751 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1752 
1753 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1754                          const u8 *addr);
1755 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1756                       u64 mask0, u64 mask1, unsigned int crc, bool enable);
1757 
1758 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1759                 enum dev_master master, enum dev_state *state);
1760 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1761 int t4_early_init(struct adapter *adap, unsigned int mbox);
1762 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1763 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1764                           unsigned int cache_line_size);
1765 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1766 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1767                     unsigned int vf, unsigned int nparams, const u32 *params,
1768                     u32 *val);
1769 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1770                        unsigned int vf, unsigned int nparams, const u32 *params,
1771                        u32 *val);
1772 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1773                        unsigned int vf, unsigned int nparams, const u32 *params,
1774                        u32 *val, int rw, bool sleep_ok);
1775 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1776                           unsigned int pf, unsigned int vf,
1777                           unsigned int nparams, const u32 *params,
1778                           const u32 *val, int timeout);
1779 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1780                   unsigned int vf, unsigned int nparams, const u32 *params,
1781                   const u32 *val);
1782 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1783                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1784                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1785                 unsigned int vi, unsigned int cmask, unsigned int pmask,
1786                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1787 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1788                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1789                 unsigned int *rss_size, u8 *vivld, u8 *vin);
1790 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1791                unsigned int pf, unsigned int vf,
1792                unsigned int viid);
1793 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1794                 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1795                 bool sleep_ok);
1796 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1797                          const u8 *addr, const u8 *mask, unsigned int idx,
1798                          u8 lookup_type, u8 port_id, bool sleep_ok);
1799 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1800                            bool sleep_ok);
1801 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1802                             const u8 *addr, const u8 *mask, unsigned int vni,
1803                             unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1804                             bool sleep_ok);
1805 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1806                           const u8 *addr, const u8 *mask, unsigned int idx,
1807                           u8 lookup_type, u8 port_id, bool sleep_ok);
1808 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1809                       unsigned int viid, bool free, unsigned int naddr,
1810                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1811 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1812                      unsigned int viid, unsigned int naddr,
1813                      const u8 **addr, bool sleep_ok);
1814 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1815                   int idx, const u8 *addr, bool persist, u8 *smt_idx);
1816 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1817                      bool ucast, u64 vec, bool sleep_ok);
1818 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1819                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1820 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1821                         struct port_info *pi,
1822                         bool rx_en, bool tx_en, bool dcb_en);
1823 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1824                  bool rx_en, bool tx_en);
1825 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1826                      unsigned int nblinks);
1827 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1828                unsigned int mmd, unsigned int reg, u16 *valp);
1829 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1830                unsigned int mmd, unsigned int reg, u16 val);
1831 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1832                unsigned int vf, unsigned int iqtype, unsigned int iqid,
1833                unsigned int fl0id, unsigned int fl1id);
1834 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1835                unsigned int vf, unsigned int iqtype, unsigned int iqid,
1836                unsigned int fl0id, unsigned int fl1id);
1837 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1838                    unsigned int vf, unsigned int eqid);
1839 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1840                     unsigned int vf, unsigned int eqid);
1841 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1842                     unsigned int vf, unsigned int eqid);
1843 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1844 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1845                           u16 *dbqtimers);
1846 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1847 int t4_update_port_info(struct port_info *pi);
1848 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1849                        unsigned int *speedp, unsigned int *mtup);
1850 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1851 void t4_db_full(struct adapter *adapter);
1852 void t4_db_dropped(struct adapter *adapter);
1853 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1854                         int filter_index, int enable);
1855 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1856                          int filter_index, int *enabled);
1857 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1858                          u32 addr, u32 val);
1859 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1860 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1861                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1862 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1863                    enum ctxt_type ctype, u32 *data);
1864 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1865                       enum ctxt_type ctype, u32 *data);
1866 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1867                     int rateunit, int ratemode, int channel, int class,
1868                     int minrate, int maxrate, int weight, int pktsize);
1869 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1870 void t4_idma_monitor_init(struct adapter *adapter,
1871                           struct sge_idma_monitor_state *idma);
1872 void t4_idma_monitor(struct adapter *adapter,
1873                      struct sge_idma_monitor_state *idma,
1874                      int hz, int ticks);
1875 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1876                       unsigned int naddr, u8 *addr);
1877 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1878                     u32 start_index, bool sleep_ok);
1879 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1880                        u32 start_index, bool sleep_ok);
1881 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1882                     u32 start_index, bool sleep_ok);
1883 
1884 void t4_uld_mem_free(struct adapter *adap);
1885 int t4_uld_mem_alloc(struct adapter *adap);
1886 void t4_uld_clean_up(struct adapter *adap);
1887 void t4_register_netevent_notifier(void);
1888 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1889               unsigned int devid, unsigned int offset,
1890               unsigned int len, u8 *buf);
1891 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1892 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1893                   unsigned int n, bool unmap);
1894 void free_txq(struct adapter *adap, struct sge_txq *q);
1895 void cxgb4_reclaim_completed_tx(struct adapter *adap,
1896                                 struct sge_txq *q, bool unmap);
1897 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1898                   dma_addr_t *addr);
1899 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1900                          void *pos);
1901 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1902                      struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1903                      const dma_addr_t *addr);
1904 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1905 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1906                     u16 vlan);
1907 int cxgb4_dcb_enabled(const struct net_device *dev);
1908 
1909 int cxgb4_thermal_init(struct adapter *adap);
1910 int cxgb4_thermal_remove(struct adapter *adap);
1911 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
1912                        cpumask_var_t *aff_mask, int idx);
1913 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
1914 
1915 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
1916                      int *tcam_idx, const u8 *addr,
1917                      bool persistent, u8 *smt_idx);
1918 
1919 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
1920                          bool free, unsigned int naddr,
1921                          const u8 **addr, u16 *idx,
1922                          u64 *hash, bool sleep_ok);
1923 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
1924                         unsigned int naddr, const u8 **addr, bool sleep_ok);
1925 int cxgb4_init_mps_ref_entries(struct adapter *adap);
1926 void cxgb4_free_mps_ref_entries(struct adapter *adap);
1927 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1928                                const u8 *addr, const u8 *mask,
1929                                unsigned int vni, unsigned int vni_mask,
1930                                u8 dip_hit, u8 lookup_type, bool sleep_ok);
1931 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
1932                               int idx, bool sleep_ok);
1933 int cxgb4_free_raw_mac_filt(struct adapter *adap,
1934                             unsigned int viid,
1935                             const u8 *addr,
1936                             const u8 *mask,
1937                             unsigned int idx,
1938                             u8 lookup_type,
1939                             u8 port_id,
1940                             bool sleep_ok);
1941 int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
1942                              unsigned int viid,
1943                              const u8 *addr,
1944                              const u8 *mask,
1945                              unsigned int idx,
1946                              u8 lookup_type,
1947                              u8 port_id,
1948                              bool sleep_ok);
1949 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
1950                           int *tcam_idx, const u8 *addr,
1951                           bool persistent, u8 *smt_idx);
1952 
1953 #endif /* __CXGB4_H__ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

INCLUDED FROM

DEFINITIONS
