This source file includes following definitions.
- get_msglevel
- set_msglevel
- get_sset_count
- get_regs_len
- get_eeprom_len
- get_drvinfo
- get_strings
- collect_sge_port_stats
- collect_adapter_stats
- get_stats
- get_regs
- restart_autoneg
- identify_port
- from_fw_port_mod_type
- speed_to_fw_caps
- fw_caps_to_lmm
- lmm_to_fw_caps
- get_link_ksettings
- set_link_ksettings
- fwcap_to_eth_fec
- cc_to_eth_fec
- eth_to_cc_fec
- get_fecparam
- set_fecparam
- get_pauseparam
- set_pauseparam
- get_sge_param
- set_sge_param
- set_rx_intr_params
- set_adaptive_rx_setting
- get_adaptive_rx_setting
- get_dbqtimer_tick
- get_dbqtimer
- set_dbqtimer_tick
- set_dbqtimer
- set_dbqtimer_tickval
- set_coalesce
- get_coalesce
- eeprom_rd_phys
- eeprom_wr_phys
- get_eeprom
- set_eeprom
- set_flash
- get_ts_info
- get_rss_table_size
- get_rss_table
- set_rss_table
- get_rxnfc
- set_dump
- get_dump_flag
- get_dump_data
- cxgb4_get_module_info
- cxgb4_get_module_eeprom
- cxgb4_get_priv_flags
- set_flags
- cxgb4_set_priv_flags
- cxgb4_set_ethtool_ops
1
2
3
4
5
6 #include <linux/firmware.h>
7 #include <linux/mdio.h>
8
9 #include "cxgb4.h"
10 #include "t4_regs.h"
11 #include "t4fw_api.h"
12 #include "cxgb4_cudbg.h"
13
14 #define EEPROM_MAGIC 0x38E2F10C
15
16 static u32 get_msglevel(struct net_device *dev)
17 {
18 return netdev2adap(dev)->msg_enable;
19 }
20
21 static void set_msglevel(struct net_device *dev, u32 val)
22 {
23 netdev2adap(dev)->msg_enable = val;
24 }
25
26 static const char stats_strings[][ETH_GSTRING_LEN] = {
27 "tx_octets_ok ",
28 "tx_frames_ok ",
29 "tx_broadcast_frames ",
30 "tx_multicast_frames ",
31 "tx_unicast_frames ",
32 "tx_error_frames ",
33
34 "tx_frames_64 ",
35 "tx_frames_65_to_127 ",
36 "tx_frames_128_to_255 ",
37 "tx_frames_256_to_511 ",
38 "tx_frames_512_to_1023 ",
39 "tx_frames_1024_to_1518 ",
40 "tx_frames_1519_to_max ",
41
42 "tx_frames_dropped ",
43 "tx_pause_frames ",
44 "tx_ppp0_frames ",
45 "tx_ppp1_frames ",
46 "tx_ppp2_frames ",
47 "tx_ppp3_frames ",
48 "tx_ppp4_frames ",
49 "tx_ppp5_frames ",
50 "tx_ppp6_frames ",
51 "tx_ppp7_frames ",
52
53 "rx_octets_ok ",
54 "rx_frames_ok ",
55 "rx_broadcast_frames ",
56 "rx_multicast_frames ",
57 "rx_unicast_frames ",
58
59 "rx_frames_too_long ",
60 "rx_jabber_errors ",
61 "rx_fcs_errors ",
62 "rx_length_errors ",
63 "rx_symbol_errors ",
64 "rx_runt_frames ",
65
66 "rx_frames_64 ",
67 "rx_frames_65_to_127 ",
68 "rx_frames_128_to_255 ",
69 "rx_frames_256_to_511 ",
70 "rx_frames_512_to_1023 ",
71 "rx_frames_1024_to_1518 ",
72 "rx_frames_1519_to_max ",
73
74 "rx_pause_frames ",
75 "rx_ppp0_frames ",
76 "rx_ppp1_frames ",
77 "rx_ppp2_frames ",
78 "rx_ppp3_frames ",
79 "rx_ppp4_frames ",
80 "rx_ppp5_frames ",
81 "rx_ppp6_frames ",
82 "rx_ppp7_frames ",
83
84 "rx_bg0_frames_dropped ",
85 "rx_bg1_frames_dropped ",
86 "rx_bg2_frames_dropped ",
87 "rx_bg3_frames_dropped ",
88 "rx_bg0_frames_trunc ",
89 "rx_bg1_frames_trunc ",
90 "rx_bg2_frames_trunc ",
91 "rx_bg3_frames_trunc ",
92
93 "tso ",
94 "tx_csum_offload ",
95 "rx_csum_good ",
96 "vlan_extractions ",
97 "vlan_insertions ",
98 "gro_packets ",
99 "gro_merged ",
100 };
101
102 static char adapter_stats_strings[][ETH_GSTRING_LEN] = {
103 "db_drop ",
104 "db_full ",
105 "db_empty ",
106 "write_coal_success ",
107 "write_coal_fail ",
108 };
109
110 static char loopback_stats_strings[][ETH_GSTRING_LEN] = {
111 "-------Loopback----------- ",
112 "octets_ok ",
113 "frames_ok ",
114 "bcast_frames ",
115 "mcast_frames ",
116 "ucast_frames ",
117 "error_frames ",
118 "frames_64 ",
119 "frames_65_to_127 ",
120 "frames_128_to_255 ",
121 "frames_256_to_511 ",
122 "frames_512_to_1023 ",
123 "frames_1024_to_1518 ",
124 "frames_1519_to_max ",
125 "frames_dropped ",
126 "bg0_frames_dropped ",
127 "bg1_frames_dropped ",
128 "bg2_frames_dropped ",
129 "bg3_frames_dropped ",
130 "bg0_frames_trunc ",
131 "bg1_frames_trunc ",
132 "bg2_frames_trunc ",
133 "bg3_frames_trunc ",
134 };
135
136 static const char cxgb4_priv_flags_strings[][ETH_GSTRING_LEN] = {
137 [PRIV_FLAG_PORT_TX_VM_BIT] = "port_tx_vm_wr",
138 };
139
140 static int get_sset_count(struct net_device *dev, int sset)
141 {
142 switch (sset) {
143 case ETH_SS_STATS:
144 return ARRAY_SIZE(stats_strings) +
145 ARRAY_SIZE(adapter_stats_strings) +
146 ARRAY_SIZE(loopback_stats_strings);
147 case ETH_SS_PRIV_FLAGS:
148 return ARRAY_SIZE(cxgb4_priv_flags_strings);
149 default:
150 return -EOPNOTSUPP;
151 }
152 }
153
154 static int get_regs_len(struct net_device *dev)
155 {
156 struct adapter *adap = netdev2adap(dev);
157
158 return t4_get_regs_len(adap);
159 }
160
161 static int get_eeprom_len(struct net_device *dev)
162 {
163 return EEPROMSIZE;
164 }
165
166 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
167 {
168 struct adapter *adapter = netdev2adap(dev);
169 u32 exprom_vers;
170
171 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
172 strlcpy(info->version, cxgb4_driver_version,
173 sizeof(info->version));
174 strlcpy(info->bus_info, pci_name(adapter->pdev),
175 sizeof(info->bus_info));
176 info->regdump_len = get_regs_len(dev);
177
178 if (!adapter->params.fw_vers)
179 strcpy(info->fw_version, "N/A");
180 else
181 snprintf(info->fw_version, sizeof(info->fw_version),
182 "%u.%u.%u.%u, TP %u.%u.%u.%u",
183 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
184 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
185 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
186 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
187 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
188 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
189 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
190 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
191
192 if (!t4_get_exprom_version(adapter, &exprom_vers))
193 snprintf(info->erom_version, sizeof(info->erom_version),
194 "%u.%u.%u.%u",
195 FW_HDR_FW_VER_MAJOR_G(exprom_vers),
196 FW_HDR_FW_VER_MINOR_G(exprom_vers),
197 FW_HDR_FW_VER_MICRO_G(exprom_vers),
198 FW_HDR_FW_VER_BUILD_G(exprom_vers));
199 info->n_priv_flags = ARRAY_SIZE(cxgb4_priv_flags_strings);
200 }
201
202 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
203 {
204 if (stringset == ETH_SS_STATS) {
205 memcpy(data, stats_strings, sizeof(stats_strings));
206 data += sizeof(stats_strings);
207 memcpy(data, adapter_stats_strings,
208 sizeof(adapter_stats_strings));
209 data += sizeof(adapter_stats_strings);
210 memcpy(data, loopback_stats_strings,
211 sizeof(loopback_stats_strings));
212 } else if (stringset == ETH_SS_PRIV_FLAGS) {
213 memcpy(data, cxgb4_priv_flags_strings,
214 sizeof(cxgb4_priv_flags_strings));
215 }
216 }
217
218
219
220
221 struct queue_port_stats {
222 u64 tso;
223 u64 tx_csum;
224 u64 rx_csum;
225 u64 vlan_ex;
226 u64 vlan_ins;
227 u64 gro_pkts;
228 u64 gro_merged;
229 };
230
231 struct adapter_stats {
232 u64 db_drop;
233 u64 db_full;
234 u64 db_empty;
235 u64 wc_success;
236 u64 wc_fail;
237 };
238
239 static void collect_sge_port_stats(const struct adapter *adap,
240 const struct port_info *p,
241 struct queue_port_stats *s)
242 {
243 int i;
244 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
245 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
246
247 memset(s, 0, sizeof(*s));
248 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
249 s->tso += tx->tso;
250 s->tx_csum += tx->tx_cso;
251 s->rx_csum += rx->stats.rx_cso;
252 s->vlan_ex += rx->stats.vlan_ex;
253 s->vlan_ins += tx->vlan_ins;
254 s->gro_pkts += rx->stats.lro_pkts;
255 s->gro_merged += rx->stats.lro_merged;
256 }
257 }
258
259 static void collect_adapter_stats(struct adapter *adap, struct adapter_stats *s)
260 {
261 u64 val1, val2;
262
263 memset(s, 0, sizeof(*s));
264
265 s->db_drop = adap->db_stats.db_drop;
266 s->db_full = adap->db_stats.db_full;
267 s->db_empty = adap->db_stats.db_empty;
268
269 if (!is_t4(adap->params.chip)) {
270 int v;
271
272 v = t4_read_reg(adap, SGE_STAT_CFG_A);
273 if (STATSOURCE_T5_G(v) == 7) {
274 val2 = t4_read_reg(adap, SGE_STAT_MATCH_A);
275 val1 = t4_read_reg(adap, SGE_STAT_TOTAL_A);
276 s->wc_success = val1 - val2;
277 s->wc_fail = val2;
278 }
279 }
280 }
281
282 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
283 u64 *data)
284 {
285 struct port_info *pi = netdev_priv(dev);
286 struct adapter *adapter = pi->adapter;
287 struct lb_port_stats s;
288 int i;
289 u64 *p0;
290
291 t4_get_port_stats_offset(adapter, pi->tx_chan,
292 (struct port_stats *)data,
293 &pi->stats_base);
294
295 data += sizeof(struct port_stats) / sizeof(u64);
296 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
297 data += sizeof(struct queue_port_stats) / sizeof(u64);
298 collect_adapter_stats(adapter, (struct adapter_stats *)data);
299 data += sizeof(struct adapter_stats) / sizeof(u64);
300
301 *data++ = (u64)pi->port_id;
302 memset(&s, 0, sizeof(s));
303 t4_get_lb_stats(adapter, pi->port_id, &s);
304
305 p0 = &s.octets;
306 for (i = 0; i < ARRAY_SIZE(loopback_stats_strings) - 1; i++)
307 *data++ = (unsigned long long)*p0++;
308 }
309
310 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
311 void *buf)
312 {
313 struct adapter *adap = netdev2adap(dev);
314 size_t buf_size;
315
316 buf_size = t4_get_regs_len(adap);
317 regs->version = mk_adap_vers(adap);
318 t4_get_regs(adap, buf, buf_size);
319 }
320
321 static int restart_autoneg(struct net_device *dev)
322 {
323 struct port_info *p = netdev_priv(dev);
324
325 if (!netif_running(dev))
326 return -EAGAIN;
327 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
328 return -EINVAL;
329 t4_restart_aneg(p->adapter, p->adapter->pf, p->tx_chan);
330 return 0;
331 }
332
333 static int identify_port(struct net_device *dev,
334 enum ethtool_phys_id_state state)
335 {
336 unsigned int val;
337 struct adapter *adap = netdev2adap(dev);
338
339 if (state == ETHTOOL_ID_ACTIVE)
340 val = 0xffff;
341 else if (state == ETHTOOL_ID_INACTIVE)
342 val = 0;
343 else
344 return -EINVAL;
345
346 return t4_identify_port(adap, adap->pf, netdev2pinfo(dev)->viid, val);
347 }
348
349
350
351
352
353
354
355
356 static int from_fw_port_mod_type(enum fw_port_type port_type,
357 enum fw_port_module_type mod_type)
358 {
359 if (port_type == FW_PORT_TYPE_BT_SGMII ||
360 port_type == FW_PORT_TYPE_BT_XFI ||
361 port_type == FW_PORT_TYPE_BT_XAUI) {
362 return PORT_TP;
363 } else if (port_type == FW_PORT_TYPE_FIBER_XFI ||
364 port_type == FW_PORT_TYPE_FIBER_XAUI) {
365 return PORT_FIBRE;
366 } else if (port_type == FW_PORT_TYPE_SFP ||
367 port_type == FW_PORT_TYPE_QSFP_10G ||
368 port_type == FW_PORT_TYPE_QSA ||
369 port_type == FW_PORT_TYPE_QSFP ||
370 port_type == FW_PORT_TYPE_CR4_QSFP ||
371 port_type == FW_PORT_TYPE_CR_QSFP ||
372 port_type == FW_PORT_TYPE_CR2_QSFP ||
373 port_type == FW_PORT_TYPE_SFP28) {
374 if (mod_type == FW_PORT_MOD_TYPE_LR ||
375 mod_type == FW_PORT_MOD_TYPE_SR ||
376 mod_type == FW_PORT_MOD_TYPE_ER ||
377 mod_type == FW_PORT_MOD_TYPE_LRM)
378 return PORT_FIBRE;
379 else if (mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
380 mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
381 return PORT_DA;
382 else
383 return PORT_OTHER;
384 } else if (port_type == FW_PORT_TYPE_KR4_100G ||
385 port_type == FW_PORT_TYPE_KR_SFP28 ||
386 port_type == FW_PORT_TYPE_KR_XLAUI) {
387 return PORT_NONE;
388 }
389
390 return PORT_OTHER;
391 }
392
393
394
395
396
397
398
399
400 static unsigned int speed_to_fw_caps(int speed)
401 {
402 if (speed == 100)
403 return FW_PORT_CAP32_SPEED_100M;
404 if (speed == 1000)
405 return FW_PORT_CAP32_SPEED_1G;
406 if (speed == 10000)
407 return FW_PORT_CAP32_SPEED_10G;
408 if (speed == 25000)
409 return FW_PORT_CAP32_SPEED_25G;
410 if (speed == 40000)
411 return FW_PORT_CAP32_SPEED_40G;
412 if (speed == 50000)
413 return FW_PORT_CAP32_SPEED_50G;
414 if (speed == 100000)
415 return FW_PORT_CAP32_SPEED_100G;
416 if (speed == 200000)
417 return FW_PORT_CAP32_SPEED_200G;
418 if (speed == 400000)
419 return FW_PORT_CAP32_SPEED_400G;
420 return 0;
421 }
422
423
424
425
426
427
428
429
430
431
432 static void fw_caps_to_lmm(enum fw_port_type port_type,
433 fw_port_cap32_t fw_caps,
434 unsigned long *link_mode_mask)
435 {
436 #define SET_LMM(__lmm_name) \
437 do { \
438 __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
439 link_mode_mask); \
440 } while (0)
441
442 #define FW_CAPS_TO_LMM(__fw_name, __lmm_name) \
443 do { \
444 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
445 SET_LMM(__lmm_name); \
446 } while (0)
447
448 switch (port_type) {
449 case FW_PORT_TYPE_BT_SGMII:
450 case FW_PORT_TYPE_BT_XFI:
451 case FW_PORT_TYPE_BT_XAUI:
452 SET_LMM(TP);
453 FW_CAPS_TO_LMM(SPEED_100M, 100baseT_Full);
454 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
455 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
456 break;
457
458 case FW_PORT_TYPE_KX4:
459 case FW_PORT_TYPE_KX:
460 SET_LMM(Backplane);
461 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
462 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
463 break;
464
465 case FW_PORT_TYPE_KR:
466 SET_LMM(Backplane);
467 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
468 break;
469
470 case FW_PORT_TYPE_BP_AP:
471 SET_LMM(Backplane);
472 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
473 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
474 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
475 break;
476
477 case FW_PORT_TYPE_BP4_AP:
478 SET_LMM(Backplane);
479 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
480 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
481 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
482 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
483 break;
484
485 case FW_PORT_TYPE_FIBER_XFI:
486 case FW_PORT_TYPE_FIBER_XAUI:
487 case FW_PORT_TYPE_SFP:
488 case FW_PORT_TYPE_QSFP_10G:
489 case FW_PORT_TYPE_QSA:
490 SET_LMM(FIBRE);
491 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
492 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
493 break;
494
495 case FW_PORT_TYPE_BP40_BA:
496 case FW_PORT_TYPE_QSFP:
497 SET_LMM(FIBRE);
498 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
499 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
500 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
501 break;
502
503 case FW_PORT_TYPE_CR_QSFP:
504 case FW_PORT_TYPE_SFP28:
505 SET_LMM(FIBRE);
506 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
507 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
508 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
509 break;
510
511 case FW_PORT_TYPE_KR_SFP28:
512 SET_LMM(Backplane);
513 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
514 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
515 FW_CAPS_TO_LMM(SPEED_25G, 25000baseKR_Full);
516 break;
517
518 case FW_PORT_TYPE_KR_XLAUI:
519 SET_LMM(Backplane);
520 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
521 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
522 FW_CAPS_TO_LMM(SPEED_40G, 40000baseKR4_Full);
523 break;
524
525 case FW_PORT_TYPE_CR2_QSFP:
526 SET_LMM(FIBRE);
527 FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
528 break;
529
530 case FW_PORT_TYPE_KR4_100G:
531 case FW_PORT_TYPE_CR4_QSFP:
532 SET_LMM(FIBRE);
533 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
534 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
535 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
536 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
537 FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);
538 FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
539 break;
540
541 default:
542 break;
543 }
544
545 if (fw_caps & FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M)) {
546 FW_CAPS_TO_LMM(FEC_RS, FEC_RS);
547 FW_CAPS_TO_LMM(FEC_BASER_RS, FEC_BASER);
548 } else {
549 SET_LMM(FEC_NONE);
550 }
551
552 FW_CAPS_TO_LMM(ANEG, Autoneg);
553 FW_CAPS_TO_LMM(802_3_PAUSE, Pause);
554 FW_CAPS_TO_LMM(802_3_ASM_DIR, Asym_Pause);
555
556 #undef FW_CAPS_TO_LMM
557 #undef SET_LMM
558 }
559
560
561
562
563
564
565
566
567
568 static unsigned int lmm_to_fw_caps(const unsigned long *link_mode_mask)
569 {
570 unsigned int fw_caps = 0;
571
572 #define LMM_TO_FW_CAPS(__lmm_name, __fw_name) \
573 do { \
574 if (test_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
575 link_mode_mask)) \
576 fw_caps |= FW_PORT_CAP32_ ## __fw_name; \
577 } while (0)
578
579 LMM_TO_FW_CAPS(100baseT_Full, SPEED_100M);
580 LMM_TO_FW_CAPS(1000baseT_Full, SPEED_1G);
581 LMM_TO_FW_CAPS(10000baseT_Full, SPEED_10G);
582 LMM_TO_FW_CAPS(40000baseSR4_Full, SPEED_40G);
583 LMM_TO_FW_CAPS(25000baseCR_Full, SPEED_25G);
584 LMM_TO_FW_CAPS(50000baseCR2_Full, SPEED_50G);
585 LMM_TO_FW_CAPS(100000baseCR4_Full, SPEED_100G);
586
587 #undef LMM_TO_FW_CAPS
588
589 return fw_caps;
590 }
591
592 static int get_link_ksettings(struct net_device *dev,
593 struct ethtool_link_ksettings *link_ksettings)
594 {
595 struct port_info *pi = netdev_priv(dev);
596 struct ethtool_link_settings *base = &link_ksettings->base;
597
598
599
600
601
602 if (!netif_running(dev))
603 (void)t4_update_port_info(pi);
604
605 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
606 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
607 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
608
609 base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type);
610
611 if (pi->mdio_addr >= 0) {
612 base->phy_address = pi->mdio_addr;
613 base->mdio_support = (pi->port_type == FW_PORT_TYPE_BT_SGMII
614 ? ETH_MDIO_SUPPORTS_C22
615 : ETH_MDIO_SUPPORTS_C45);
616 } else {
617 base->phy_address = 255;
618 base->mdio_support = 0;
619 }
620
621 fw_caps_to_lmm(pi->port_type, pi->link_cfg.pcaps,
622 link_ksettings->link_modes.supported);
623 fw_caps_to_lmm(pi->port_type,
624 t4_link_acaps(pi->adapter,
625 pi->lport,
626 &pi->link_cfg),
627 link_ksettings->link_modes.advertising);
628 fw_caps_to_lmm(pi->port_type, pi->link_cfg.lpacaps,
629 link_ksettings->link_modes.lp_advertising);
630
631 base->speed = (netif_carrier_ok(dev)
632 ? pi->link_cfg.speed
633 : SPEED_UNKNOWN);
634 base->duplex = DUPLEX_FULL;
635
636 base->autoneg = pi->link_cfg.autoneg;
637 if (pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)
638 ethtool_link_ksettings_add_link_mode(link_ksettings,
639 supported, Autoneg);
640 if (pi->link_cfg.autoneg)
641 ethtool_link_ksettings_add_link_mode(link_ksettings,
642 advertising, Autoneg);
643
644 return 0;
645 }
646
647 static int set_link_ksettings(struct net_device *dev,
648 const struct ethtool_link_ksettings *link_ksettings)
649 {
650 struct port_info *pi = netdev_priv(dev);
651 struct link_config *lc = &pi->link_cfg;
652 const struct ethtool_link_settings *base = &link_ksettings->base;
653 struct link_config old_lc;
654 unsigned int fw_caps;
655 int ret = 0;
656
657
658 if (base->duplex != DUPLEX_FULL)
659 return -EINVAL;
660
661 old_lc = *lc;
662 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) ||
663 base->autoneg == AUTONEG_DISABLE) {
664 fw_caps = speed_to_fw_caps(base->speed);
665
666
667 if (!(lc->pcaps & fw_caps))
668 return -EINVAL;
669
670 lc->speed_caps = fw_caps;
671 lc->acaps = fw_caps;
672 } else {
673 fw_caps =
674 lmm_to_fw_caps(link_ksettings->link_modes.advertising);
675 if (!(lc->pcaps & fw_caps))
676 return -EINVAL;
677 lc->speed_caps = 0;
678 lc->acaps = fw_caps | FW_PORT_CAP32_ANEG;
679 }
680 lc->autoneg = base->autoneg;
681
682
683
684
685 ret = t4_link_l1cfg(pi->adapter, pi->adapter->mbox, pi->tx_chan, lc);
686 if (ret)
687 *lc = old_lc;
688
689 return ret;
690 }
691
692
693 static inline unsigned int fwcap_to_eth_fec(unsigned int fw_fec)
694 {
695 unsigned int eth_fec = 0;
696
697 if (fw_fec & FW_PORT_CAP32_FEC_RS)
698 eth_fec |= ETHTOOL_FEC_RS;
699 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
700 eth_fec |= ETHTOOL_FEC_BASER;
701
702
703 if (!eth_fec)
704 eth_fec = ETHTOOL_FEC_OFF;
705
706 return eth_fec;
707 }
708
709
710 static inline unsigned int cc_to_eth_fec(unsigned int cc_fec)
711 {
712 unsigned int eth_fec = 0;
713
714 if (cc_fec & FEC_AUTO)
715 eth_fec |= ETHTOOL_FEC_AUTO;
716 if (cc_fec & FEC_RS)
717 eth_fec |= ETHTOOL_FEC_RS;
718 if (cc_fec & FEC_BASER_RS)
719 eth_fec |= ETHTOOL_FEC_BASER;
720
721
722 if (!eth_fec)
723 eth_fec = ETHTOOL_FEC_OFF;
724
725 return eth_fec;
726 }
727
728
729 static inline unsigned int eth_to_cc_fec(unsigned int eth_fec)
730 {
731 unsigned int cc_fec = 0;
732
733 if (eth_fec & ETHTOOL_FEC_OFF)
734 return cc_fec;
735
736 if (eth_fec & ETHTOOL_FEC_AUTO)
737 cc_fec |= FEC_AUTO;
738 if (eth_fec & ETHTOOL_FEC_RS)
739 cc_fec |= FEC_RS;
740 if (eth_fec & ETHTOOL_FEC_BASER)
741 cc_fec |= FEC_BASER_RS;
742
743 return cc_fec;
744 }
745
746 static int get_fecparam(struct net_device *dev, struct ethtool_fecparam *fec)
747 {
748 const struct port_info *pi = netdev_priv(dev);
749 const struct link_config *lc = &pi->link_cfg;
750
751
752
753
754
755 fec->fec = fwcap_to_eth_fec(lc->pcaps);
756 if (fec->fec != ETHTOOL_FEC_OFF)
757 fec->fec |= ETHTOOL_FEC_AUTO;
758
759
760
761
762 fec->active_fec = cc_to_eth_fec(lc->fec);
763
764 return 0;
765 }
766
767 static int set_fecparam(struct net_device *dev, struct ethtool_fecparam *fec)
768 {
769 struct port_info *pi = netdev_priv(dev);
770 struct link_config *lc = &pi->link_cfg;
771 struct link_config old_lc;
772 int ret;
773
774
775
776
777 old_lc = *lc;
778
779
780
781
782 lc->requested_fec = eth_to_cc_fec(fec->fec);
783 ret = t4_link_l1cfg(pi->adapter, pi->adapter->mbox,
784 pi->tx_chan, lc);
785 if (ret)
786 *lc = old_lc;
787 return ret;
788 }
789
790 static void get_pauseparam(struct net_device *dev,
791 struct ethtool_pauseparam *epause)
792 {
793 struct port_info *p = netdev_priv(dev);
794
795 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
796 epause->rx_pause = (p->link_cfg.advertised_fc & PAUSE_RX) != 0;
797 epause->tx_pause = (p->link_cfg.advertised_fc & PAUSE_TX) != 0;
798 }
799
800 static int set_pauseparam(struct net_device *dev,
801 struct ethtool_pauseparam *epause)
802 {
803 struct port_info *p = netdev_priv(dev);
804 struct link_config *lc = &p->link_cfg;
805
806 if (epause->autoneg == AUTONEG_DISABLE)
807 lc->requested_fc = 0;
808 else if (lc->pcaps & FW_PORT_CAP32_ANEG)
809 lc->requested_fc = PAUSE_AUTONEG;
810 else
811 return -EINVAL;
812
813 if (epause->rx_pause)
814 lc->requested_fc |= PAUSE_RX;
815 if (epause->tx_pause)
816 lc->requested_fc |= PAUSE_TX;
817 if (netif_running(dev))
818 return t4_link_l1cfg(p->adapter, p->adapter->mbox, p->tx_chan,
819 lc);
820 return 0;
821 }
822
823 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
824 {
825 const struct port_info *pi = netdev_priv(dev);
826 const struct sge *s = &pi->adapter->sge;
827
828 e->rx_max_pending = MAX_RX_BUFFERS;
829 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
830 e->rx_jumbo_max_pending = 0;
831 e->tx_max_pending = MAX_TXQ_ENTRIES;
832
833 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
834 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
835 e->rx_jumbo_pending = 0;
836 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
837 }
838
839 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
840 {
841 int i;
842 const struct port_info *pi = netdev_priv(dev);
843 struct adapter *adapter = pi->adapter;
844 struct sge *s = &adapter->sge;
845
846 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
847 e->tx_pending > MAX_TXQ_ENTRIES ||
848 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
849 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
850 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
851 return -EINVAL;
852
853 if (adapter->flags & CXGB4_FULL_INIT_DONE)
854 return -EBUSY;
855
856 for (i = 0; i < pi->nqsets; ++i) {
857 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
858 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
859 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
860 }
861 return 0;
862 }
863
864
865
866
867
868
869
870
871
872 static int set_rx_intr_params(struct net_device *dev,
873 unsigned int us, unsigned int cnt)
874 {
875 int i, err;
876 struct port_info *pi = netdev_priv(dev);
877 struct adapter *adap = pi->adapter;
878 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
879
880 for (i = 0; i < pi->nqsets; i++, q++) {
881 err = cxgb4_set_rspq_intr_params(&q->rspq, us, cnt);
882 if (err)
883 return err;
884 }
885 return 0;
886 }
887
888 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
889 {
890 int i;
891 struct port_info *pi = netdev_priv(dev);
892 struct adapter *adap = pi->adapter;
893 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
894
895 for (i = 0; i < pi->nqsets; i++, q++)
896 q->rspq.adaptive_rx = adaptive_rx;
897
898 return 0;
899 }
900
901 static int get_adaptive_rx_setting(struct net_device *dev)
902 {
903 struct port_info *pi = netdev_priv(dev);
904 struct adapter *adap = pi->adapter;
905 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
906
907 return q->rspq.adaptive_rx;
908 }
909
910
911
912
913 static int get_dbqtimer_tick(struct net_device *dev)
914 {
915 struct port_info *pi = netdev_priv(dev);
916 struct adapter *adap = pi->adapter;
917
918 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
919 return 0;
920
921 return adap->sge.dbqtimer_tick;
922 }
923
924
925
926
927 static int get_dbqtimer(struct net_device *dev)
928 {
929 struct port_info *pi = netdev_priv(dev);
930 struct adapter *adap = pi->adapter;
931 struct sge_eth_txq *txq;
932
933 txq = &adap->sge.ethtxq[pi->first_qset];
934
935 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
936 return 0;
937
938
939 return adap->sge.dbqtimer_val[txq->dbqtimerix];
940 }
941
942
943
944
945
946
947
948
949 static int set_dbqtimer_tick(struct net_device *dev, int usecs)
950 {
951 struct port_info *pi = netdev_priv(dev);
952 struct adapter *adap = pi->adapter;
953 struct sge *s = &adap->sge;
954 u32 param, val;
955 int ret;
956
957 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
958 return 0;
959
960
961 if (s->dbqtimer_tick == usecs)
962 return 0;
963
964
965 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
966 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
967 val = usecs;
968 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
969 if (ret)
970 return ret;
971 s->dbqtimer_tick = usecs;
972
973
974 ret = t4_read_sge_dbqtimers(adap, ARRAY_SIZE(s->dbqtimer_val),
975 s->dbqtimer_val);
976 return ret;
977 }
978
979
980
981
982
983 static int set_dbqtimer(struct net_device *dev, int usecs)
984 {
985 int qix, timerix, min_timerix, delta, min_delta;
986 struct port_info *pi = netdev_priv(dev);
987 struct adapter *adap = pi->adapter;
988 struct sge *s = &adap->sge;
989 struct sge_eth_txq *txq;
990 u32 param, val;
991 int ret;
992
993 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
994 return 0;
995
996
997
998
999 min_delta = INT_MAX;
1000 min_timerix = 0;
1001 for (timerix = 0; timerix < ARRAY_SIZE(s->dbqtimer_val); timerix++) {
1002 delta = s->dbqtimer_val[timerix] - usecs;
1003 if (delta < 0)
1004 delta = -delta;
1005 if (delta < min_delta) {
1006 min_delta = delta;
1007 min_timerix = timerix;
1008 }
1009 }
1010
1011
1012
1013
1014
1015 txq = &s->ethtxq[pi->first_qset];
1016 if (txq->dbqtimerix == min_timerix)
1017 return 0;
1018
1019 for (qix = 0; qix < pi->nqsets; qix++, txq++) {
1020 if (adap->flags & CXGB4_FULL_INIT_DONE) {
1021 param =
1022 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1023 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX) |
1024 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
1025 val = min_timerix;
1026 ret = t4_set_params(adap, adap->mbox, adap->pf, 0,
1027 1, ¶m, &val);
1028 if (ret)
1029 return ret;
1030 }
1031 txq->dbqtimerix = min_timerix;
1032 }
1033 return 0;
1034 }
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046 static int set_dbqtimer_tickval(struct net_device *dev,
1047 int tick_usecs, int timer_usecs)
1048 {
1049 struct port_info *pi = netdev_priv(dev);
1050 struct adapter *adap = pi->adapter;
1051 int timer[MAX_NPORTS];
1052 unsigned int port;
1053 int ret;
1054
1055
1056
1057
1058 for_each_port(adap, port)
1059 if (port == pi->port_id)
1060 timer[port] = timer_usecs;
1061 else
1062 timer[port] = get_dbqtimer(adap->port[port]);
1063
1064
1065 ret = set_dbqtimer_tick(dev, tick_usecs);
1066 if (ret)
1067 return ret;
1068
1069
1070 for_each_port(adap, port) {
1071 ret = set_dbqtimer(adap->port[port], timer[port]);
1072 if (ret)
1073 return ret;
1074 }
1075
1076 return 0;
1077 }
1078
1079 static int set_coalesce(struct net_device *dev,
1080 struct ethtool_coalesce *coalesce)
1081 {
1082 int ret;
1083
1084 set_adaptive_rx_setting(dev, coalesce->use_adaptive_rx_coalesce);
1085
1086 ret = set_rx_intr_params(dev, coalesce->rx_coalesce_usecs,
1087 coalesce->rx_max_coalesced_frames);
1088 if (ret)
1089 return ret;
1090
1091 return set_dbqtimer_tickval(dev,
1092 coalesce->tx_coalesce_usecs_irq,
1093 coalesce->tx_coalesce_usecs);
1094 }
1095
1096 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1097 {
1098 const struct port_info *pi = netdev_priv(dev);
1099 const struct adapter *adap = pi->adapter;
1100 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
1101
1102 c->rx_coalesce_usecs = qtimer_val(adap, rq);
1103 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN_F) ?
1104 adap->sge.counter_val[rq->pktcnt_idx] : 0;
1105 c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
1106 c->tx_coalesce_usecs_irq = get_dbqtimer_tick(dev);
1107 c->tx_coalesce_usecs = get_dbqtimer(dev);
1108 return 0;
1109 }
1110
1111
1112
1113 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1114 {
1115 int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1116
1117 if (vaddr >= 0)
1118 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
1119 return vaddr < 0 ? vaddr : 0;
1120 }
1121
1122 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1123 {
1124 int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1125
1126 if (vaddr >= 0)
1127 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
1128 return vaddr < 0 ? vaddr : 0;
1129 }
1130
1131 #define EEPROM_MAGIC 0x38E2F10C
1132
1133 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1134 u8 *data)
1135 {
1136 int i, err = 0;
1137 struct adapter *adapter = netdev2adap(dev);
1138 u8 *buf = kvzalloc(EEPROMSIZE, GFP_KERNEL);
1139
1140 if (!buf)
1141 return -ENOMEM;
1142
1143 e->magic = EEPROM_MAGIC;
1144 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
1145 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1146
1147 if (!err)
1148 memcpy(data, buf + e->offset, e->len);
1149 kvfree(buf);
1150 return err;
1151 }
1152
1153 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1154 u8 *data)
1155 {
1156 u8 *buf;
1157 int err = 0;
1158 u32 aligned_offset, aligned_len, *p;
1159 struct adapter *adapter = netdev2adap(dev);
1160
1161 if (eeprom->magic != EEPROM_MAGIC)
1162 return -EINVAL;
1163
1164 aligned_offset = eeprom->offset & ~3;
1165 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1166
1167 if (adapter->pf > 0) {
1168 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1169
1170 if (aligned_offset < start ||
1171 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1172 return -EPERM;
1173 }
1174
1175 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1176
1177
1178 buf = kvzalloc(aligned_len, GFP_KERNEL);
1179 if (!buf)
1180 return -ENOMEM;
1181 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1182 if (!err && aligned_len > 4)
1183 err = eeprom_rd_phys(adapter,
1184 aligned_offset + aligned_len - 4,
1185 (u32 *)&buf[aligned_len - 4]);
1186 if (err)
1187 goto out;
1188 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1189 } else {
1190 buf = data;
1191 }
1192
1193 err = t4_seeprom_wp(adapter, false);
1194 if (err)
1195 goto out;
1196
1197 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1198 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1199 aligned_offset += 4;
1200 }
1201
1202 if (!err)
1203 err = t4_seeprom_wp(adapter, true);
1204 out:
1205 if (buf != data)
1206 kvfree(buf);
1207 return err;
1208 }
1209
1210 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
1211 {
1212 int ret;
1213 const struct firmware *fw;
1214 struct adapter *adap = netdev2adap(netdev);
1215 unsigned int mbox = PCIE_FW_MASTER_M + 1;
1216 u32 pcie_fw;
1217 unsigned int master;
1218 u8 master_vld = 0;
1219
1220 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
1221 master = PCIE_FW_MASTER_G(pcie_fw);
1222 if (pcie_fw & PCIE_FW_MASTER_VLD_F)
1223 master_vld = 1;
1224
1225 if (master_vld && (master != adap->pf)) {
1226 dev_warn(adap->pdev_dev,
1227 "cxgb4 driver needs to be loaded as MASTER to support FW flash\n");
1228 return -EOPNOTSUPP;
1229 }
1230
1231 ef->data[sizeof(ef->data) - 1] = '\0';
1232 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
1233 if (ret < 0)
1234 return ret;
1235
1236
1237
1238
1239
1240
1241 if (adap->flags & CXGB4_FULL_INIT_DONE)
1242 mbox = adap->mbox;
1243
1244 ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
1245 release_firmware(fw);
1246 if (!ret)
1247 dev_info(adap->pdev_dev,
1248 "loaded firmware %s, reload cxgb4 driver\n", ef->data);
1249 return ret;
1250 }
1251
1252 static int get_ts_info(struct net_device *dev, struct ethtool_ts_info *ts_info)
1253 {
1254 struct port_info *pi = netdev_priv(dev);
1255 struct adapter *adapter = pi->adapter;
1256
1257 ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1258 SOF_TIMESTAMPING_RX_SOFTWARE |
1259 SOF_TIMESTAMPING_SOFTWARE;
1260
1261 ts_info->so_timestamping |= SOF_TIMESTAMPING_RX_HARDWARE |
1262 SOF_TIMESTAMPING_TX_HARDWARE |
1263 SOF_TIMESTAMPING_RAW_HARDWARE;
1264
1265 ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1266 (1 << HWTSTAMP_TX_ON);
1267
1268 ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1269 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1270 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1271 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1272 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1273 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
1274
1275 if (adapter->ptp_clock)
1276 ts_info->phc_index = ptp_clock_index(adapter->ptp_clock);
1277 else
1278 ts_info->phc_index = -1;
1279
1280 return 0;
1281 }
1282
1283 static u32 get_rss_table_size(struct net_device *dev)
1284 {
1285 const struct port_info *pi = netdev_priv(dev);
1286
1287 return pi->rss_size;
1288 }
1289
1290 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key, u8 *hfunc)
1291 {
1292 const struct port_info *pi = netdev_priv(dev);
1293 unsigned int n = pi->rss_size;
1294
1295 if (hfunc)
1296 *hfunc = ETH_RSS_HASH_TOP;
1297 if (!p)
1298 return 0;
1299 while (n--)
1300 p[n] = pi->rss[n];
1301 return 0;
1302 }
1303
1304 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,
1305 const u8 hfunc)
1306 {
1307 unsigned int i;
1308 struct port_info *pi = netdev_priv(dev);
1309
1310
1311
1312
1313 if (key ||
1314 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
1315 return -EOPNOTSUPP;
1316 if (!p)
1317 return 0;
1318
1319
1320 if (pi->adapter->flags & CXGB4_FULL_INIT_DONE) {
1321 for (i = 0; i < pi->rss_size; i++)
1322 pi->rss[i] = p[i];
1323
1324 return cxgb4_write_rss(pi, pi->rss);
1325 }
1326
1327 return -EPERM;
1328 }
1329
1330 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1331 u32 *rules)
1332 {
1333 const struct port_info *pi = netdev_priv(dev);
1334
1335 switch (info->cmd) {
1336 case ETHTOOL_GRXFH: {
1337 unsigned int v = pi->rss_mode;
1338
1339 info->data = 0;
1340 switch (info->flow_type) {
1341 case TCP_V4_FLOW:
1342 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
1343 info->data = RXH_IP_SRC | RXH_IP_DST |
1344 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1345 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1346 info->data = RXH_IP_SRC | RXH_IP_DST;
1347 break;
1348 case UDP_V4_FLOW:
1349 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
1350 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
1351 info->data = RXH_IP_SRC | RXH_IP_DST |
1352 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1353 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1354 info->data = RXH_IP_SRC | RXH_IP_DST;
1355 break;
1356 case SCTP_V4_FLOW:
1357 case AH_ESP_V4_FLOW:
1358 case IPV4_FLOW:
1359 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1360 info->data = RXH_IP_SRC | RXH_IP_DST;
1361 break;
1362 case TCP_V6_FLOW:
1363 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
1364 info->data = RXH_IP_SRC | RXH_IP_DST |
1365 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1366 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1367 info->data = RXH_IP_SRC | RXH_IP_DST;
1368 break;
1369 case UDP_V6_FLOW:
1370 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
1371 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
1372 info->data = RXH_IP_SRC | RXH_IP_DST |
1373 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1374 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1375 info->data = RXH_IP_SRC | RXH_IP_DST;
1376 break;
1377 case SCTP_V6_FLOW:
1378 case AH_ESP_V6_FLOW:
1379 case IPV6_FLOW:
1380 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1381 info->data = RXH_IP_SRC | RXH_IP_DST;
1382 break;
1383 }
1384 return 0;
1385 }
1386 case ETHTOOL_GRXRINGS:
1387 info->data = pi->nqsets;
1388 return 0;
1389 }
1390 return -EOPNOTSUPP;
1391 }
1392
1393 static int set_dump(struct net_device *dev, struct ethtool_dump *eth_dump)
1394 {
1395 struct adapter *adapter = netdev2adap(dev);
1396 u32 len = 0;
1397
1398 len = sizeof(struct cudbg_hdr) +
1399 sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY;
1400 len += cxgb4_get_dump_length(adapter, eth_dump->flag);
1401
1402 adapter->eth_dump.flag = eth_dump->flag;
1403 adapter->eth_dump.len = len;
1404 return 0;
1405 }
1406
1407 static int get_dump_flag(struct net_device *dev, struct ethtool_dump *eth_dump)
1408 {
1409 struct adapter *adapter = netdev2adap(dev);
1410
1411 eth_dump->flag = adapter->eth_dump.flag;
1412 eth_dump->len = adapter->eth_dump.len;
1413 eth_dump->version = adapter->eth_dump.version;
1414 return 0;
1415 }
1416
1417 static int get_dump_data(struct net_device *dev, struct ethtool_dump *eth_dump,
1418 void *buf)
1419 {
1420 struct adapter *adapter = netdev2adap(dev);
1421 u32 len = 0;
1422 int ret = 0;
1423
1424 if (adapter->eth_dump.flag == CXGB4_ETH_DUMP_NONE)
1425 return -ENOENT;
1426
1427 len = sizeof(struct cudbg_hdr) +
1428 sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY;
1429 len += cxgb4_get_dump_length(adapter, adapter->eth_dump.flag);
1430 if (eth_dump->len < len)
1431 return -ENOMEM;
1432
1433 ret = cxgb4_cudbg_collect(adapter, buf, &len, adapter->eth_dump.flag);
1434 if (ret)
1435 return ret;
1436
1437 eth_dump->flag = adapter->eth_dump.flag;
1438 eth_dump->len = len;
1439 eth_dump->version = adapter->eth_dump.version;
1440 return 0;
1441 }
1442
1443 static int cxgb4_get_module_info(struct net_device *dev,
1444 struct ethtool_modinfo *modinfo)
1445 {
1446 struct port_info *pi = netdev_priv(dev);
1447 u8 sff8472_comp, sff_diag_type, sff_rev;
1448 struct adapter *adapter = pi->adapter;
1449 int ret;
1450
1451 if (!t4_is_inserted_mod_type(pi->mod_type))
1452 return -EINVAL;
1453
1454 switch (pi->port_type) {
1455 case FW_PORT_TYPE_SFP:
1456 case FW_PORT_TYPE_QSA:
1457 case FW_PORT_TYPE_SFP28:
1458 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
1459 I2C_DEV_ADDR_A0, SFF_8472_COMP_ADDR,
1460 SFF_8472_COMP_LEN, &sff8472_comp);
1461 if (ret)
1462 return ret;
1463 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
1464 I2C_DEV_ADDR_A0, SFP_DIAG_TYPE_ADDR,
1465 SFP_DIAG_TYPE_LEN, &sff_diag_type);
1466 if (ret)
1467 return ret;
1468
1469 if (!sff8472_comp || (sff_diag_type & 4)) {
1470 modinfo->type = ETH_MODULE_SFF_8079;
1471 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1472 } else {
1473 modinfo->type = ETH_MODULE_SFF_8472;
1474 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1475 }
1476 break;
1477
1478 case FW_PORT_TYPE_QSFP:
1479 case FW_PORT_TYPE_QSFP_10G:
1480 case FW_PORT_TYPE_CR_QSFP:
1481 case FW_PORT_TYPE_CR2_QSFP:
1482 case FW_PORT_TYPE_CR4_QSFP:
1483 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
1484 I2C_DEV_ADDR_A0, SFF_REV_ADDR,
1485 SFF_REV_LEN, &sff_rev);
1486
1487
1488
1489 if (ret)
1490 return ret;
1491 if (sff_rev >= 0x3) {
1492 modinfo->type = ETH_MODULE_SFF_8636;
1493 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1494 } else {
1495 modinfo->type = ETH_MODULE_SFF_8436;
1496 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1497 }
1498 break;
1499
1500 default:
1501 return -EINVAL;
1502 }
1503
1504 return 0;
1505 }
1506
1507 static int cxgb4_get_module_eeprom(struct net_device *dev,
1508 struct ethtool_eeprom *eprom, u8 *data)
1509 {
1510 int ret = 0, offset = eprom->offset, len = eprom->len;
1511 struct port_info *pi = netdev_priv(dev);
1512 struct adapter *adapter = pi->adapter;
1513
1514 memset(data, 0, eprom->len);
1515 if (offset + len <= I2C_PAGE_SIZE)
1516 return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
1517 I2C_DEV_ADDR_A0, offset, len, data);
1518
1519
1520 if (offset <= I2C_PAGE_SIZE) {
1521
1522 len = I2C_PAGE_SIZE - offset;
1523 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
1524 I2C_DEV_ADDR_A0, offset, len, data);
1525 if (ret)
1526 return ret;
1527 offset = I2C_PAGE_SIZE;
1528
1529
1530
1531 len = eprom->len - len;
1532 }
1533
1534 return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan, I2C_DEV_ADDR_A2,
1535 offset, len, &data[eprom->len - len]);
1536 }
1537
1538 static u32 cxgb4_get_priv_flags(struct net_device *netdev)
1539 {
1540 struct port_info *pi = netdev_priv(netdev);
1541 struct adapter *adapter = pi->adapter;
1542
1543 return (adapter->eth_flags | pi->eth_flags);
1544 }
1545
1546
1547
1548
1549
1550
1551
1552 static inline void set_flags(u32 *cur_flags, u32 new_flags, u32 flags)
1553 {
1554 *cur_flags = (*cur_flags & ~flags) | (new_flags & flags);
1555 }
1556
1557 static int cxgb4_set_priv_flags(struct net_device *netdev, u32 flags)
1558 {
1559 struct port_info *pi = netdev_priv(netdev);
1560 struct adapter *adapter = pi->adapter;
1561
1562 set_flags(&adapter->eth_flags, flags, PRIV_FLAGS_ADAP);
1563 set_flags(&pi->eth_flags, flags, PRIV_FLAGS_PORT);
1564
1565 return 0;
1566 }
1567
1568 static const struct ethtool_ops cxgb_ethtool_ops = {
1569 .get_link_ksettings = get_link_ksettings,
1570 .set_link_ksettings = set_link_ksettings,
1571 .get_fecparam = get_fecparam,
1572 .set_fecparam = set_fecparam,
1573 .get_drvinfo = get_drvinfo,
1574 .get_msglevel = get_msglevel,
1575 .set_msglevel = set_msglevel,
1576 .get_ringparam = get_sge_param,
1577 .set_ringparam = set_sge_param,
1578 .get_coalesce = get_coalesce,
1579 .set_coalesce = set_coalesce,
1580 .get_eeprom_len = get_eeprom_len,
1581 .get_eeprom = get_eeprom,
1582 .set_eeprom = set_eeprom,
1583 .get_pauseparam = get_pauseparam,
1584 .set_pauseparam = set_pauseparam,
1585 .get_link = ethtool_op_get_link,
1586 .get_strings = get_strings,
1587 .set_phys_id = identify_port,
1588 .nway_reset = restart_autoneg,
1589 .get_sset_count = get_sset_count,
1590 .get_ethtool_stats = get_stats,
1591 .get_regs_len = get_regs_len,
1592 .get_regs = get_regs,
1593 .get_rxnfc = get_rxnfc,
1594 .get_rxfh_indir_size = get_rss_table_size,
1595 .get_rxfh = get_rss_table,
1596 .set_rxfh = set_rss_table,
1597 .flash_device = set_flash,
1598 .get_ts_info = get_ts_info,
1599 .set_dump = set_dump,
1600 .get_dump_flag = get_dump_flag,
1601 .get_dump_data = get_dump_data,
1602 .get_module_info = cxgb4_get_module_info,
1603 .get_module_eeprom = cxgb4_get_module_eeprom,
1604 .get_priv_flags = cxgb4_get_priv_flags,
1605 .set_priv_flags = cxgb4_set_priv_flags,
1606 };
1607
1608 void cxgb4_set_ethtool_ops(struct net_device *netdev)
1609 {
1610 netdev->ethtool_ops = &cxgb_ethtool_ops;
1611 }