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35 #ifndef __T4_REGS_H
36 #define __T4_REGS_H
37
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47
48 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
49 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
50
51 #define MYPORT_BASE 0x1c000
52 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
53
54 #define PORT0_BASE 0x20000
55 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
56
57 #define PORT_STRIDE 0x2000
58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
60
61 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
62 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
63
64 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
65 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
66 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
67 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
68
69 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
70
71 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
72 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
73
74 #define SGE_PF_KDOORBELL_A 0x0
75
76 #define QID_S 15
77 #define QID_V(x) ((x) << QID_S)
78
79 #define DBPRIO_S 14
80 #define DBPRIO_V(x) ((x) << DBPRIO_S)
81 #define DBPRIO_F DBPRIO_V(1U)
82
83 #define PIDX_S 0
84 #define PIDX_V(x) ((x) << PIDX_S)
85
86 #define SGE_VF_KDOORBELL_A 0x0
87
88 #define DBTYPE_S 13
89 #define DBTYPE_V(x) ((x) << DBTYPE_S)
90 #define DBTYPE_F DBTYPE_V(1U)
91
92 #define PIDX_T5_S 0
93 #define PIDX_T5_M 0x1fffU
94 #define PIDX_T5_V(x) ((x) << PIDX_T5_S)
95 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
96
97 #define SGE_PF_GTS_A 0x4
98
99 #define INGRESSQID_S 16
100 #define INGRESSQID_V(x) ((x) << INGRESSQID_S)
101
102 #define TIMERREG_S 13
103 #define TIMERREG_V(x) ((x) << TIMERREG_S)
104
105 #define SEINTARM_S 12
106 #define SEINTARM_V(x) ((x) << SEINTARM_S)
107
108 #define CIDXINC_S 0
109 #define CIDXINC_M 0xfffU
110 #define CIDXINC_V(x) ((x) << CIDXINC_S)
111
112 #define SGE_CONTROL_A 0x1008
113 #define SGE_CONTROL2_A 0x1124
114
115 #define RXPKTCPLMODE_S 18
116 #define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
117 #define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
118
119 #define EGRSTATUSPAGESIZE_S 17
120 #define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
121 #define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
122
123 #define PKTSHIFT_S 10
124 #define PKTSHIFT_M 0x7U
125 #define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
126 #define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
127
128 #define INGPCIEBOUNDARY_S 7
129 #define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
130
131 #define INGPADBOUNDARY_S 4
132 #define INGPADBOUNDARY_M 0x7U
133 #define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
134 #define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
135
136 #define EGRPCIEBOUNDARY_S 1
137 #define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
138
139 #define INGPACKBOUNDARY_S 16
140 #define INGPACKBOUNDARY_M 0x7U
141 #define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
142 #define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
143 & INGPACKBOUNDARY_M)
144
145 #define VFIFO_ENABLE_S 10
146 #define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)
147 #define VFIFO_ENABLE_F VFIFO_ENABLE_V(1U)
148
149 #define SGE_DBVFIFO_BADDR_A 0x1138
150
151 #define DBVFIFO_SIZE_S 6
152 #define DBVFIFO_SIZE_M 0xfffU
153 #define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)
154
155 #define T6_DBVFIFO_SIZE_S 0
156 #define T6_DBVFIFO_SIZE_M 0x1fffU
157 #define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
158
159 #define SGE_CTXT_CMD_A 0x11fc
160
161 #define BUSY_S 31
162 #define BUSY_V(x) ((x) << BUSY_S)
163 #define BUSY_F BUSY_V(1U)
164
165 #define CTXTTYPE_S 24
166 #define CTXTTYPE_M 0x3U
167 #define CTXTTYPE_V(x) ((x) << CTXTTYPE_S)
168
169 #define CTXTQID_S 0
170 #define CTXTQID_M 0x1ffffU
171 #define CTXTQID_V(x) ((x) << CTXTQID_S)
172
173 #define SGE_CTXT_DATA0_A 0x1200
174 #define SGE_CTXT_DATA5_A 0x1214
175
176 #define GLOBALENABLE_S 0
177 #define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
178 #define GLOBALENABLE_F GLOBALENABLE_V(1U)
179
180 #define SGE_HOST_PAGE_SIZE_A 0x100c
181
182 #define HOSTPAGESIZEPF7_S 28
183 #define HOSTPAGESIZEPF7_M 0xfU
184 #define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
185 #define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
186
187 #define HOSTPAGESIZEPF6_S 24
188 #define HOSTPAGESIZEPF6_M 0xfU
189 #define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
190 #define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
191
192 #define HOSTPAGESIZEPF5_S 20
193 #define HOSTPAGESIZEPF5_M 0xfU
194 #define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
195 #define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
196
197 #define HOSTPAGESIZEPF4_S 16
198 #define HOSTPAGESIZEPF4_M 0xfU
199 #define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
200 #define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
201
202 #define HOSTPAGESIZEPF3_S 12
203 #define HOSTPAGESIZEPF3_M 0xfU
204 #define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
205 #define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
206
207 #define HOSTPAGESIZEPF2_S 8
208 #define HOSTPAGESIZEPF2_M 0xfU
209 #define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
210 #define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
211
212 #define HOSTPAGESIZEPF1_S 4
213 #define HOSTPAGESIZEPF1_M 0xfU
214 #define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
215 #define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
216
217 #define HOSTPAGESIZEPF0_S 0
218 #define HOSTPAGESIZEPF0_M 0xfU
219 #define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
220 #define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
221
222 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
223 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
224
225 #define QUEUESPERPAGEPF1_S 4
226
227 #define QUEUESPERPAGEPF0_S 0
228 #define QUEUESPERPAGEPF0_M 0xfU
229 #define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
230 #define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
231
232 #define SGE_INT_CAUSE1_A 0x1024
233 #define SGE_INT_CAUSE2_A 0x1030
234 #define SGE_INT_CAUSE3_A 0x103c
235
236 #define ERR_FLM_DBP_S 31
237 #define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
238 #define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)
239
240 #define ERR_FLM_IDMA1_S 30
241 #define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
242 #define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)
243
244 #define ERR_FLM_IDMA0_S 29
245 #define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
246 #define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)
247
248 #define ERR_FLM_HINT_S 28
249 #define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
250 #define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)
251
252 #define ERR_PCIE_ERROR3_S 27
253 #define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
254 #define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)
255
256 #define ERR_PCIE_ERROR2_S 26
257 #define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
258 #define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)
259
260 #define ERR_PCIE_ERROR1_S 25
261 #define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
262 #define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)
263
264 #define ERR_PCIE_ERROR0_S 24
265 #define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
266 #define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
267
268 #define ERR_CPL_EXCEED_IQE_SIZE_S 22
269 #define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
270 #define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
271
272 #define ERR_INVALID_CIDX_INC_S 21
273 #define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
274 #define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
275
276 #define ERR_CPL_OPCODE_0_S 19
277 #define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
278 #define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
279
280 #define ERR_DROPPED_DB_S 18
281 #define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
282 #define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)
283
284 #define ERR_DATA_CPL_ON_HIGH_QID1_S 17
285 #define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
286 #define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
287
288 #define ERR_DATA_CPL_ON_HIGH_QID0_S 16
289 #define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
290 #define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
291
292 #define ERR_BAD_DB_PIDX3_S 15
293 #define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
294 #define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)
295
296 #define ERR_BAD_DB_PIDX2_S 14
297 #define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
298 #define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)
299
300 #define ERR_BAD_DB_PIDX1_S 13
301 #define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
302 #define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)
303
304 #define ERR_BAD_DB_PIDX0_S 12
305 #define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
306 #define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
307
308 #define ERR_ING_CTXT_PRIO_S 10
309 #define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
310 #define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
311
312 #define ERR_EGR_CTXT_PRIO_S 9
313 #define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
314 #define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)
315
316 #define DBFIFO_HP_INT_S 8
317 #define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
318 #define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)
319
320 #define DBFIFO_LP_INT_S 7
321 #define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
322 #define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
323
324 #define INGRESS_SIZE_ERR_S 5
325 #define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
326 #define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
327
328 #define EGRESS_SIZE_ERR_S 4
329 #define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
330 #define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
331
332 #define SGE_INT_ENABLE3_A 0x1040
333 #define SGE_FL_BUFFER_SIZE0_A 0x1044
334 #define SGE_FL_BUFFER_SIZE1_A 0x1048
335 #define SGE_FL_BUFFER_SIZE2_A 0x104c
336 #define SGE_FL_BUFFER_SIZE3_A 0x1050
337 #define SGE_FL_BUFFER_SIZE4_A 0x1054
338 #define SGE_FL_BUFFER_SIZE5_A 0x1058
339 #define SGE_FL_BUFFER_SIZE6_A 0x105c
340 #define SGE_FL_BUFFER_SIZE7_A 0x1060
341 #define SGE_FL_BUFFER_SIZE8_A 0x1064
342
343 #define SGE_IMSG_CTXT_BADDR_A 0x1088
344 #define SGE_FLM_CACHE_BADDR_A 0x108c
345 #define SGE_FLM_CFG_A 0x1090
346
347 #define NOHDR_S 18
348 #define NOHDR_V(x) ((x) << NOHDR_S)
349 #define NOHDR_F NOHDR_V(1U)
350
351 #define HDRSTARTFLQ_S 11
352 #define HDRSTARTFLQ_M 0x7U
353 #define HDRSTARTFLQ_G(x) (((x) >> HDRSTARTFLQ_S) & HDRSTARTFLQ_M)
354
355 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
356
357 #define THRESHOLD_0_S 24
358 #define THRESHOLD_0_M 0x3fU
359 #define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
360 #define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
361
362 #define THRESHOLD_1_S 16
363 #define THRESHOLD_1_M 0x3fU
364 #define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
365 #define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
366
367 #define THRESHOLD_2_S 8
368 #define THRESHOLD_2_M 0x3fU
369 #define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
370 #define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
371
372 #define THRESHOLD_3_S 0
373 #define THRESHOLD_3_M 0x3fU
374 #define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
375 #define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
376
377 #define SGE_CONM_CTRL_A 0x1094
378
379 #define EGRTHRESHOLD_S 8
380 #define EGRTHRESHOLD_M 0x3fU
381 #define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
382 #define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
383
384 #define EGRTHRESHOLDPACKING_S 14
385 #define EGRTHRESHOLDPACKING_M 0x3fU
386 #define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
387 #define EGRTHRESHOLDPACKING_G(x) \
388 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
389
390 #define T6_EGRTHRESHOLDPACKING_S 16
391 #define T6_EGRTHRESHOLDPACKING_M 0xffU
392 #define T6_EGRTHRESHOLDPACKING_G(x) \
393 (((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)
394
395 #define SGE_TIMESTAMP_LO_A 0x1098
396 #define SGE_TIMESTAMP_HI_A 0x109c
397
398 #define TSOP_S 28
399 #define TSOP_M 0x3U
400 #define TSOP_V(x) ((x) << TSOP_S)
401 #define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
402
403 #define TSVAL_S 0
404 #define TSVAL_M 0xfffffffU
405 #define TSVAL_V(x) ((x) << TSVAL_S)
406 #define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
407
408 #define SGE_DBFIFO_STATUS_A 0x10a4
409 #define SGE_DBVFIFO_SIZE_A 0x113c
410
411 #define HP_INT_THRESH_S 28
412 #define HP_INT_THRESH_M 0xfU
413 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
414
415 #define LP_INT_THRESH_S 12
416 #define LP_INT_THRESH_M 0xfU
417 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
418
419 #define SGE_DOORBELL_CONTROL_A 0x10a8
420
421 #define NOCOALESCE_S 26
422 #define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
423 #define NOCOALESCE_F NOCOALESCE_V(1U)
424
425 #define ENABLE_DROP_S 13
426 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
427 #define ENABLE_DROP_F ENABLE_DROP_V(1U)
428
429 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
430
431 #define TIMERVALUE0_S 16
432 #define TIMERVALUE0_M 0xffffU
433 #define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
434 #define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
435
436 #define TIMERVALUE1_S 0
437 #define TIMERVALUE1_M 0xffffU
438 #define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
439 #define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
440
441 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
442
443 #define TIMERVALUE2_S 16
444 #define TIMERVALUE2_M 0xffffU
445 #define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
446 #define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
447
448 #define TIMERVALUE3_S 0
449 #define TIMERVALUE3_M 0xffffU
450 #define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
451 #define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
452
453 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
454
455 #define TIMERVALUE4_S 16
456 #define TIMERVALUE4_M 0xffffU
457 #define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
458 #define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
459
460 #define TIMERVALUE5_S 0
461 #define TIMERVALUE5_M 0xffffU
462 #define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
463 #define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
464
465 #define SGE_DEBUG_INDEX_A 0x10cc
466 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
467 #define SGE_DEBUG_DATA_LOW_A 0x10d4
468
469 #define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
470 #define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
471 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
472
473 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
474 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
475
476 #define SGE_ERROR_STATS_A 0x1100
477
478 #define UNCAPTURED_ERROR_S 18
479 #define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
480 #define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U)
481
482 #define ERROR_QID_VALID_S 17
483 #define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
484 #define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U)
485
486 #define ERROR_QID_S 0
487 #define ERROR_QID_M 0x1ffffU
488 #define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
489
490 #define HP_INT_THRESH_S 28
491 #define HP_INT_THRESH_M 0xfU
492 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
493
494 #define HP_COUNT_S 16
495 #define HP_COUNT_M 0x7ffU
496 #define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
497
498 #define LP_INT_THRESH_S 12
499 #define LP_INT_THRESH_M 0xfU
500 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
501
502 #define LP_COUNT_S 0
503 #define LP_COUNT_M 0x7ffU
504 #define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
505
506 #define LP_INT_THRESH_T5_S 18
507 #define LP_INT_THRESH_T5_M 0xfffU
508 #define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
509
510 #define LP_COUNT_T5_S 0
511 #define LP_COUNT_T5_M 0x3ffffU
512 #define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
513
514 #define SGE_DOORBELL_CONTROL_A 0x10a8
515
516 #define SGE_STAT_TOTAL_A 0x10e4
517 #define SGE_STAT_MATCH_A 0x10e8
518 #define SGE_STAT_CFG_A 0x10ec
519
520 #define STATMODE_S 2
521 #define STATMODE_V(x) ((x) << STATMODE_S)
522
523 #define STATSOURCE_T5_S 9
524 #define STATSOURCE_T5_M 0xfU
525 #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
526 #define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)
527
528 #define T6_STATMODE_S 0
529 #define T6_STATMODE_V(x) ((x) << T6_STATMODE_S)
530
531 #define SGE_DBFIFO_STATUS2_A 0x1118
532
533 #define HP_INT_THRESH_T5_S 10
534 #define HP_INT_THRESH_T5_M 0xfU
535 #define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
536
537 #define HP_COUNT_T5_S 0
538 #define HP_COUNT_T5_M 0x3ffU
539 #define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
540
541 #define ENABLE_DROP_S 13
542 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
543 #define ENABLE_DROP_F ENABLE_DROP_V(1U)
544
545 #define DROPPED_DB_S 0
546 #define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
547 #define DROPPED_DB_F DROPPED_DB_V(1U)
548
549 #define SGE_CTXT_CMD_A 0x11fc
550 #define SGE_DBQ_CTXT_BADDR_A 0x1084
551
552
553 #define PCIE_PF_CFG_A 0x40
554
555 #define AIVEC_S 4
556 #define AIVEC_M 0x3ffU
557 #define AIVEC_V(x) ((x) << AIVEC_S)
558
559 #define PCIE_PF_CLI_A 0x44
560 #define PCIE_INT_CAUSE_A 0x3004
561
562 #define UNXSPLCPLERR_S 29
563 #define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
564 #define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
565
566 #define PCIEPINT_S 28
567 #define PCIEPINT_V(x) ((x) << PCIEPINT_S)
568 #define PCIEPINT_F PCIEPINT_V(1U)
569
570 #define PCIESINT_S 27
571 #define PCIESINT_V(x) ((x) << PCIESINT_S)
572 #define PCIESINT_F PCIESINT_V(1U)
573
574 #define RPLPERR_S 26
575 #define RPLPERR_V(x) ((x) << RPLPERR_S)
576 #define RPLPERR_F RPLPERR_V(1U)
577
578 #define RXWRPERR_S 25
579 #define RXWRPERR_V(x) ((x) << RXWRPERR_S)
580 #define RXWRPERR_F RXWRPERR_V(1U)
581
582 #define RXCPLPERR_S 24
583 #define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
584 #define RXCPLPERR_F RXCPLPERR_V(1U)
585
586 #define PIOTAGPERR_S 23
587 #define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
588 #define PIOTAGPERR_F PIOTAGPERR_V(1U)
589
590 #define MATAGPERR_S 22
591 #define MATAGPERR_V(x) ((x) << MATAGPERR_S)
592 #define MATAGPERR_F MATAGPERR_V(1U)
593
594 #define INTXCLRPERR_S 21
595 #define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
596 #define INTXCLRPERR_F INTXCLRPERR_V(1U)
597
598 #define FIDPERR_S 20
599 #define FIDPERR_V(x) ((x) << FIDPERR_S)
600 #define FIDPERR_F FIDPERR_V(1U)
601
602 #define CFGSNPPERR_S 19
603 #define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
604 #define CFGSNPPERR_F CFGSNPPERR_V(1U)
605
606 #define HRSPPERR_S 18
607 #define HRSPPERR_V(x) ((x) << HRSPPERR_S)
608 #define HRSPPERR_F HRSPPERR_V(1U)
609
610 #define HREQPERR_S 17
611 #define HREQPERR_V(x) ((x) << HREQPERR_S)
612 #define HREQPERR_F HREQPERR_V(1U)
613
614 #define HCNTPERR_S 16
615 #define HCNTPERR_V(x) ((x) << HCNTPERR_S)
616 #define HCNTPERR_F HCNTPERR_V(1U)
617
618 #define DRSPPERR_S 15
619 #define DRSPPERR_V(x) ((x) << DRSPPERR_S)
620 #define DRSPPERR_F DRSPPERR_V(1U)
621
622 #define DREQPERR_S 14
623 #define DREQPERR_V(x) ((x) << DREQPERR_S)
624 #define DREQPERR_F DREQPERR_V(1U)
625
626 #define DCNTPERR_S 13
627 #define DCNTPERR_V(x) ((x) << DCNTPERR_S)
628 #define DCNTPERR_F DCNTPERR_V(1U)
629
630 #define CRSPPERR_S 12
631 #define CRSPPERR_V(x) ((x) << CRSPPERR_S)
632 #define CRSPPERR_F CRSPPERR_V(1U)
633
634 #define CREQPERR_S 11
635 #define CREQPERR_V(x) ((x) << CREQPERR_S)
636 #define CREQPERR_F CREQPERR_V(1U)
637
638 #define CCNTPERR_S 10
639 #define CCNTPERR_V(x) ((x) << CCNTPERR_S)
640 #define CCNTPERR_F CCNTPERR_V(1U)
641
642 #define TARTAGPERR_S 9
643 #define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
644 #define TARTAGPERR_F TARTAGPERR_V(1U)
645
646 #define PIOREQPERR_S 8
647 #define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
648 #define PIOREQPERR_F PIOREQPERR_V(1U)
649
650 #define PIOCPLPERR_S 7
651 #define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
652 #define PIOCPLPERR_F PIOCPLPERR_V(1U)
653
654 #define MSIXDIPERR_S 6
655 #define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
656 #define MSIXDIPERR_F MSIXDIPERR_V(1U)
657
658 #define MSIXDATAPERR_S 5
659 #define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
660 #define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
661
662 #define MSIXADDRHPERR_S 4
663 #define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
664 #define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
665
666 #define MSIXADDRLPERR_S 3
667 #define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
668 #define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
669
670 #define MSIDATAPERR_S 2
671 #define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
672 #define MSIDATAPERR_F MSIDATAPERR_V(1U)
673
674 #define MSIADDRHPERR_S 1
675 #define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
676 #define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
677
678 #define MSIADDRLPERR_S 0
679 #define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
680 #define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
681
682 #define READRSPERR_S 29
683 #define READRSPERR_V(x) ((x) << READRSPERR_S)
684 #define READRSPERR_F READRSPERR_V(1U)
685
686 #define TRGT1GRPPERR_S 28
687 #define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
688 #define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
689
690 #define IPSOTPERR_S 27
691 #define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
692 #define IPSOTPERR_F IPSOTPERR_V(1U)
693
694 #define IPRETRYPERR_S 26
695 #define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
696 #define IPRETRYPERR_F IPRETRYPERR_V(1U)
697
698 #define IPRXDATAGRPPERR_S 25
699 #define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
700 #define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
701
702 #define IPRXHDRGRPPERR_S 24
703 #define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
704 #define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
705
706 #define MAGRPPERR_S 22
707 #define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
708 #define MAGRPPERR_F MAGRPPERR_V(1U)
709
710 #define VFIDPERR_S 21
711 #define VFIDPERR_V(x) ((x) << VFIDPERR_S)
712 #define VFIDPERR_F VFIDPERR_V(1U)
713
714 #define HREQWRPERR_S 16
715 #define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
716 #define HREQWRPERR_F HREQWRPERR_V(1U)
717
718 #define DREQWRPERR_S 13
719 #define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
720 #define DREQWRPERR_F DREQWRPERR_V(1U)
721
722 #define CREQRDPERR_S 11
723 #define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
724 #define CREQRDPERR_F CREQRDPERR_V(1U)
725
726 #define MSTTAGQPERR_S 10
727 #define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
728 #define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
729
730 #define PIOREQGRPPERR_S 8
731 #define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
732 #define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
733
734 #define PIOCPLGRPPERR_S 7
735 #define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
736 #define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
737
738 #define MSIXSTIPERR_S 2
739 #define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
740 #define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
741
742 #define MSTTIMEOUTPERR_S 1
743 #define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
744 #define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
745
746 #define MSTGRPPERR_S 0
747 #define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
748 #define MSTGRPPERR_F MSTGRPPERR_V(1U)
749
750 #define PCIE_NONFAT_ERR_A 0x3010
751 #define PCIE_CFG_SPACE_REQ_A 0x3060
752 #define PCIE_CFG_SPACE_DATA_A 0x3064
753 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
754
755 #define PCIEOFST_S 10
756 #define PCIEOFST_M 0x3fffffU
757 #define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
758
759 #define BIR_S 8
760 #define BIR_M 0x3U
761 #define BIR_V(x) ((x) << BIR_S)
762 #define BIR_G(x) (((x) >> BIR_S) & BIR_M)
763
764 #define WINDOW_S 0
765 #define WINDOW_M 0xffU
766 #define WINDOW_V(x) ((x) << WINDOW_S)
767 #define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
768
769 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
770
771 #define ENABLE_S 30
772 #define ENABLE_V(x) ((x) << ENABLE_S)
773 #define ENABLE_F ENABLE_V(1U)
774
775 #define LOCALCFG_S 28
776 #define LOCALCFG_V(x) ((x) << LOCALCFG_S)
777 #define LOCALCFG_F LOCALCFG_V(1U)
778
779 #define FUNCTION_S 12
780 #define FUNCTION_V(x) ((x) << FUNCTION_S)
781
782 #define REGISTER_S 0
783 #define REGISTER_V(x) ((x) << REGISTER_S)
784
785 #define T6_ENABLE_S 31
786 #define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
787 #define T6_ENABLE_F T6_ENABLE_V(1U)
788
789 #define PFNUM_S 0
790 #define PFNUM_V(x) ((x) << PFNUM_S)
791
792 #define PCIE_FW_A 0x30b8
793 #define PCIE_FW_PF_A 0x30bc
794
795 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
796
797 #define RNPP_S 31
798 #define RNPP_V(x) ((x) << RNPP_S)
799 #define RNPP_F RNPP_V(1U)
800
801 #define RPCP_S 29
802 #define RPCP_V(x) ((x) << RPCP_S)
803 #define RPCP_F RPCP_V(1U)
804
805 #define RCIP_S 27
806 #define RCIP_V(x) ((x) << RCIP_S)
807 #define RCIP_F RCIP_V(1U)
808
809 #define RCCP_S 26
810 #define RCCP_V(x) ((x) << RCCP_S)
811 #define RCCP_F RCCP_V(1U)
812
813 #define RFTP_S 23
814 #define RFTP_V(x) ((x) << RFTP_S)
815 #define RFTP_F RFTP_V(1U)
816
817 #define PTRP_S 20
818 #define PTRP_V(x) ((x) << PTRP_S)
819 #define PTRP_F PTRP_V(1U)
820
821 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
822
823 #define TPCP_S 30
824 #define TPCP_V(x) ((x) << TPCP_S)
825 #define TPCP_F TPCP_V(1U)
826
827 #define TNPP_S 29
828 #define TNPP_V(x) ((x) << TNPP_S)
829 #define TNPP_F TNPP_V(1U)
830
831 #define TFTP_S 28
832 #define TFTP_V(x) ((x) << TFTP_S)
833 #define TFTP_F TFTP_V(1U)
834
835 #define TCAP_S 27
836 #define TCAP_V(x) ((x) << TCAP_S)
837 #define TCAP_F TCAP_V(1U)
838
839 #define TCIP_S 26
840 #define TCIP_V(x) ((x) << TCIP_S)
841 #define TCIP_F TCIP_V(1U)
842
843 #define RCAP_S 25
844 #define RCAP_V(x) ((x) << RCAP_S)
845 #define RCAP_F RCAP_V(1U)
846
847 #define PLUP_S 23
848 #define PLUP_V(x) ((x) << PLUP_S)
849 #define PLUP_F PLUP_V(1U)
850
851 #define PLDN_S 22
852 #define PLDN_V(x) ((x) << PLDN_S)
853 #define PLDN_F PLDN_V(1U)
854
855 #define OTDD_S 21
856 #define OTDD_V(x) ((x) << OTDD_S)
857 #define OTDD_F OTDD_V(1U)
858
859 #define GTRP_S 20
860 #define GTRP_V(x) ((x) << GTRP_S)
861 #define GTRP_F GTRP_V(1U)
862
863 #define RDPE_S 18
864 #define RDPE_V(x) ((x) << RDPE_S)
865 #define RDPE_F RDPE_V(1U)
866
867 #define TDCE_S 17
868 #define TDCE_V(x) ((x) << TDCE_S)
869 #define TDCE_F TDCE_V(1U)
870
871 #define TDUE_S 16
872 #define TDUE_V(x) ((x) << TDUE_S)
873 #define TDUE_F TDUE_V(1U)
874
875
876 #define MC_INT_CAUSE_A 0x7518
877 #define MC_P_INT_CAUSE_A 0x41318
878
879 #define ECC_UE_INT_CAUSE_S 2
880 #define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
881 #define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
882
883 #define ECC_CE_INT_CAUSE_S 1
884 #define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
885 #define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)
886
887 #define PERR_INT_CAUSE_S 0
888 #define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
889 #define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)
890
891 #define DBG_GPIO_EN_A 0x6010
892 #define XGMAC_PORT_CFG_A 0x1000
893 #define MAC_PORT_CFG_A 0x800
894
895 #define SIGNAL_DET_S 14
896 #define SIGNAL_DET_V(x) ((x) << SIGNAL_DET_S)
897 #define SIGNAL_DET_F SIGNAL_DET_V(1U)
898
899 #define MC_ECC_STATUS_A 0x751c
900 #define MC_P_ECC_STATUS_A 0x4131c
901
902 #define ECC_CECNT_S 16
903 #define ECC_CECNT_M 0xffffU
904 #define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
905 #define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
906
907 #define ECC_UECNT_S 0
908 #define ECC_UECNT_M 0xffffU
909 #define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
910 #define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
911
912 #define MC_BIST_CMD_A 0x7600
913
914 #define START_BIST_S 31
915 #define START_BIST_V(x) ((x) << START_BIST_S)
916 #define START_BIST_F START_BIST_V(1U)
917
918 #define BIST_CMD_GAP_S 8
919 #define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
920
921 #define BIST_OPCODE_S 0
922 #define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
923
924 #define MC_BIST_CMD_ADDR_A 0x7604
925 #define MC_BIST_CMD_LEN_A 0x7608
926 #define MC_BIST_DATA_PATTERN_A 0x760c
927
928 #define MC_BIST_STATUS_RDATA_A 0x7688
929
930
931 #define MA_EDRAM0_BAR_A 0x77c0
932
933 #define EDRAM0_BASE_S 16
934 #define EDRAM0_BASE_M 0xfffU
935 #define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)
936
937 #define EDRAM0_SIZE_S 0
938 #define EDRAM0_SIZE_M 0xfffU
939 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
940 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
941
942 #define MA_EDRAM1_BAR_A 0x77c4
943
944 #define EDRAM1_BASE_S 16
945 #define EDRAM1_BASE_M 0xfffU
946 #define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)
947
948 #define EDRAM1_SIZE_S 0
949 #define EDRAM1_SIZE_M 0xfffU
950 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
951 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
952
953 #define MA_EXT_MEMORY_BAR_A 0x77c8
954
955 #define EXT_MEM_BASE_S 16
956 #define EXT_MEM_BASE_M 0xfffU
957 #define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
958 #define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
959
960 #define EXT_MEM_SIZE_S 0
961 #define EXT_MEM_SIZE_M 0xfffU
962 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
963 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
964
965 #define MA_EXT_MEMORY1_BAR_A 0x7808
966
967 #define HMA_MUX_S 5
968 #define HMA_MUX_V(x) ((x) << HMA_MUX_S)
969 #define HMA_MUX_F HMA_MUX_V(1U)
970
971 #define EXT_MEM1_BASE_S 16
972 #define EXT_MEM1_BASE_M 0xfffU
973 #define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)
974
975 #define EXT_MEM1_SIZE_S 0
976 #define EXT_MEM1_SIZE_M 0xfffU
977 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
978 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
979
980 #define MA_EXT_MEMORY0_BAR_A 0x77c8
981
982 #define EXT_MEM0_BASE_S 16
983 #define EXT_MEM0_BASE_M 0xfffU
984 #define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
985
986 #define EXT_MEM0_SIZE_S 0
987 #define EXT_MEM0_SIZE_M 0xfffU
988 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
989 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
990
991 #define MA_TARGET_MEM_ENABLE_A 0x77d8
992
993 #define EXT_MEM_ENABLE_S 2
994 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
995 #define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
996
997 #define EDRAM1_ENABLE_S 1
998 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
999 #define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
1000
1001 #define EDRAM0_ENABLE_S 0
1002 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
1003 #define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
1004
1005 #define EXT_MEM1_ENABLE_S 4
1006 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
1007 #define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
1008
1009 #define EXT_MEM0_ENABLE_S 2
1010 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
1011 #define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
1012
1013 #define MA_INT_CAUSE_A 0x77e0
1014
1015 #define MEM_PERR_INT_CAUSE_S 1
1016 #define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
1017 #define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)
1018
1019 #define MEM_WRAP_INT_CAUSE_S 0
1020 #define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
1021 #define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
1022
1023 #define MA_INT_WRAP_STATUS_A 0x77e4
1024
1025 #define MEM_WRAP_ADDRESS_S 4
1026 #define MEM_WRAP_ADDRESS_M 0xfffffffU
1027 #define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
1028
1029 #define MEM_WRAP_CLIENT_NUM_S 0
1030 #define MEM_WRAP_CLIENT_NUM_M 0xfU
1031 #define MEM_WRAP_CLIENT_NUM_G(x) \
1032 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
1033
1034 #define MA_PARITY_ERROR_STATUS_A 0x77f4
1035 #define MA_PARITY_ERROR_STATUS1_A 0x77f4
1036 #define MA_PARITY_ERROR_STATUS2_A 0x7804
1037
1038
1039 #define EDC_0_BASE_ADDR 0x7900
1040
1041 #define EDC_BIST_CMD_A 0x7904
1042 #define EDC_BIST_CMD_ADDR_A 0x7908
1043 #define EDC_BIST_CMD_LEN_A 0x790c
1044 #define EDC_BIST_DATA_PATTERN_A 0x7910
1045 #define EDC_BIST_STATUS_RDATA_A 0x7928
1046 #define EDC_INT_CAUSE_A 0x7978
1047
1048 #define ECC_UE_PAR_S 5
1049 #define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
1050 #define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
1051
1052 #define ECC_CE_PAR_S 4
1053 #define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
1054 #define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
1055
1056 #define PERR_PAR_CAUSE_S 3
1057 #define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
1058 #define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
1059
1060 #define EDC_ECC_STATUS_A 0x797c
1061
1062
1063 #define EDC_1_BASE_ADDR 0x7980
1064
1065
1066 #define CIM_BOOT_CFG_A 0x7b00
1067 #define CIM_SDRAM_BASE_ADDR_A 0x7b14
1068 #define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1069 #define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1070 #define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1071 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1072
1073 #define BOOTADDR_M 0xffffff00U
1074
1075 #define UPCRST_S 0
1076 #define UPCRST_V(x) ((x) << UPCRST_S)
1077 #define UPCRST_F UPCRST_V(1U)
1078
1079 #define CIM_PF_MAILBOX_DATA_A 0x240
1080 #define CIM_PF_MAILBOX_CTRL_A 0x280
1081
1082 #define MBMSGVALID_S 3
1083 #define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
1084 #define MBMSGVALID_F MBMSGVALID_V(1U)
1085
1086 #define MBINTREQ_S 2
1087 #define MBINTREQ_V(x) ((x) << MBINTREQ_S)
1088 #define MBINTREQ_F MBINTREQ_V(1U)
1089
1090 #define MBOWNER_S 0
1091 #define MBOWNER_M 0x3U
1092 #define MBOWNER_V(x) ((x) << MBOWNER_S)
1093 #define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
1094
1095 #define CIM_PF_HOST_INT_ENABLE_A 0x288
1096
1097 #define MBMSGRDYINTEN_S 19
1098 #define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
1099 #define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)
1100
1101 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
1102
1103 #define MBMSGRDYINT_S 19
1104 #define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
1105 #define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
1106
1107 #define CIM_HOST_INT_CAUSE_A 0x7b2c
1108
1109 #define TIEQOUTPARERRINT_S 20
1110 #define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
1111 #define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)
1112
1113 #define TIEQINPARERRINT_S 19
1114 #define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
1115 #define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
1116
1117 #define TIMER0INT_S 2
1118 #define TIMER0INT_V(x) ((x) << TIMER0INT_S)
1119 #define TIMER0INT_F TIMER0INT_V(1U)
1120
1121 #define PREFDROPINT_S 1
1122 #define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
1123 #define PREFDROPINT_F PREFDROPINT_V(1U)
1124
1125 #define UPACCNONZERO_S 0
1126 #define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1127 #define UPACCNONZERO_F UPACCNONZERO_V(1U)
1128
1129 #define MBHOSTPARERR_S 18
1130 #define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1131 #define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
1132
1133 #define MBUPPARERR_S 17
1134 #define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1135 #define MBUPPARERR_F MBUPPARERR_V(1U)
1136
1137 #define IBQTP0PARERR_S 16
1138 #define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1139 #define IBQTP0PARERR_F IBQTP0PARERR_V(1U)
1140
1141 #define IBQTP1PARERR_S 15
1142 #define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1143 #define IBQTP1PARERR_F IBQTP1PARERR_V(1U)
1144
1145 #define IBQULPPARERR_S 14
1146 #define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1147 #define IBQULPPARERR_F IBQULPPARERR_V(1U)
1148
1149 #define IBQSGELOPARERR_S 13
1150 #define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1151 #define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)
1152
1153 #define IBQSGEHIPARERR_S 12
1154 #define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1155 #define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)
1156
1157 #define IBQNCSIPARERR_S 11
1158 #define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1159 #define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)
1160
1161 #define OBQULP0PARERR_S 10
1162 #define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1163 #define OBQULP0PARERR_F OBQULP0PARERR_V(1U)
1164
1165 #define OBQULP1PARERR_S 9
1166 #define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1167 #define OBQULP1PARERR_F OBQULP1PARERR_V(1U)
1168
1169 #define OBQULP2PARERR_S 8
1170 #define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1171 #define OBQULP2PARERR_F OBQULP2PARERR_V(1U)
1172
1173 #define OBQULP3PARERR_S 7
1174 #define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1175 #define OBQULP3PARERR_F OBQULP3PARERR_V(1U)
1176
1177 #define OBQSGEPARERR_S 6
1178 #define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1179 #define OBQSGEPARERR_F OBQSGEPARERR_V(1U)
1180
1181 #define OBQNCSIPARERR_S 5
1182 #define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1183 #define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
1184
1185 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1186
1187 #define EEPROMWRINT_S 30
1188 #define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1189 #define EEPROMWRINT_F EEPROMWRINT_V(1U)
1190
1191 #define TIMEOUTMAINT_S 29
1192 #define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1193 #define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)
1194
1195 #define TIMEOUTINT_S 28
1196 #define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1197 #define TIMEOUTINT_F TIMEOUTINT_V(1U)
1198
1199 #define RSPOVRLOOKUPINT_S 27
1200 #define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1201 #define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)
1202
1203 #define REQOVRLOOKUPINT_S 26
1204 #define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1205 #define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)
1206
1207 #define BLKWRPLINT_S 25
1208 #define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1209 #define BLKWRPLINT_F BLKWRPLINT_V(1U)
1210
1211 #define BLKRDPLINT_S 24
1212 #define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1213 #define BLKRDPLINT_F BLKRDPLINT_V(1U)
1214
1215 #define SGLWRPLINT_S 23
1216 #define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1217 #define SGLWRPLINT_F SGLWRPLINT_V(1U)
1218
1219 #define SGLRDPLINT_S 22
1220 #define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1221 #define SGLRDPLINT_F SGLRDPLINT_V(1U)
1222
1223 #define BLKWRCTLINT_S 21
1224 #define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1225 #define BLKWRCTLINT_F BLKWRCTLINT_V(1U)
1226
1227 #define BLKRDCTLINT_S 20
1228 #define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1229 #define BLKRDCTLINT_F BLKRDCTLINT_V(1U)
1230
1231 #define SGLWRCTLINT_S 19
1232 #define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1233 #define SGLWRCTLINT_F SGLWRCTLINT_V(1U)
1234
1235 #define SGLRDCTLINT_S 18
1236 #define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1237 #define SGLRDCTLINT_F SGLRDCTLINT_V(1U)
1238
1239 #define BLKWREEPROMINT_S 17
1240 #define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1241 #define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)
1242
1243 #define BLKRDEEPROMINT_S 16
1244 #define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1245 #define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)
1246
1247 #define SGLWREEPROMINT_S 15
1248 #define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1249 #define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)
1250
1251 #define SGLRDEEPROMINT_S 14
1252 #define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1253 #define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)
1254
1255 #define BLKWRFLASHINT_S 13
1256 #define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1257 #define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)
1258
1259 #define BLKRDFLASHINT_S 12
1260 #define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1261 #define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)
1262
1263 #define SGLWRFLASHINT_S 11
1264 #define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1265 #define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)
1266
1267 #define SGLRDFLASHINT_S 10
1268 #define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1269 #define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)
1270
1271 #define BLKWRBOOTINT_S 9
1272 #define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1273 #define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)
1274
1275 #define BLKRDBOOTINT_S 8
1276 #define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1277 #define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)
1278
1279 #define SGLWRBOOTINT_S 7
1280 #define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1281 #define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)
1282
1283 #define SGLRDBOOTINT_S 6
1284 #define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1285 #define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)
1286
1287 #define ILLWRBEINT_S 5
1288 #define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1289 #define ILLWRBEINT_F ILLWRBEINT_V(1U)
1290
1291 #define ILLRDBEINT_S 4
1292 #define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1293 #define ILLRDBEINT_F ILLRDBEINT_V(1U)
1294
1295 #define ILLRDINT_S 3
1296 #define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1297 #define ILLRDINT_F ILLRDINT_V(1U)
1298
1299 #define ILLWRINT_S 2
1300 #define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1301 #define ILLWRINT_F ILLWRINT_V(1U)
1302
1303 #define ILLTRANSINT_S 1
1304 #define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1305 #define ILLTRANSINT_F ILLTRANSINT_V(1U)
1306
1307 #define RSVDSPACEINT_S 0
1308 #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1309 #define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
1310
1311
1312 #define DBGLAWHLF_S 23
1313 #define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1314 #define DBGLAWHLF_F DBGLAWHLF_V(1U)
1315
1316 #define DBGLAWPTR_S 16
1317 #define DBGLAWPTR_M 0x7fU
1318 #define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1319
1320 #define DBGLAENABLE_S 12
1321 #define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1322 #define DBGLAENABLE_F DBGLAENABLE_V(1U)
1323
1324 #define DBGLARPTR_S 0
1325 #define DBGLARPTR_M 0x7fU
1326 #define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1327
1328 #define CRXPKTENC_S 3
1329 #define CRXPKTENC_V(x) ((x) << CRXPKTENC_S)
1330 #define CRXPKTENC_F CRXPKTENC_V(1U)
1331
1332 #define TP_DBG_LA_DATAL_A 0x7ed8
1333 #define TP_DBG_LA_CONFIG_A 0x7ed4
1334 #define TP_OUT_CONFIG_A 0x7d04
1335 #define TP_GLOBAL_CONFIG_A 0x7d08
1336
1337 #define ACTIVEFILTERCOUNTS_S 22
1338 #define ACTIVEFILTERCOUNTS_V(x) ((x) << ACTIVEFILTERCOUNTS_S)
1339 #define ACTIVEFILTERCOUNTS_F ACTIVEFILTERCOUNTS_V(1U)
1340
1341 #define TP_CMM_TCB_BASE_A 0x7d10
1342 #define TP_CMM_MM_BASE_A 0x7d14
1343 #define TP_CMM_TIMER_BASE_A 0x7d18
1344 #define TP_PMM_TX_BASE_A 0x7d20
1345 #define TP_PMM_RX_BASE_A 0x7d28
1346 #define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1347 #define TP_PMM_RX_MAX_PAGE_A 0x7d30
1348 #define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1349 #define TP_PMM_TX_MAX_PAGE_A 0x7d38
1350 #define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1351
1352 #define PMRXNUMCHN_S 31
1353 #define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)
1354 #define PMRXNUMCHN_F PMRXNUMCHN_V(1U)
1355
1356 #define PMTXNUMCHN_S 30
1357 #define PMTXNUMCHN_M 0x3U
1358 #define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)
1359
1360 #define PMTXMAXPAGE_S 0
1361 #define PMTXMAXPAGE_M 0x1fffffU
1362 #define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)
1363
1364 #define PMRXMAXPAGE_S 0
1365 #define PMRXMAXPAGE_M 0x1fffffU
1366 #define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)
1367
1368 #define DBGLAMODE_S 14
1369 #define DBGLAMODE_M 0x3U
1370 #define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1371
1372 #define FIVETUPLELOOKUP_S 17
1373 #define FIVETUPLELOOKUP_M 0x3U
1374 #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1375 #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1376
1377 #define TP_PARA_REG2_A 0x7d68
1378
1379 #define MAXRXDATA_S 16
1380 #define MAXRXDATA_M 0xffffU
1381 #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1382
1383 #define TP_TIMER_RESOLUTION_A 0x7d90
1384
1385 #define TIMERRESOLUTION_S 16
1386 #define TIMERRESOLUTION_M 0xffU
1387 #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1388
1389 #define TIMESTAMPRESOLUTION_S 8
1390 #define TIMESTAMPRESOLUTION_M 0xffU
1391 #define TIMESTAMPRESOLUTION_G(x) \
1392 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1393
1394 #define DELAYEDACKRESOLUTION_S 0
1395 #define DELAYEDACKRESOLUTION_M 0xffU
1396 #define DELAYEDACKRESOLUTION_G(x) \
1397 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1398
1399 #define TP_SHIFT_CNT_A 0x7dc0
1400 #define TP_RXT_MIN_A 0x7d98
1401 #define TP_RXT_MAX_A 0x7d9c
1402 #define TP_PERS_MIN_A 0x7da0
1403 #define TP_PERS_MAX_A 0x7da4
1404 #define TP_KEEP_IDLE_A 0x7da8
1405 #define TP_KEEP_INTVL_A 0x7dac
1406 #define TP_INIT_SRTT_A 0x7db0
1407 #define TP_DACK_TIMER_A 0x7db4
1408 #define TP_FINWAIT2_TIMER_A 0x7db8
1409
1410 #define INITSRTT_S 0
1411 #define INITSRTT_M 0xffffU
1412 #define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1413
1414 #define PERSMAX_S 0
1415 #define PERSMAX_M 0x3fffffffU
1416 #define PERSMAX_V(x) ((x) << PERSMAX_S)
1417 #define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1418
1419 #define SYNSHIFTMAX_S 24
1420 #define SYNSHIFTMAX_M 0xffU
1421 #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1422 #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1423
1424 #define RXTSHIFTMAXR1_S 20
1425 #define RXTSHIFTMAXR1_M 0xfU
1426 #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1427 #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1428
1429 #define RXTSHIFTMAXR2_S 16
1430 #define RXTSHIFTMAXR2_M 0xfU
1431 #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1432 #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1433
1434 #define PERSHIFTBACKOFFMAX_S 12
1435 #define PERSHIFTBACKOFFMAX_M 0xfU
1436 #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1437 #define PERSHIFTBACKOFFMAX_G(x) \
1438 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1439
1440 #define PERSHIFTMAX_S 8
1441 #define PERSHIFTMAX_M 0xfU
1442 #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1443 #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1444
1445 #define KEEPALIVEMAXR1_S 4
1446 #define KEEPALIVEMAXR1_M 0xfU
1447 #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1448 #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1449
1450 #define KEEPALIVEMAXR2_S 0
1451 #define KEEPALIVEMAXR2_M 0xfU
1452 #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1453 #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1454
1455 #define ROWINDEX_S 16
1456 #define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1457
1458 #define TP_CCTRL_TABLE_A 0x7ddc
1459 #define TP_PACE_TABLE_A 0x7dd8
1460 #define TP_MTU_TABLE_A 0x7de4
1461
1462 #define MTUINDEX_S 24
1463 #define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1464
1465 #define MTUWIDTH_S 16
1466 #define MTUWIDTH_M 0xfU
1467 #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1468 #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1469
1470 #define MTUVALUE_S 0
1471 #define MTUVALUE_M 0x3fffU
1472 #define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1473 #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1474
1475 #define TP_RSS_LKP_TABLE_A 0x7dec
1476 #define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1477 #define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1478 #define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1479
1480 #define LKPTBLROWVLD_S 31
1481 #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1482 #define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
1483
1484 #define LKPTBLQUEUE1_S 10
1485 #define LKPTBLQUEUE1_M 0x3ffU
1486 #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1487
1488 #define LKPTBLQUEUE0_S 0
1489 #define LKPTBLQUEUE0_M 0x3ffU
1490 #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1491
1492 #define TP_TM_PIO_ADDR_A 0x7e18
1493 #define TP_TM_PIO_DATA_A 0x7e1c
1494 #define TP_MOD_CONFIG_A 0x7e24
1495
1496 #define TIMERMODE_S 8
1497 #define TIMERMODE_M 0xffU
1498 #define TIMERMODE_G(x) (((x) >> TIMERMODE_S) & TIMERMODE_M)
1499
1500 #define TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A 0x3
1501 #define TP_TX_MOD_Q1_Q0_RATE_LIMIT_A 0x8
1502
1503 #define TP_PIO_ADDR_A 0x7e40
1504 #define TP_PIO_DATA_A 0x7e44
1505 #define TP_MIB_INDEX_A 0x7e50
1506 #define TP_MIB_DATA_A 0x7e54
1507 #define TP_INT_CAUSE_A 0x7e74
1508
1509 #define TP_FLM_FREE_PS_CNT_A 0x7e80
1510 #define TP_FLM_FREE_RX_CNT_A 0x7e84
1511
1512 #define FREEPSTRUCTCOUNT_S 0
1513 #define FREEPSTRUCTCOUNT_M 0x1fffffU
1514 #define FREEPSTRUCTCOUNT_G(x) (((x) >> FREEPSTRUCTCOUNT_S) & FREEPSTRUCTCOUNT_M)
1515
1516 #define FREERXPAGECOUNT_S 0
1517 #define FREERXPAGECOUNT_M 0x1fffffU
1518 #define FREERXPAGECOUNT_V(x) ((x) << FREERXPAGECOUNT_S)
1519 #define FREERXPAGECOUNT_G(x) (((x) >> FREERXPAGECOUNT_S) & FREERXPAGECOUNT_M)
1520
1521 #define TP_FLM_FREE_TX_CNT_A 0x7e88
1522
1523 #define FREETXPAGECOUNT_S 0
1524 #define FREETXPAGECOUNT_M 0x1fffffU
1525 #define FREETXPAGECOUNT_V(x) ((x) << FREETXPAGECOUNT_S)
1526 #define FREETXPAGECOUNT_G(x) (((x) >> FREETXPAGECOUNT_S) & FREETXPAGECOUNT_M)
1527
1528 #define FLMTXFLSTEMPTY_S 30
1529 #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1530 #define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
1531
1532 #define TP_TX_ORATE_A 0x7ebc
1533
1534 #define OFDRATE3_S 24
1535 #define OFDRATE3_M 0xffU
1536 #define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)
1537
1538 #define OFDRATE2_S 16
1539 #define OFDRATE2_M 0xffU
1540 #define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)
1541
1542 #define OFDRATE1_S 8
1543 #define OFDRATE1_M 0xffU
1544 #define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)
1545
1546 #define OFDRATE0_S 0
1547 #define OFDRATE0_M 0xffU
1548 #define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)
1549
1550 #define TP_TX_TRATE_A 0x7ed0
1551
1552 #define TNLRATE3_S 24
1553 #define TNLRATE3_M 0xffU
1554 #define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)
1555
1556 #define TNLRATE2_S 16
1557 #define TNLRATE2_M 0xffU
1558 #define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)
1559
1560 #define TNLRATE1_S 8
1561 #define TNLRATE1_M 0xffU
1562 #define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)
1563
1564 #define TNLRATE0_S 0
1565 #define TNLRATE0_M 0xffU
1566 #define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)
1567
1568 #define TP_VLAN_PRI_MAP_A 0x140
1569
1570 #define FRAGMENTATION_S 9
1571 #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1572 #define FRAGMENTATION_F FRAGMENTATION_V(1U)
1573
1574 #define MPSHITTYPE_S 8
1575 #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1576 #define MPSHITTYPE_F MPSHITTYPE_V(1U)
1577
1578 #define MACMATCH_S 7
1579 #define MACMATCH_V(x) ((x) << MACMATCH_S)
1580 #define MACMATCH_F MACMATCH_V(1U)
1581
1582 #define ETHERTYPE_S 6
1583 #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1584 #define ETHERTYPE_F ETHERTYPE_V(1U)
1585
1586 #define PROTOCOL_S 5
1587 #define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1588 #define PROTOCOL_F PROTOCOL_V(1U)
1589
1590 #define TOS_S 4
1591 #define TOS_V(x) ((x) << TOS_S)
1592 #define TOS_F TOS_V(1U)
1593
1594 #define VLAN_S 3
1595 #define VLAN_V(x) ((x) << VLAN_S)
1596 #define VLAN_F VLAN_V(1U)
1597
1598 #define VNIC_ID_S 2
1599 #define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1600 #define VNIC_ID_F VNIC_ID_V(1U)
1601
1602 #define PORT_S 1
1603 #define PORT_V(x) ((x) << PORT_S)
1604 #define PORT_F PORT_V(1U)
1605
1606 #define FCOE_S 0
1607 #define FCOE_V(x) ((x) << FCOE_S)
1608 #define FCOE_F FCOE_V(1U)
1609
1610 #define FILTERMODE_S 15
1611 #define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1612 #define FILTERMODE_F FILTERMODE_V(1U)
1613
1614 #define FCOEMASK_S 14
1615 #define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1616 #define FCOEMASK_F FCOEMASK_V(1U)
1617
1618 #define TP_INGRESS_CONFIG_A 0x141
1619
1620 #define VNIC_S 11
1621 #define VNIC_V(x) ((x) << VNIC_S)
1622 #define VNIC_F VNIC_V(1U)
1623
1624 #define USE_ENC_IDX_S 13
1625 #define USE_ENC_IDX_V(x) ((x) << USE_ENC_IDX_S)
1626 #define USE_ENC_IDX_F USE_ENC_IDX_V(1U)
1627
1628 #define CSUM_HAS_PSEUDO_HDR_S 10
1629 #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1630 #define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
1631
1632 #define TP_MIB_MAC_IN_ERR_0_A 0x0
1633 #define TP_MIB_HDR_IN_ERR_0_A 0x4
1634 #define TP_MIB_TCP_IN_ERR_0_A 0x8
1635 #define TP_MIB_TCP_OUT_RST_A 0xc
1636 #define TP_MIB_TCP_IN_SEG_HI_A 0x10
1637 #define TP_MIB_TCP_IN_SEG_LO_A 0x11
1638 #define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1639 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1640 #define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1641 #define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1642 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1643 #define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1644 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1645 #define TP_MIB_TCP_V6OUT_RST_A 0x2c
1646 #define TP_MIB_OFD_ARP_DROP_A 0x36
1647 #define TP_MIB_CPL_IN_REQ_0_A 0x38
1648 #define TP_MIB_CPL_OUT_RSP_0_A 0x3c
1649 #define TP_MIB_TNL_DROP_0_A 0x44
1650 #define TP_MIB_FCOE_DDP_0_A 0x48
1651 #define TP_MIB_FCOE_DROP_0_A 0x4c
1652 #define TP_MIB_FCOE_BYTE_0_HI_A 0x50
1653 #define TP_MIB_OFD_VLN_DROP_0_A 0x58
1654 #define TP_MIB_USM_PKTS_A 0x5c
1655 #define TP_MIB_RQE_DFR_PKT_A 0x64
1656
1657 #define ULP_TX_INT_CAUSE_A 0x8dcc
1658 #define ULP_TX_TPT_LLIMIT_A 0x8dd4
1659 #define ULP_TX_TPT_ULIMIT_A 0x8dd8
1660 #define ULP_TX_PBL_LLIMIT_A 0x8ddc
1661 #define ULP_TX_PBL_ULIMIT_A 0x8de0
1662 #define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1663
1664 #define PBL_BOUND_ERR_CH3_S 31
1665 #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1666 #define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
1667
1668 #define PBL_BOUND_ERR_CH2_S 30
1669 #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1670 #define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
1671
1672 #define PBL_BOUND_ERR_CH1_S 29
1673 #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1674 #define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
1675
1676 #define PBL_BOUND_ERR_CH0_S 28
1677 #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1678 #define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
1679
1680 #define PM_RX_INT_CAUSE_A 0x8fdc
1681 #define PM_RX_STAT_CONFIG_A 0x8fc8
1682 #define PM_RX_STAT_COUNT_A 0x8fcc
1683 #define PM_RX_STAT_LSB_A 0x8fd0
1684 #define PM_RX_DBG_CTRL_A 0x8fd0
1685 #define PM_RX_DBG_DATA_A 0x8fd4
1686 #define PM_RX_DBG_STAT_MSB_A 0x10013
1687
1688 #define PMRX_FRAMING_ERROR_F 0x003ffff0U
1689
1690 #define ZERO_E_CMD_ERROR_S 22
1691 #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1692 #define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
1693
1694 #define OCSPI_PAR_ERROR_S 3
1695 #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1696 #define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
1697
1698 #define DB_OPTIONS_PAR_ERROR_S 2
1699 #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1700 #define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
1701
1702 #define IESPI_PAR_ERROR_S 1
1703 #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1704 #define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
1705
1706 #define ULP_TX_LA_RDPTR_0_A 0x8ec0
1707 #define ULP_TX_LA_RDDATA_0_A 0x8ec4
1708 #define ULP_TX_LA_WRPTR_0_A 0x8ec8
1709 #define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f70
1710
1711 #define ULP_TX_ASIC_DEBUG_0_A 0x8f74
1712 #define ULP_TX_ASIC_DEBUG_1_A 0x8f78
1713 #define ULP_TX_ASIC_DEBUG_2_A 0x8f7c
1714 #define ULP_TX_ASIC_DEBUG_3_A 0x8f80
1715 #define ULP_TX_ASIC_DEBUG_4_A 0x8f84
1716
1717
1718 #define PM_RX_BASE_ADDR 0x8fc0
1719
1720 #define PMRX_E_PCMD_PAR_ERROR_S 0
1721 #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1722 #define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
1723
1724 #define PM_TX_INT_CAUSE_A 0x8ffc
1725 #define PM_TX_STAT_CONFIG_A 0x8fe8
1726 #define PM_TX_STAT_COUNT_A 0x8fec
1727 #define PM_TX_STAT_LSB_A 0x8ff0
1728 #define PM_TX_DBG_CTRL_A 0x8ff0
1729 #define PM_TX_DBG_DATA_A 0x8ff4
1730 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1731
1732 #define PCMD_LEN_OVFL0_S 31
1733 #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1734 #define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
1735
1736 #define PCMD_LEN_OVFL1_S 30
1737 #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1738 #define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
1739
1740 #define PCMD_LEN_OVFL2_S 29
1741 #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1742 #define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
1743
1744 #define ZERO_C_CMD_ERROR_S 28
1745 #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1746 #define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
1747
1748 #define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1749
1750 #define OESPI_PAR_ERROR_S 3
1751 #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1752 #define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
1753
1754 #define ICSPI_PAR_ERROR_S 1
1755 #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1756 #define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
1757
1758 #define PMTX_C_PCMD_PAR_ERROR_S 0
1759 #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1760 #define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
1761
1762 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1763 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1764 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1765 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1766 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1767 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1768 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1769 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1770 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1771 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1772 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1773 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1774 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1775 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1776 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1777 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1778 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1779 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1780 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1781 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1782 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1783 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1784 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1785 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1786 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1787 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1788 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1789 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1790 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1791 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1792 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1793 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1794 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1795 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1796 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1797 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1798 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1799 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1800 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1801 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1802 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1803 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1804 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1805 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1806 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1807 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1808 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1809 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1810 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1811 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1812 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1813 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1814 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1815 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1816 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1817 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1818 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1819 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1820 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1821 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1822 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1823 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1824 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1825 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1826 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1827 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1828 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1829 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1830 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1831 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1832 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1833 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1834 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1835 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1836 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1837 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1838 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1839 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1840 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1841 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1842 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1843 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1844 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1845 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1846 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1847 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1848 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1849 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1850 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1851 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1852 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1853 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1854 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1855 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1856 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1857 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1858 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1859 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1860 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1861 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1862 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1863 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1864 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1865 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1866 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1867 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1868 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1869 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1870 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1871 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1872 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1873 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1874 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1875 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1876 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1877 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1878 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1879 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1880 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1881 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1882 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1883 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1884 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1885 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1886 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1887 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1888 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1889 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1890 #define MAC_PORT_MAGIC_MACID_LO 0x824
1891 #define MAC_PORT_MAGIC_MACID_HI 0x828
1892 #define MAC_PORT_TX_TS_VAL_LO 0x928
1893 #define MAC_PORT_TX_TS_VAL_HI 0x92c
1894
1895 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1896 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1897 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1898 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1899 #define MAC_PORT_EPIO_OP_A 0x8d0
1900
1901 #define MAC_PORT_CFG2_A 0x818
1902
1903 #define MAC_PORT_PTP_SUM_LO_A 0x990
1904 #define MAC_PORT_PTP_SUM_HI_A 0x994
1905
1906 #define MPS_CMN_CTL_A 0x9000
1907
1908 #define COUNTPAUSEMCRX_S 5
1909 #define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)
1910 #define COUNTPAUSEMCRX_F COUNTPAUSEMCRX_V(1U)
1911
1912 #define COUNTPAUSESTATRX_S 4
1913 #define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)
1914 #define COUNTPAUSESTATRX_F COUNTPAUSESTATRX_V(1U)
1915
1916 #define COUNTPAUSEMCTX_S 3
1917 #define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)
1918 #define COUNTPAUSEMCTX_F COUNTPAUSEMCTX_V(1U)
1919
1920 #define COUNTPAUSESTATTX_S 2
1921 #define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)
1922 #define COUNTPAUSESTATTX_F COUNTPAUSESTATTX_V(1U)
1923
1924 #define NUMPORTS_S 0
1925 #define NUMPORTS_M 0x3U
1926 #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1927
1928 #define MPS_INT_CAUSE_A 0x9008
1929 #define MPS_TX_INT_CAUSE_A 0x9408
1930 #define MPS_STAT_CTL_A 0x9600
1931
1932 #define FRMERR_S 15
1933 #define FRMERR_V(x) ((x) << FRMERR_S)
1934 #define FRMERR_F FRMERR_V(1U)
1935
1936 #define SECNTERR_S 14
1937 #define SECNTERR_V(x) ((x) << SECNTERR_S)
1938 #define SECNTERR_F SECNTERR_V(1U)
1939
1940 #define BUBBLE_S 13
1941 #define BUBBLE_V(x) ((x) << BUBBLE_S)
1942 #define BUBBLE_F BUBBLE_V(1U)
1943
1944 #define TXDESCFIFO_S 9
1945 #define TXDESCFIFO_M 0xfU
1946 #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1947
1948 #define TXDATAFIFO_S 5
1949 #define TXDATAFIFO_M 0xfU
1950 #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1951
1952 #define NCSIFIFO_S 4
1953 #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1954 #define NCSIFIFO_F NCSIFIFO_V(1U)
1955
1956 #define TPFIFO_S 0
1957 #define TPFIFO_M 0xfU
1958 #define TPFIFO_V(x) ((x) << TPFIFO_S)
1959
1960 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1961 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1962 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1963
1964 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1965 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1966 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1967 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1968 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1969 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1970 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1971 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1972 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1973 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1974 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1975 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1976 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1977 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1978 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1979 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1980 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1981 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1982 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1983 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1984 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1985 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1986 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1987 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1988 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1989 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1990 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1991 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1992 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1993 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1994 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1995 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1996
1997 #define MPS_TRC_CFG_A 0x9800
1998
1999 #define TRCFIFOEMPTY_S 4
2000 #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
2001 #define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
2002
2003 #define TRCIGNOREDROPINPUT_S 3
2004 #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
2005 #define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
2006
2007 #define TRCKEEPDUPLICATES_S 2
2008 #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
2009 #define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
2010
2011 #define TRCEN_S 1
2012 #define TRCEN_V(x) ((x) << TRCEN_S)
2013 #define TRCEN_F TRCEN_V(1U)
2014
2015 #define TRCMULTIFILTER_S 0
2016 #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
2017 #define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
2018
2019 #define MPS_TRC_RSS_CONTROL_A 0x9808
2020 #define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
2021 #define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
2022 #define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
2023 #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
2024
2025 #define RSSCONTROL_S 16
2026 #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
2027
2028 #define QUEUENUMBER_S 0
2029 #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
2030
2031 #define TFINVERTMATCH_S 24
2032 #define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
2033 #define TFINVERTMATCH_F TFINVERTMATCH_V(1U)
2034
2035 #define TFEN_S 22
2036 #define TFEN_V(x) ((x) << TFEN_S)
2037 #define TFEN_F TFEN_V(1U)
2038
2039 #define TFPORT_S 18
2040 #define TFPORT_M 0xfU
2041 #define TFPORT_V(x) ((x) << TFPORT_S)
2042 #define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
2043
2044 #define TFLENGTH_S 8
2045 #define TFLENGTH_M 0x1fU
2046 #define TFLENGTH_V(x) ((x) << TFLENGTH_S)
2047 #define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
2048
2049 #define TFOFFSET_S 0
2050 #define TFOFFSET_M 0x1fU
2051 #define TFOFFSET_V(x) ((x) << TFOFFSET_S)
2052 #define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
2053
2054 #define T5_TFINVERTMATCH_S 25
2055 #define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
2056 #define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)
2057
2058 #define T5_TFEN_S 23
2059 #define T5_TFEN_V(x) ((x) << T5_TFEN_S)
2060 #define T5_TFEN_F T5_TFEN_V(1U)
2061
2062 #define T5_TFPORT_S 18
2063 #define T5_TFPORT_M 0x1fU
2064 #define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
2065 #define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
2066
2067 #define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
2068 #define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
2069
2070 #define TFMINPKTSIZE_S 16
2071 #define TFMINPKTSIZE_M 0x1ffU
2072 #define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
2073 #define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
2074
2075 #define TFCAPTUREMAX_S 0
2076 #define TFCAPTUREMAX_M 0x3fffU
2077 #define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
2078 #define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
2079
2080 #define MPS_TRC_FILTER0_MATCH_A 0x9c00
2081 #define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
2082 #define MPS_TRC_FILTER1_MATCH_A 0x9d00
2083
2084 #define TP_RSS_CONFIG_A 0x7df0
2085
2086 #define TNL4TUPENIPV6_S 31
2087 #define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
2088 #define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
2089
2090 #define TNL2TUPENIPV6_S 30
2091 #define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
2092 #define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
2093
2094 #define TNL4TUPENIPV4_S 29
2095 #define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
2096 #define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
2097
2098 #define TNL2TUPENIPV4_S 28
2099 #define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
2100 #define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
2101
2102 #define TNLTCPSEL_S 27
2103 #define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
2104 #define TNLTCPSEL_F TNLTCPSEL_V(1U)
2105
2106 #define TNLIP6SEL_S 26
2107 #define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
2108 #define TNLIP6SEL_F TNLIP6SEL_V(1U)
2109
2110 #define TNLVRTSEL_S 25
2111 #define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
2112 #define TNLVRTSEL_F TNLVRTSEL_V(1U)
2113
2114 #define TNLMAPEN_S 24
2115 #define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
2116 #define TNLMAPEN_F TNLMAPEN_V(1U)
2117
2118 #define OFDHASHSAVE_S 19
2119 #define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
2120 #define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
2121
2122 #define OFDVRTSEL_S 18
2123 #define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
2124 #define OFDVRTSEL_F OFDVRTSEL_V(1U)
2125
2126 #define OFDMAPEN_S 17
2127 #define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
2128 #define OFDMAPEN_F OFDMAPEN_V(1U)
2129
2130 #define OFDLKPEN_S 16
2131 #define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
2132 #define OFDLKPEN_F OFDLKPEN_V(1U)
2133
2134 #define SYN4TUPENIPV6_S 15
2135 #define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
2136 #define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
2137
2138 #define SYN2TUPENIPV6_S 14
2139 #define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
2140 #define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
2141
2142 #define SYN4TUPENIPV4_S 13
2143 #define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
2144 #define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
2145
2146 #define SYN2TUPENIPV4_S 12
2147 #define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
2148 #define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
2149
2150 #define SYNIP6SEL_S 11
2151 #define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
2152 #define SYNIP6SEL_F SYNIP6SEL_V(1U)
2153
2154 #define SYNVRTSEL_S 10
2155 #define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
2156 #define SYNVRTSEL_F SYNVRTSEL_V(1U)
2157
2158 #define SYNMAPEN_S 9
2159 #define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
2160 #define SYNMAPEN_F SYNMAPEN_V(1U)
2161
2162 #define SYNLKPEN_S 8
2163 #define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
2164 #define SYNLKPEN_F SYNLKPEN_V(1U)
2165
2166 #define CHANNELENABLE_S 7
2167 #define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
2168 #define CHANNELENABLE_F CHANNELENABLE_V(1U)
2169
2170 #define PORTENABLE_S 6
2171 #define PORTENABLE_V(x) ((x) << PORTENABLE_S)
2172 #define PORTENABLE_F PORTENABLE_V(1U)
2173
2174 #define TNLALLLOOKUP_S 5
2175 #define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
2176 #define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
2177
2178 #define VIRTENABLE_S 4
2179 #define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
2180 #define VIRTENABLE_F VIRTENABLE_V(1U)
2181
2182 #define CONGESTIONENABLE_S 3
2183 #define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
2184 #define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
2185
2186 #define HASHTOEPLITZ_S 2
2187 #define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
2188 #define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
2189
2190 #define UDPENABLE_S 1
2191 #define UDPENABLE_V(x) ((x) << UDPENABLE_S)
2192 #define UDPENABLE_F UDPENABLE_V(1U)
2193
2194 #define DISABLE_S 0
2195 #define DISABLE_V(x) ((x) << DISABLE_S)
2196 #define DISABLE_F DISABLE_V(1U)
2197
2198 #define TP_RSS_CONFIG_TNL_A 0x7df4
2199
2200 #define MASKSIZE_S 28
2201 #define MASKSIZE_M 0xfU
2202 #define MASKSIZE_V(x) ((x) << MASKSIZE_S)
2203 #define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
2204
2205 #define MASKFILTER_S 16
2206 #define MASKFILTER_M 0x7ffU
2207 #define MASKFILTER_V(x) ((x) << MASKFILTER_S)
2208 #define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
2209
2210 #define USEWIRECH_S 0
2211 #define USEWIRECH_V(x) ((x) << USEWIRECH_S)
2212 #define USEWIRECH_F USEWIRECH_V(1U)
2213
2214 #define HASHALL_S 2
2215 #define HASHALL_V(x) ((x) << HASHALL_S)
2216 #define HASHALL_F HASHALL_V(1U)
2217
2218 #define HASHETH_S 1
2219 #define HASHETH_V(x) ((x) << HASHETH_S)
2220 #define HASHETH_F HASHETH_V(1U)
2221
2222 #define TP_RSS_CONFIG_OFD_A 0x7df8
2223
2224 #define RRCPLMAPEN_S 20
2225 #define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
2226 #define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
2227
2228 #define RRCPLQUEWIDTH_S 16
2229 #define RRCPLQUEWIDTH_M 0xfU
2230 #define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
2231 #define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
2232
2233 #define TP_RSS_CONFIG_SYN_A 0x7dfc
2234 #define TP_RSS_CONFIG_VRT_A 0x7e00
2235
2236 #define VFRDRG_S 25
2237 #define VFRDRG_V(x) ((x) << VFRDRG_S)
2238 #define VFRDRG_F VFRDRG_V(1U)
2239
2240 #define VFRDEN_S 24
2241 #define VFRDEN_V(x) ((x) << VFRDEN_S)
2242 #define VFRDEN_F VFRDEN_V(1U)
2243
2244 #define VFPERREN_S 23
2245 #define VFPERREN_V(x) ((x) << VFPERREN_S)
2246 #define VFPERREN_F VFPERREN_V(1U)
2247
2248 #define KEYPERREN_S 22
2249 #define KEYPERREN_V(x) ((x) << KEYPERREN_S)
2250 #define KEYPERREN_F KEYPERREN_V(1U)
2251
2252 #define DISABLEVLAN_S 21
2253 #define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
2254 #define DISABLEVLAN_F DISABLEVLAN_V(1U)
2255
2256 #define ENABLEUP0_S 20
2257 #define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
2258 #define ENABLEUP0_F ENABLEUP0_V(1U)
2259
2260 #define HASHDELAY_S 16
2261 #define HASHDELAY_M 0xfU
2262 #define HASHDELAY_V(x) ((x) << HASHDELAY_S)
2263 #define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
2264
2265 #define VFWRADDR_S 8
2266 #define VFWRADDR_M 0x7fU
2267 #define VFWRADDR_V(x) ((x) << VFWRADDR_S)
2268 #define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
2269
2270 #define KEYMODE_S 6
2271 #define KEYMODE_M 0x3U
2272 #define KEYMODE_V(x) ((x) << KEYMODE_S)
2273 #define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
2274
2275 #define VFWREN_S 5
2276 #define VFWREN_V(x) ((x) << VFWREN_S)
2277 #define VFWREN_F VFWREN_V(1U)
2278
2279 #define KEYWREN_S 4
2280 #define KEYWREN_V(x) ((x) << KEYWREN_S)
2281 #define KEYWREN_F KEYWREN_V(1U)
2282
2283 #define KEYWRADDR_S 0
2284 #define KEYWRADDR_M 0xfU
2285 #define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
2286 #define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
2287
2288 #define KEYWRADDRX_S 30
2289 #define KEYWRADDRX_M 0x3U
2290 #define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
2291 #define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
2292
2293 #define KEYEXTEND_S 26
2294 #define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
2295 #define KEYEXTEND_F KEYEXTEND_V(1U)
2296
2297 #define LKPIDXSIZE_S 24
2298 #define LKPIDXSIZE_M 0x3U
2299 #define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
2300 #define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
2301
2302 #define TP_RSS_VFL_CONFIG_A 0x3a
2303 #define TP_RSS_VFH_CONFIG_A 0x3b
2304
2305 #define ENABLEUDPHASH_S 31
2306 #define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
2307 #define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
2308
2309 #define VFUPEN_S 30
2310 #define VFUPEN_V(x) ((x) << VFUPEN_S)
2311 #define VFUPEN_F VFUPEN_V(1U)
2312
2313 #define VFVLNEX_S 28
2314 #define VFVLNEX_V(x) ((x) << VFVLNEX_S)
2315 #define VFVLNEX_F VFVLNEX_V(1U)
2316
2317 #define VFPRTEN_S 27
2318 #define VFPRTEN_V(x) ((x) << VFPRTEN_S)
2319 #define VFPRTEN_F VFPRTEN_V(1U)
2320
2321 #define VFCHNEN_S 26
2322 #define VFCHNEN_V(x) ((x) << VFCHNEN_S)
2323 #define VFCHNEN_F VFCHNEN_V(1U)
2324
2325 #define DEFAULTQUEUE_S 16
2326 #define DEFAULTQUEUE_M 0x3ffU
2327 #define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
2328
2329 #define VFIP6TWOTUPEN_S 6
2330 #define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
2331 #define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
2332
2333 #define VFIP4FOURTUPEN_S 5
2334 #define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
2335 #define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
2336
2337 #define VFIP4TWOTUPEN_S 4
2338 #define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
2339 #define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
2340
2341 #define KEYINDEX_S 0
2342 #define KEYINDEX_M 0xfU
2343 #define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2344
2345 #define MAPENABLE_S 31
2346 #define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2347 #define MAPENABLE_F MAPENABLE_V(1U)
2348
2349 #define CHNENABLE_S 30
2350 #define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2351 #define CHNENABLE_F CHNENABLE_V(1U)
2352
2353 #define LE_DB_DBGI_CONFIG_A 0x19cf0
2354
2355 #define DBGICMDBUSY_S 3
2356 #define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)
2357 #define DBGICMDBUSY_F DBGICMDBUSY_V(1U)
2358
2359 #define DBGICMDSTRT_S 2
2360 #define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)
2361 #define DBGICMDSTRT_F DBGICMDSTRT_V(1U)
2362
2363 #define DBGICMDMODE_S 0
2364 #define DBGICMDMODE_M 0x3U
2365 #define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)
2366
2367 #define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
2368
2369 #define DBGICMD_S 20
2370 #define DBGICMD_M 0xfU
2371 #define DBGICMD_V(x) ((x) << DBGICMD_S)
2372
2373 #define DBGITID_S 0
2374 #define DBGITID_M 0xfffffU
2375 #define DBGITID_V(x) ((x) << DBGITID_S)
2376
2377 #define LE_DB_DBGI_REQ_DATA_A 0x19d00
2378 #define LE_DB_DBGI_RSP_STATUS_A 0x19d94
2379
2380 #define LE_DB_DBGI_RSP_DATA_A 0x19da0
2381
2382 #define PRTENABLE_S 29
2383 #define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2384 #define PRTENABLE_F PRTENABLE_V(1U)
2385
2386 #define UDPFOURTUPEN_S 28
2387 #define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2388 #define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
2389
2390 #define IP6FOURTUPEN_S 27
2391 #define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2392 #define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
2393
2394 #define IP6TWOTUPEN_S 26
2395 #define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2396 #define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
2397
2398 #define IP4FOURTUPEN_S 25
2399 #define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2400 #define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
2401
2402 #define IP4TWOTUPEN_S 24
2403 #define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2404 #define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
2405
2406 #define IVFWIDTH_S 20
2407 #define IVFWIDTH_M 0xfU
2408 #define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2409 #define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2410
2411 #define CH1DEFAULTQUEUE_S 10
2412 #define CH1DEFAULTQUEUE_M 0x3ffU
2413 #define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2414 #define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2415
2416 #define CH0DEFAULTQUEUE_S 0
2417 #define CH0DEFAULTQUEUE_M 0x3ffU
2418 #define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2419 #define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2420
2421 #define VFLKPIDX_S 8
2422 #define VFLKPIDX_M 0xffU
2423 #define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2424
2425 #define T6_VFWRADDR_S 8
2426 #define T6_VFWRADDR_M 0xffU
2427 #define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2428 #define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2429
2430 #define TP_RSS_CONFIG_CNG_A 0x7e04
2431 #define TP_RSS_SECRET_KEY0_A 0x40
2432 #define TP_RSS_PF0_CONFIG_A 0x30
2433 #define TP_RSS_PF_MAP_A 0x38
2434 #define TP_RSS_PF_MSK_A 0x39
2435
2436 #define PF1LKPIDX_S 3
2437
2438 #define PF0LKPIDX_M 0x7U
2439
2440 #define PF1MSKSIZE_S 4
2441 #define PF1MSKSIZE_M 0xfU
2442
2443 #define CHNCOUNT3_S 31
2444 #define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2445 #define CHNCOUNT3_F CHNCOUNT3_V(1U)
2446
2447 #define CHNCOUNT2_S 30
2448 #define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2449 #define CHNCOUNT2_F CHNCOUNT2_V(1U)
2450
2451 #define CHNCOUNT1_S 29
2452 #define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2453 #define CHNCOUNT1_F CHNCOUNT1_V(1U)
2454
2455 #define CHNCOUNT0_S 28
2456 #define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2457 #define CHNCOUNT0_F CHNCOUNT0_V(1U)
2458
2459 #define CHNUNDFLOW3_S 27
2460 #define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2461 #define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
2462
2463 #define CHNUNDFLOW2_S 26
2464 #define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2465 #define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
2466
2467 #define CHNUNDFLOW1_S 25
2468 #define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2469 #define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
2470
2471 #define CHNUNDFLOW0_S 24
2472 #define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2473 #define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
2474
2475 #define RSTCHN3_S 19
2476 #define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2477 #define RSTCHN3_F RSTCHN3_V(1U)
2478
2479 #define RSTCHN2_S 18
2480 #define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2481 #define RSTCHN2_F RSTCHN2_V(1U)
2482
2483 #define RSTCHN1_S 17
2484 #define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2485 #define RSTCHN1_F RSTCHN1_V(1U)
2486
2487 #define RSTCHN0_S 16
2488 #define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2489 #define RSTCHN0_F RSTCHN0_V(1U)
2490
2491 #define UPDVLD_S 15
2492 #define UPDVLD_V(x) ((x) << UPDVLD_S)
2493 #define UPDVLD_F UPDVLD_V(1U)
2494
2495 #define XOFF_S 14
2496 #define XOFF_V(x) ((x) << XOFF_S)
2497 #define XOFF_F XOFF_V(1U)
2498
2499 #define UPDCHN3_S 13
2500 #define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2501 #define UPDCHN3_F UPDCHN3_V(1U)
2502
2503 #define UPDCHN2_S 12
2504 #define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2505 #define UPDCHN2_F UPDCHN2_V(1U)
2506
2507 #define UPDCHN1_S 11
2508 #define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2509 #define UPDCHN1_F UPDCHN1_V(1U)
2510
2511 #define UPDCHN0_S 10
2512 #define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2513 #define UPDCHN0_F UPDCHN0_V(1U)
2514
2515 #define QUEUE_S 0
2516 #define QUEUE_M 0x3ffU
2517 #define QUEUE_V(x) ((x) << QUEUE_S)
2518 #define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2519
2520 #define MPS_TRC_INT_CAUSE_A 0x985c
2521
2522 #define MISCPERR_S 8
2523 #define MISCPERR_V(x) ((x) << MISCPERR_S)
2524 #define MISCPERR_F MISCPERR_V(1U)
2525
2526 #define PKTFIFO_S 4
2527 #define PKTFIFO_M 0xfU
2528 #define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2529
2530 #define FILTMEM_S 0
2531 #define FILTMEM_M 0xfU
2532 #define FILTMEM_V(x) ((x) << FILTMEM_S)
2533
2534 #define MPS_CLS_INT_CAUSE_A 0xd028
2535
2536 #define HASHSRAM_S 2
2537 #define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2538 #define HASHSRAM_F HASHSRAM_V(1U)
2539
2540 #define MATCHTCAM_S 1
2541 #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2542 #define MATCHTCAM_F MATCHTCAM_V(1U)
2543
2544 #define MATCHSRAM_S 0
2545 #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2546 #define MATCHSRAM_F MATCHSRAM_V(1U)
2547
2548 #define MPS_RX_PG_RSV0_A 0x11010
2549 #define MPS_RX_PG_RSV4_A 0x11020
2550 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2551 #define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2552 #define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2553
2554 #define MPS_RX_VXLAN_TYPE_A 0x11234
2555
2556 #define VXLAN_EN_S 16
2557 #define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)
2558 #define VXLAN_EN_F VXLAN_EN_V(1U)
2559
2560 #define VXLAN_S 0
2561 #define VXLAN_M 0xffffU
2562 #define VXLAN_V(x) ((x) << VXLAN_S)
2563 #define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)
2564
2565 #define MPS_RX_GENEVE_TYPE_A 0x11238
2566
2567 #define GENEVE_EN_S 16
2568 #define GENEVE_EN_V(x) ((x) << GENEVE_EN_S)
2569 #define GENEVE_EN_F GENEVE_EN_V(1U)
2570
2571 #define GENEVE_S 0
2572 #define GENEVE_M 0xffffU
2573 #define GENEVE_V(x) ((x) << GENEVE_S)
2574 #define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)
2575
2576 #define MPS_CLS_TCAM_Y_L_A 0xf000
2577 #define MPS_CLS_TCAM_DATA0_A 0xf000
2578 #define MPS_CLS_TCAM_DATA1_A 0xf004
2579
2580 #define CTLREQID_S 30
2581 #define CTLREQID_V(x) ((x) << CTLREQID_S)
2582
2583 #define MPS_VF_RPLCT_MAP0_A 0x1111c
2584 #define MPS_VF_RPLCT_MAP1_A 0x11120
2585 #define MPS_VF_RPLCT_MAP2_A 0x11124
2586 #define MPS_VF_RPLCT_MAP3_A 0x11128
2587 #define MPS_VF_RPLCT_MAP4_A 0x11300
2588 #define MPS_VF_RPLCT_MAP5_A 0x11304
2589 #define MPS_VF_RPLCT_MAP6_A 0x11308
2590 #define MPS_VF_RPLCT_MAP7_A 0x1130c
2591
2592 #define VIDL_S 16
2593 #define VIDL_M 0xffffU
2594 #define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
2595
2596 #define DATALKPTYPE_S 10
2597 #define DATALKPTYPE_M 0x3U
2598 #define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2599
2600 #define DATAPORTNUM_S 12
2601 #define DATAPORTNUM_M 0xfU
2602 #define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)
2603 #define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
2604
2605 #define DATALKPTYPE_S 10
2606 #define DATALKPTYPE_M 0x3U
2607 #define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)
2608 #define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2609
2610 #define DATADIPHIT_S 8
2611 #define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
2612 #define DATADIPHIT_F DATADIPHIT_V(1U)
2613
2614 #define DATAVIDH2_S 7
2615 #define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
2616 #define DATAVIDH2_F DATAVIDH2_V(1U)
2617
2618 #define DATAVIDH1_S 0
2619 #define DATAVIDH1_M 0x7fU
2620 #define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
2621
2622 #define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
2623 #define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
2624 #define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
2625
2626 #define USED_S 16
2627 #define USED_M 0x7ffU
2628 #define USED_G(x) (((x) >> USED_S) & USED_M)
2629
2630 #define ALLOC_S 0
2631 #define ALLOC_M 0x7ffU
2632 #define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
2633
2634 #define T5_USED_S 16
2635 #define T5_USED_M 0xfffU
2636 #define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
2637
2638 #define T5_ALLOC_S 0
2639 #define T5_ALLOC_M 0xfffU
2640 #define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
2641
2642 #define DMACH_S 0
2643 #define DMACH_M 0xffffU
2644 #define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2645
2646 #define MPS_CLS_TCAM_X_L_A 0xf008
2647 #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2648
2649 #define CTLCMDTYPE_S 31
2650 #define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2651 #define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
2652
2653 #define CTLTCAMSEL_S 25
2654 #define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2655
2656 #define CTLTCAMINDEX_S 17
2657 #define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2658
2659 #define CTLXYBITSEL_S 16
2660 #define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2661
2662 #define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2663 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2664
2665 #define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2666 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2667
2668 #define MPS_CLS_SRAM_L_A 0xe000
2669
2670 #define T6_MULTILISTEN0_S 26
2671
2672 #define T6_SRAM_PRIO3_S 23
2673 #define T6_SRAM_PRIO3_M 0x7U
2674 #define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2675
2676 #define T6_SRAM_PRIO2_S 20
2677 #define T6_SRAM_PRIO2_M 0x7U
2678 #define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2679
2680 #define T6_SRAM_PRIO1_S 17
2681 #define T6_SRAM_PRIO1_M 0x7U
2682 #define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2683
2684 #define T6_SRAM_PRIO0_S 14
2685 #define T6_SRAM_PRIO0_M 0x7U
2686 #define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2687
2688 #define T6_SRAM_VLD_S 13
2689 #define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2690 #define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
2691
2692 #define T6_REPLICATE_S 12
2693 #define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2694 #define T6_REPLICATE_F T6_REPLICATE_V(1U)
2695
2696 #define T6_PF_S 9
2697 #define T6_PF_M 0x7U
2698 #define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2699
2700 #define T6_VF_VALID_S 8
2701 #define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2702 #define T6_VF_VALID_F T6_VF_VALID_V(1U)
2703
2704 #define T6_VF_S 0
2705 #define T6_VF_M 0xffU
2706 #define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2707
2708 #define MPS_CLS_SRAM_H_A 0xe004
2709
2710 #define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2711 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2712
2713 #define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2714 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2715
2716 #define MULTILISTEN0_S 25
2717
2718 #define REPLICATE_S 11
2719 #define REPLICATE_V(x) ((x) << REPLICATE_S)
2720 #define REPLICATE_F REPLICATE_V(1U)
2721
2722 #define PF_S 8
2723 #define PF_M 0x7U
2724 #define PF_G(x) (((x) >> PF_S) & PF_M)
2725
2726 #define VF_VALID_S 7
2727 #define VF_VALID_V(x) ((x) << VF_VALID_S)
2728 #define VF_VALID_F VF_VALID_V(1U)
2729
2730 #define VF_S 0
2731 #define VF_M 0x7fU
2732 #define VF_G(x) (((x) >> VF_S) & VF_M)
2733
2734 #define SRAM_PRIO3_S 22
2735 #define SRAM_PRIO3_M 0x7U
2736 #define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2737
2738 #define SRAM_PRIO2_S 19
2739 #define SRAM_PRIO2_M 0x7U
2740 #define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2741
2742 #define SRAM_PRIO1_S 16
2743 #define SRAM_PRIO1_M 0x7U
2744 #define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2745
2746 #define SRAM_PRIO0_S 13
2747 #define SRAM_PRIO0_M 0x7U
2748 #define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2749
2750 #define SRAM_VLD_S 12
2751 #define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2752 #define SRAM_VLD_F SRAM_VLD_V(1U)
2753
2754 #define PORTMAP_S 0
2755 #define PORTMAP_M 0xfU
2756 #define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2757
2758 #define CPL_INTR_CAUSE_A 0x19054
2759
2760 #define CIM_OP_MAP_PERR_S 5
2761 #define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2762 #define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
2763
2764 #define CIM_OVFL_ERROR_S 4
2765 #define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2766 #define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
2767
2768 #define TP_FRAMING_ERROR_S 3
2769 #define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2770 #define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
2771
2772 #define SGE_FRAMING_ERROR_S 2
2773 #define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2774 #define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
2775
2776 #define CIM_FRAMING_ERROR_S 1
2777 #define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2778 #define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
2779
2780 #define ZERO_SWITCH_ERROR_S 0
2781 #define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2782 #define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
2783
2784 #define SMB_INT_CAUSE_A 0x19090
2785
2786 #define MSTTXFIFOPARINT_S 21
2787 #define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2788 #define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
2789
2790 #define MSTRXFIFOPARINT_S 20
2791 #define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2792 #define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
2793
2794 #define SLVFIFOPARINT_S 19
2795 #define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2796 #define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
2797
2798 #define ULP_RX_INT_CAUSE_A 0x19158
2799 #define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2800 #define ULP_RX_ISCSI_ULIMIT_A 0x19160
2801 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2802 #define ULP_RX_ISCSI_PSZ_A 0x19168
2803 #define ULP_RX_TDDP_LLIMIT_A 0x1916c
2804 #define ULP_RX_TDDP_ULIMIT_A 0x19170
2805 #define ULP_RX_STAG_LLIMIT_A 0x1917c
2806 #define ULP_RX_STAG_ULIMIT_A 0x19180
2807 #define ULP_RX_RQ_LLIMIT_A 0x19184
2808 #define ULP_RX_RQ_ULIMIT_A 0x19188
2809 #define ULP_RX_PBL_LLIMIT_A 0x1918c
2810 #define ULP_RX_PBL_ULIMIT_A 0x19190
2811 #define ULP_RX_CTX_BASE_A 0x19194
2812 #define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2813 #define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2814 #define ULP_RX_LA_CTL_A 0x1923c
2815 #define ULP_RX_LA_RDPTR_A 0x19240
2816 #define ULP_RX_LA_RDDATA_A 0x19244
2817 #define ULP_RX_LA_WRPTR_A 0x19248
2818 #define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac
2819 #define ULP_RX_TLS_KEY_ULIMIT_A 0x192b0
2820
2821 #define HPZ3_S 24
2822 #define HPZ3_V(x) ((x) << HPZ3_S)
2823
2824 #define HPZ2_S 16
2825 #define HPZ2_V(x) ((x) << HPZ2_S)
2826
2827 #define HPZ1_S 8
2828 #define HPZ1_V(x) ((x) << HPZ1_S)
2829
2830 #define HPZ0_S 0
2831 #define HPZ0_V(x) ((x) << HPZ0_S)
2832
2833 #define ULP_RX_TDDP_PSZ_A 0x19178
2834
2835
2836 #define SF_DATA_A 0x193f8
2837 #define SF_OP_A 0x193fc
2838
2839 #define SF_BUSY_S 31
2840 #define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2841 #define SF_BUSY_F SF_BUSY_V(1U)
2842
2843 #define SF_LOCK_S 4
2844 #define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2845 #define SF_LOCK_F SF_LOCK_V(1U)
2846
2847 #define SF_CONT_S 3
2848 #define SF_CONT_V(x) ((x) << SF_CONT_S)
2849 #define SF_CONT_F SF_CONT_V(1U)
2850
2851 #define BYTECNT_S 1
2852 #define BYTECNT_V(x) ((x) << BYTECNT_S)
2853
2854 #define OP_S 0
2855 #define OP_V(x) ((x) << OP_S)
2856 #define OP_F OP_V(1U)
2857
2858 #define PL_PF_INT_CAUSE_A 0x3c0
2859
2860 #define PFSW_S 3
2861 #define PFSW_V(x) ((x) << PFSW_S)
2862 #define PFSW_F PFSW_V(1U)
2863
2864 #define PFCIM_S 1
2865 #define PFCIM_V(x) ((x) << PFCIM_S)
2866 #define PFCIM_F PFCIM_V(1U)
2867
2868 #define PL_PF_INT_ENABLE_A 0x3c4
2869 #define PL_PF_CTL_A 0x3c8
2870
2871 #define PL_WHOAMI_A 0x19400
2872
2873 #define SOURCEPF_S 8
2874 #define SOURCEPF_M 0x7U
2875 #define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2876
2877 #define T6_SOURCEPF_S 9
2878 #define T6_SOURCEPF_M 0x7U
2879 #define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
2880
2881 #define PL_INT_CAUSE_A 0x1940c
2882
2883 #define ULP_TX_S 27
2884 #define ULP_TX_V(x) ((x) << ULP_TX_S)
2885 #define ULP_TX_F ULP_TX_V(1U)
2886
2887 #define SGE_S 26
2888 #define SGE_V(x) ((x) << SGE_S)
2889 #define SGE_F SGE_V(1U)
2890
2891 #define CPL_SWITCH_S 24
2892 #define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2893 #define CPL_SWITCH_F CPL_SWITCH_V(1U)
2894
2895 #define ULP_RX_S 23
2896 #define ULP_RX_V(x) ((x) << ULP_RX_S)
2897 #define ULP_RX_F ULP_RX_V(1U)
2898
2899 #define PM_RX_S 22
2900 #define PM_RX_V(x) ((x) << PM_RX_S)
2901 #define PM_RX_F PM_RX_V(1U)
2902
2903 #define PM_TX_S 21
2904 #define PM_TX_V(x) ((x) << PM_TX_S)
2905 #define PM_TX_F PM_TX_V(1U)
2906
2907 #define MA_S 20
2908 #define MA_V(x) ((x) << MA_S)
2909 #define MA_F MA_V(1U)
2910
2911 #define TP_S 19
2912 #define TP_V(x) ((x) << TP_S)
2913 #define TP_F TP_V(1U)
2914
2915 #define LE_S 18
2916 #define LE_V(x) ((x) << LE_S)
2917 #define LE_F LE_V(1U)
2918
2919 #define EDC1_S 17
2920 #define EDC1_V(x) ((x) << EDC1_S)
2921 #define EDC1_F EDC1_V(1U)
2922
2923 #define EDC0_S 16
2924 #define EDC0_V(x) ((x) << EDC0_S)
2925 #define EDC0_F EDC0_V(1U)
2926
2927 #define MC_S 15
2928 #define MC_V(x) ((x) << MC_S)
2929 #define MC_F MC_V(1U)
2930
2931 #define PCIE_S 14
2932 #define PCIE_V(x) ((x) << PCIE_S)
2933 #define PCIE_F PCIE_V(1U)
2934
2935 #define XGMAC_KR1_S 12
2936 #define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2937 #define XGMAC_KR1_F XGMAC_KR1_V(1U)
2938
2939 #define XGMAC_KR0_S 11
2940 #define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2941 #define XGMAC_KR0_F XGMAC_KR0_V(1U)
2942
2943 #define XGMAC1_S 10
2944 #define XGMAC1_V(x) ((x) << XGMAC1_S)
2945 #define XGMAC1_F XGMAC1_V(1U)
2946
2947 #define XGMAC0_S 9
2948 #define XGMAC0_V(x) ((x) << XGMAC0_S)
2949 #define XGMAC0_F XGMAC0_V(1U)
2950
2951 #define SMB_S 8
2952 #define SMB_V(x) ((x) << SMB_S)
2953 #define SMB_F SMB_V(1U)
2954
2955 #define SF_S 7
2956 #define SF_V(x) ((x) << SF_S)
2957 #define SF_F SF_V(1U)
2958
2959 #define PL_S 6
2960 #define PL_V(x) ((x) << PL_S)
2961 #define PL_F PL_V(1U)
2962
2963 #define NCSI_S 5
2964 #define NCSI_V(x) ((x) << NCSI_S)
2965 #define NCSI_F NCSI_V(1U)
2966
2967 #define MPS_S 4
2968 #define MPS_V(x) ((x) << MPS_S)
2969 #define MPS_F MPS_V(1U)
2970
2971 #define CIM_S 0
2972 #define CIM_V(x) ((x) << CIM_S)
2973 #define CIM_F CIM_V(1U)
2974
2975 #define MC1_S 31
2976 #define MC1_V(x) ((x) << MC1_S)
2977 #define MC1_F MC1_V(1U)
2978
2979 #define PL_INT_ENABLE_A 0x19410
2980 #define PL_INT_MAP0_A 0x19414
2981 #define PL_RST_A 0x19428
2982
2983 #define PIORST_S 1
2984 #define PIORST_V(x) ((x) << PIORST_S)
2985 #define PIORST_F PIORST_V(1U)
2986
2987 #define PIORSTMODE_S 0
2988 #define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2989 #define PIORSTMODE_F PIORSTMODE_V(1U)
2990
2991 #define PL_PL_INT_CAUSE_A 0x19430
2992
2993 #define FATALPERR_S 4
2994 #define FATALPERR_V(x) ((x) << FATALPERR_S)
2995 #define FATALPERR_F FATALPERR_V(1U)
2996
2997 #define PERRVFID_S 0
2998 #define PERRVFID_V(x) ((x) << PERRVFID_S)
2999 #define PERRVFID_F PERRVFID_V(1U)
3000
3001 #define PL_REV_A 0x1943c
3002
3003 #define REV_S 0
3004 #define REV_M 0xfU
3005 #define REV_V(x) ((x) << REV_S)
3006 #define REV_G(x) (((x) >> REV_S) & REV_M)
3007
3008 #define T6_UNKNOWNCMD_S 3
3009 #define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
3010 #define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
3011
3012 #define T6_LIP0_S 2
3013 #define T6_LIP0_V(x) ((x) << T6_LIP0_S)
3014 #define T6_LIP0_F T6_LIP0_V(1U)
3015
3016 #define T6_LIPMISS_S 1
3017 #define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
3018 #define T6_LIPMISS_F T6_LIPMISS_V(1U)
3019
3020 #define LE_DB_CONFIG_A 0x19c04
3021 #define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
3022 #define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
3023 #define LE_DB_FILTER_TABLE_INDEX_A 0x19c14
3024 #define LE_DB_SERVER_INDEX_A 0x19c18
3025 #define LE_DB_SRVR_START_INDEX_A 0x19c18
3026 #define LE_DB_CLIP_TABLE_INDEX_A 0x19c1c
3027 #define LE_DB_ACT_CNT_IPV4_A 0x19c20
3028 #define LE_DB_ACT_CNT_IPV6_A 0x19c24
3029 #define LE_DB_HASH_CONFIG_A 0x19c28
3030
3031 #define HASHTIDSIZE_S 16
3032 #define HASHTIDSIZE_M 0x3fU
3033 #define HASHTIDSIZE_G(x) (((x) >> HASHTIDSIZE_S) & HASHTIDSIZE_M)
3034
3035 #define LE_DB_HASH_TID_BASE_A 0x19c30
3036 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
3037 #define LE_DB_INT_CAUSE_A 0x19c3c
3038 #define LE_DB_CLCAM_TID_BASE_A 0x19df4
3039 #define LE_DB_TID_HASHBASE_A 0x19df8
3040 #define T6_LE_DB_HASH_TID_BASE_A 0x19df8
3041
3042 #define HASHEN_S 20
3043 #define HASHEN_V(x) ((x) << HASHEN_S)
3044 #define HASHEN_F HASHEN_V(1U)
3045
3046 #define ASLIPCOMPEN_S 17
3047 #define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S)
3048 #define ASLIPCOMPEN_F ASLIPCOMPEN_V(1U)
3049
3050 #define REQQPARERR_S 16
3051 #define REQQPARERR_V(x) ((x) << REQQPARERR_S)
3052 #define REQQPARERR_F REQQPARERR_V(1U)
3053
3054 #define UNKNOWNCMD_S 15
3055 #define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
3056 #define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
3057
3058 #define PARITYERR_S 6
3059 #define PARITYERR_V(x) ((x) << PARITYERR_S)
3060 #define PARITYERR_F PARITYERR_V(1U)
3061
3062 #define LIPMISS_S 5
3063 #define LIPMISS_V(x) ((x) << LIPMISS_S)
3064 #define LIPMISS_F LIPMISS_V(1U)
3065
3066 #define LIP0_S 4
3067 #define LIP0_V(x) ((x) << LIP0_S)
3068 #define LIP0_F LIP0_V(1U)
3069
3070 #define BASEADDR_S 3
3071 #define BASEADDR_M 0x1fffffffU
3072 #define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
3073
3074 #define TCAMINTPERR_S 13
3075 #define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
3076 #define TCAMINTPERR_F TCAMINTPERR_V(1U)
3077
3078 #define SSRAMINTPERR_S 10
3079 #define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
3080 #define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
3081
3082 #define LE_DB_RSP_CODE_0_A 0x19c74
3083
3084 #define TCAM_ACTV_HIT_S 0
3085 #define TCAM_ACTV_HIT_M 0x1fU
3086 #define TCAM_ACTV_HIT_V(x) ((x) << TCAM_ACTV_HIT_S)
3087 #define TCAM_ACTV_HIT_G(x) (((x) >> TCAM_ACTV_HIT_S) & TCAM_ACTV_HIT_M)
3088
3089 #define LE_DB_RSP_CODE_1_A 0x19c78
3090
3091 #define HASH_ACTV_HIT_S 25
3092 #define HASH_ACTV_HIT_M 0x1fU
3093 #define HASH_ACTV_HIT_V(x) ((x) << HASH_ACTV_HIT_S)
3094 #define HASH_ACTV_HIT_G(x) (((x) >> HASH_ACTV_HIT_S) & HASH_ACTV_HIT_M)
3095
3096 #define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac
3097 #define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb0
3098
3099 #define NCSI_INT_CAUSE_A 0x1a0d8
3100
3101 #define CIM_DM_PRTY_ERR_S 8
3102 #define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
3103 #define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
3104
3105 #define MPS_DM_PRTY_ERR_S 7
3106 #define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
3107 #define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
3108
3109 #define TXFIFO_PRTY_ERR_S 1
3110 #define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
3111 #define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
3112
3113 #define RXFIFO_PRTY_ERR_S 0
3114 #define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
3115 #define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
3116
3117 #define XGMAC_PORT_CFG2_A 0x1018
3118
3119 #define PATEN_S 18
3120 #define PATEN_V(x) ((x) << PATEN_S)
3121 #define PATEN_F PATEN_V(1U)
3122
3123 #define MAGICEN_S 17
3124 #define MAGICEN_V(x) ((x) << MAGICEN_S)
3125 #define MAGICEN_F MAGICEN_V(1U)
3126
3127 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
3128 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
3129
3130 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
3131 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
3132 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
3133 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
3134 #define XGMAC_PORT_EPIO_OP_A 0x10d0
3135
3136 #define EPIOWR_S 8
3137 #define EPIOWR_V(x) ((x) << EPIOWR_S)
3138 #define EPIOWR_F EPIOWR_V(1U)
3139
3140 #define ADDRESS_S 0
3141 #define ADDRESS_V(x) ((x) << ADDRESS_S)
3142
3143 #define MAC_PORT_INT_CAUSE_A 0x8dc
3144 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
3145
3146 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
3147
3148 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
3149 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
3150
3151 #define TX_MOD_QUEUE_REQ_MAP_S 0
3152 #define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
3153
3154 #define TX_MODQ_WEIGHT3_S 24
3155 #define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
3156
3157 #define TX_MODQ_WEIGHT2_S 16
3158 #define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
3159
3160 #define TX_MODQ_WEIGHT1_S 8
3161 #define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
3162
3163 #define TX_MODQ_WEIGHT0_S 0
3164 #define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
3165
3166 #define TP_TX_SCHED_HDR_A 0x23
3167 #define TP_TX_SCHED_FIFO_A 0x24
3168 #define TP_TX_SCHED_PCMD_A 0x25
3169
3170 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
3171 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
3172
3173 #define T5_PORT0_BASE 0x30000
3174 #define T5_PORT_STRIDE 0x4000
3175 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
3176 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
3177
3178 #define MC_0_BASE_ADDR 0x40000
3179 #define MC_1_BASE_ADDR 0x48000
3180 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
3181 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
3182
3183 #define MC_P_BIST_CMD_A 0x41400
3184 #define MC_P_BIST_CMD_ADDR_A 0x41404
3185 #define MC_P_BIST_CMD_LEN_A 0x41408
3186 #define MC_P_BIST_DATA_PATTERN_A 0x4140c
3187 #define MC_P_BIST_STATUS_RDATA_A 0x41488
3188
3189 #define EDC_T50_BASE_ADDR 0x50000
3190
3191 #define EDC_H_BIST_CMD_A 0x50004
3192 #define EDC_H_BIST_CMD_ADDR_A 0x50008
3193 #define EDC_H_BIST_CMD_LEN_A 0x5000c
3194 #define EDC_H_BIST_DATA_PATTERN_A 0x50010
3195 #define EDC_H_BIST_STATUS_RDATA_A 0x50028
3196
3197 #define EDC_H_ECC_ERR_ADDR_A 0x50084
3198 #define EDC_T51_BASE_ADDR 0x50800
3199
3200 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
3201 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
3202
3203 #define PL_VF_REV_A 0x4
3204 #define PL_VF_WHOAMI_A 0x0
3205 #define PL_VF_REVISION_A 0x8
3206
3207
3208 #define CIM_HOST_ACC_CTRL_A 0x7b50
3209 #define CIM_HOST_ACC_DATA_A 0x7b54
3210 #define UP_UP_DBG_LA_CFG_A 0x140
3211 #define UP_UP_DBG_LA_DATA_A 0x144
3212
3213 #define HOSTBUSY_S 17
3214 #define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
3215 #define HOSTBUSY_F HOSTBUSY_V(1U)
3216
3217 #define HOSTWRITE_S 16
3218 #define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
3219 #define HOSTWRITE_F HOSTWRITE_V(1U)
3220
3221 #define CIM_IBQ_DBG_CFG_A 0x7b60
3222
3223 #define IBQDBGADDR_S 16
3224 #define IBQDBGADDR_M 0xfffU
3225 #define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
3226 #define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
3227
3228 #define IBQDBGBUSY_S 1
3229 #define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
3230 #define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
3231
3232 #define IBQDBGEN_S 0
3233 #define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
3234 #define IBQDBGEN_F IBQDBGEN_V(1U)
3235
3236 #define CIM_OBQ_DBG_CFG_A 0x7b64
3237
3238 #define OBQDBGADDR_S 16
3239 #define OBQDBGADDR_M 0xfffU
3240 #define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
3241 #define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
3242
3243 #define OBQDBGBUSY_S 1
3244 #define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
3245 #define OBQDBGBUSY_F OBQDBGBUSY_V(1U)
3246
3247 #define OBQDBGEN_S 0
3248 #define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
3249 #define OBQDBGEN_F OBQDBGEN_V(1U)
3250
3251 #define CIM_IBQ_DBG_DATA_A 0x7b68
3252 #define CIM_OBQ_DBG_DATA_A 0x7b6c
3253 #define CIM_DEBUGCFG_A 0x7b70
3254 #define CIM_DEBUGSTS_A 0x7b74
3255
3256 #define POLADBGRDPTR_S 23
3257 #define POLADBGRDPTR_M 0x1ffU
3258 #define POLADBGRDPTR_V(x) ((x) << POLADBGRDPTR_S)
3259
3260 #define POLADBGWRPTR_S 16
3261 #define POLADBGWRPTR_M 0x1ffU
3262 #define POLADBGWRPTR_G(x) (((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)
3263
3264 #define PILADBGRDPTR_S 14
3265 #define PILADBGRDPTR_M 0x1ffU
3266 #define PILADBGRDPTR_V(x) ((x) << PILADBGRDPTR_S)
3267
3268 #define PILADBGWRPTR_S 0
3269 #define PILADBGWRPTR_M 0x1ffU
3270 #define PILADBGWRPTR_G(x) (((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)
3271
3272 #define LADBGEN_S 12
3273 #define LADBGEN_V(x) ((x) << LADBGEN_S)
3274 #define LADBGEN_F LADBGEN_V(1U)
3275
3276 #define CIM_PO_LA_DEBUGDATA_A 0x7b78
3277 #define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3278 #define CIM_PO_LA_MADEBUGDATA_A 0x7b80
3279 #define CIM_PI_LA_MADEBUGDATA_A 0x7b84
3280
3281 #define UPDBGLARDEN_S 1
3282 #define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
3283 #define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
3284
3285 #define UPDBGLAEN_S 0
3286 #define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
3287 #define UPDBGLAEN_F UPDBGLAEN_V(1U)
3288
3289 #define UPDBGLARDPTR_S 2
3290 #define UPDBGLARDPTR_M 0xfffU
3291 #define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
3292
3293 #define UPDBGLAWRPTR_S 16
3294 #define UPDBGLAWRPTR_M 0xfffU
3295 #define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
3296
3297 #define UPDBGLACAPTPCONLY_S 30
3298 #define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
3299 #define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
3300
3301 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
3302 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3303
3304 #define CIMQSIZE_S 24
3305 #define CIMQSIZE_M 0x3fU
3306 #define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
3307
3308 #define CIMQBASE_S 16
3309 #define CIMQBASE_M 0x3fU
3310 #define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
3311
3312 #define QUEFULLTHRSH_S 0
3313 #define QUEFULLTHRSH_M 0x1ffU
3314 #define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
3315
3316 #define UP_IBQ_0_RDADDR_A 0x10
3317 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3318 #define UP_OBQ_0_REALADDR_A 0x104
3319 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3320
3321 #define IBQRDADDR_S 0
3322 #define IBQRDADDR_M 0x1fffU
3323 #define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
3324
3325 #define IBQWRADDR_S 0
3326 #define IBQWRADDR_M 0x1fffU
3327 #define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
3328
3329 #define QUERDADDR_S 0
3330 #define QUERDADDR_M 0x7fffU
3331 #define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
3332
3333 #define QUEREMFLITS_S 0
3334 #define QUEREMFLITS_M 0x7ffU
3335 #define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
3336
3337 #define QUEEOPCNT_S 16
3338 #define QUEEOPCNT_M 0xfffU
3339 #define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
3340
3341 #define QUESOPCNT_S 0
3342 #define QUESOPCNT_M 0xfffU
3343 #define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
3344
3345 #define OBQSELECT_S 4
3346 #define OBQSELECT_V(x) ((x) << OBQSELECT_S)
3347 #define OBQSELECT_F OBQSELECT_V(1U)
3348
3349 #define IBQSELECT_S 3
3350 #define IBQSELECT_V(x) ((x) << IBQSELECT_S)
3351 #define IBQSELECT_F IBQSELECT_V(1U)
3352
3353 #define QUENUMSELECT_S 0
3354 #define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
3355
3356 #endif