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35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37
38 enum fw_retval {
39 FW_SUCCESS = 0,
40 FW_EPERM = 1,
41 FW_ENOENT = 2,
42 FW_EIO = 5,
43 FW_ENOEXEC = 8,
44 FW_EAGAIN = 11,
45 FW_ENOMEM = 12,
46 FW_EFAULT = 14,
47 FW_EBUSY = 16,
48 FW_EEXIST = 17,
49 FW_ENODEV = 19,
50 FW_EINVAL = 22,
51 FW_ENOSPC = 28,
52 FW_ENOSYS = 38,
53 FW_ENODATA = 61,
54 FW_EPROTO = 71,
55 FW_EADDRINUSE = 98,
56 FW_EADDRNOTAVAIL = 99,
57 FW_ENETDOWN = 100,
58 FW_ENETUNREACH = 101,
59 FW_ENOBUFS = 105,
60 FW_ETIMEDOUT = 110,
61 FW_EINPROGRESS = 115,
62 FW_SCSI_ABORT_REQUESTED = 128,
63 FW_SCSI_ABORT_TIMEDOUT = 129,
64 FW_SCSI_ABORTED = 130,
65 FW_SCSI_CLOSE_REQUESTED = 131,
66 FW_ERR_LINK_DOWN = 132,
67 FW_RDEV_NOT_READY = 133,
68 FW_ERR_RDEV_LOST = 134,
69 FW_ERR_RDEV_LOGO = 135,
70 FW_FCOE_NO_XCHG = 136,
71 FW_SCSI_RSP_ERR = 137,
72 FW_ERR_RDEV_IMPL_LOGO = 138,
73 FW_SCSI_UNDER_FLOW_ERR = 139,
74 FW_SCSI_OVER_FLOW_ERR = 140,
75 FW_SCSI_DDP_ERR = 141,
76 FW_SCSI_TASK_ERR = 142,
77 };
78
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
84
85 enum fw_wr_opcodes {
86 FW_FILTER_WR = 0x02,
87 FW_ULPTX_WR = 0x04,
88 FW_TP_WR = 0x05,
89 FW_ETH_TX_PKT_WR = 0x08,
90 FW_OFLD_CONNECTION_WR = 0x2f,
91 FW_FLOWC_WR = 0x0a,
92 FW_OFLD_TX_DATA_WR = 0x0b,
93 FW_CMD_WR = 0x10,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RES_WR = 0x0c,
96 FW_RI_INIT_WR = 0x0d,
97 FW_RI_RDMA_WRITE_WR = 0x14,
98 FW_RI_SEND_WR = 0x15,
99 FW_RI_RDMA_READ_WR = 0x16,
100 FW_RI_RECV_WR = 0x17,
101 FW_RI_BIND_MW_WR = 0x18,
102 FW_RI_FR_NSMR_WR = 0x19,
103 FW_RI_FR_NSMR_TPTE_WR = 0x20,
104 FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
105 FW_RI_INV_LSTAG_WR = 0x1a,
106 FW_ISCSI_TX_DATA_WR = 0x45,
107 FW_PTP_TX_PKT_WR = 0x46,
108 FW_TLSTX_DATA_WR = 0x68,
109 FW_CRYPTO_LOOKASIDE_WR = 0X6d,
110 FW_LASTC2E_WR = 0x70,
111 FW_FILTER2_WR = 0x77
112 };
113
114 struct fw_wr_hdr {
115 __be32 hi;
116 __be32 lo;
117 };
118
119
120 #define FW_WR_OP_S 24
121 #define FW_WR_OP_M 0xff
122 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
123 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
124
125
126 #define FW_WR_ATOMIC_S 23
127 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
128
129
130
131
132 #define FW_WR_FLUSH_S 22
133 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
134
135
136 #define FW_WR_COMPL_S 21
137 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
138 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
139
140
141 #define FW_WR_IMMDLEN_S 0
142 #define FW_WR_IMMDLEN_M 0xff
143 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
144
145
146 #define FW_WR_EQUIQ_S 31
147 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
148 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
149
150
151 #define FW_WR_EQUEQ_S 30
152 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
153 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
154
155
156 #define FW_WR_FLOWID_S 8
157 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
158
159
160 #define FW_WR_LEN16_S 0
161 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
162
163 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
164 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
165
166
167 enum fw_filter_wr_cookie {
168 FW_FILTER_WR_SUCCESS,
169 FW_FILTER_WR_FLT_ADDED,
170 FW_FILTER_WR_FLT_DELETED,
171 FW_FILTER_WR_SMT_TBL_FULL,
172 FW_FILTER_WR_EINVAL,
173 };
174
175 struct fw_filter_wr {
176 __be32 op_pkd;
177 __be32 len16_pkd;
178 __be64 r3;
179 __be32 tid_to_iq;
180 __be32 del_filter_to_l2tix;
181 __be16 ethtype;
182 __be16 ethtypem;
183 __u8 frag_to_ovlan_vldm;
184 __u8 smac_sel;
185 __be16 rx_chan_rx_rpl_iq;
186 __be32 maci_to_matchtypem;
187 __u8 ptcl;
188 __u8 ptclm;
189 __u8 ttyp;
190 __u8 ttypm;
191 __be16 ivlan;
192 __be16 ivlanm;
193 __be16 ovlan;
194 __be16 ovlanm;
195 __u8 lip[16];
196 __u8 lipm[16];
197 __u8 fip[16];
198 __u8 fipm[16];
199 __be16 lp;
200 __be16 lpm;
201 __be16 fp;
202 __be16 fpm;
203 __be16 r7;
204 __u8 sma[6];
205 };
206
207 struct fw_filter2_wr {
208 __be32 op_pkd;
209 __be32 len16_pkd;
210 __be64 r3;
211 __be32 tid_to_iq;
212 __be32 del_filter_to_l2tix;
213 __be16 ethtype;
214 __be16 ethtypem;
215 __u8 frag_to_ovlan_vldm;
216 __u8 smac_sel;
217 __be16 rx_chan_rx_rpl_iq;
218 __be32 maci_to_matchtypem;
219 __u8 ptcl;
220 __u8 ptclm;
221 __u8 ttyp;
222 __u8 ttypm;
223 __be16 ivlan;
224 __be16 ivlanm;
225 __be16 ovlan;
226 __be16 ovlanm;
227 __u8 lip[16];
228 __u8 lipm[16];
229 __u8 fip[16];
230 __u8 fipm[16];
231 __be16 lp;
232 __be16 lpm;
233 __be16 fp;
234 __be16 fpm;
235 __be16 r7;
236 __u8 sma[6];
237 __be16 r8;
238 __u8 filter_type_swapmac;
239 __u8 natmode_to_ulp_type;
240 __be16 newlport;
241 __be16 newfport;
242 __u8 newlip[16];
243 __u8 newfip[16];
244 __be32 natseqcheck;
245 __be32 r9;
246 __be64 r10;
247 __be64 r11;
248 __be64 r12;
249 __be64 r13;
250 };
251
252 #define FW_FILTER_WR_TID_S 12
253 #define FW_FILTER_WR_TID_M 0xfffff
254 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
255 #define FW_FILTER_WR_TID_G(x) \
256 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
257
258 #define FW_FILTER_WR_RQTYPE_S 11
259 #define FW_FILTER_WR_RQTYPE_M 0x1
260 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
261 #define FW_FILTER_WR_RQTYPE_G(x) \
262 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
263 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
264
265 #define FW_FILTER_WR_NOREPLY_S 10
266 #define FW_FILTER_WR_NOREPLY_M 0x1
267 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
268 #define FW_FILTER_WR_NOREPLY_G(x) \
269 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
270 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
271
272 #define FW_FILTER_WR_IQ_S 0
273 #define FW_FILTER_WR_IQ_M 0x3ff
274 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
275 #define FW_FILTER_WR_IQ_G(x) \
276 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
277
278 #define FW_FILTER_WR_DEL_FILTER_S 31
279 #define FW_FILTER_WR_DEL_FILTER_M 0x1
280 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
281 #define FW_FILTER_WR_DEL_FILTER_G(x) \
282 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
283 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
284
285 #define FW_FILTER_WR_RPTTID_S 25
286 #define FW_FILTER_WR_RPTTID_M 0x1
287 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
288 #define FW_FILTER_WR_RPTTID_G(x) \
289 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
290 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
291
292 #define FW_FILTER_WR_DROP_S 24
293 #define FW_FILTER_WR_DROP_M 0x1
294 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
295 #define FW_FILTER_WR_DROP_G(x) \
296 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
297 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
298
299 #define FW_FILTER_WR_DIRSTEER_S 23
300 #define FW_FILTER_WR_DIRSTEER_M 0x1
301 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
302 #define FW_FILTER_WR_DIRSTEER_G(x) \
303 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
304 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
305
306 #define FW_FILTER_WR_MASKHASH_S 22
307 #define FW_FILTER_WR_MASKHASH_M 0x1
308 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
309 #define FW_FILTER_WR_MASKHASH_G(x) \
310 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
311 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
312
313 #define FW_FILTER_WR_DIRSTEERHASH_S 21
314 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
315 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
316 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
317 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
318 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
319
320 #define FW_FILTER_WR_LPBK_S 20
321 #define FW_FILTER_WR_LPBK_M 0x1
322 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
323 #define FW_FILTER_WR_LPBK_G(x) \
324 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
325 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
326
327 #define FW_FILTER_WR_DMAC_S 19
328 #define FW_FILTER_WR_DMAC_M 0x1
329 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
330 #define FW_FILTER_WR_DMAC_G(x) \
331 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
332 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
333
334 #define FW_FILTER_WR_SMAC_S 18
335 #define FW_FILTER_WR_SMAC_M 0x1
336 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
337 #define FW_FILTER_WR_SMAC_G(x) \
338 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
339 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
340
341 #define FW_FILTER_WR_INSVLAN_S 17
342 #define FW_FILTER_WR_INSVLAN_M 0x1
343 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
344 #define FW_FILTER_WR_INSVLAN_G(x) \
345 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
346 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
347
348 #define FW_FILTER_WR_RMVLAN_S 16
349 #define FW_FILTER_WR_RMVLAN_M 0x1
350 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
351 #define FW_FILTER_WR_RMVLAN_G(x) \
352 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
353 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
354
355 #define FW_FILTER_WR_HITCNTS_S 15
356 #define FW_FILTER_WR_HITCNTS_M 0x1
357 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
358 #define FW_FILTER_WR_HITCNTS_G(x) \
359 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
360 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
361
362 #define FW_FILTER_WR_TXCHAN_S 13
363 #define FW_FILTER_WR_TXCHAN_M 0x3
364 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
365 #define FW_FILTER_WR_TXCHAN_G(x) \
366 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
367
368 #define FW_FILTER_WR_PRIO_S 12
369 #define FW_FILTER_WR_PRIO_M 0x1
370 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
371 #define FW_FILTER_WR_PRIO_G(x) \
372 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
373 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
374
375 #define FW_FILTER_WR_L2TIX_S 0
376 #define FW_FILTER_WR_L2TIX_M 0xfff
377 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
378 #define FW_FILTER_WR_L2TIX_G(x) \
379 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
380
381 #define FW_FILTER_WR_FRAG_S 7
382 #define FW_FILTER_WR_FRAG_M 0x1
383 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
384 #define FW_FILTER_WR_FRAG_G(x) \
385 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
386 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
387
388 #define FW_FILTER_WR_FRAGM_S 6
389 #define FW_FILTER_WR_FRAGM_M 0x1
390 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
391 #define FW_FILTER_WR_FRAGM_G(x) \
392 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
393 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
394
395 #define FW_FILTER_WR_IVLAN_VLD_S 5
396 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
397 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
398 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
399 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
400 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
401
402 #define FW_FILTER_WR_OVLAN_VLD_S 4
403 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
404 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
405 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
406 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
407 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
408
409 #define FW_FILTER_WR_IVLAN_VLDM_S 3
410 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
411 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
412 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
413 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
414 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
415
416 #define FW_FILTER_WR_OVLAN_VLDM_S 2
417 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
418 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
419 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
420 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
421 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
422
423 #define FW_FILTER_WR_RX_CHAN_S 15
424 #define FW_FILTER_WR_RX_CHAN_M 0x1
425 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
426 #define FW_FILTER_WR_RX_CHAN_G(x) \
427 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
428 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
429
430 #define FW_FILTER_WR_RX_RPL_IQ_S 0
431 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
432 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
433 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
434 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
435
436 #define FW_FILTER2_WR_FILTER_TYPE_S 1
437 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1
438 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
439 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \
440 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
441 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U)
442
443 #define FW_FILTER2_WR_NATMODE_S 5
444 #define FW_FILTER2_WR_NATMODE_M 0x7
445 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)
446 #define FW_FILTER2_WR_NATMODE_G(x) \
447 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
448
449 #define FW_FILTER2_WR_NATFLAGCHECK_S 4
450 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1
451 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
452 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
453 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
454 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U)
455
456 #define FW_FILTER2_WR_ULP_TYPE_S 0
457 #define FW_FILTER2_WR_ULP_TYPE_M 0xf
458 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)
459 #define FW_FILTER2_WR_ULP_TYPE_G(x) \
460 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
461
462 #define FW_FILTER_WR_MACI_S 23
463 #define FW_FILTER_WR_MACI_M 0x1ff
464 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
465 #define FW_FILTER_WR_MACI_G(x) \
466 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
467
468 #define FW_FILTER_WR_MACIM_S 14
469 #define FW_FILTER_WR_MACIM_M 0x1ff
470 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
471 #define FW_FILTER_WR_MACIM_G(x) \
472 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
473
474 #define FW_FILTER_WR_FCOE_S 13
475 #define FW_FILTER_WR_FCOE_M 0x1
476 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
477 #define FW_FILTER_WR_FCOE_G(x) \
478 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
479 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
480
481 #define FW_FILTER_WR_FCOEM_S 12
482 #define FW_FILTER_WR_FCOEM_M 0x1
483 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
484 #define FW_FILTER_WR_FCOEM_G(x) \
485 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
486 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
487
488 #define FW_FILTER_WR_PORT_S 9
489 #define FW_FILTER_WR_PORT_M 0x7
490 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
491 #define FW_FILTER_WR_PORT_G(x) \
492 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
493
494 #define FW_FILTER_WR_PORTM_S 6
495 #define FW_FILTER_WR_PORTM_M 0x7
496 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
497 #define FW_FILTER_WR_PORTM_G(x) \
498 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
499
500 #define FW_FILTER_WR_MATCHTYPE_S 3
501 #define FW_FILTER_WR_MATCHTYPE_M 0x7
502 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
503 #define FW_FILTER_WR_MATCHTYPE_G(x) \
504 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
505
506 #define FW_FILTER_WR_MATCHTYPEM_S 0
507 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
508 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
509 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
510 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
511
512 struct fw_ulptx_wr {
513 __be32 op_to_compl;
514 __be32 flowid_len16;
515 u64 cookie;
516 };
517
518 #define FW_ULPTX_WR_DATA_S 28
519 #define FW_ULPTX_WR_DATA_M 0x1
520 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S)
521 #define FW_ULPTX_WR_DATA_G(x) \
522 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
523 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U)
524
525 struct fw_tp_wr {
526 __be32 op_to_immdlen;
527 __be32 flowid_len16;
528 u64 cookie;
529 };
530
531 struct fw_eth_tx_pkt_wr {
532 __be32 op_immdlen;
533 __be32 equiq_to_len16;
534 __be64 r3;
535 };
536
537 struct fw_ofld_connection_wr {
538 __be32 op_compl;
539 __be32 len16_pkd;
540 __u64 cookie;
541 __be64 r2;
542 __be64 r3;
543 struct fw_ofld_connection_le {
544 __be32 version_cpl;
545 __be32 filter;
546 __be32 r1;
547 __be16 lport;
548 __be16 pport;
549 union fw_ofld_connection_leip {
550 struct fw_ofld_connection_le_ipv4 {
551 __be32 pip;
552 __be32 lip;
553 __be64 r0;
554 __be64 r1;
555 __be64 r2;
556 } ipv4;
557 struct fw_ofld_connection_le_ipv6 {
558 __be64 pip_hi;
559 __be64 pip_lo;
560 __be64 lip_hi;
561 __be64 lip_lo;
562 } ipv6;
563 } u;
564 } le;
565 struct fw_ofld_connection_tcb {
566 __be32 t_state_to_astid;
567 __be16 cplrxdataack_cplpassacceptrpl;
568 __be16 rcv_adv;
569 __be32 rcv_nxt;
570 __be32 tx_max;
571 __be64 opt0;
572 __be32 opt2;
573 __be32 r1;
574 __be64 r2;
575 __be64 r3;
576 } tcb;
577 };
578
579 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
580 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
581 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
582 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
583 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
584 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
585 FW_OFLD_CONNECTION_WR_VERSION_M)
586 #define FW_OFLD_CONNECTION_WR_VERSION_F \
587 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
588
589 #define FW_OFLD_CONNECTION_WR_CPL_S 30
590 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
591 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
592 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
593 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
594 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
595
596 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
597 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
598 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
599 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
600 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
601 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
602 FW_OFLD_CONNECTION_WR_T_STATE_M)
603
604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
605 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
607 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
608 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
609 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
610 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
611
612 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
613 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
614 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
615 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
616 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
617 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
618
619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
620 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
622 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
623 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
624 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
625 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
626 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
627 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
628
629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
630 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
632 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
633 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
634 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
635 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
636 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
637 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
638
639 enum fw_flowc_mnem_tcpstate {
640 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0,
641 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1,
642 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2,
643 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3,
644 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4,
645 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5,
646 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6,
647
648
649 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7,
650
651
652
653 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8,
654
655
656
657 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9,
658
659
660 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10,
661 };
662
663 enum fw_flowc_mnem {
664 FW_FLOWC_MNEM_PFNVFN,
665 FW_FLOWC_MNEM_CH,
666 FW_FLOWC_MNEM_PORT,
667 FW_FLOWC_MNEM_IQID,
668 FW_FLOWC_MNEM_SNDNXT,
669 FW_FLOWC_MNEM_RCVNXT,
670 FW_FLOWC_MNEM_SNDBUF,
671 FW_FLOWC_MNEM_MSS,
672 FW_FLOWC_MNEM_TXDATAPLEN_MAX,
673 FW_FLOWC_MNEM_TCPSTATE,
674 FW_FLOWC_MNEM_EOSTATE,
675 FW_FLOWC_MNEM_SCHEDCLASS,
676 FW_FLOWC_MNEM_DCBPRIO,
677 FW_FLOWC_MNEM_SND_SCALE,
678 FW_FLOWC_MNEM_RCV_SCALE,
679 FW_FLOWC_MNEM_ULD_MODE,
680 FW_FLOWC_MNEM_MAX,
681 };
682
683 struct fw_flowc_mnemval {
684 u8 mnemonic;
685 u8 r4[3];
686 __be32 val;
687 };
688
689 struct fw_flowc_wr {
690 __be32 op_to_nparams;
691 __be32 flowid_len16;
692 struct fw_flowc_mnemval mnemval[0];
693 };
694
695 #define FW_FLOWC_WR_NPARAMS_S 0
696 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
697
698 struct fw_ofld_tx_data_wr {
699 __be32 op_to_immdlen;
700 __be32 flowid_len16;
701 __be32 plen;
702 __be32 tunnel_to_proxy;
703 };
704
705 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30
706 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
707 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
708
709 #define FW_OFLD_TX_DATA_WR_SHOVE_S 29
710 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
711 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
712
713 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
714 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
715
716 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
717 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
718
719 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
720 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
721 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
722
723 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
724 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
725
726 #define FW_OFLD_TX_DATA_WR_MORE_S 15
727 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
728
729 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
730 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
731
732 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
733 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
734 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
735
736 struct fw_cmd_wr {
737 __be32 op_dma;
738 __be32 len16_pkd;
739 __be64 cookie_daddr;
740 };
741
742 #define FW_CMD_WR_DMA_S 17
743 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
744
745 struct fw_eth_tx_pkt_vm_wr {
746 __be32 op_immdlen;
747 __be32 equiq_to_len16;
748 __be32 r3[2];
749 u8 ethmacdst[6];
750 u8 ethmacsrc[6];
751 __be16 ethtype;
752 __be16 vlantci;
753 };
754
755 #define FW_CMD_MAX_TIMEOUT 10000
756
757
758
759
760
761
762
763
764 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
765 #define FW_CMD_HELLO_RETRIES 3
766
767
768 enum fw_cmd_opcodes {
769 FW_LDST_CMD = 0x01,
770 FW_RESET_CMD = 0x03,
771 FW_HELLO_CMD = 0x04,
772 FW_BYE_CMD = 0x05,
773 FW_INITIALIZE_CMD = 0x06,
774 FW_CAPS_CONFIG_CMD = 0x07,
775 FW_PARAMS_CMD = 0x08,
776 FW_PFVF_CMD = 0x09,
777 FW_IQ_CMD = 0x10,
778 FW_EQ_MNGT_CMD = 0x11,
779 FW_EQ_ETH_CMD = 0x12,
780 FW_EQ_CTRL_CMD = 0x13,
781 FW_EQ_OFLD_CMD = 0x21,
782 FW_VI_CMD = 0x14,
783 FW_VI_MAC_CMD = 0x15,
784 FW_VI_RXMODE_CMD = 0x16,
785 FW_VI_ENABLE_CMD = 0x17,
786 FW_ACL_MAC_CMD = 0x18,
787 FW_ACL_VLAN_CMD = 0x19,
788 FW_VI_STATS_CMD = 0x1a,
789 FW_PORT_CMD = 0x1b,
790 FW_PORT_STATS_CMD = 0x1c,
791 FW_PORT_LB_STATS_CMD = 0x1d,
792 FW_PORT_TRACE_CMD = 0x1e,
793 FW_PORT_TRACE_MMAP_CMD = 0x1f,
794 FW_RSS_IND_TBL_CMD = 0x20,
795 FW_RSS_GLB_CONFIG_CMD = 0x22,
796 FW_RSS_VI_CONFIG_CMD = 0x23,
797 FW_SCHED_CMD = 0x24,
798 FW_DEVLOG_CMD = 0x25,
799 FW_CLIP_CMD = 0x28,
800 FW_PTP_CMD = 0x3e,
801 FW_HMA_CMD = 0x3f,
802 FW_LASTC2E_CMD = 0x40,
803 FW_ERROR_CMD = 0x80,
804 FW_DEBUG_CMD = 0x81,
805 };
806
807 enum fw_cmd_cap {
808 FW_CMD_CAP_PF = 0x01,
809 FW_CMD_CAP_DMAQ = 0x02,
810 FW_CMD_CAP_PORT = 0x04,
811 FW_CMD_CAP_PORTPROMISC = 0x08,
812 FW_CMD_CAP_PORTSTATS = 0x10,
813 FW_CMD_CAP_VF = 0x80,
814 };
815
816
817
818
819 struct fw_cmd_hdr {
820 __be32 hi;
821 __be32 lo;
822 };
823
824 #define FW_CMD_OP_S 24
825 #define FW_CMD_OP_M 0xff
826 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
827 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
828
829 #define FW_CMD_REQUEST_S 23
830 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
831 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
832
833 #define FW_CMD_READ_S 22
834 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
835 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
836
837 #define FW_CMD_WRITE_S 21
838 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
839 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
840
841 #define FW_CMD_EXEC_S 20
842 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
843 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
844
845 #define FW_CMD_RAMASK_S 20
846 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
847
848 #define FW_CMD_RETVAL_S 8
849 #define FW_CMD_RETVAL_M 0xff
850 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
851 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
852
853 #define FW_CMD_LEN16_S 0
854 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
855
856 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
857
858 enum fw_ldst_addrspc {
859 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
860 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
861 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
862 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
863 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
864 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
865 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
866 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
867 FW_LDST_ADDRSPC_MDIO = 0x0018,
868 FW_LDST_ADDRSPC_MPS = 0x0020,
869 FW_LDST_ADDRSPC_FUNC = 0x0028,
870 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
871 FW_LDST_ADDRSPC_I2C = 0x0038,
872 };
873
874 enum fw_ldst_mps_fid {
875 FW_LDST_MPS_ATRB,
876 FW_LDST_MPS_RPLC
877 };
878
879 enum fw_ldst_func_access_ctl {
880 FW_LDST_FUNC_ACC_CTL_VIID,
881 FW_LDST_FUNC_ACC_CTL_FID
882 };
883
884 enum fw_ldst_func_mod_index {
885 FW_LDST_FUNC_MPS
886 };
887
888 struct fw_ldst_cmd {
889 __be32 op_to_addrspace;
890 __be32 cycles_to_len16;
891 union fw_ldst {
892 struct fw_ldst_addrval {
893 __be32 addr;
894 __be32 val;
895 } addrval;
896 struct fw_ldst_idctxt {
897 __be32 physid;
898 __be32 msg_ctxtflush;
899 __be32 ctxt_data7;
900 __be32 ctxt_data6;
901 __be32 ctxt_data5;
902 __be32 ctxt_data4;
903 __be32 ctxt_data3;
904 __be32 ctxt_data2;
905 __be32 ctxt_data1;
906 __be32 ctxt_data0;
907 } idctxt;
908 struct fw_ldst_mdio {
909 __be16 paddr_mmd;
910 __be16 raddr;
911 __be16 vctl;
912 __be16 rval;
913 } mdio;
914 struct fw_ldst_cim_rq {
915 u8 req_first64[8];
916 u8 req_second64[8];
917 u8 resp_first64[8];
918 u8 resp_second64[8];
919 __be32 r3[2];
920 } cim_rq;
921 union fw_ldst_mps {
922 struct fw_ldst_mps_rplc {
923 __be16 fid_idx;
924 __be16 rplcpf_pkd;
925 __be32 rplc255_224;
926 __be32 rplc223_192;
927 __be32 rplc191_160;
928 __be32 rplc159_128;
929 __be32 rplc127_96;
930 __be32 rplc95_64;
931 __be32 rplc63_32;
932 __be32 rplc31_0;
933 } rplc;
934 struct fw_ldst_mps_atrb {
935 __be16 fid_mpsid;
936 __be16 r2[3];
937 __be32 r3[2];
938 __be32 r4;
939 __be32 atrb;
940 __be16 vlan[16];
941 } atrb;
942 } mps;
943 struct fw_ldst_func {
944 u8 access_ctl;
945 u8 mod_index;
946 __be16 ctl_id;
947 __be32 offset;
948 __be64 data0;
949 __be64 data1;
950 } func;
951 struct fw_ldst_pcie {
952 u8 ctrl_to_fn;
953 u8 bnum;
954 u8 r;
955 u8 ext_r;
956 u8 select_naccess;
957 u8 pcie_fn;
958 __be16 nset_pkd;
959 __be32 data[12];
960 } pcie;
961 struct fw_ldst_i2c_deprecated {
962 u8 pid_pkd;
963 u8 base;
964 u8 boffset;
965 u8 data;
966 __be32 r9;
967 } i2c_deprecated;
968 struct fw_ldst_i2c {
969 u8 pid;
970 u8 did;
971 u8 boffset;
972 u8 blen;
973 __be32 r9;
974 __u8 data[48];
975 } i2c;
976 struct fw_ldst_le {
977 __be32 index;
978 __be32 r9;
979 u8 val[33];
980 u8 r11[7];
981 } le;
982 } u;
983 };
984
985 #define FW_LDST_CMD_ADDRSPACE_S 0
986 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)
987
988 #define FW_LDST_CMD_MSG_S 31
989 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)
990
991 #define FW_LDST_CMD_CTXTFLUSH_S 30
992 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)
993 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U)
994
995 #define FW_LDST_CMD_PADDR_S 8
996 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
997
998 #define FW_LDST_CMD_MMD_S 0
999 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)
1000
1001 #define FW_LDST_CMD_FID_S 15
1002 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
1003
1004 #define FW_LDST_CMD_IDX_S 0
1005 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)
1006
1007 #define FW_LDST_CMD_RPLCPF_S 0
1008 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
1009
1010 #define FW_LDST_CMD_LC_S 4
1011 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)
1012 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)
1013
1014 #define FW_LDST_CMD_FN_S 0
1015 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)
1016
1017 #define FW_LDST_CMD_NACCESS_S 0
1018 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)
1019
1020 struct fw_reset_cmd {
1021 __be32 op_to_write;
1022 __be32 retval_len16;
1023 __be32 val;
1024 __be32 halt_pkd;
1025 };
1026
1027 #define FW_RESET_CMD_HALT_S 31
1028 #define FW_RESET_CMD_HALT_M 0x1
1029 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)
1030 #define FW_RESET_CMD_HALT_G(x) \
1031 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1032 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)
1033
1034 enum fw_hellow_cmd {
1035 fw_hello_cmd_stage_os = 0x0
1036 };
1037
1038 struct fw_hello_cmd {
1039 __be32 op_to_write;
1040 __be32 retval_len16;
1041 __be32 err_to_clearinit;
1042 __be32 fwrev;
1043 };
1044
1045 #define FW_HELLO_CMD_ERR_S 31
1046 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)
1047 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)
1048
1049 #define FW_HELLO_CMD_INIT_S 30
1050 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)
1051 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)
1052
1053 #define FW_HELLO_CMD_MASTERDIS_S 29
1054 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)
1055
1056 #define FW_HELLO_CMD_MASTERFORCE_S 28
1057 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1058
1059 #define FW_HELLO_CMD_MBMASTER_S 24
1060 #define FW_HELLO_CMD_MBMASTER_M 0xfU
1061 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)
1062 #define FW_HELLO_CMD_MBMASTER_G(x) \
1063 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1064
1065 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23
1066 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1067
1068 #define FW_HELLO_CMD_MBASYNCNOT_S 20
1069 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1070
1071 #define FW_HELLO_CMD_STAGE_S 17
1072 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)
1073
1074 #define FW_HELLO_CMD_CLEARINIT_S 16
1075 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)
1076 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)
1077
1078 struct fw_bye_cmd {
1079 __be32 op_to_write;
1080 __be32 retval_len16;
1081 __be64 r3;
1082 };
1083
1084 struct fw_initialize_cmd {
1085 __be32 op_to_write;
1086 __be32 retval_len16;
1087 __be64 r3;
1088 };
1089
1090 enum fw_caps_config_hm {
1091 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
1092 FW_CAPS_CONFIG_HM_PL = 0x00000002,
1093 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
1094 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
1095 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
1096 FW_CAPS_CONFIG_HM_TP = 0x00000020,
1097 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
1098 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
1099 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
1100 FW_CAPS_CONFIG_HM_MC = 0x00000200,
1101 FW_CAPS_CONFIG_HM_LE = 0x00000400,
1102 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
1103 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
1104 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
1105 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
1106 FW_CAPS_CONFIG_HM_MI = 0x00008000,
1107 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
1108 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
1109 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
1110 FW_CAPS_CONFIG_HM_MA = 0x00080000,
1111 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
1112 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
1113 FW_CAPS_CONFIG_HM_UART = 0x00400000,
1114 FW_CAPS_CONFIG_HM_SF = 0x00800000,
1115 };
1116
1117 enum fw_caps_config_nbm {
1118 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
1119 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
1120 };
1121
1122 enum fw_caps_config_link {
1123 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
1124 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
1125 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
1126 };
1127
1128 enum fw_caps_config_switch {
1129 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
1130 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
1131 };
1132
1133 enum fw_caps_config_nic {
1134 FW_CAPS_CONFIG_NIC = 0x00000001,
1135 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
1136 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
1137 };
1138
1139 enum fw_caps_config_ofld {
1140 FW_CAPS_CONFIG_OFLD = 0x00000001,
1141 };
1142
1143 enum fw_caps_config_rdma {
1144 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
1145 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
1146 };
1147
1148 enum fw_caps_config_iscsi {
1149 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1150 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1151 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1152 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1153 };
1154
1155 enum fw_caps_config_crypto {
1156 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1157 FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1158 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1159 };
1160
1161 enum fw_caps_config_fcoe {
1162 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
1163 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
1164 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
1165 };
1166
1167 enum fw_memtype_cf {
1168 FW_MEMTYPE_CF_EDC0 = 0x0,
1169 FW_MEMTYPE_CF_EDC1 = 0x1,
1170 FW_MEMTYPE_CF_EXTMEM = 0x2,
1171 FW_MEMTYPE_CF_FLASH = 0x4,
1172 FW_MEMTYPE_CF_INTERNAL = 0x5,
1173 FW_MEMTYPE_CF_EXTMEM1 = 0x6,
1174 FW_MEMTYPE_CF_HMA = 0x7,
1175 };
1176
1177 struct fw_caps_config_cmd {
1178 __be32 op_to_write;
1179 __be32 cfvalid_to_len16;
1180 __be32 r2;
1181 __be32 hwmbitmap;
1182 __be16 nbmcaps;
1183 __be16 linkcaps;
1184 __be16 switchcaps;
1185 __be16 r3;
1186 __be16 niccaps;
1187 __be16 ofldcaps;
1188 __be16 rdmacaps;
1189 __be16 cryptocaps;
1190 __be16 iscsicaps;
1191 __be16 fcoecaps;
1192 __be32 cfcsum;
1193 __be32 finiver;
1194 __be32 finicsum;
1195 };
1196
1197 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27
1198 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1199 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1200
1201 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24
1202 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \
1203 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1204
1205 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16
1206 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \
1207 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1208
1209
1210
1211
1212 enum fw_params_mnem {
1213 FW_PARAMS_MNEM_DEV = 1,
1214 FW_PARAMS_MNEM_PFVF = 2,
1215 FW_PARAMS_MNEM_REG = 3,
1216 FW_PARAMS_MNEM_DMAQ = 4,
1217 FW_PARAMS_MNEM_CHNET = 5,
1218 FW_PARAMS_MNEM_LAST
1219 };
1220
1221
1222
1223
1224
1225 #define FW_PARAMS_PARAM_FILTER_MODE_S 16
1226 #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff
1227 #define FW_PARAMS_PARAM_FILTER_MODE_V(x) \
1228 ((x) << FW_PARAMS_PARAM_FILTER_MODE_S)
1229 #define FW_PARAMS_PARAM_FILTER_MODE_G(x) \
1230 (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \
1231 FW_PARAMS_PARAM_FILTER_MODE_M)
1232
1233 #define FW_PARAMS_PARAM_FILTER_MASK_S 0
1234 #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff
1235 #define FW_PARAMS_PARAM_FILTER_MASK_V(x) \
1236 ((x) << FW_PARAMS_PARAM_FILTER_MASK_S)
1237 #define FW_PARAMS_PARAM_FILTER_MASK_G(x) \
1238 (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \
1239 FW_PARAMS_PARAM_FILTER_MASK_M)
1240
1241 enum fw_params_param_dev {
1242 FW_PARAMS_PARAM_DEV_CCLK = 0x00,
1243 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01,
1244 FW_PARAMS_PARAM_DEV_NTID = 0x02,
1245
1246
1247
1248 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1249 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
1250 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1251 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1252 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
1253 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1254 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1255 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1256 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1257 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1258 FW_PARAMS_PARAM_DEV_CF = 0x0D,
1259 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1260 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1261 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13,
1262 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14,
1263 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1264 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1265 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1266 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1267 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
1268 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
1269 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
1270 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
1271 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
1272 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1273 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
1274 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
1275 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
1276 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
1277 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
1278 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
1279 FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
1280 };
1281
1282
1283
1284
1285 enum fw_params_param_pfvf {
1286 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
1287 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1288 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1289 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1290 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1291 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1292 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1293 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1294 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1295 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1296 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1297 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1298 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1299 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1300 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1301 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1302 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
1303 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1304 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
1305 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1306 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1307 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1308 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
1309 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
1310 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
1311 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
1312 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
1313 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1314 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
1315 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1316 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
1317 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
1318 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
1319 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1320 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1321 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
1322 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
1323 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1324 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1325 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1326 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1327 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1328 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1329 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1330 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1331 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1332 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
1333 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
1334 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1335 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1336 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
1337 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
1338 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
1339 };
1340
1341
1342 enum vf_link_states {
1343 FW_VF_LINK_STATE_AUTO = 0x00,
1344 FW_VF_LINK_STATE_ENABLE = 0x01,
1345 FW_VF_LINK_STATE_DISABLE = 0x02,
1346 };
1347
1348
1349
1350
1351 enum fw_params_param_dmaq {
1352 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1353 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1354 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1355 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1356 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1357 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1358 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
1359 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1360 };
1361
1362 enum fw_params_param_dev_phyfw {
1363 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1364 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1365 };
1366
1367 enum fw_params_param_dev_diag {
1368 FW_PARAM_DEV_DIAG_TMP = 0x00,
1369 FW_PARAM_DEV_DIAG_VDD = 0x01,
1370 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
1371 };
1372
1373 enum fw_params_param_dev_filter {
1374 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
1375 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
1376 };
1377
1378 enum fw_params_param_dev_fwcache {
1379 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
1380 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
1381 };
1382
1383 #define FW_PARAMS_MNEM_S 24
1384 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)
1385
1386 #define FW_PARAMS_PARAM_X_S 16
1387 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)
1388
1389 #define FW_PARAMS_PARAM_Y_S 8
1390 #define FW_PARAMS_PARAM_Y_M 0xffU
1391 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)
1392 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\
1393 FW_PARAMS_PARAM_Y_M)
1394
1395 #define FW_PARAMS_PARAM_Z_S 0
1396 #define FW_PARAMS_PARAM_Z_M 0xffu
1397 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)
1398 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\
1399 FW_PARAMS_PARAM_Z_M)
1400
1401 #define FW_PARAMS_PARAM_XYZ_S 0
1402 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)
1403
1404 #define FW_PARAMS_PARAM_YZ_S 0
1405 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)
1406
1407 struct fw_params_cmd {
1408 __be32 op_to_vfn;
1409 __be32 retval_len16;
1410 struct fw_params_param {
1411 __be32 mnem;
1412 __be32 val;
1413 } param[7];
1414 };
1415
1416 #define FW_PARAMS_CMD_PFN_S 8
1417 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)
1418
1419 #define FW_PARAMS_CMD_VFN_S 0
1420 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)
1421
1422 struct fw_pfvf_cmd {
1423 __be32 op_to_vfn;
1424 __be32 retval_len16;
1425 __be32 niqflint_niq;
1426 __be32 type_to_neq;
1427 __be32 tc_to_nexactf;
1428 __be32 r_caps_to_nethctrl;
1429 __be16 nricq;
1430 __be16 nriqp;
1431 __be32 r4;
1432 };
1433
1434 #define FW_PFVF_CMD_PFN_S 8
1435 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)
1436
1437 #define FW_PFVF_CMD_VFN_S 0
1438 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)
1439
1440 #define FW_PFVF_CMD_NIQFLINT_S 20
1441 #define FW_PFVF_CMD_NIQFLINT_M 0xfff
1442 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)
1443 #define FW_PFVF_CMD_NIQFLINT_G(x) \
1444 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1445
1446 #define FW_PFVF_CMD_NIQ_S 0
1447 #define FW_PFVF_CMD_NIQ_M 0xfffff
1448 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)
1449 #define FW_PFVF_CMD_NIQ_G(x) \
1450 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1451
1452 #define FW_PFVF_CMD_TYPE_S 31
1453 #define FW_PFVF_CMD_TYPE_M 0x1
1454 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)
1455 #define FW_PFVF_CMD_TYPE_G(x) \
1456 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1457 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)
1458
1459 #define FW_PFVF_CMD_CMASK_S 24
1460 #define FW_PFVF_CMD_CMASK_M 0xf
1461 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)
1462 #define FW_PFVF_CMD_CMASK_G(x) \
1463 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1464
1465 #define FW_PFVF_CMD_PMASK_S 20
1466 #define FW_PFVF_CMD_PMASK_M 0xf
1467 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)
1468 #define FW_PFVF_CMD_PMASK_G(x) \
1469 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1470
1471 #define FW_PFVF_CMD_NEQ_S 0
1472 #define FW_PFVF_CMD_NEQ_M 0xfffff
1473 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)
1474 #define FW_PFVF_CMD_NEQ_G(x) \
1475 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1476
1477 #define FW_PFVF_CMD_TC_S 24
1478 #define FW_PFVF_CMD_TC_M 0xff
1479 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)
1480 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1481
1482 #define FW_PFVF_CMD_NVI_S 16
1483 #define FW_PFVF_CMD_NVI_M 0xff
1484 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)
1485 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1486
1487 #define FW_PFVF_CMD_NEXACTF_S 0
1488 #define FW_PFVF_CMD_NEXACTF_M 0xffff
1489 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)
1490 #define FW_PFVF_CMD_NEXACTF_G(x) \
1491 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1492
1493 #define FW_PFVF_CMD_R_CAPS_S 24
1494 #define FW_PFVF_CMD_R_CAPS_M 0xff
1495 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1496 #define FW_PFVF_CMD_R_CAPS_G(x) \
1497 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1498
1499 #define FW_PFVF_CMD_WX_CAPS_S 16
1500 #define FW_PFVF_CMD_WX_CAPS_M 0xff
1501 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)
1502 #define FW_PFVF_CMD_WX_CAPS_G(x) \
1503 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1504
1505 #define FW_PFVF_CMD_NETHCTRL_S 0
1506 #define FW_PFVF_CMD_NETHCTRL_M 0xffff
1507 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)
1508 #define FW_PFVF_CMD_NETHCTRL_G(x) \
1509 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1510
1511 enum fw_iq_type {
1512 FW_IQ_TYPE_FL_INT_CAP,
1513 FW_IQ_TYPE_NO_FL_INT_CAP
1514 };
1515
1516 enum fw_iq_iqtype {
1517 FW_IQ_IQTYPE_OTHER,
1518 FW_IQ_IQTYPE_NIC,
1519 FW_IQ_IQTYPE_OFLD,
1520 };
1521
1522 struct fw_iq_cmd {
1523 __be32 op_to_vfn;
1524 __be32 alloc_to_len16;
1525 __be16 physiqid;
1526 __be16 iqid;
1527 __be16 fl0id;
1528 __be16 fl1id;
1529 __be32 type_to_iqandstindex;
1530 __be16 iqdroprss_to_iqesize;
1531 __be16 iqsize;
1532 __be64 iqaddr;
1533 __be32 iqns_to_fl0congen;
1534 __be16 fl0dcaen_to_fl0cidxfthresh;
1535 __be16 fl0size;
1536 __be64 fl0addr;
1537 __be32 fl1cngchmap_to_fl1congen;
1538 __be16 fl1dcaen_to_fl1cidxfthresh;
1539 __be16 fl1size;
1540 __be64 fl1addr;
1541 };
1542
1543 #define FW_IQ_CMD_PFN_S 8
1544 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)
1545
1546 #define FW_IQ_CMD_VFN_S 0
1547 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)
1548
1549 #define FW_IQ_CMD_ALLOC_S 31
1550 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)
1551 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)
1552
1553 #define FW_IQ_CMD_FREE_S 30
1554 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)
1555 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)
1556
1557 #define FW_IQ_CMD_MODIFY_S 29
1558 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)
1559 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)
1560
1561 #define FW_IQ_CMD_IQSTART_S 28
1562 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)
1563 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)
1564
1565 #define FW_IQ_CMD_IQSTOP_S 27
1566 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)
1567 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)
1568
1569 #define FW_IQ_CMD_TYPE_S 29
1570 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)
1571
1572 #define FW_IQ_CMD_IQASYNCH_S 28
1573 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1574
1575 #define FW_IQ_CMD_VIID_S 16
1576 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)
1577
1578 #define FW_IQ_CMD_IQANDST_S 15
1579 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)
1580
1581 #define FW_IQ_CMD_IQANUS_S 14
1582 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)
1583
1584 #define FW_IQ_CMD_IQANUD_S 12
1585 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)
1586
1587 #define FW_IQ_CMD_IQANDSTINDEX_S 0
1588 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1589
1590 #define FW_IQ_CMD_IQDROPRSS_S 15
1591 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)
1592 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)
1593
1594 #define FW_IQ_CMD_IQGTSMODE_S 14
1595 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)
1596 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)
1597
1598 #define FW_IQ_CMD_IQPCIECH_S 12
1599 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1600
1601 #define FW_IQ_CMD_IQDCAEN_S 11
1602 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)
1603
1604 #define FW_IQ_CMD_IQDCACPU_S 6
1605 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1606
1607 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4
1608 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1609
1610 #define FW_IQ_CMD_IQO_S 3
1611 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)
1612 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)
1613
1614 #define FW_IQ_CMD_IQCPRIO_S 2
1615 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)
1616
1617 #define FW_IQ_CMD_IQESIZE_S 0
1618 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)
1619
1620 #define FW_IQ_CMD_IQNS_S 31
1621 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)
1622
1623 #define FW_IQ_CMD_IQRO_S 30
1624 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)
1625
1626 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28
1627 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1628
1629 #define FW_IQ_CMD_IQFLINTCONGEN_S 27
1630 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1631 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1632
1633 #define FW_IQ_CMD_IQFLINTISCSIC_S 26
1634 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1635
1636 #define FW_IQ_CMD_IQTYPE_S 24
1637 #define FW_IQ_CMD_IQTYPE_M 0x3
1638 #define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S)
1639 #define FW_IQ_CMD_IQTYPE_G(x) \
1640 (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
1641
1642 #define FW_IQ_CMD_FL0CNGCHMAP_S 20
1643 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1644
1645 #define FW_IQ_CMD_FL0CACHELOCK_S 15
1646 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1647
1648 #define FW_IQ_CMD_FL0DBP_S 14
1649 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)
1650
1651 #define FW_IQ_CMD_FL0DATANS_S 13
1652 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)
1653
1654 #define FW_IQ_CMD_FL0DATARO_S 12
1655 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)
1656 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)
1657
1658 #define FW_IQ_CMD_FL0CONGCIF_S 11
1659 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1660 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U)
1661
1662 #define FW_IQ_CMD_FL0ONCHIP_S 10
1663 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1664
1665 #define FW_IQ_CMD_FL0STATUSPGNS_S 9
1666 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1667
1668 #define FW_IQ_CMD_FL0STATUSPGRO_S 8
1669 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1670
1671 #define FW_IQ_CMD_FL0FETCHNS_S 7
1672 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1673
1674 #define FW_IQ_CMD_FL0FETCHRO_S 6
1675 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1676 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)
1677
1678 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4
1679 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1680
1681 #define FW_IQ_CMD_FL0CPRIO_S 3
1682 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1683
1684 #define FW_IQ_CMD_FL0PADEN_S 2
1685 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1686 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)
1687
1688 #define FW_IQ_CMD_FL0PACKEN_S 1
1689 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)
1690 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)
1691
1692 #define FW_IQ_CMD_FL0CONGEN_S 0
1693 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)
1694 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)
1695
1696 #define FW_IQ_CMD_FL0DCAEN_S 15
1697 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1698
1699 #define FW_IQ_CMD_FL0DCACPU_S 10
1700 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)
1701
1702 #define FW_IQ_CMD_FL0FBMIN_S 7
1703 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1704
1705 #define FW_IQ_CMD_FL0FBMAX_S 4
1706 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1707
1708 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3
1709 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1710 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1711
1712 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0
1713 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1714
1715 #define FW_IQ_CMD_FL1CNGCHMAP_S 20
1716 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1717
1718 #define FW_IQ_CMD_FL1CACHELOCK_S 15
1719 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1720
1721 #define FW_IQ_CMD_FL1DBP_S 14
1722 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)
1723
1724 #define FW_IQ_CMD_FL1DATANS_S 13
1725 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)
1726
1727 #define FW_IQ_CMD_FL1DATARO_S 12
1728 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)
1729
1730 #define FW_IQ_CMD_FL1CONGCIF_S 11
1731 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1732
1733 #define FW_IQ_CMD_FL1ONCHIP_S 10
1734 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1735
1736 #define FW_IQ_CMD_FL1STATUSPGNS_S 9
1737 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1738
1739 #define FW_IQ_CMD_FL1STATUSPGRO_S 8
1740 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1741
1742 #define FW_IQ_CMD_FL1FETCHNS_S 7
1743 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1744
1745 #define FW_IQ_CMD_FL1FETCHRO_S 6
1746 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1747
1748 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4
1749 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1750
1751 #define FW_IQ_CMD_FL1CPRIO_S 3
1752 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1753
1754 #define FW_IQ_CMD_FL1PADEN_S 2
1755 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1756 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)
1757
1758 #define FW_IQ_CMD_FL1PACKEN_S 1
1759 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)
1760 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)
1761
1762 #define FW_IQ_CMD_FL1CONGEN_S 0
1763 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)
1764 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)
1765
1766 #define FW_IQ_CMD_FL1DCAEN_S 15
1767 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1768
1769 #define FW_IQ_CMD_FL1DCACPU_S 10
1770 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)
1771
1772 #define FW_IQ_CMD_FL1FBMIN_S 7
1773 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1774
1775 #define FW_IQ_CMD_FL1FBMAX_S 4
1776 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1777
1778 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3
1779 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1780 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1781
1782 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0
1783 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1784
1785 struct fw_eq_eth_cmd {
1786 __be32 op_to_vfn;
1787 __be32 alloc_to_len16;
1788 __be32 eqid_pkd;
1789 __be32 physeqid_pkd;
1790 __be32 fetchszm_to_iqid;
1791 __be32 dcaen_to_eqsize;
1792 __be64 eqaddr;
1793 __be32 autoequiqe_to_viid;
1794 __be32 timeren_timerix;
1795 __be64 r9;
1796 };
1797
1798 #define FW_EQ_ETH_CMD_PFN_S 8
1799 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)
1800
1801 #define FW_EQ_ETH_CMD_VFN_S 0
1802 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)
1803
1804 #define FW_EQ_ETH_CMD_ALLOC_S 31
1805 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1806 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)
1807
1808 #define FW_EQ_ETH_CMD_FREE_S 30
1809 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1810 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)
1811
1812 #define FW_EQ_ETH_CMD_MODIFY_S 29
1813 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1814 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)
1815
1816 #define FW_EQ_ETH_CMD_EQSTART_S 28
1817 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1818 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1819
1820 #define FW_EQ_ETH_CMD_EQSTOP_S 27
1821 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1822 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
1823
1824 #define FW_EQ_ETH_CMD_EQID_S 0
1825 #define FW_EQ_ETH_CMD_EQID_M 0xfffff
1826 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1827 #define FW_EQ_ETH_CMD_EQID_G(x) \
1828 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1829
1830 #define FW_EQ_ETH_CMD_PHYSEQID_S 0
1831 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff
1832 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1833 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \
1834 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1835
1836 #define FW_EQ_ETH_CMD_FETCHSZM_S 26
1837 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1838 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1839
1840 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25
1841 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1842
1843 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24
1844 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1845
1846 #define FW_EQ_ETH_CMD_FETCHNS_S 23
1847 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1848
1849 #define FW_EQ_ETH_CMD_FETCHRO_S 22
1850 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1851 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U)
1852
1853 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20
1854 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1855
1856 #define FW_EQ_ETH_CMD_CPRIO_S 19
1857 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1858
1859 #define FW_EQ_ETH_CMD_ONCHIP_S 18
1860 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1861
1862 #define FW_EQ_ETH_CMD_PCIECHN_S 16
1863 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1864
1865 #define FW_EQ_ETH_CMD_IQID_S 0
1866 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1867
1868 #define FW_EQ_ETH_CMD_DCAEN_S 31
1869 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1870
1871 #define FW_EQ_ETH_CMD_DCACPU_S 26
1872 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1873
1874 #define FW_EQ_ETH_CMD_FBMIN_S 23
1875 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1876
1877 #define FW_EQ_ETH_CMD_FBMAX_S 20
1878 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1879
1880 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19
1881 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1882
1883 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16
1884 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1885
1886 #define FW_EQ_ETH_CMD_EQSIZE_S 0
1887 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1888
1889 #define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31
1890 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)
1891 #define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)
1892
1893 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30
1894 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1895 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1896
1897 #define FW_EQ_ETH_CMD_VIID_S 16
1898 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1899
1900 #define FW_EQ_ETH_CMD_TIMEREN_S 3
1901 #define FW_EQ_ETH_CMD_TIMEREN_M 0x1
1902 #define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S)
1903 #define FW_EQ_ETH_CMD_TIMEREN_G(x) \
1904 (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M)
1905 #define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U)
1906
1907 #define FW_EQ_ETH_CMD_TIMERIX_S 0
1908 #define FW_EQ_ETH_CMD_TIMERIX_M 0x7
1909 #define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S)
1910 #define FW_EQ_ETH_CMD_TIMERIX_G(x) \
1911 (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M)
1912
1913 struct fw_eq_ctrl_cmd {
1914 __be32 op_to_vfn;
1915 __be32 alloc_to_len16;
1916 __be32 cmpliqid_eqid;
1917 __be32 physeqid_pkd;
1918 __be32 fetchszm_to_iqid;
1919 __be32 dcaen_to_eqsize;
1920 __be64 eqaddr;
1921 };
1922
1923 #define FW_EQ_CTRL_CMD_PFN_S 8
1924 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1925
1926 #define FW_EQ_CTRL_CMD_VFN_S 0
1927 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1928
1929 #define FW_EQ_CTRL_CMD_ALLOC_S 31
1930 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1931 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)
1932
1933 #define FW_EQ_CTRL_CMD_FREE_S 30
1934 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)
1935 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)
1936
1937 #define FW_EQ_CTRL_CMD_MODIFY_S 29
1938 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1939 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)
1940
1941 #define FW_EQ_CTRL_CMD_EQSTART_S 28
1942 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1943 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)
1944
1945 #define FW_EQ_CTRL_CMD_EQSTOP_S 27
1946 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1947 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1948
1949 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20
1950 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1951
1952 #define FW_EQ_CTRL_CMD_EQID_S 0
1953 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff
1954 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
1955 #define FW_EQ_CTRL_CMD_EQID_G(x) \
1956 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1957
1958 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0
1959 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff
1960 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \
1961 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1962
1963 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26
1964 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1965 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1966
1967 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25
1968 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1969 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1970
1971 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24
1972 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1973 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1974
1975 #define FW_EQ_CTRL_CMD_FETCHNS_S 23
1976 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1977 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1978
1979 #define FW_EQ_CTRL_CMD_FETCHRO_S 22
1980 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1981 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1982
1983 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20
1984 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1985
1986 #define FW_EQ_CTRL_CMD_CPRIO_S 19
1987 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1988
1989 #define FW_EQ_CTRL_CMD_ONCHIP_S 18
1990 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1991
1992 #define FW_EQ_CTRL_CMD_PCIECHN_S 16
1993 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1994
1995 #define FW_EQ_CTRL_CMD_IQID_S 0
1996 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)
1997
1998 #define FW_EQ_CTRL_CMD_DCAEN_S 31
1999 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
2000
2001 #define FW_EQ_CTRL_CMD_DCACPU_S 26
2002 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
2003
2004 #define FW_EQ_CTRL_CMD_FBMIN_S 23
2005 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
2006
2007 #define FW_EQ_CTRL_CMD_FBMAX_S 20
2008 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
2009
2010 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19
2011 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \
2012 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
2013
2014 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16
2015 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
2016
2017 #define FW_EQ_CTRL_CMD_EQSIZE_S 0
2018 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
2019
2020 struct fw_eq_ofld_cmd {
2021 __be32 op_to_vfn;
2022 __be32 alloc_to_len16;
2023 __be32 eqid_pkd;
2024 __be32 physeqid_pkd;
2025 __be32 fetchszm_to_iqid;
2026 __be32 dcaen_to_eqsize;
2027 __be64 eqaddr;
2028 };
2029
2030 #define FW_EQ_OFLD_CMD_PFN_S 8
2031 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
2032
2033 #define FW_EQ_OFLD_CMD_VFN_S 0
2034 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
2035
2036 #define FW_EQ_OFLD_CMD_ALLOC_S 31
2037 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
2038 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U)
2039
2040 #define FW_EQ_OFLD_CMD_FREE_S 30
2041 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)
2042 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U)
2043
2044 #define FW_EQ_OFLD_CMD_MODIFY_S 29
2045 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
2046 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U)
2047
2048 #define FW_EQ_OFLD_CMD_EQSTART_S 28
2049 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
2050 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
2051
2052 #define FW_EQ_OFLD_CMD_EQSTOP_S 27
2053 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
2054 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
2055
2056 #define FW_EQ_OFLD_CMD_EQID_S 0
2057 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff
2058 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)
2059 #define FW_EQ_OFLD_CMD_EQID_G(x) \
2060 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
2061
2062 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0
2063 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff
2064 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \
2065 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
2066
2067 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26
2068 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
2069
2070 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25
2071 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2072
2073 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24
2074 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2075
2076 #define FW_EQ_OFLD_CMD_FETCHNS_S 23
2077 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2078
2079 #define FW_EQ_OFLD_CMD_FETCHRO_S 22
2080 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2081 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2082
2083 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20
2084 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2085
2086 #define FW_EQ_OFLD_CMD_CPRIO_S 19
2087 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2088
2089 #define FW_EQ_OFLD_CMD_ONCHIP_S 18
2090 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2091
2092 #define FW_EQ_OFLD_CMD_PCIECHN_S 16
2093 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2094
2095 #define FW_EQ_OFLD_CMD_IQID_S 0
2096 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)
2097
2098 #define FW_EQ_OFLD_CMD_DCAEN_S 31
2099 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2100
2101 #define FW_EQ_OFLD_CMD_DCACPU_S 26
2102 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2103
2104 #define FW_EQ_OFLD_CMD_FBMIN_S 23
2105 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2106
2107 #define FW_EQ_OFLD_CMD_FBMAX_S 20
2108 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2109
2110 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19
2111 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \
2112 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2113
2114 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16
2115 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2116
2117 #define FW_EQ_OFLD_CMD_EQSIZE_S 0
2118 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2119
2120
2121
2122
2123
2124
2125 #define FW_VIID_PFN_S 8
2126 #define FW_VIID_PFN_M 0x7
2127 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2128
2129 #define FW_VIID_VIVLD_S 7
2130 #define FW_VIID_VIVLD_M 0x1
2131 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2132
2133 #define FW_VIID_VIN_S 0
2134 #define FW_VIID_VIN_M 0x7F
2135 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2136
2137 struct fw_vi_cmd {
2138 __be32 op_to_vfn;
2139 __be32 alloc_to_len16;
2140 __be16 type_viid;
2141 u8 mac[6];
2142 u8 portid_pkd;
2143 u8 nmac;
2144 u8 nmac0[6];
2145 __be16 rsssize_pkd;
2146 u8 nmac1[6];
2147 __be16 idsiiq_pkd;
2148 u8 nmac2[6];
2149 __be16 idseiq_pkd;
2150 u8 nmac3[6];
2151 __be64 r9;
2152 __be64 r10;
2153 };
2154
2155 #define FW_VI_CMD_PFN_S 8
2156 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)
2157
2158 #define FW_VI_CMD_VFN_S 0
2159 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)
2160
2161 #define FW_VI_CMD_ALLOC_S 31
2162 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)
2163 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U)
2164
2165 #define FW_VI_CMD_FREE_S 30
2166 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)
2167 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U)
2168
2169 #define FW_VI_CMD_VFVLD_S 24
2170 #define FW_VI_CMD_VFVLD_M 0x1
2171 #define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S)
2172 #define FW_VI_CMD_VFVLD_G(x) \
2173 (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2174 #define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1U)
2175
2176 #define FW_VI_CMD_VIN_S 16
2177 #define FW_VI_CMD_VIN_M 0xff
2178 #define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S)
2179 #define FW_VI_CMD_VIN_G(x) \
2180 (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2181
2182 #define FW_VI_CMD_VIID_S 0
2183 #define FW_VI_CMD_VIID_M 0xfff
2184 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)
2185 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2186
2187 #define FW_VI_CMD_PORTID_S 4
2188 #define FW_VI_CMD_PORTID_M 0xf
2189 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)
2190 #define FW_VI_CMD_PORTID_G(x) \
2191 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2192
2193 #define FW_VI_CMD_RSSSIZE_S 0
2194 #define FW_VI_CMD_RSSSIZE_M 0x7ff
2195 #define FW_VI_CMD_RSSSIZE_G(x) \
2196 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2197
2198
2199 #define FW_VI_MAC_ADD_MAC 0x3FF
2200 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
2201 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
2202 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
2203 #define FW_CLS_TCAM_NUM_ENTRIES 336
2204
2205 enum fw_vi_mac_smac {
2206 FW_VI_MAC_MPS_TCAM_ENTRY,
2207 FW_VI_MAC_MPS_TCAM_ONLY,
2208 FW_VI_MAC_SMT_ONLY,
2209 FW_VI_MAC_SMT_AND_MPSTCAM
2210 };
2211
2212 enum fw_vi_mac_result {
2213 FW_VI_MAC_R_SUCCESS,
2214 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2215 FW_VI_MAC_R_SMAC_FAIL,
2216 FW_VI_MAC_R_F_ACL_CHECK
2217 };
2218
2219 enum fw_vi_mac_entry_types {
2220 FW_VI_MAC_TYPE_EXACTMAC,
2221 FW_VI_MAC_TYPE_HASHVEC,
2222 FW_VI_MAC_TYPE_RAW,
2223 FW_VI_MAC_TYPE_EXACTMAC_VNI,
2224 };
2225
2226 struct fw_vi_mac_cmd {
2227 __be32 op_to_viid;
2228 __be32 freemacs_to_len16;
2229 union fw_vi_mac {
2230 struct fw_vi_mac_exact {
2231 __be16 valid_to_idx;
2232 u8 macaddr[6];
2233 } exact[7];
2234 struct fw_vi_mac_hash {
2235 __be64 hashvec;
2236 } hash;
2237 struct fw_vi_mac_raw {
2238 __be32 raw_idx_pkd;
2239 __be32 data0_pkd;
2240 __be32 data1[2];
2241 __be64 data0m_pkd;
2242 __be32 data1m[2];
2243 } raw;
2244 struct fw_vi_mac_vni {
2245 __be16 valid_to_idx;
2246 __u8 macaddr[6];
2247 __be16 r7;
2248 __u8 macaddr_mask[6];
2249 __be32 lookup_type_to_vni;
2250 __be32 vni_mask_pkd;
2251 } exact_vni[2];
2252 } u;
2253 };
2254
2255 #define FW_VI_MAC_CMD_SMTID_S 12
2256 #define FW_VI_MAC_CMD_SMTID_M 0xff
2257 #define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S)
2258 #define FW_VI_MAC_CMD_SMTID_G(x) \
2259 (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
2260
2261 #define FW_VI_MAC_CMD_VIID_S 0
2262 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2263
2264 #define FW_VI_MAC_CMD_FREEMACS_S 31
2265 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2266
2267 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23
2268 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7
2269 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2270 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \
2271 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2272
2273 #define FW_VI_MAC_CMD_HASHVECEN_S 23
2274 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2275 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
2276
2277 #define FW_VI_MAC_CMD_HASHUNIEN_S 22
2278 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2279
2280 #define FW_VI_MAC_CMD_VALID_S 15
2281 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)
2282 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U)
2283
2284 #define FW_VI_MAC_CMD_PRIO_S 12
2285 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2286
2287 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10
2288 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3
2289 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2290 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \
2291 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2292
2293 #define FW_VI_MAC_CMD_IDX_S 0
2294 #define FW_VI_MAC_CMD_IDX_M 0x3ff
2295 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)
2296 #define FW_VI_MAC_CMD_IDX_G(x) \
2297 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2298
2299 #define FW_VI_MAC_CMD_RAW_IDX_S 16
2300 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff
2301 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2302 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \
2303 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2304
2305 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31
2306 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0x1
2307 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2308 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \
2309 (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2310 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2311
2312 #define FW_VI_MAC_CMD_DIP_HIT_S 30
2313 #define FW_VI_MAC_CMD_DIP_HIT_M 0x1
2314 #define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2315 #define FW_VI_MAC_CMD_DIP_HIT_G(x) \
2316 (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2317 #define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1U)
2318
2319 #define FW_VI_MAC_CMD_VNI_S 0
2320 #define FW_VI_MAC_CMD_VNI_M 0xffffff
2321 #define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S)
2322 #define FW_VI_MAC_CMD_VNI_G(x) \
2323 (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2324
2325 #define FW_VI_MAC_CMD_VNI_MASK_S 0
2326 #define FW_VI_MAC_CMD_VNI_MASK_M 0xffffff
2327 #define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2328 #define FW_VI_MAC_CMD_VNI_MASK_G(x) \
2329 (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2330
2331 #define FW_RXMODE_MTU_NO_CHG 65535
2332
2333 struct fw_vi_rxmode_cmd {
2334 __be32 op_to_viid;
2335 __be32 retval_len16;
2336 __be32 mtu_to_vlanexen;
2337 __be32 r4_lo;
2338 };
2339
2340 #define FW_VI_RXMODE_CMD_VIID_S 0
2341 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)
2342
2343 #define FW_VI_RXMODE_CMD_MTU_S 16
2344 #define FW_VI_RXMODE_CMD_MTU_M 0xffff
2345 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)
2346
2347 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14
2348 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3
2349 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2350
2351 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12
2352 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3
2353 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \
2354 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2355
2356 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10
2357 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3
2358 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \
2359 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2360
2361 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8
2362 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3
2363 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2364
2365 struct fw_vi_enable_cmd {
2366 __be32 op_to_viid;
2367 __be32 ien_to_len16;
2368 __be16 blinkdur;
2369 __be16 r3;
2370 __be32 r4;
2371 };
2372
2373 #define FW_VI_ENABLE_CMD_VIID_S 0
2374 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)
2375
2376 #define FW_VI_ENABLE_CMD_IEN_S 31
2377 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)
2378
2379 #define FW_VI_ENABLE_CMD_EEN_S 30
2380 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)
2381
2382 #define FW_VI_ENABLE_CMD_LED_S 29
2383 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)
2384 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U)
2385
2386 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28
2387 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2388
2389
2390 #define VI_VF_NUM_STATS 16
2391 enum fw_vi_stats_vf_index {
2392 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2393 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2394 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2395 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2396 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2397 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2398 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2399 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2400 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2401 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2402 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2403 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2404 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2405 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2406 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2407 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2408 };
2409
2410
2411 #define VI_PF_NUM_STATS 17
2412 enum fw_vi_stats_pf_index {
2413 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2414 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2415 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2416 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2417 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2418 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2419 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2420 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2421 FW_VI_PF_STAT_RX_BYTES_IX,
2422 FW_VI_PF_STAT_RX_FRAMES_IX,
2423 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2424 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2425 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2426 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2427 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2428 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2429 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2430 };
2431
2432 struct fw_vi_stats_cmd {
2433 __be32 op_to_viid;
2434 __be32 retval_len16;
2435 union fw_vi_stats {
2436 struct fw_vi_stats_ctl {
2437 __be16 nstats_ix;
2438 __be16 r6;
2439 __be32 r7;
2440 __be64 stat0;
2441 __be64 stat1;
2442 __be64 stat2;
2443 __be64 stat3;
2444 __be64 stat4;
2445 __be64 stat5;
2446 } ctl;
2447 struct fw_vi_stats_pf {
2448 __be64 tx_bcast_bytes;
2449 __be64 tx_bcast_frames;
2450 __be64 tx_mcast_bytes;
2451 __be64 tx_mcast_frames;
2452 __be64 tx_ucast_bytes;
2453 __be64 tx_ucast_frames;
2454 __be64 tx_offload_bytes;
2455 __be64 tx_offload_frames;
2456 __be64 rx_pf_bytes;
2457 __be64 rx_pf_frames;
2458 __be64 rx_bcast_bytes;
2459 __be64 rx_bcast_frames;
2460 __be64 rx_mcast_bytes;
2461 __be64 rx_mcast_frames;
2462 __be64 rx_ucast_bytes;
2463 __be64 rx_ucast_frames;
2464 __be64 rx_err_frames;
2465 } pf;
2466 struct fw_vi_stats_vf {
2467 __be64 tx_bcast_bytes;
2468 __be64 tx_bcast_frames;
2469 __be64 tx_mcast_bytes;
2470 __be64 tx_mcast_frames;
2471 __be64 tx_ucast_bytes;
2472 __be64 tx_ucast_frames;
2473 __be64 tx_drop_frames;
2474 __be64 tx_offload_bytes;
2475 __be64 tx_offload_frames;
2476 __be64 rx_bcast_bytes;
2477 __be64 rx_bcast_frames;
2478 __be64 rx_mcast_bytes;
2479 __be64 rx_mcast_frames;
2480 __be64 rx_ucast_bytes;
2481 __be64 rx_ucast_frames;
2482 __be64 rx_err_frames;
2483 } vf;
2484 } u;
2485 };
2486
2487 #define FW_VI_STATS_CMD_VIID_S 0
2488 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)
2489
2490 #define FW_VI_STATS_CMD_NSTATS_S 12
2491 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)
2492
2493 #define FW_VI_STATS_CMD_IX_S 0
2494 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2495
2496 struct fw_acl_mac_cmd {
2497 __be32 op_to_vfn;
2498 __be32 en_to_len16;
2499 u8 nmac;
2500 u8 r3[7];
2501 __be16 r4;
2502 u8 macaddr0[6];
2503 __be16 r5;
2504 u8 macaddr1[6];
2505 __be16 r6;
2506 u8 macaddr2[6];
2507 __be16 r7;
2508 u8 macaddr3[6];
2509 };
2510
2511 #define FW_ACL_MAC_CMD_PFN_S 8
2512 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2513
2514 #define FW_ACL_MAC_CMD_VFN_S 0
2515 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2516
2517 #define FW_ACL_MAC_CMD_EN_S 31
2518 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)
2519
2520 struct fw_acl_vlan_cmd {
2521 __be32 op_to_vfn;
2522 __be32 en_to_len16;
2523 u8 nvlan;
2524 u8 dropnovlan_fm;
2525 u8 r3_lo[6];
2526 __be16 vlanid[16];
2527 };
2528
2529 #define FW_ACL_VLAN_CMD_PFN_S 8
2530 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)
2531
2532 #define FW_ACL_VLAN_CMD_VFN_S 0
2533 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)
2534
2535 #define FW_ACL_VLAN_CMD_EN_S 31
2536 #define FW_ACL_VLAN_CMD_EN_M 0x1
2537 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2538 #define FW_ACL_VLAN_CMD_EN_G(x) \
2539 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2540 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U)
2541
2542 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
2543 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2544 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
2545
2546 #define FW_ACL_VLAN_CMD_FM_S 6
2547 #define FW_ACL_VLAN_CMD_FM_M 0x1
2548 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2549 #define FW_ACL_VLAN_CMD_FM_G(x) \
2550 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2551 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U)
2552
2553
2554 enum fw_port_cap {
2555 FW_PORT_CAP_SPEED_100M = 0x0001,
2556 FW_PORT_CAP_SPEED_1G = 0x0002,
2557 FW_PORT_CAP_SPEED_25G = 0x0004,
2558 FW_PORT_CAP_SPEED_10G = 0x0008,
2559 FW_PORT_CAP_SPEED_40G = 0x0010,
2560 FW_PORT_CAP_SPEED_100G = 0x0020,
2561 FW_PORT_CAP_FC_RX = 0x0040,
2562 FW_PORT_CAP_FC_TX = 0x0080,
2563 FW_PORT_CAP_ANEG = 0x0100,
2564 FW_PORT_CAP_MDIAUTO = 0x0200,
2565 FW_PORT_CAP_MDISTRAIGHT = 0x0400,
2566 FW_PORT_CAP_FEC_RS = 0x0800,
2567 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
2568 FW_PORT_CAP_FORCE_PAUSE = 0x2000,
2569 FW_PORT_CAP_802_3_PAUSE = 0x4000,
2570 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
2571 };
2572
2573 #define FW_PORT_CAP_SPEED_S 0
2574 #define FW_PORT_CAP_SPEED_M 0x3f
2575 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S)
2576 #define FW_PORT_CAP_SPEED_G(x) \
2577 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2578
2579 enum fw_port_mdi {
2580 FW_PORT_CAP_MDI_UNCHANGED,
2581 FW_PORT_CAP_MDI_AUTO,
2582 FW_PORT_CAP_MDI_F_STRAIGHT,
2583 FW_PORT_CAP_MDI_F_CROSSOVER
2584 };
2585
2586 #define FW_PORT_CAP_MDI_S 9
2587 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2588
2589
2590 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
2591 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
2592 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
2593 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
2594 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
2595 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
2596 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
2597 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
2598 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
2599 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
2600 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
2601 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
2602 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
2603 #define FW_PORT_CAP32_FC_RX 0x00010000UL
2604 #define FW_PORT_CAP32_FC_TX 0x00020000UL
2605 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
2606 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
2607 #define FW_PORT_CAP32_ANEG 0x00100000UL
2608 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL
2609 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
2610 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
2611 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
2612 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
2613 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
2614 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
2615 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
2616 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL
2617
2618 #define FW_PORT_CAP32_SPEED_S 0
2619 #define FW_PORT_CAP32_SPEED_M 0xfff
2620 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S)
2621 #define FW_PORT_CAP32_SPEED_G(x) \
2622 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2623
2624 #define FW_PORT_CAP32_FC_S 16
2625 #define FW_PORT_CAP32_FC_M 0x3
2626 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S)
2627 #define FW_PORT_CAP32_FC_G(x) \
2628 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2629
2630 #define FW_PORT_CAP32_802_3_S 18
2631 #define FW_PORT_CAP32_802_3_M 0x3
2632 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S)
2633 #define FW_PORT_CAP32_802_3_G(x) \
2634 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2635
2636 #define FW_PORT_CAP32_ANEG_S 20
2637 #define FW_PORT_CAP32_ANEG_M 0x1
2638 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2639 #define FW_PORT_CAP32_ANEG_G(x) \
2640 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2641
2642 enum fw_port_mdi32 {
2643 FW_PORT_CAP32_MDI_UNCHANGED,
2644 FW_PORT_CAP32_MDI_AUTO,
2645 FW_PORT_CAP32_MDI_F_STRAIGHT,
2646 FW_PORT_CAP32_MDI_F_CROSSOVER
2647 };
2648
2649 #define FW_PORT_CAP32_MDI_S 21
2650 #define FW_PORT_CAP32_MDI_M 3
2651 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2652 #define FW_PORT_CAP32_MDI_G(x) \
2653 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2654
2655 #define FW_PORT_CAP32_FEC_S 23
2656 #define FW_PORT_CAP32_FEC_M 0x1f
2657 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S)
2658 #define FW_PORT_CAP32_FEC_G(x) \
2659 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2660
2661
2662 #define CAP32_SPEED(__cap32) \
2663 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2664
2665 #define CAP32_FEC(__cap32) \
2666 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2667
2668 enum fw_port_action {
2669 FW_PORT_ACTION_L1_CFG = 0x0001,
2670 FW_PORT_ACTION_L2_CFG = 0x0002,
2671 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
2672 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
2673 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
2674 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
2675 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
2676 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
2677 FW_PORT_ACTION_L1_CFG32 = 0x0009,
2678 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
2679 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2680 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
2681 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
2682 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
2683 FW_PORT_ACTION_L1_LPBK = 0x0021,
2684 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
2685 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
2686 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2687 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2688 FW_PORT_ACTION_PHY_RESET = 0x0040,
2689 FW_PORT_ACTION_PMA_RESET = 0x0041,
2690 FW_PORT_ACTION_PCS_RESET = 0x0042,
2691 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
2692 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
2693 FW_PORT_ACTION_AN_RESET = 0x0045
2694 };
2695
2696 enum fw_port_l2cfg_ctlbf {
2697 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2698 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2699 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2700 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2701 FW_PORT_L2_CTLBF_IVLAN = 0x10,
2702 FW_PORT_L2_CTLBF_TXIPG = 0x20
2703 };
2704
2705 enum fw_port_dcb_versions {
2706 FW_PORT_DCB_VER_UNKNOWN,
2707 FW_PORT_DCB_VER_CEE1D0,
2708 FW_PORT_DCB_VER_CEE1D01,
2709 FW_PORT_DCB_VER_IEEE,
2710 FW_PORT_DCB_VER_AUTO = 7
2711 };
2712
2713 enum fw_port_dcb_cfg {
2714 FW_PORT_DCB_CFG_PG = 0x01,
2715 FW_PORT_DCB_CFG_PFC = 0x02,
2716 FW_PORT_DCB_CFG_APPL = 0x04
2717 };
2718
2719 enum fw_port_dcb_cfg_rc {
2720 FW_PORT_DCB_CFG_SUCCESS = 0x0,
2721 FW_PORT_DCB_CFG_ERROR = 0x1
2722 };
2723
2724 enum fw_port_dcb_type {
2725 FW_PORT_DCB_TYPE_PGID = 0x00,
2726 FW_PORT_DCB_TYPE_PGRATE = 0x01,
2727 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
2728 FW_PORT_DCB_TYPE_PFC = 0x03,
2729 FW_PORT_DCB_TYPE_APP_ID = 0x04,
2730 FW_PORT_DCB_TYPE_CONTROL = 0x05,
2731 };
2732
2733 enum fw_port_dcb_feature_state {
2734 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2735 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2736 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2737 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2738 };
2739
2740 struct fw_port_cmd {
2741 __be32 op_to_portid;
2742 __be32 action_to_len16;
2743 union fw_port {
2744 struct fw_port_l1cfg {
2745 __be32 rcap;
2746 __be32 r;
2747 } l1cfg;
2748 struct fw_port_l2cfg {
2749 __u8 ctlbf;
2750 __u8 ovlan3_to_ivlan0;
2751 __be16 ivlantype;
2752 __be16 txipg_force_pinfo;
2753 __be16 mtu;
2754 __be16 ovlan0mask;
2755 __be16 ovlan0type;
2756 __be16 ovlan1mask;
2757 __be16 ovlan1type;
2758 __be16 ovlan2mask;
2759 __be16 ovlan2type;
2760 __be16 ovlan3mask;
2761 __be16 ovlan3type;
2762 } l2cfg;
2763 struct fw_port_info {
2764 __be32 lstatus_to_modtype;
2765 __be16 pcap;
2766 __be16 acap;
2767 __be16 mtu;
2768 __u8 cbllen;
2769 __u8 auxlinfo;
2770 __u8 dcbxdis_pkd;
2771 __u8 r8_lo;
2772 __be16 lpacap;
2773 __be64 r9;
2774 } info;
2775 struct fw_port_diags {
2776 __u8 diagop;
2777 __u8 r[3];
2778 __be32 diagval;
2779 } diags;
2780 union fw_port_dcb {
2781 struct fw_port_dcb_pgid {
2782 __u8 type;
2783 __u8 apply_pkd;
2784 __u8 r10_lo[2];
2785 __be32 pgid;
2786 __be64 r11;
2787 } pgid;
2788 struct fw_port_dcb_pgrate {
2789 __u8 type;
2790 __u8 apply_pkd;
2791 __u8 r10_lo[5];
2792 __u8 num_tcs_supported;
2793 __u8 pgrate[8];
2794 __u8 tsa[8];
2795 } pgrate;
2796 struct fw_port_dcb_priorate {
2797 __u8 type;
2798 __u8 apply_pkd;
2799 __u8 r10_lo[6];
2800 __u8 strict_priorate[8];
2801 } priorate;
2802 struct fw_port_dcb_pfc {
2803 __u8 type;
2804 __u8 pfcen;
2805 __u8 r10[5];
2806 __u8 max_pfc_tcs;
2807 __be64 r11;
2808 } pfc;
2809 struct fw_port_app_priority {
2810 __u8 type;
2811 __u8 r10[2];
2812 __u8 idx;
2813 __u8 user_prio_map;
2814 __u8 sel_field;
2815 __be16 protocolid;
2816 __be64 r12;
2817 } app_priority;
2818 struct fw_port_dcb_control {
2819 __u8 type;
2820 __u8 all_syncd_pkd;
2821 __be16 dcb_version_to_app_state;
2822 __be32 r11;
2823 __be64 r12;
2824 } control;
2825 } dcb;
2826 struct fw_port_l1cfg32 {
2827 __be32 rcap32;
2828 __be32 r;
2829 } l1cfg32;
2830 struct fw_port_info32 {
2831 __be32 lstatus32_to_cbllen32;
2832 __be32 auxlinfo32_mtu32;
2833 __be32 linkattr32;
2834 __be32 pcaps32;
2835 __be32 acaps32;
2836 __be32 lpacaps32;
2837 } info32;
2838 } u;
2839 };
2840
2841 #define FW_PORT_CMD_READ_S 22
2842 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)
2843 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U)
2844
2845 #define FW_PORT_CMD_PORTID_S 0
2846 #define FW_PORT_CMD_PORTID_M 0xf
2847 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2848 #define FW_PORT_CMD_PORTID_G(x) \
2849 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2850
2851 #define FW_PORT_CMD_ACTION_S 16
2852 #define FW_PORT_CMD_ACTION_M 0xffff
2853 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2854 #define FW_PORT_CMD_ACTION_G(x) \
2855 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2856
2857 #define FW_PORT_CMD_OVLAN3_S 7
2858 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2859
2860 #define FW_PORT_CMD_OVLAN2_S 6
2861 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2862
2863 #define FW_PORT_CMD_OVLAN1_S 5
2864 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2865
2866 #define FW_PORT_CMD_OVLAN0_S 4
2867 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2868
2869 #define FW_PORT_CMD_IVLAN0_S 3
2870 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2871
2872 #define FW_PORT_CMD_TXIPG_S 3
2873 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)
2874
2875 #define FW_PORT_CMD_LSTATUS_S 31
2876 #define FW_PORT_CMD_LSTATUS_M 0x1
2877 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)
2878 #define FW_PORT_CMD_LSTATUS_G(x) \
2879 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2880 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U)
2881
2882 #define FW_PORT_CMD_LSPEED_S 24
2883 #define FW_PORT_CMD_LSPEED_M 0x3f
2884 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2885 #define FW_PORT_CMD_LSPEED_G(x) \
2886 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2887
2888 #define FW_PORT_CMD_TXPAUSE_S 23
2889 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)
2890 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U)
2891
2892 #define FW_PORT_CMD_RXPAUSE_S 22
2893 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)
2894 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U)
2895
2896 #define FW_PORT_CMD_MDIOCAP_S 21
2897 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)
2898 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U)
2899
2900 #define FW_PORT_CMD_MDIOADDR_S 16
2901 #define FW_PORT_CMD_MDIOADDR_M 0x1f
2902 #define FW_PORT_CMD_MDIOADDR_G(x) \
2903 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2904
2905 #define FW_PORT_CMD_LPTXPAUSE_S 15
2906 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2907 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2908
2909 #define FW_PORT_CMD_LPRXPAUSE_S 14
2910 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2911 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2912
2913 #define FW_PORT_CMD_PTYPE_S 8
2914 #define FW_PORT_CMD_PTYPE_M 0x1f
2915 #define FW_PORT_CMD_PTYPE_G(x) \
2916 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2917
2918 #define FW_PORT_CMD_LINKDNRC_S 5
2919 #define FW_PORT_CMD_LINKDNRC_M 0x7
2920 #define FW_PORT_CMD_LINKDNRC_G(x) \
2921 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2922
2923 #define FW_PORT_CMD_MODTYPE_S 0
2924 #define FW_PORT_CMD_MODTYPE_M 0x1f
2925 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)
2926 #define FW_PORT_CMD_MODTYPE_G(x) \
2927 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2928
2929 #define FW_PORT_CMD_DCBXDIS_S 7
2930 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)
2931 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U)
2932
2933 #define FW_PORT_CMD_APPLY_S 7
2934 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)
2935 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U)
2936
2937 #define FW_PORT_CMD_ALL_SYNCD_S 7
2938 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2939 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2940
2941 #define FW_PORT_CMD_DCB_VERSION_S 12
2942 #define FW_PORT_CMD_DCB_VERSION_M 0x7
2943 #define FW_PORT_CMD_DCB_VERSION_G(x) \
2944 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2945
2946 #define FW_PORT_CMD_LSTATUS32_S 31
2947 #define FW_PORT_CMD_LSTATUS32_M 0x1
2948 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S)
2949 #define FW_PORT_CMD_LSTATUS32_G(x) \
2950 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2951 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
2952
2953 #define FW_PORT_CMD_LINKDNRC32_S 28
2954 #define FW_PORT_CMD_LINKDNRC32_M 0x7
2955 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S)
2956 #define FW_PORT_CMD_LINKDNRC32_G(x) \
2957 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2958
2959 #define FW_PORT_CMD_DCBXDIS32_S 27
2960 #define FW_PORT_CMD_DCBXDIS32_M 0x1
2961 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S)
2962 #define FW_PORT_CMD_DCBXDIS32_G(x) \
2963 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2964 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
2965
2966 #define FW_PORT_CMD_MDIOCAP32_S 26
2967 #define FW_PORT_CMD_MDIOCAP32_M 0x1
2968 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S)
2969 #define FW_PORT_CMD_MDIOCAP32_G(x) \
2970 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
2971 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
2972
2973 #define FW_PORT_CMD_MDIOADDR32_S 21
2974 #define FW_PORT_CMD_MDIOADDR32_M 0x1f
2975 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S)
2976 #define FW_PORT_CMD_MDIOADDR32_G(x) \
2977 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
2978
2979 #define FW_PORT_CMD_PORTTYPE32_S 13
2980 #define FW_PORT_CMD_PORTTYPE32_M 0xff
2981 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S)
2982 #define FW_PORT_CMD_PORTTYPE32_G(x) \
2983 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
2984
2985 #define FW_PORT_CMD_MODTYPE32_S 8
2986 #define FW_PORT_CMD_MODTYPE32_M 0x1f
2987 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S)
2988 #define FW_PORT_CMD_MODTYPE32_G(x) \
2989 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
2990
2991 #define FW_PORT_CMD_CBLLEN32_S 0
2992 #define FW_PORT_CMD_CBLLEN32_M 0xff
2993 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S)
2994 #define FW_PORT_CMD_CBLLEN32_G(x) \
2995 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
2996
2997 #define FW_PORT_CMD_AUXLINFO32_S 24
2998 #define FW_PORT_CMD_AUXLINFO32_M 0xff
2999 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S)
3000 #define FW_PORT_CMD_AUXLINFO32_G(x) \
3001 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
3002
3003 #define FW_PORT_AUXLINFO32_KX4_S 2
3004 #define FW_PORT_AUXLINFO32_KX4_M 0x1
3005 #define FW_PORT_AUXLINFO32_KX4_V(x) \
3006 ((x) << FW_PORT_AUXLINFO32_KX4_S)
3007 #define FW_PORT_AUXLINFO32_KX4_G(x) \
3008 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
3009 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U)
3010
3011 #define FW_PORT_AUXLINFO32_KR_S 1
3012 #define FW_PORT_AUXLINFO32_KR_M 0x1
3013 #define FW_PORT_AUXLINFO32_KR_V(x) \
3014 ((x) << FW_PORT_AUXLINFO32_KR_S)
3015 #define FW_PORT_AUXLINFO32_KR_G(x) \
3016 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
3017 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
3018
3019 #define FW_PORT_CMD_MTU32_S 0
3020 #define FW_PORT_CMD_MTU32_M 0xffff
3021 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S)
3022 #define FW_PORT_CMD_MTU32_G(x) \
3023 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
3024
3025 enum fw_port_type {
3026 FW_PORT_TYPE_FIBER_XFI,
3027 FW_PORT_TYPE_FIBER_XAUI,
3028 FW_PORT_TYPE_BT_SGMII,
3029 FW_PORT_TYPE_BT_XFI,
3030 FW_PORT_TYPE_BT_XAUI,
3031 FW_PORT_TYPE_KX4,
3032 FW_PORT_TYPE_CX4,
3033 FW_PORT_TYPE_KX,
3034 FW_PORT_TYPE_KR,
3035 FW_PORT_TYPE_SFP,
3036 FW_PORT_TYPE_BP_AP,
3037 FW_PORT_TYPE_BP4_AP,
3038 FW_PORT_TYPE_QSFP_10G,
3039 FW_PORT_TYPE_QSA,
3040 FW_PORT_TYPE_QSFP,
3041 FW_PORT_TYPE_BP40_BA,
3042 FW_PORT_TYPE_KR4_100G,
3043 FW_PORT_TYPE_CR4_QSFP,
3044 FW_PORT_TYPE_CR_QSFP,
3045 FW_PORT_TYPE_CR2_QSFP,
3046 FW_PORT_TYPE_SFP28,
3047 FW_PORT_TYPE_KR_SFP28,
3048 FW_PORT_TYPE_KR_XLAUI,
3049
3050 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
3051 };
3052
3053 enum fw_port_module_type {
3054 FW_PORT_MOD_TYPE_NA,
3055 FW_PORT_MOD_TYPE_LR,
3056 FW_PORT_MOD_TYPE_SR,
3057 FW_PORT_MOD_TYPE_ER,
3058 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
3059 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
3060 FW_PORT_MOD_TYPE_LRM,
3061 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
3062 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
3063 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
3064
3065 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
3066 };
3067
3068 enum fw_port_mod_sub_type {
3069 FW_PORT_MOD_SUB_TYPE_NA,
3070 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
3071 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
3072 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
3073 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
3074 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
3075 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
3076
3077
3078
3079
3080
3081 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
3082 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
3083 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
3084 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
3085 };
3086
3087 enum fw_port_stats_tx_index {
3088 FW_STAT_TX_PORT_BYTES_IX = 0,
3089 FW_STAT_TX_PORT_FRAMES_IX,
3090 FW_STAT_TX_PORT_BCAST_IX,
3091 FW_STAT_TX_PORT_MCAST_IX,
3092 FW_STAT_TX_PORT_UCAST_IX,
3093 FW_STAT_TX_PORT_ERROR_IX,
3094 FW_STAT_TX_PORT_64B_IX,
3095 FW_STAT_TX_PORT_65B_127B_IX,
3096 FW_STAT_TX_PORT_128B_255B_IX,
3097 FW_STAT_TX_PORT_256B_511B_IX,
3098 FW_STAT_TX_PORT_512B_1023B_IX,
3099 FW_STAT_TX_PORT_1024B_1518B_IX,
3100 FW_STAT_TX_PORT_1519B_MAX_IX,
3101 FW_STAT_TX_PORT_DROP_IX,
3102 FW_STAT_TX_PORT_PAUSE_IX,
3103 FW_STAT_TX_PORT_PPP0_IX,
3104 FW_STAT_TX_PORT_PPP1_IX,
3105 FW_STAT_TX_PORT_PPP2_IX,
3106 FW_STAT_TX_PORT_PPP3_IX,
3107 FW_STAT_TX_PORT_PPP4_IX,
3108 FW_STAT_TX_PORT_PPP5_IX,
3109 FW_STAT_TX_PORT_PPP6_IX,
3110 FW_STAT_TX_PORT_PPP7_IX,
3111 FW_NUM_PORT_TX_STATS
3112 };
3113
3114 enum fw_port_stat_rx_index {
3115 FW_STAT_RX_PORT_BYTES_IX = 0,
3116 FW_STAT_RX_PORT_FRAMES_IX,
3117 FW_STAT_RX_PORT_BCAST_IX,
3118 FW_STAT_RX_PORT_MCAST_IX,
3119 FW_STAT_RX_PORT_UCAST_IX,
3120 FW_STAT_RX_PORT_MTU_ERROR_IX,
3121 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
3122 FW_STAT_RX_PORT_CRC_ERROR_IX,
3123 FW_STAT_RX_PORT_LEN_ERROR_IX,
3124 FW_STAT_RX_PORT_SYM_ERROR_IX,
3125 FW_STAT_RX_PORT_64B_IX,
3126 FW_STAT_RX_PORT_65B_127B_IX,
3127 FW_STAT_RX_PORT_128B_255B_IX,
3128 FW_STAT_RX_PORT_256B_511B_IX,
3129 FW_STAT_RX_PORT_512B_1023B_IX,
3130 FW_STAT_RX_PORT_1024B_1518B_IX,
3131 FW_STAT_RX_PORT_1519B_MAX_IX,
3132 FW_STAT_RX_PORT_PAUSE_IX,
3133 FW_STAT_RX_PORT_PPP0_IX,
3134 FW_STAT_RX_PORT_PPP1_IX,
3135 FW_STAT_RX_PORT_PPP2_IX,
3136 FW_STAT_RX_PORT_PPP3_IX,
3137 FW_STAT_RX_PORT_PPP4_IX,
3138 FW_STAT_RX_PORT_PPP5_IX,
3139 FW_STAT_RX_PORT_PPP6_IX,
3140 FW_STAT_RX_PORT_PPP7_IX,
3141 FW_STAT_RX_PORT_LESS_64B_IX,
3142 FW_STAT_RX_PORT_MAC_ERROR_IX,
3143 FW_NUM_PORT_RX_STATS
3144 };
3145
3146
3147 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3148
3149 struct fw_port_stats_cmd {
3150 __be32 op_to_portid;
3151 __be32 retval_len16;
3152 union fw_port_stats {
3153 struct fw_port_stats_ctl {
3154 u8 nstats_bg_bm;
3155 u8 tx_ix;
3156 __be16 r6;
3157 __be32 r7;
3158 __be64 stat0;
3159 __be64 stat1;
3160 __be64 stat2;
3161 __be64 stat3;
3162 __be64 stat4;
3163 __be64 stat5;
3164 } ctl;
3165 struct fw_port_stats_all {
3166 __be64 tx_bytes;
3167 __be64 tx_frames;
3168 __be64 tx_bcast;
3169 __be64 tx_mcast;
3170 __be64 tx_ucast;
3171 __be64 tx_error;
3172 __be64 tx_64b;
3173 __be64 tx_65b_127b;
3174 __be64 tx_128b_255b;
3175 __be64 tx_256b_511b;
3176 __be64 tx_512b_1023b;
3177 __be64 tx_1024b_1518b;
3178 __be64 tx_1519b_max;
3179 __be64 tx_drop;
3180 __be64 tx_pause;
3181 __be64 tx_ppp0;
3182 __be64 tx_ppp1;
3183 __be64 tx_ppp2;
3184 __be64 tx_ppp3;
3185 __be64 tx_ppp4;
3186 __be64 tx_ppp5;
3187 __be64 tx_ppp6;
3188 __be64 tx_ppp7;
3189 __be64 rx_bytes;
3190 __be64 rx_frames;
3191 __be64 rx_bcast;
3192 __be64 rx_mcast;
3193 __be64 rx_ucast;
3194 __be64 rx_mtu_error;
3195 __be64 rx_mtu_crc_error;
3196 __be64 rx_crc_error;
3197 __be64 rx_len_error;
3198 __be64 rx_sym_error;
3199 __be64 rx_64b;
3200 __be64 rx_65b_127b;
3201 __be64 rx_128b_255b;
3202 __be64 rx_256b_511b;
3203 __be64 rx_512b_1023b;
3204 __be64 rx_1024b_1518b;
3205 __be64 rx_1519b_max;
3206 __be64 rx_pause;
3207 __be64 rx_ppp0;
3208 __be64 rx_ppp1;
3209 __be64 rx_ppp2;
3210 __be64 rx_ppp3;
3211 __be64 rx_ppp4;
3212 __be64 rx_ppp5;
3213 __be64 rx_ppp6;
3214 __be64 rx_ppp7;
3215 __be64 rx_less_64b;
3216 __be64 rx_bg_drop;
3217 __be64 rx_bg_trunc;
3218 } all;
3219 } u;
3220 };
3221
3222
3223 #define FW_NUM_LB_STATS 16
3224 enum fw_port_lb_stats_index {
3225 FW_STAT_LB_PORT_BYTES_IX,
3226 FW_STAT_LB_PORT_FRAMES_IX,
3227 FW_STAT_LB_PORT_BCAST_IX,
3228 FW_STAT_LB_PORT_MCAST_IX,
3229 FW_STAT_LB_PORT_UCAST_IX,
3230 FW_STAT_LB_PORT_ERROR_IX,
3231 FW_STAT_LB_PORT_64B_IX,
3232 FW_STAT_LB_PORT_65B_127B_IX,
3233 FW_STAT_LB_PORT_128B_255B_IX,
3234 FW_STAT_LB_PORT_256B_511B_IX,
3235 FW_STAT_LB_PORT_512B_1023B_IX,
3236 FW_STAT_LB_PORT_1024B_1518B_IX,
3237 FW_STAT_LB_PORT_1519B_MAX_IX,
3238 FW_STAT_LB_PORT_DROP_FRAMES_IX
3239 };
3240
3241 struct fw_port_lb_stats_cmd {
3242 __be32 op_to_lbport;
3243 __be32 retval_len16;
3244 union fw_port_lb_stats {
3245 struct fw_port_lb_stats_ctl {
3246 u8 nstats_bg_bm;
3247 u8 ix_pkd;
3248 __be16 r6;
3249 __be32 r7;
3250 __be64 stat0;
3251 __be64 stat1;
3252 __be64 stat2;
3253 __be64 stat3;
3254 __be64 stat4;
3255 __be64 stat5;
3256 } ctl;
3257 struct fw_port_lb_stats_all {
3258 __be64 tx_bytes;
3259 __be64 tx_frames;
3260 __be64 tx_bcast;
3261 __be64 tx_mcast;
3262 __be64 tx_ucast;
3263 __be64 tx_error;
3264 __be64 tx_64b;
3265 __be64 tx_65b_127b;
3266 __be64 tx_128b_255b;
3267 __be64 tx_256b_511b;
3268 __be64 tx_512b_1023b;
3269 __be64 tx_1024b_1518b;
3270 __be64 tx_1519b_max;
3271 __be64 rx_lb_drop;
3272 __be64 rx_lb_trunc;
3273 } all;
3274 } u;
3275 };
3276
3277 enum fw_ptp_subop {
3278
3279 FW_PTP_SC_INIT_TIMER = 0x00,
3280 FW_PTP_SC_TX_TYPE = 0x01,
3281
3282 FW_PTP_SC_RXTIME_STAMP = 0x08,
3283 FW_PTP_SC_RDRX_TYPE = 0x09,
3284
3285 FW_PTP_SC_ADJ_FREQ = 0x10,
3286 FW_PTP_SC_ADJ_TIME = 0x11,
3287 FW_PTP_SC_ADJ_FTIME = 0x12,
3288 FW_PTP_SC_WALL_CLOCK = 0x13,
3289 FW_PTP_SC_GET_TIME = 0x14,
3290 FW_PTP_SC_SET_TIME = 0x15,
3291 };
3292
3293 struct fw_ptp_cmd {
3294 __be32 op_to_portid;
3295 __be32 retval_len16;
3296 union fw_ptp {
3297 struct fw_ptp_sc {
3298 __u8 sc;
3299 __u8 r3[7];
3300 } scmd;
3301 struct fw_ptp_init {
3302 __u8 sc;
3303 __u8 txchan;
3304 __be16 absid;
3305 __be16 mode;
3306 __be16 r3;
3307 } init;
3308 struct fw_ptp_ts {
3309 __u8 sc;
3310 __u8 sign;
3311 __be16 r3;
3312 __be32 ppb;
3313 __be64 tm;
3314 } ts;
3315 } u;
3316 __be64 r3;
3317 };
3318
3319 #define FW_PTP_CMD_PORTID_S 0
3320 #define FW_PTP_CMD_PORTID_M 0xf
3321 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S)
3322 #define FW_PTP_CMD_PORTID_G(x) \
3323 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3324
3325 struct fw_rss_ind_tbl_cmd {
3326 __be32 op_to_viid;
3327 __be32 retval_len16;
3328 __be16 niqid;
3329 __be16 startidx;
3330 __be32 r3;
3331 __be32 iq0_to_iq2;
3332 __be32 iq3_to_iq5;
3333 __be32 iq6_to_iq8;
3334 __be32 iq9_to_iq11;
3335 __be32 iq12_to_iq14;
3336 __be32 iq15_to_iq17;
3337 __be32 iq18_to_iq20;
3338 __be32 iq21_to_iq23;
3339 __be32 iq24_to_iq26;
3340 __be32 iq27_to_iq29;
3341 __be32 iq30_iq31;
3342 __be32 r15_lo;
3343 };
3344
3345 #define FW_RSS_IND_TBL_CMD_VIID_S 0
3346 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3347
3348 #define FW_RSS_IND_TBL_CMD_IQ0_S 20
3349 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3350
3351 #define FW_RSS_IND_TBL_CMD_IQ1_S 10
3352 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3353
3354 #define FW_RSS_IND_TBL_CMD_IQ2_S 0
3355 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3356
3357 struct fw_rss_glb_config_cmd {
3358 __be32 op_to_write;
3359 __be32 retval_len16;
3360 union fw_rss_glb_config {
3361 struct fw_rss_glb_config_manual {
3362 __be32 mode_pkd;
3363 __be32 r3;
3364 __be64 r4;
3365 __be64 r5;
3366 } manual;
3367 struct fw_rss_glb_config_basicvirtual {
3368 __be32 mode_pkd;
3369 __be32 synmapen_to_hashtoeplitz;
3370 __be64 r8;
3371 __be64 r9;
3372 } basicvirtual;
3373 } u;
3374 };
3375
3376 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
3377 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
3378 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3379 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3380 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3381
3382 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
3383 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3384
3385 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
3386 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
3387 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3388 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
3389 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3390
3391 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
3392 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
3393 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3394 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
3395 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3396
3397 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
3398 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
3399 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3400 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
3401 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3402
3403 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
3404 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
3405 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3406 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
3407 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3408
3409 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
3410 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
3411 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3412 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
3413 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3414
3415 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
3416 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
3417 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3418 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
3419 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3420
3421 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
3422 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
3423 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3424 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
3425 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3426
3427 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
3428 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
3429 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3430 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
3431 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3432
3433 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
3434 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3435 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3436 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
3437 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3438
3439 struct fw_rss_vi_config_cmd {
3440 __be32 op_to_viid;
3441 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3442 __be32 retval_len16;
3443 union fw_rss_vi_config {
3444 struct fw_rss_vi_config_manual {
3445 __be64 r3;
3446 __be64 r4;
3447 __be64 r5;
3448 } manual;
3449 struct fw_rss_vi_config_basicvirtual {
3450 __be32 r6;
3451 __be32 defaultq_to_udpen;
3452 __be64 r9;
3453 __be64 r10;
3454 } basicvirtual;
3455 } u;
3456 };
3457
3458 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0
3459 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3460
3461 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
3462 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
3463 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
3464 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3465 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
3466 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3467 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3468
3469 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
3470 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
3471 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3472 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
3473 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3474
3475 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
3476 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
3477 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3478 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
3479 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3480
3481 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
3482 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
3483 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3484 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
3485 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3486
3487 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
3488 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
3489 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3490 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
3491 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3492
3493 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
3494 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3495 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3496
3497 enum fw_sched_sc {
3498 FW_SCHED_SC_PARAMS = 1,
3499 };
3500
3501 struct fw_sched_cmd {
3502 __be32 op_to_write;
3503 __be32 retval_len16;
3504 union fw_sched {
3505 struct fw_sched_config {
3506 __u8 sc;
3507 __u8 type;
3508 __u8 minmaxen;
3509 __u8 r3[5];
3510 __u8 nclasses[4];
3511 __be32 r4;
3512 } config;
3513 struct fw_sched_params {
3514 __u8 sc;
3515 __u8 type;
3516 __u8 level;
3517 __u8 mode;
3518 __u8 unit;
3519 __u8 rate;
3520 __u8 ch;
3521 __u8 cl;
3522 __be32 min;
3523 __be32 max;
3524 __be16 weight;
3525 __be16 pktsize;
3526 __be16 burstsize;
3527 __be16 r4;
3528 } params;
3529 } u;
3530 };
3531
3532 struct fw_clip_cmd {
3533 __be32 op_to_write;
3534 __be32 alloc_to_len16;
3535 __be64 ip_hi;
3536 __be64 ip_lo;
3537 __be32 r4[2];
3538 };
3539
3540 #define FW_CLIP_CMD_ALLOC_S 31
3541 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
3542 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
3543
3544 #define FW_CLIP_CMD_FREE_S 30
3545 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
3546 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
3547
3548 enum fw_error_type {
3549 FW_ERROR_TYPE_EXCEPTION = 0x0,
3550 FW_ERROR_TYPE_HWMODULE = 0x1,
3551 FW_ERROR_TYPE_WR = 0x2,
3552 FW_ERROR_TYPE_ACL = 0x3,
3553 };
3554
3555 struct fw_error_cmd {
3556 __be32 op_to_type;
3557 __be32 len16_pkd;
3558 union fw_error {
3559 struct fw_error_exception {
3560 __be32 info[6];
3561 } exception;
3562 struct fw_error_hwmodule {
3563 __be32 regaddr;
3564 __be32 regval;
3565 } hwmodule;
3566 struct fw_error_wr {
3567 __be16 cidx;
3568 __be16 pfn_vfn;
3569 __be32 eqid;
3570 u8 wrhdr[16];
3571 } wr;
3572 struct fw_error_acl {
3573 __be16 cidx;
3574 __be16 pfn_vfn;
3575 __be32 eqid;
3576 __be16 mv_pkd;
3577 u8 val[6];
3578 __be64 r4;
3579 } acl;
3580 } u;
3581 };
3582
3583 struct fw_debug_cmd {
3584 __be32 op_type;
3585 __be32 len16_pkd;
3586 union fw_debug {
3587 struct fw_debug_assert {
3588 __be32 fcid;
3589 __be32 line;
3590 __be32 x;
3591 __be32 y;
3592 u8 filename_0_7[8];
3593 u8 filename_8_15[8];
3594 __be64 r3;
3595 } assert;
3596 struct fw_debug_prt {
3597 __be16 dprtstridx;
3598 __be16 r3[3];
3599 __be32 dprtstrparam0;
3600 __be32 dprtstrparam1;
3601 __be32 dprtstrparam2;
3602 __be32 dprtstrparam3;
3603 } prt;
3604 } u;
3605 };
3606
3607 #define FW_DEBUG_CMD_TYPE_S 0
3608 #define FW_DEBUG_CMD_TYPE_M 0xff
3609 #define FW_DEBUG_CMD_TYPE_G(x) \
3610 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3611
3612 struct fw_hma_cmd {
3613 __be32 op_pkd;
3614 __be32 retval_len16;
3615 __be32 mode_to_pcie_params;
3616 __be32 naddr_size;
3617 __be32 addr_size_pkd;
3618 __be32 r6;
3619 __be64 phy_address[5];
3620 };
3621
3622 #define FW_HMA_CMD_MODE_S 31
3623 #define FW_HMA_CMD_MODE_M 0x1
3624 #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S)
3625 #define FW_HMA_CMD_MODE_G(x) \
3626 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3627 #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U)
3628
3629 #define FW_HMA_CMD_SOC_S 30
3630 #define FW_HMA_CMD_SOC_M 0x1
3631 #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S)
3632 #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3633 #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U)
3634
3635 #define FW_HMA_CMD_EOC_S 29
3636 #define FW_HMA_CMD_EOC_M 0x1
3637 #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S)
3638 #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3639 #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U)
3640
3641 #define FW_HMA_CMD_PCIE_PARAMS_S 0
3642 #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff
3643 #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3644 #define FW_HMA_CMD_PCIE_PARAMS_G(x) \
3645 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3646
3647 #define FW_HMA_CMD_NADDR_S 12
3648 #define FW_HMA_CMD_NADDR_M 0x3f
3649 #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S)
3650 #define FW_HMA_CMD_NADDR_G(x) \
3651 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3652
3653 #define FW_HMA_CMD_SIZE_S 0
3654 #define FW_HMA_CMD_SIZE_M 0xfff
3655 #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S)
3656 #define FW_HMA_CMD_SIZE_G(x) \
3657 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3658
3659 #define FW_HMA_CMD_ADDR_SIZE_S 11
3660 #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff
3661 #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S)
3662 #define FW_HMA_CMD_ADDR_SIZE_G(x) \
3663 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3664
3665 enum pcie_fw_eval {
3666 PCIE_FW_EVAL_CRASH = 0,
3667 };
3668
3669 #define PCIE_FW_ERR_S 31
3670 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
3671 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
3672
3673 #define PCIE_FW_INIT_S 30
3674 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
3675 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
3676
3677 #define PCIE_FW_HALT_S 29
3678 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
3679 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
3680
3681 #define PCIE_FW_EVAL_S 24
3682 #define PCIE_FW_EVAL_M 0x7
3683 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3684
3685 #define PCIE_FW_MASTER_VLD_S 15
3686 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3687 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
3688
3689 #define PCIE_FW_MASTER_S 12
3690 #define PCIE_FW_MASTER_M 0x7
3691 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
3692 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3693
3694 struct fw_hdr {
3695 u8 ver;
3696 u8 chip;
3697 __be16 len512;
3698 __be32 fw_ver;
3699 __be32 tp_microcode_ver;
3700 u8 intfver_nic;
3701 u8 intfver_vnic;
3702 u8 intfver_ofld;
3703 u8 intfver_ri;
3704 u8 intfver_iscsipdu;
3705 u8 intfver_iscsi;
3706 u8 intfver_fcoepdu;
3707 u8 intfver_fcoe;
3708 __u32 reserved2;
3709 __u32 reserved3;
3710 __u32 reserved4;
3711 __be32 flags;
3712 __be32 reserved6[23];
3713 };
3714
3715 enum fw_hdr_chip {
3716 FW_HDR_CHIP_T4,
3717 FW_HDR_CHIP_T5,
3718 FW_HDR_CHIP_T6
3719 };
3720
3721 #define FW_HDR_FW_VER_MAJOR_S 24
3722 #define FW_HDR_FW_VER_MAJOR_M 0xff
3723 #define FW_HDR_FW_VER_MAJOR_V(x) \
3724 ((x) << FW_HDR_FW_VER_MAJOR_S)
3725 #define FW_HDR_FW_VER_MAJOR_G(x) \
3726 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3727
3728 #define FW_HDR_FW_VER_MINOR_S 16
3729 #define FW_HDR_FW_VER_MINOR_M 0xff
3730 #define FW_HDR_FW_VER_MINOR_V(x) \
3731 ((x) << FW_HDR_FW_VER_MINOR_S)
3732 #define FW_HDR_FW_VER_MINOR_G(x) \
3733 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3734
3735 #define FW_HDR_FW_VER_MICRO_S 8
3736 #define FW_HDR_FW_VER_MICRO_M 0xff
3737 #define FW_HDR_FW_VER_MICRO_V(x) \
3738 ((x) << FW_HDR_FW_VER_MICRO_S)
3739 #define FW_HDR_FW_VER_MICRO_G(x) \
3740 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3741
3742 #define FW_HDR_FW_VER_BUILD_S 0
3743 #define FW_HDR_FW_VER_BUILD_M 0xff
3744 #define FW_HDR_FW_VER_BUILD_V(x) \
3745 ((x) << FW_HDR_FW_VER_BUILD_S)
3746 #define FW_HDR_FW_VER_BUILD_G(x) \
3747 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3748
3749 enum fw_hdr_intfver {
3750 FW_HDR_INTFVER_NIC = 0x00,
3751 FW_HDR_INTFVER_VNIC = 0x00,
3752 FW_HDR_INTFVER_OFLD = 0x00,
3753 FW_HDR_INTFVER_RI = 0x00,
3754 FW_HDR_INTFVER_ISCSIPDU = 0x00,
3755 FW_HDR_INTFVER_ISCSI = 0x00,
3756 FW_HDR_INTFVER_FCOEPDU = 0x00,
3757 FW_HDR_INTFVER_FCOE = 0x00,
3758 };
3759
3760 enum fw_hdr_flags {
3761 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3762 };
3763
3764
3765 #define FW_DEVLOG_FMT_LEN 192
3766
3767
3768 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3769
3770
3771 enum fw_devlog_level {
3772 FW_DEVLOG_LEVEL_EMERG = 0x0,
3773 FW_DEVLOG_LEVEL_CRIT = 0x1,
3774 FW_DEVLOG_LEVEL_ERR = 0x2,
3775 FW_DEVLOG_LEVEL_NOTICE = 0x3,
3776 FW_DEVLOG_LEVEL_INFO = 0x4,
3777 FW_DEVLOG_LEVEL_DEBUG = 0x5,
3778 FW_DEVLOG_LEVEL_MAX = 0x5,
3779 };
3780
3781
3782 enum fw_devlog_facility {
3783 FW_DEVLOG_FACILITY_CORE = 0x00,
3784 FW_DEVLOG_FACILITY_CF = 0x01,
3785 FW_DEVLOG_FACILITY_SCHED = 0x02,
3786 FW_DEVLOG_FACILITY_TIMER = 0x04,
3787 FW_DEVLOG_FACILITY_RES = 0x06,
3788 FW_DEVLOG_FACILITY_HW = 0x08,
3789 FW_DEVLOG_FACILITY_FLR = 0x10,
3790 FW_DEVLOG_FACILITY_DMAQ = 0x12,
3791 FW_DEVLOG_FACILITY_PHY = 0x14,
3792 FW_DEVLOG_FACILITY_MAC = 0x16,
3793 FW_DEVLOG_FACILITY_PORT = 0x18,
3794 FW_DEVLOG_FACILITY_VI = 0x1A,
3795 FW_DEVLOG_FACILITY_FILTER = 0x1C,
3796 FW_DEVLOG_FACILITY_ACL = 0x1E,
3797 FW_DEVLOG_FACILITY_TM = 0x20,
3798 FW_DEVLOG_FACILITY_QFC = 0x22,
3799 FW_DEVLOG_FACILITY_DCB = 0x24,
3800 FW_DEVLOG_FACILITY_ETH = 0x26,
3801 FW_DEVLOG_FACILITY_OFLD = 0x28,
3802 FW_DEVLOG_FACILITY_RI = 0x2A,
3803 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
3804 FW_DEVLOG_FACILITY_FCOE = 0x2E,
3805 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
3806 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
3807 FW_DEVLOG_FACILITY_CHNET = 0x34,
3808 FW_DEVLOG_FACILITY_MAX = 0x34,
3809 };
3810
3811
3812 struct fw_devlog_e {
3813 __be64 timestamp;
3814 __be32 seqno;
3815 __be16 reserved1;
3816 __u8 level;
3817 __u8 facility;
3818 __u8 fmt[FW_DEVLOG_FMT_LEN];
3819 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
3820 __be32 reserved3[4];
3821 };
3822
3823 struct fw_devlog_cmd {
3824 __be32 op_to_write;
3825 __be32 retval_len16;
3826 __u8 level;
3827 __u8 r2[7];
3828 __be32 memtype_devlog_memaddr16_devlog;
3829 __be32 memsize_devlog;
3830 __be32 r3[2];
3831 };
3832
3833 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3834 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3835 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3836 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3837 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3838
3839 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3840 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3841 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3842 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3843 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855 #define PCIE_FW_PF_DEVLOG 7
3856
3857 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3858 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3859 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3860 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3861 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3862 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3863 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3864
3865 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4
3866 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff
3867 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3868 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3869 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3870
3871 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
3872 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
3873 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3874 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3875 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3876
3877 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3878
3879 struct fw_crypto_lookaside_wr {
3880 __be32 op_to_cctx_size;
3881 __be32 len16_pkd;
3882 __be32 session_id;
3883 __be32 rx_chid_to_rx_q_id;
3884 __be32 key_addr;
3885 __be32 pld_size_hash_size;
3886 __be64 cookie;
3887 };
3888
3889 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3890 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3891 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3892 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3893 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3894 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3895 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3896
3897 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3898 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3899 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3900 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3901 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3902 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3903 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3904 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3905
3906 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3907 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3908 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3909 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3910 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3911 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3912 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3913
3914 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3915 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3916 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3917 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3918 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3919 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3920 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3921
3922 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3923 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3924 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3925 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3926 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3927 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3928 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3929
3930 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3931 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3932 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3933 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3934 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3935 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3936 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3937
3938 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3939 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3940 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3941 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3942 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3943 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3944 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3945
3946 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27
3947 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3
3948 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3949 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3950 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3951 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3952
3953 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3954 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3955 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3956 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3957 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3958 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3959 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3960
3961 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23
3962 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3
3963 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3964 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3965 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3966 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3967
3968 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15
3969 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff
3970 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
3971 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
3972 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
3973 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
3974 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
3975
3976 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3977 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3978 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3979 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3980 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3981 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3982 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3983
3984 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3985 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3986 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3987 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3988 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3989 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3990 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3991
3992 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3993 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3994 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3995 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3996 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3997 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3998 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3999
4000 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
4001 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
4002 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
4003 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
4004 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
4005 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
4006 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
4007
4008 struct fw_tlstx_data_wr {
4009 __be32 op_to_immdlen;
4010 __be32 flowid_len16;
4011 __be32 plen;
4012 __be32 lsodisable_to_flags;
4013 __be32 r5;
4014 __be32 ctxloc_to_exp;
4015 __be16 mfs;
4016 __be16 adjustedplen_pkd;
4017 __be16 expinplenmax_pkd;
4018 u8 pdusinplenmax_pkd;
4019 u8 r10;
4020 };
4021
4022 #define FW_TLSTX_DATA_WR_OPCODE_S 24
4023 #define FW_TLSTX_DATA_WR_OPCODE_M 0xff
4024 #define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
4025 #define FW_TLSTX_DATA_WR_OPCODE_G(x) \
4026 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
4027
4028 #define FW_TLSTX_DATA_WR_COMPL_S 21
4029 #define FW_TLSTX_DATA_WR_COMPL_M 0x1
4030 #define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S)
4031 #define FW_TLSTX_DATA_WR_COMPL_G(x) \
4032 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
4033 #define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U)
4034
4035 #define FW_TLSTX_DATA_WR_IMMDLEN_S 0
4036 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff
4037 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
4038 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \
4039 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
4040
4041 #define FW_TLSTX_DATA_WR_FLOWID_S 8
4042 #define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff
4043 #define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
4044 #define FW_TLSTX_DATA_WR_FLOWID_G(x) \
4045 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
4046
4047 #define FW_TLSTX_DATA_WR_LEN16_S 0
4048 #define FW_TLSTX_DATA_WR_LEN16_M 0xff
4049 #define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S)
4050 #define FW_TLSTX_DATA_WR_LEN16_G(x) \
4051 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
4052
4053 #define FW_TLSTX_DATA_WR_LSODISABLE_S 31
4054 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1
4055 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
4056 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
4057 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
4058 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
4059 #define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
4060
4061 #define FW_TLSTX_DATA_WR_ALIGNPLD_S 30
4062 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1
4063 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
4064 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \
4065 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
4066 #define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
4067
4068 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
4069 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
4070 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
4071 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
4072 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
4073 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
4074 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
4075 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
4076
4077 #define FW_TLSTX_DATA_WR_FLAGS_S 0
4078 #define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff
4079 #define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
4080 #define FW_TLSTX_DATA_WR_FLAGS_G(x) \
4081 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
4082
4083 #define FW_TLSTX_DATA_WR_CTXLOC_S 30
4084 #define FW_TLSTX_DATA_WR_CTXLOC_M 0x3
4085 #define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
4086 #define FW_TLSTX_DATA_WR_CTXLOC_G(x) \
4087 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
4088
4089 #define FW_TLSTX_DATA_WR_IVDSGL_S 29
4090 #define FW_TLSTX_DATA_WR_IVDSGL_M 0x1
4091 #define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4092 #define FW_TLSTX_DATA_WR_IVDSGL_G(x) \
4093 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4094 #define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4095
4096 #define FW_TLSTX_DATA_WR_KEYSIZE_S 24
4097 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f
4098 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4099 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \
4100 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4101
4102 #define FW_TLSTX_DATA_WR_NUMIVS_S 14
4103 #define FW_TLSTX_DATA_WR_NUMIVS_M 0xff
4104 #define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4105 #define FW_TLSTX_DATA_WR_NUMIVS_G(x) \
4106 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4107
4108 #define FW_TLSTX_DATA_WR_EXP_S 0
4109 #define FW_TLSTX_DATA_WR_EXP_M 0x3fff
4110 #define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S)
4111 #define FW_TLSTX_DATA_WR_EXP_G(x) \
4112 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4113
4114 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4115 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4116 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4117
4118 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4119 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4120 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4121
4122 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4123 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4124 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4125
4126 #endif