drivers/net/ethernet/chelsio/cxgb4/cxgb4

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This source file includes following definitions.
link_report
dcb_tx_queue_prio_enable
cxgb4_dcb_enabled
t4_os_link_changed
t4_os_portmod_changed
cxgb4_set_addr_hash
cxgb4_mac_sync
cxgb4_mac_unsync
set_rxmode
cxgb4_change_mac
link_start
dcb_rpl
fwevtq_handler
disable_msi
t4_nondata_intr
name_msix_vecs
cxgb4_set_msix_aff
cxgb4_clear_msix_aff
request_msix_queue_irqs
free_msix_queue_irqs
setup_ppod_edram
cxgb4_write_rss
setup_rss
rxq_to_chan
quiesce_rx
disable_interrupts
enable_rx
setup_fw_sge_queues
setup_sge_queues
cxgb_select_queue
closest_timer
closest_thres
cxgb4_set_rspq_intr_params
cxgb_set_features
setup_debugfs
cxgb4_alloc_atid
cxgb4_free_atid
cxgb4_alloc_stid
cxgb4_alloc_sftid
cxgb4_free_stid
mk_tid_release
cxgb4_queue_tid_release
process_tid_release_list
cxgb4_remove_tid
tid_init
cxgb4_create_server
cxgb4_create_server6
cxgb4_remove_server
cxgb4_best_mtu
cxgb4_best_aligned_mtu
cxgb4_port_chan
cxgb4_port_e2cchan
cxgb4_dbfifo_count
cxgb4_port_viid
cxgb4_port_idx
cxgb4_get_tcp_stats
cxgb4_iscsi_init
cxgb4_flush_eq_cache
read_eq_indices
cxgb4_sync_txq_pidx
cxgb4_read_tpte
cxgb4_read_sge_timestamp
cxgb4_bar2_sge_qregs
check_neigh_update
netevent_cb
drain_db_fifo
disable_txq_db
enable_txq_db
disable_dbs
enable_dbs
notify_rdma_uld
process_db_full
sync_txq_pidx
recover_all_queues
process_db_drop
t4_db_full
t4_db_dropped
t4_register_netevent_notifier
detach_ulds
notify_ulds
cxgb4_inet6addr_handler
update_clip
cxgb_up
cxgb_down
cxgb_open
cxgb_close
cxgb4_create_server_filter
cxgb4_remove_server_filter
cxgb_get_stats
cxgb_ioctl
cxgb_set_rxmode
cxgb_change_mtu
cxgb4_mgmt_open
cxgb4_mgmt_fill_vf_station_mac_addr
cxgb4_mgmt_set_vf_mac
cxgb4_mgmt_get_vf_config
cxgb4_mgmt_get_phys_port_id
cxgb4_mgmt_set_vf_rate
cxgb4_mgmt_set_vf_vlan
cxgb4_mgmt_set_vf_link_state
cxgb_set_mac_addr
cxgb_netpoll
cxgb_set_tx_maxrate
cxgb_setup_tc_flower
cxgb_setup_tc_cls_u32
cxgb_setup_tc_block_cb
cxgb_setup_tc
cxgb_del_udp_tunnel
cxgb_add_udp_tunnel
cxgb_features_check
cxgb_fix_features
cxgb4_mgmt_get_drvinfo
notify_fatal_err
t4_fatal_err
setup_memwin
setup_memwin_rdma
adap_free_hma_mem
adap_config_hma
adap_init1
adap_init0_tweaks
phy_aq1202_version
find_phy_info
adap_init0_phy
adap_init0_config
find_fw_info
adap_init0
eeh_err_detected
eeh_slot_reset
eeh_resume
is_x_10g_port
cfg_queues
reduce_ethqs
get_msix_info
free_msix_info
enable_msix
init_rss
print_adapter_info
print_port_info
free_some_resources
t4_get_chip_type
cxgb4_mgmt_setup
cxgb4_iov_configure
init_one
remove_one
shutdown_one
cxgb4_init_module
cxgb4_cleanup_module
   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34 
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36 
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <linux/uaccess.h>
  66 #include <linux/crash_dump.h>
  67 #include <net/udp_tunnel.h>
  68 
  69 #include "cxgb4.h"
  70 #include "cxgb4_filter.h"
  71 #include "t4_regs.h"
  72 #include "t4_values.h"
  73 #include "t4_msg.h"
  74 #include "t4fw_api.h"
  75 #include "t4fw_version.h"
  76 #include "cxgb4_dcb.h"
  77 #include "srq.h"
  78 #include "cxgb4_debugfs.h"
  79 #include "clip_tbl.h"
  80 #include "l2t.h"
  81 #include "smt.h"
  82 #include "sched.h"
  83 #include "cxgb4_tc_u32.h"
  84 #include "cxgb4_tc_flower.h"
  85 #include "cxgb4_ptp.h"
  86 #include "cxgb4_cudbg.h"
  87 
  88 char cxgb4_driver_name[] = KBUILD_MODNAME;
  89 
  90 #ifdef DRV_VERSION
  91 #undef DRV_VERSION
  92 #endif
  93 #define DRV_VERSION "2.0.0-ko"
  94 const char cxgb4_driver_version[] = DRV_VERSION;
  95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  96 
  97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  98                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  99                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 100 
 101 /* Macros needed to support the PCI Device ID Table ...
 102  */
 103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 104         static const struct pci_device_id cxgb4_pci_tbl[] = {
 105 #define CXGB4_UNIFIED_PF 0x4
 106 
 107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
 108 
 109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 110  * called for both.
 111  */
 112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 113 
 114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 115                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
 116 
 117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 118                 { 0, } \
 119         }
 120 
 121 #include "t4_pci_id_tbl.h"
 122 
 123 #define FW4_FNAME "cxgb4/t4fw.bin"
 124 #define FW5_FNAME "cxgb4/t5fw.bin"
 125 #define FW6_FNAME "cxgb4/t6fw.bin"
 126 #define FW4_CFNAME "cxgb4/t4-config.txt"
 127 #define FW5_CFNAME "cxgb4/t5-config.txt"
 128 #define FW6_CFNAME "cxgb4/t6-config.txt"
 129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 131 #define PHY_AQ1202_DEVICEID 0x4409
 132 #define PHY_BCM84834_DEVICEID 0x4486
 133 
 134 MODULE_DESCRIPTION(DRV_DESC);
 135 MODULE_AUTHOR("Chelsio Communications");
 136 MODULE_LICENSE("Dual BSD/GPL");
 137 MODULE_VERSION(DRV_VERSION);
 138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 139 MODULE_FIRMWARE(FW4_FNAME);
 140 MODULE_FIRMWARE(FW5_FNAME);
 141 MODULE_FIRMWARE(FW6_FNAME);
 142 
 143 /*
 144  * The driver uses the best interrupt scheme available on a platform in the
 145  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 146  * of these schemes the driver may consider as follows:
 147  *
 148  * msi = 2: choose from among all three options
 149  * msi = 1: only consider MSI and INTx interrupts
 150  * msi = 0: force INTx interrupts
 151  */
 152 static int msi = 2;
 153 
 154 module_param(msi, int, 0644);
 155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 156 
 157 /*
 158  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 159  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 160  * boundaries.  This is a requirement for many architectures which will throw
 161  * a machine check fault if an attempt is made to access one of the 4-byte IP
 162  * header fields on a non-4-byte boundary.  And it's a major performance issue
 163  * even on some architectures which allow it like some implementations of the
 164  * x86 ISA.  However, some architectures don't mind this and for some very
 165  * edge-case performance sensitive applications (like forwarding large volumes
 166  * of small packets), setting this DMA offset to 0 will decrease the number of
 167  * PCI-E Bus transfers enough to measurably affect performance.
 168  */
 169 static int rx_dma_offset = 2;
 170 
 171 /* TX Queue select used to determine what algorithm to use for selecting TX
 172  * queue. Select between the kernel provided function (select_queue=0) or user
 173  * cxgb_select_queue function (select_queue=1)
 174  *
 175  * Default: select_queue=0
 176  */
 177 static int select_queue;
 178 module_param(select_queue, int, 0644);
 179 MODULE_PARM_DESC(select_queue,
 180                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 181 
 182 static struct dentry *cxgb4_debugfs_root;
 183 
 184 LIST_HEAD(adapter_list);
 185 DEFINE_MUTEX(uld_mutex);
 186 
 187 static void link_report(struct net_device *dev)
 188 {
 189         if (!netif_carrier_ok(dev))
 190                 netdev_info(dev, "link down\n");
 191         else {
 192                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 193 
 194                 const char *s;
 195                 const struct port_info *p = netdev_priv(dev);
 196 
 197                 switch (p->link_cfg.speed) {
 198                 case 100:
 199                         s = "100Mbps";
 200                         break;
 201                 case 1000:
 202                         s = "1Gbps";
 203                         break;
 204                 case 10000:
 205                         s = "10Gbps";
 206                         break;
 207                 case 25000:
 208                         s = "25Gbps";
 209                         break;
 210                 case 40000:
 211                         s = "40Gbps";
 212                         break;
 213                 case 50000:
 214                         s = "50Gbps";
 215                         break;
 216                 case 100000:
 217                         s = "100Gbps";
 218                         break;
 219                 default:
 220                         pr_info("%s: unsupported speed: %d\n",
 221                                 dev->name, p->link_cfg.speed);
 222                         return;
 223                 }
 224 
 225                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 226                             fc[p->link_cfg.fc]);
 227         }
 228 }
 229 
 230 #ifdef CONFIG_CHELSIO_T4_DCB
 231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 233 {
 234         struct port_info *pi = netdev_priv(dev);
 235         struct adapter *adap = pi->adapter;
 236         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 237         int i;
 238 
 239         /* We use a simple mapping of Port TX Queue Index to DCB
 240          * Priority when we're enabling DCB.
 241          */
 242         for (i = 0; i < pi->nqsets; i++, txq++) {
 243                 u32 name, value;
 244                 int err;
 245 
 246                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 247                         FW_PARAMS_PARAM_X_V(
 248                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 249                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 250                 value = enable ? i : 0xffffffff;
 251 
 252                 /* Since we can be called while atomic (from "interrupt
 253                  * level") we need to issue the Set Parameters Commannd
 254                  * without sleeping (timeout < 0).
 255                  */
 256                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 257                                             &name, &value,
 258                                             -FW_CMD_MAX_TIMEOUT);
 259 
 260                 if (err)
 261                         dev_err(adap->pdev_dev,
 262                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 263                                 enable ? "set" : "unset", pi->port_id, i, -err);
 264                 else
 265                         txq->dcb_prio = enable ? value : 0;
 266         }
 267 }
 268 
 269 int cxgb4_dcb_enabled(const struct net_device *dev)
 270 {
 271         struct port_info *pi = netdev_priv(dev);
 272 
 273         if (!pi->dcb.enabled)
 274                 return 0;
 275 
 276         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 277                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 278 }
 279 #endif /* CONFIG_CHELSIO_T4_DCB */
 280 
 281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 282 {
 283         struct net_device *dev = adapter->port[port_id];
 284 
 285         /* Skip changes from disabled ports. */
 286         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 287                 if (link_stat)
 288                         netif_carrier_on(dev);
 289                 else {
 290 #ifdef CONFIG_CHELSIO_T4_DCB
 291                         if (cxgb4_dcb_enabled(dev)) {
 292                                 cxgb4_dcb_reset(dev);
 293                                 dcb_tx_queue_prio_enable(dev, false);
 294                         }
 295 #endif /* CONFIG_CHELSIO_T4_DCB */
 296                         netif_carrier_off(dev);
 297                 }
 298 
 299                 link_report(dev);
 300         }
 301 }
 302 
 303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
 304 {
 305         static const char *mod_str[] = {
 306                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 307         };
 308 
 309         struct net_device *dev = adap->port[port_id];
 310         struct port_info *pi = netdev_priv(dev);
 311 
 312         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 313                 netdev_info(dev, "port module unplugged\n");
 314         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 315                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 316         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 317                 netdev_info(dev, "%s: unsupported port module inserted\n",
 318                             dev->name);
 319         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 320                 netdev_info(dev, "%s: unknown port module inserted\n",
 321                             dev->name);
 322         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 323                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 324         else
 325                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 326                             dev->name, pi->mod_type);
 327 
 328         /* If the interface is running, then we'll need any "sticky" Link
 329          * Parameters redone with a new Transceiver Module.
 330          */
 331         pi->link_cfg.redo_l1cfg = netif_running(dev);
 332 }
 333 
 334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 335 module_param(dbfifo_int_thresh, int, 0644);
 336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 337 
 338 /*
 339  * usecs to sleep while draining the dbfifo
 340  */
 341 static int dbfifo_drain_delay = 1000;
 342 module_param(dbfifo_drain_delay, int, 0644);
 343 MODULE_PARM_DESC(dbfifo_drain_delay,
 344                  "usecs to sleep while draining the dbfifo");
 345 
 346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 347 {
 348         struct adapter *adap = pi->adapter;
 349         u64 vec = 0;
 350         bool ucast = false;
 351         struct hash_mac_addr *entry;
 352 
 353         /* Calculate the hash vector for the updated list and program it */
 354         list_for_each_entry(entry, &adap->mac_hlist, list) {
 355                 ucast |= is_unicast_ether_addr(entry->addr);
 356                 vec |= (1ULL << hash_mac_addr(entry->addr));
 357         }
 358         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 359                                 vec, false);
 360 }
 361 
 362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 363 {
 364         struct port_info *pi = netdev_priv(netdev);
 365         struct adapter *adap = pi->adapter;
 366         int ret;
 367         u64 mhash = 0;
 368         u64 uhash = 0;
 369         /* idx stores the index of allocated filters,
 370          * its size should be modified based on the number of
 371          * MAC addresses that we allocate filters for
 372          */
 373 
 374         u16 idx[1] = {};
 375         bool free = false;
 376         bool ucast = is_unicast_ether_addr(mac_addr);
 377         const u8 *maclist[1] = {mac_addr};
 378         struct hash_mac_addr *new_entry;
 379 
 380         ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist,
 381                                    idx, ucast ? &uhash : &mhash, false);
 382         if (ret < 0)
 383                 goto out;
 384         /* if hash != 0, then add the addr to hash addr list
 385          * so on the end we will calculate the hash for the
 386          * list and program it
 387          */
 388         if (uhash || mhash) {
 389                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 390                 if (!new_entry)
 391                         return -ENOMEM;
 392                 ether_addr_copy(new_entry->addr, mac_addr);
 393                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 394                 ret = cxgb4_set_addr_hash(pi);
 395         }
 396 out:
 397         return ret < 0 ? ret : 0;
 398 }
 399 
 400 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 401 {
 402         struct port_info *pi = netdev_priv(netdev);
 403         struct adapter *adap = pi->adapter;
 404         int ret;
 405         const u8 *maclist[1] = {mac_addr};
 406         struct hash_mac_addr *entry, *tmp;
 407 
 408         /* If the MAC address to be removed is in the hash addr
 409          * list, delete it from the list and update hash vector
 410          */
 411         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 412                 if (ether_addr_equal(entry->addr, mac_addr)) {
 413                         list_del(&entry->list);
 414                         kfree(entry);
 415                         return cxgb4_set_addr_hash(pi);
 416                 }
 417         }
 418 
 419         ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false);
 420         return ret < 0 ? -EINVAL : 0;
 421 }
 422 
 423 /*
 424  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 425  * If @mtu is -1 it is left unchanged.
 426  */
 427 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 428 {
 429         struct port_info *pi = netdev_priv(dev);
 430         struct adapter *adapter = pi->adapter;
 431 
 432         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 433         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 434 
 435         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 436                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 437                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 438                              sleep_ok);
 439 }
 440 
 441 /**
 442  *      cxgb4_change_mac - Update match filter for a MAC address.
 443  *      @pi: the port_info
 444  *      @viid: the VI id
 445  *      @tcam_idx: TCAM index of existing filter for old value of MAC address,
 446  *                 or -1
 447  *      @addr: the new MAC address value
 448  *      @persist: whether a new MAC allocation should be persistent
 449  *      @add_smt: if true also add the address to the HW SMT
 450  *
 451  *      Modifies an MPS filter and sets it to the new MAC address if
 452  *      @tcam_idx >= 0, or adds the MAC address to a new filter if
 453  *      @tcam_idx < 0. In the latter case the address is added persistently
 454  *      if @persist is %true.
 455  *      Addresses are programmed to hash region, if tcam runs out of entries.
 456  *
 457  */
 458 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
 459                      int *tcam_idx, const u8 *addr, bool persist,
 460                      u8 *smt_idx)
 461 {
 462         struct adapter *adapter = pi->adapter;
 463         struct hash_mac_addr *entry, *new_entry;
 464         int ret;
 465 
 466         ret = t4_change_mac(adapter, adapter->mbox, viid,
 467                             *tcam_idx, addr, persist, smt_idx);
 468         /* We ran out of TCAM entries. try programming hash region. */
 469         if (ret == -ENOMEM) {
 470                 /* If the MAC address to be updated is in the hash addr
 471                  * list, update it from the list
 472                  */
 473                 list_for_each_entry(entry, &adapter->mac_hlist, list) {
 474                         if (entry->iface_mac) {
 475                                 ether_addr_copy(entry->addr, addr);
 476                                 goto set_hash;
 477                         }
 478                 }
 479                 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
 480                 if (!new_entry)
 481                         return -ENOMEM;
 482                 ether_addr_copy(new_entry->addr, addr);
 483                 new_entry->iface_mac = true;
 484                 list_add_tail(&new_entry->list, &adapter->mac_hlist);
 485 set_hash:
 486                 ret = cxgb4_set_addr_hash(pi);
 487         } else if (ret >= 0) {
 488                 *tcam_idx = ret;
 489                 ret = 0;
 490         }
 491 
 492         return ret;
 493 }
 494 
 495 /*
 496  *      link_start - enable a port
 497  *      @dev: the port to enable
 498  *
 499  *      Performs the MAC and PHY actions needed to enable a port.
 500  */
 501 static int link_start(struct net_device *dev)
 502 {
 503         int ret;
 504         struct port_info *pi = netdev_priv(dev);
 505         unsigned int mb = pi->adapter->pf;
 506 
 507         /*
 508          * We do not set address filters and promiscuity here, the stack does
 509          * that step explicitly.
 510          */
 511         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 512                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 513         if (ret == 0)
 514                 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
 515                                             dev->dev_addr, true, &pi->smt_idx);
 516         if (ret == 0)
 517                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 518                                     &pi->link_cfg);
 519         if (ret == 0) {
 520                 local_bh_disable();
 521                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
 522                                           true, CXGB4_DCB_ENABLED);
 523                 local_bh_enable();
 524         }
 525 
 526         return ret;
 527 }
 528 
 529 #ifdef CONFIG_CHELSIO_T4_DCB
 530 /* Handle a Data Center Bridging update message from the firmware. */
 531 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 532 {
 533         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 534         struct net_device *dev = adap->port[adap->chan_map[port]];
 535         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 536         int new_dcb_enabled;
 537 
 538         cxgb4_dcb_handle_fw_update(adap, pcmd);
 539         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 540 
 541         /* If the DCB has become enabled or disabled on the port then we're
 542          * going to need to set up/tear down DCB Priority parameters for the
 543          * TX Queues associated with the port.
 544          */
 545         if (new_dcb_enabled != old_dcb_enabled)
 546                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 547 }
 548 #endif /* CONFIG_CHELSIO_T4_DCB */
 549 
 550 /* Response queue handler for the FW event queue.
 551  */
 552 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 553                           const struct pkt_gl *gl)
 554 {
 555         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 556 
 557         rsp++;                                          /* skip RSS header */
 558 
 559         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 560          */
 561         if (unlikely(opcode == CPL_FW4_MSG &&
 562            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 563                 rsp++;
 564                 opcode = ((const struct rss_header *)rsp)->opcode;
 565                 rsp++;
 566                 if (opcode != CPL_SGE_EGR_UPDATE) {
 567                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 568                                 , opcode);
 569                         goto out;
 570                 }
 571         }
 572 
 573         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 574                 const struct cpl_sge_egr_update *p = (void *)rsp;
 575                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 576                 struct sge_txq *txq;
 577 
 578                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 579                 txq->restarts++;
 580                 if (txq->q_type == CXGB4_TXQ_ETH) {
 581                         struct sge_eth_txq *eq;
 582 
 583                         eq = container_of(txq, struct sge_eth_txq, q);
 584                         t4_sge_eth_txq_egress_update(q->adap, eq, -1);
 585                 } else {
 586                         struct sge_uld_txq *oq;
 587 
 588                         oq = container_of(txq, struct sge_uld_txq, q);
 589                         tasklet_schedule(&oq->qresume_tsk);
 590                 }
 591         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 592                 const struct cpl_fw6_msg *p = (void *)rsp;
 593 
 594 #ifdef CONFIG_CHELSIO_T4_DCB
 595                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 596                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 597                 unsigned int action =
 598                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 599 
 600                 if (cmd == FW_PORT_CMD &&
 601                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
 602                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 603                         int port = FW_PORT_CMD_PORTID_G(
 604                                         be32_to_cpu(pcmd->op_to_portid));
 605                         struct net_device *dev;
 606                         int dcbxdis, state_input;
 607 
 608                         dev = q->adap->port[q->adap->chan_map[port]];
 609                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
 610                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
 611                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
 612                                & FW_PORT_CMD_DCBXDIS32_F));
 613                         state_input = (dcbxdis
 614                                        ? CXGB4_DCB_INPUT_FW_DISABLED
 615                                        : CXGB4_DCB_INPUT_FW_ENABLED);
 616 
 617                         cxgb4_dcb_state_fsm(dev, state_input);
 618                 }
 619 
 620                 if (cmd == FW_PORT_CMD &&
 621                     action == FW_PORT_ACTION_L2_DCB_CFG)
 622                         dcb_rpl(q->adap, pcmd);
 623                 else
 624 #endif
 625                         if (p->type == 0)
 626                                 t4_handle_fw_rpl(q->adap, p->data);
 627         } else if (opcode == CPL_L2T_WRITE_RPL) {
 628                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 629 
 630                 do_l2t_write_rpl(q->adap, p);
 631         } else if (opcode == CPL_SMT_WRITE_RPL) {
 632                 const struct cpl_smt_write_rpl *p = (void *)rsp;
 633 
 634                 do_smt_write_rpl(q->adap, p);
 635         } else if (opcode == CPL_SET_TCB_RPL) {
 636                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 637 
 638                 filter_rpl(q->adap, p);
 639         } else if (opcode == CPL_ACT_OPEN_RPL) {
 640                 const struct cpl_act_open_rpl *p = (void *)rsp;
 641 
 642                 hash_filter_rpl(q->adap, p);
 643         } else if (opcode == CPL_ABORT_RPL_RSS) {
 644                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
 645 
 646                 hash_del_filter_rpl(q->adap, p);
 647         } else if (opcode == CPL_SRQ_TABLE_RPL) {
 648                 const struct cpl_srq_table_rpl *p = (void *)rsp;
 649 
 650                 do_srq_table_rpl(q->adap, p);
 651         } else
 652                 dev_err(q->adap->pdev_dev,
 653                         "unexpected CPL %#x on FW event queue\n", opcode);
 654 out:
 655         return 0;
 656 }
 657 
 658 static void disable_msi(struct adapter *adapter)
 659 {
 660         if (adapter->flags & CXGB4_USING_MSIX) {
 661                 pci_disable_msix(adapter->pdev);
 662                 adapter->flags &= ~CXGB4_USING_MSIX;
 663         } else if (adapter->flags & CXGB4_USING_MSI) {
 664                 pci_disable_msi(adapter->pdev);
 665                 adapter->flags &= ~CXGB4_USING_MSI;
 666         }
 667 }
 668 
 669 /*
 670  * Interrupt handler for non-data events used with MSI-X.
 671  */
 672 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 673 {
 674         struct adapter *adap = cookie;
 675         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 676 
 677         if (v & PFSW_F) {
 678                 adap->swintr = 1;
 679                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 680         }
 681         if (adap->flags & CXGB4_MASTER_PF)
 682                 t4_slow_intr_handler(adap);
 683         return IRQ_HANDLED;
 684 }
 685 
 686 /*
 687  * Name the MSI-X interrupts.
 688  */
 689 static void name_msix_vecs(struct adapter *adap)
 690 {
 691         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 692 
 693         /* non-data interrupts */
 694         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 695 
 696         /* FW events */
 697         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 698                  adap->port[0]->name);
 699 
 700         /* Ethernet queues */
 701         for_each_port(adap, j) {
 702                 struct net_device *d = adap->port[j];
 703                 const struct port_info *pi = netdev_priv(d);
 704 
 705                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 706                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 707                                  d->name, i);
 708         }
 709 }
 710 
 711 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
 712                        cpumask_var_t *aff_mask, int idx)
 713 {
 714         int rv;
 715 
 716         if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) {
 717                 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n");
 718                 return -ENOMEM;
 719         }
 720 
 721         cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)),
 722                         *aff_mask);
 723 
 724         rv = irq_set_affinity_hint(vec, *aff_mask);
 725         if (rv)
 726                 dev_warn(adap->pdev_dev,
 727                          "irq_set_affinity_hint %u failed %d\n",
 728                          vec, rv);
 729 
 730         return 0;
 731 }
 732 
 733 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask)
 734 {
 735         irq_set_affinity_hint(vec, NULL);
 736         free_cpumask_var(aff_mask);
 737 }
 738 
 739 static int request_msix_queue_irqs(struct adapter *adap)
 740 {
 741         struct sge *s = &adap->sge;
 742         struct msix_info *minfo;
 743         int err, ethqidx;
 744         int msi_index = 2;
 745 
 746         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 747                           adap->msix_info[1].desc, &s->fw_evtq);
 748         if (err)
 749                 return err;
 750 
 751         for_each_ethrxq(s, ethqidx) {
 752                 minfo = &adap->msix_info[msi_index];
 753                 err = request_irq(minfo->vec,
 754                                   t4_sge_intr_msix, 0,
 755                                   minfo->desc,
 756                                   &s->ethrxq[ethqidx].rspq);
 757                 if (err)
 758                         goto unwind;
 759 
 760                 cxgb4_set_msix_aff(adap, minfo->vec,
 761                                    &minfo->aff_mask, ethqidx);
 762                 msi_index++;
 763         }
 764         return 0;
 765 
 766 unwind:
 767         while (--ethqidx >= 0) {
 768                 msi_index--;
 769                 minfo = &adap->msix_info[msi_index];
 770                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 771                 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq);
 772         }
 773         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 774         return err;
 775 }
 776 
 777 static void free_msix_queue_irqs(struct adapter *adap)
 778 {
 779         struct sge *s = &adap->sge;
 780         struct msix_info *minfo;
 781         int i, msi_index = 2;
 782 
 783         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 784         for_each_ethrxq(s, i) {
 785                 minfo = &adap->msix_info[msi_index++];
 786                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 787                 free_irq(minfo->vec, &s->ethrxq[i].rspq);
 788         }
 789 }
 790 
 791 static int setup_ppod_edram(struct adapter *adap)
 792 {
 793         unsigned int param, val;
 794         int ret;
 795 
 796         /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check
 797          * if firmware supports ppod edram feature or not. If firmware
 798          * returns 1, then driver can enable this feature by sending
 799          * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to
 800          * enable ppod edram feature.
 801          */
 802         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
 803                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM));
 804 
 805         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 806         if (ret < 0) {
 807                 dev_warn(adap->pdev_dev,
 808                          "querying PPOD_EDRAM support failed: %d\n",
 809                          ret);
 810                 return -1;
 811         }
 812 
 813         if (val != 1)
 814                 return -1;
 815 
 816         ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 817         if (ret < 0) {
 818                 dev_err(adap->pdev_dev,
 819                         "setting PPOD_EDRAM failed: %d\n", ret);
 820                 return -1;
 821         }
 822         return 0;
 823 }
 824 
 825 /**
 826  *      cxgb4_write_rss - write the RSS table for a given port
 827  *      @pi: the port
 828  *      @queues: array of queue indices for RSS
 829  *
 830  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 831  *      packets to the Rx queues in @queues.
 832  *      Should never be called before setting up sge eth rx queues
 833  */
 834 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 835 {
 836         u16 *rss;
 837         int i, err;
 838         struct adapter *adapter = pi->adapter;
 839         const struct sge_eth_rxq *rxq;
 840 
 841         rxq = &adapter->sge.ethrxq[pi->first_qset];
 842         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
 843         if (!rss)
 844                 return -ENOMEM;
 845 
 846         /* map the queue indices to queue ids */
 847         for (i = 0; i < pi->rss_size; i++, queues++)
 848                 rss[i] = rxq[*queues].rspq.abs_id;
 849 
 850         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 851                                   pi->rss_size, rss, pi->rss_size);
 852         /* If Tunnel All Lookup isn't specified in the global RSS
 853          * Configuration, then we need to specify a default Ingress
 854          * Queue for any ingress packets which aren't hashed.  We'll
 855          * use our first ingress queue ...
 856          */
 857         if (!err)
 858                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 859                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 860                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 861                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 862                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 863                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 864                                        rss[0]);
 865         kfree(rss);
 866         return err;
 867 }
 868 
 869 /**
 870  *      setup_rss - configure RSS
 871  *      @adap: the adapter
 872  *
 873  *      Sets up RSS for each port.
 874  */
 875 static int setup_rss(struct adapter *adap)
 876 {
 877         int i, j, err;
 878 
 879         for_each_port(adap, i) {
 880                 const struct port_info *pi = adap2pinfo(adap, i);
 881 
 882                 /* Fill default values with equal distribution */
 883                 for (j = 0; j < pi->rss_size; j++)
 884                         pi->rss[j] = j % pi->nqsets;
 885 
 886                 err = cxgb4_write_rss(pi, pi->rss);
 887                 if (err)
 888                         return err;
 889         }
 890         return 0;
 891 }
 892 
 893 /*
 894  * Return the channel of the ingress queue with the given qid.
 895  */
 896 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 897 {
 898         qid -= p->ingr_start;
 899         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 900 }
 901 
 902 /*
 903  * Wait until all NAPI handlers are descheduled.
 904  */
 905 static void quiesce_rx(struct adapter *adap)
 906 {
 907         int i;
 908 
 909         for (i = 0; i < adap->sge.ingr_sz; i++) {
 910                 struct sge_rspq *q = adap->sge.ingr_map[i];
 911 
 912                 if (q && q->handler)
 913                         napi_disable(&q->napi);
 914         }
 915 }
 916 
 917 /* Disable interrupt and napi handler */
 918 static void disable_interrupts(struct adapter *adap)
 919 {
 920         if (adap->flags & CXGB4_FULL_INIT_DONE) {
 921                 t4_intr_disable(adap);
 922                 if (adap->flags & CXGB4_USING_MSIX) {
 923                         free_msix_queue_irqs(adap);
 924                         free_irq(adap->msix_info[0].vec, adap);
 925                 } else {
 926                         free_irq(adap->pdev->irq, adap);
 927                 }
 928                 quiesce_rx(adap);
 929         }
 930 }
 931 
 932 /*
 933  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 934  */
 935 static void enable_rx(struct adapter *adap)
 936 {
 937         int i;
 938 
 939         for (i = 0; i < adap->sge.ingr_sz; i++) {
 940                 struct sge_rspq *q = adap->sge.ingr_map[i];
 941 
 942                 if (!q)
 943                         continue;
 944                 if (q->handler)
 945                         napi_enable(&q->napi);
 946 
 947                 /* 0-increment GTS to start the timer and enable interrupts */
 948                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 949                              SEINTARM_V(q->intr_params) |
 950                              INGRESSQID_V(q->cntxt_id));
 951         }
 952 }
 953 
 954 
 955 static int setup_fw_sge_queues(struct adapter *adap)
 956 {
 957         struct sge *s = &adap->sge;
 958         int err = 0;
 959 
 960         bitmap_zero(s->starving_fl, s->egr_sz);
 961         bitmap_zero(s->txq_maperr, s->egr_sz);
 962 
 963         if (adap->flags & CXGB4_USING_MSIX)
 964                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 965         else {
 966                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 967                                        NULL, NULL, NULL, -1);
 968                 if (err)
 969                         return err;
 970                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
 971         }
 972 
 973         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 974                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
 975         return err;
 976 }
 977 
 978 /**
 979  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 980  *      @adap: the adapter
 981  *
 982  *      Determines how many sets of SGE queues to use and initializes them.
 983  *      We support multiple queue sets per port if we have MSI-X, otherwise
 984  *      just one queue set per port.
 985  */
 986 static int setup_sge_queues(struct adapter *adap)
 987 {
 988         int err, i, j;
 989         struct sge *s = &adap->sge;
 990         struct sge_uld_rxq_info *rxq_info = NULL;
 991         unsigned int cmplqid = 0;
 992 
 993         if (is_uld(adap))
 994                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
 995 
 996         for_each_port(adap, i) {
 997                 struct net_device *dev = adap->port[i];
 998                 struct port_info *pi = netdev_priv(dev);
 999                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1000                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1001 
1002                 for (j = 0; j < pi->nqsets; j++, q++) {
1003                         if (adap->msi_idx > 0)
1004                                 adap->msi_idx++;
1005                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1006                                                adap->msi_idx, &q->fl,
1007                                                t4_ethrx_handler,
1008                                                NULL,
1009                                                t4_get_tp_ch_map(adap,
1010                                                                 pi->tx_chan));
1011                         if (err)
1012                                 goto freeout;
1013                         q->rspq.idx = j;
1014                         memset(&q->stats, 0, sizeof(q->stats));
1015                 }
1016 
1017                 q = &s->ethrxq[pi->first_qset];
1018                 for (j = 0; j < pi->nqsets; j++, t++, q++) {
1019                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1020                                         netdev_get_tx_queue(dev, j),
1021                                         q->rspq.cntxt_id,
1022                                         !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
1023                         if (err)
1024                                 goto freeout;
1025                 }
1026         }
1027 
1028         for_each_port(adap, i) {
1029                 /* Note that cmplqid below is 0 if we don't
1030                  * have RDMA queues, and that's the right value.
1031                  */
1032                 if (rxq_info)
1033                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
1034 
1035                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1036                                             s->fw_evtq.cntxt_id, cmplqid);
1037                 if (err)
1038                         goto freeout;
1039         }
1040 
1041         if (!is_t4(adap->params.chip)) {
1042                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
1043                                            netdev_get_tx_queue(adap->port[0], 0)
1044                                            , s->fw_evtq.cntxt_id, false);
1045                 if (err)
1046                         goto freeout;
1047         }
1048 
1049         t4_write_reg(adap, is_t4(adap->params.chip) ?
1050                                 MPS_TRC_RSS_CONTROL_A :
1051                                 MPS_T5_TRC_RSS_CONTROL_A,
1052                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1053                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1054         return 0;
1055 freeout:
1056         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
1057         t4_free_sge_resources(adap);
1058         return err;
1059 }
1060 
1061 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1062                              struct net_device *sb_dev)
1063 {
1064         int txq;
1065 
1066 #ifdef CONFIG_CHELSIO_T4_DCB
1067         /* If a Data Center Bridging has been successfully negotiated on this
1068          * link then we'll use the skb's priority to map it to a TX Queue.
1069          * The skb's priority is determined via the VLAN Tag Priority Code
1070          * Point field.
1071          */
1072         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
1073                 u16 vlan_tci;
1074                 int err;
1075 
1076                 err = vlan_get_tag(skb, &vlan_tci);
1077                 if (unlikely(err)) {
1078                         if (net_ratelimit())
1079                                 netdev_warn(dev,
1080                                             "TX Packet without VLAN Tag on DCB Link\n");
1081                         txq = 0;
1082                 } else {
1083                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1084 #ifdef CONFIG_CHELSIO_T4_FCOE
1085                         if (skb->protocol == htons(ETH_P_FCOE))
1086                                 txq = skb->priority & 0x7;
1087 #endif /* CONFIG_CHELSIO_T4_FCOE */
1088                 }
1089                 return txq;
1090         }
1091 #endif /* CONFIG_CHELSIO_T4_DCB */
1092 
1093         if (select_queue) {
1094                 txq = (skb_rx_queue_recorded(skb)
1095                         ? skb_get_rx_queue(skb)
1096                         : smp_processor_id());
1097 
1098                 while (unlikely(txq >= dev->real_num_tx_queues))
1099                         txq -= dev->real_num_tx_queues;
1100 
1101                 return txq;
1102         }
1103 
1104         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1105 }
1106 
1107 static int closest_timer(const struct sge *s, int time)
1108 {
1109         int i, delta, match = 0, min_delta = INT_MAX;
1110 
1111         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1112                 delta = time - s->timer_val[i];
1113                 if (delta < 0)
1114                         delta = -delta;
1115                 if (delta < min_delta) {
1116                         min_delta = delta;
1117                         match = i;
1118                 }
1119         }
1120         return match;
1121 }
1122 
1123 static int closest_thres(const struct sge *s, int thres)
1124 {
1125         int i, delta, match = 0, min_delta = INT_MAX;
1126 
1127         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1128                 delta = thres - s->counter_val[i];
1129                 if (delta < 0)
1130                         delta = -delta;
1131                 if (delta < min_delta) {
1132                         min_delta = delta;
1133                         match = i;
1134                 }
1135         }
1136         return match;
1137 }
1138 
1139 /**
1140  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1141  *      @q: the Rx queue
1142  *      @us: the hold-off time in us, or 0 to disable timer
1143  *      @cnt: the hold-off packet count, or 0 to disable counter
1144  *
1145  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1146  *      one of the two needs to be enabled for the queue to generate interrupts.
1147  */
1148 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1149                                unsigned int us, unsigned int cnt)
1150 {
1151         struct adapter *adap = q->adap;
1152 
1153         if ((us | cnt) == 0)
1154                 cnt = 1;
1155 
1156         if (cnt) {
1157                 int err;
1158                 u32 v, new_idx;
1159 
1160                 new_idx = closest_thres(&adap->sge, cnt);
1161                 if (q->desc && q->pktcnt_idx != new_idx) {
1162                         /* the queue has already been created, update it */
1163                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1164                             FW_PARAMS_PARAM_X_V(
1165                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1166                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1167                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1168                                             &v, &new_idx);
1169                         if (err)
1170                                 return err;
1171                 }
1172                 q->pktcnt_idx = new_idx;
1173         }
1174 
1175         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1176         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1177         return 0;
1178 }
1179 
1180 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1181 {
1182         const struct port_info *pi = netdev_priv(dev);
1183         netdev_features_t changed = dev->features ^ features;
1184         int err;
1185 
1186         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1187                 return 0;
1188 
1189         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1190                             -1, -1, -1,
1191                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1192         if (unlikely(err))
1193                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1194         return err;
1195 }
1196 
1197 static int setup_debugfs(struct adapter *adap)
1198 {
1199         if (IS_ERR_OR_NULL(adap->debugfs_root))
1200                 return -1;
1201 
1202 #ifdef CONFIG_DEBUG_FS
1203         t4_setup_debugfs(adap);
1204 #endif
1205         return 0;
1206 }
1207 
1208 /*
1209  * upper-layer driver support
1210  */
1211 
1212 /*
1213  * Allocate an active-open TID and set it to the supplied value.
1214  */
1215 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1216 {
1217         int atid = -1;
1218 
1219         spin_lock_bh(&t->atid_lock);
1220         if (t->afree) {
1221                 union aopen_entry *p = t->afree;
1222 
1223                 atid = (p - t->atid_tab) + t->atid_base;
1224                 t->afree = p->next;
1225                 p->data = data;
1226                 t->atids_in_use++;
1227         }
1228         spin_unlock_bh(&t->atid_lock);
1229         return atid;
1230 }
1231 EXPORT_SYMBOL(cxgb4_alloc_atid);
1232 
1233 /*
1234  * Release an active-open TID.
1235  */
1236 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1237 {
1238         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1239 
1240         spin_lock_bh(&t->atid_lock);
1241         p->next = t->afree;
1242         t->afree = p;
1243         t->atids_in_use--;
1244         spin_unlock_bh(&t->atid_lock);
1245 }
1246 EXPORT_SYMBOL(cxgb4_free_atid);
1247 
1248 /*
1249  * Allocate a server TID and set it to the supplied value.
1250  */
1251 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1252 {
1253         int stid;
1254 
1255         spin_lock_bh(&t->stid_lock);
1256         if (family == PF_INET) {
1257                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1258                 if (stid < t->nstids)
1259                         __set_bit(stid, t->stid_bmap);
1260                 else
1261                         stid = -1;
1262         } else {
1263                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1264                 if (stid < 0)
1265                         stid = -1;
1266         }
1267         if (stid >= 0) {
1268                 t->stid_tab[stid].data = data;
1269                 stid += t->stid_base;
1270                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1271                  * This is equivalent to 4 TIDs. With CLIP enabled it
1272                  * needs 2 TIDs.
1273                  */
1274                 if (family == PF_INET6) {
1275                         t->stids_in_use += 2;
1276                         t->v6_stids_in_use += 2;
1277                 } else {
1278                         t->stids_in_use++;
1279                 }
1280         }
1281         spin_unlock_bh(&t->stid_lock);
1282         return stid;
1283 }
1284 EXPORT_SYMBOL(cxgb4_alloc_stid);
1285 
1286 /* Allocate a server filter TID and set it to the supplied value.
1287  */
1288 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1289 {
1290         int stid;
1291 
1292         spin_lock_bh(&t->stid_lock);
1293         if (family == PF_INET) {
1294                 stid = find_next_zero_bit(t->stid_bmap,
1295                                 t->nstids + t->nsftids, t->nstids);
1296                 if (stid < (t->nstids + t->nsftids))
1297                         __set_bit(stid, t->stid_bmap);
1298                 else
1299                         stid = -1;
1300         } else {
1301                 stid = -1;
1302         }
1303         if (stid >= 0) {
1304                 t->stid_tab[stid].data = data;
1305                 stid -= t->nstids;
1306                 stid += t->sftid_base;
1307                 t->sftids_in_use++;
1308         }
1309         spin_unlock_bh(&t->stid_lock);
1310         return stid;
1311 }
1312 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1313 
1314 /* Release a server TID.
1315  */
1316 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1317 {
1318         /* Is it a server filter TID? */
1319         if (t->nsftids && (stid >= t->sftid_base)) {
1320                 stid -= t->sftid_base;
1321                 stid += t->nstids;
1322         } else {
1323                 stid -= t->stid_base;
1324         }
1325 
1326         spin_lock_bh(&t->stid_lock);
1327         if (family == PF_INET)
1328                 __clear_bit(stid, t->stid_bmap);
1329         else
1330                 bitmap_release_region(t->stid_bmap, stid, 1);
1331         t->stid_tab[stid].data = NULL;
1332         if (stid < t->nstids) {
1333                 if (family == PF_INET6) {
1334                         t->stids_in_use -= 2;
1335                         t->v6_stids_in_use -= 2;
1336                 } else {
1337                         t->stids_in_use--;
1338                 }
1339         } else {
1340                 t->sftids_in_use--;
1341         }
1342 
1343         spin_unlock_bh(&t->stid_lock);
1344 }
1345 EXPORT_SYMBOL(cxgb4_free_stid);
1346 
1347 /*
1348  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1349  */
1350 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1351                            unsigned int tid)
1352 {
1353         struct cpl_tid_release *req;
1354 
1355         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1356         req = __skb_put(skb, sizeof(*req));
1357         INIT_TP_WR(req, tid);
1358         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1359 }
1360 
1361 /*
1362  * Queue a TID release request and if necessary schedule a work queue to
1363  * process it.
1364  */
1365 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1366                                     unsigned int tid)
1367 {
1368         void **p = &t->tid_tab[tid];
1369         struct adapter *adap = container_of(t, struct adapter, tids);
1370 
1371         spin_lock_bh(&adap->tid_release_lock);
1372         *p = adap->tid_release_head;
1373         /* Low 2 bits encode the Tx channel number */
1374         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1375         if (!adap->tid_release_task_busy) {
1376                 adap->tid_release_task_busy = true;
1377                 queue_work(adap->workq, &adap->tid_release_task);
1378         }
1379         spin_unlock_bh(&adap->tid_release_lock);
1380 }
1381 
1382 /*
1383  * Process the list of pending TID release requests.
1384  */
1385 static void process_tid_release_list(struct work_struct *work)
1386 {
1387         struct sk_buff *skb;
1388         struct adapter *adap;
1389 
1390         adap = container_of(work, struct adapter, tid_release_task);
1391 
1392         spin_lock_bh(&adap->tid_release_lock);
1393         while (adap->tid_release_head) {
1394                 void **p = adap->tid_release_head;
1395                 unsigned int chan = (uintptr_t)p & 3;
1396                 p = (void *)p - chan;
1397 
1398                 adap->tid_release_head = *p;
1399                 *p = NULL;
1400                 spin_unlock_bh(&adap->tid_release_lock);
1401 
1402                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1403                                          GFP_KERNEL)))
1404                         schedule_timeout_uninterruptible(1);
1405 
1406                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1407                 t4_ofld_send(adap, skb);
1408                 spin_lock_bh(&adap->tid_release_lock);
1409         }
1410         adap->tid_release_task_busy = false;
1411         spin_unlock_bh(&adap->tid_release_lock);
1412 }
1413 
1414 /*
1415  * Release a TID and inform HW.  If we are unable to allocate the release
1416  * message we defer to a work queue.
1417  */
1418 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1419                       unsigned short family)
1420 {
1421         struct sk_buff *skb;
1422         struct adapter *adap = container_of(t, struct adapter, tids);
1423 
1424         WARN_ON(tid >= t->ntids);
1425 
1426         if (t->tid_tab[tid]) {
1427                 t->tid_tab[tid] = NULL;
1428                 atomic_dec(&t->conns_in_use);
1429                 if (t->hash_base && (tid >= t->hash_base)) {
1430                         if (family == AF_INET6)
1431                                 atomic_sub(2, &t->hash_tids_in_use);
1432                         else
1433                                 atomic_dec(&t->hash_tids_in_use);
1434                 } else {
1435                         if (family == AF_INET6)
1436                                 atomic_sub(2, &t->tids_in_use);
1437                         else
1438                                 atomic_dec(&t->tids_in_use);
1439                 }
1440         }
1441 
1442         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1443         if (likely(skb)) {
1444                 mk_tid_release(skb, chan, tid);
1445                 t4_ofld_send(adap, skb);
1446         } else
1447                 cxgb4_queue_tid_release(t, chan, tid);
1448 }
1449 EXPORT_SYMBOL(cxgb4_remove_tid);
1450 
1451 /*
1452  * Allocate and initialize the TID tables.  Returns 0 on success.
1453  */
1454 static int tid_init(struct tid_info *t)
1455 {
1456         struct adapter *adap = container_of(t, struct adapter, tids);
1457         unsigned int max_ftids = t->nftids + t->nsftids;
1458         unsigned int natids = t->natids;
1459         unsigned int stid_bmap_size;
1460         unsigned int ftid_bmap_size;
1461         size_t size;
1462 
1463         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1464         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1465         size = t->ntids * sizeof(*t->tid_tab) +
1466                natids * sizeof(*t->atid_tab) +
1467                t->nstids * sizeof(*t->stid_tab) +
1468                t->nsftids * sizeof(*t->stid_tab) +
1469                stid_bmap_size * sizeof(long) +
1470                max_ftids * sizeof(*t->ftid_tab) +
1471                ftid_bmap_size * sizeof(long);
1472 
1473         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1474         if (!t->tid_tab)
1475                 return -ENOMEM;
1476 
1477         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1478         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1479         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1480         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1481         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1482         spin_lock_init(&t->stid_lock);
1483         spin_lock_init(&t->atid_lock);
1484         spin_lock_init(&t->ftid_lock);
1485 
1486         t->stids_in_use = 0;
1487         t->v6_stids_in_use = 0;
1488         t->sftids_in_use = 0;
1489         t->afree = NULL;
1490         t->atids_in_use = 0;
1491         atomic_set(&t->tids_in_use, 0);
1492         atomic_set(&t->conns_in_use, 0);
1493         atomic_set(&t->hash_tids_in_use, 0);
1494 
1495         /* Setup the free list for atid_tab and clear the stid bitmap. */
1496         if (natids) {
1497                 while (--natids)
1498                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1499                 t->afree = t->atid_tab;
1500         }
1501 
1502         if (is_offload(adap)) {
1503                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1504                 /* Reserve stid 0 for T4/T5 adapters */
1505                 if (!t->stid_base &&
1506                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1507                         __set_bit(0, t->stid_bmap);
1508         }
1509 
1510         bitmap_zero(t->ftid_bmap, t->nftids);
1511         return 0;
1512 }
1513 
1514 /**
1515  *      cxgb4_create_server - create an IP server
1516  *      @dev: the device
1517  *      @stid: the server TID
1518  *      @sip: local IP address to bind server to
1519  *      @sport: the server's TCP port
1520  *      @queue: queue to direct messages from this server to
1521  *
1522  *      Create an IP server for the given port and address.
1523  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1524  */
1525 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1526                         __be32 sip, __be16 sport, __be16 vlan,
1527                         unsigned int queue)
1528 {
1529         unsigned int chan;
1530         struct sk_buff *skb;
1531         struct adapter *adap;
1532         struct cpl_pass_open_req *req;
1533         int ret;
1534 
1535         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1536         if (!skb)
1537                 return -ENOMEM;
1538 
1539         adap = netdev2adap(dev);
1540         req = __skb_put(skb, sizeof(*req));
1541         INIT_TP_WR(req, 0);
1542         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1543         req->local_port = sport;
1544         req->peer_port = htons(0);
1545         req->local_ip = sip;
1546         req->peer_ip = htonl(0);
1547         chan = rxq_to_chan(&adap->sge, queue);
1548         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1549         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1550                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1551         ret = t4_mgmt_tx(adap, skb);
1552         return net_xmit_eval(ret);
1553 }
1554 EXPORT_SYMBOL(cxgb4_create_server);
1555 
1556 /*      cxgb4_create_server6 - create an IPv6 server
1557  *      @dev: the device
1558  *      @stid: the server TID
1559  *      @sip: local IPv6 address to bind server to
1560  *      @sport: the server's TCP port
1561  *      @queue: queue to direct messages from this server to
1562  *
1563  *      Create an IPv6 server for the given port and address.
1564  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1565  */
1566 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1567                          const struct in6_addr *sip, __be16 sport,
1568                          unsigned int queue)
1569 {
1570         unsigned int chan;
1571         struct sk_buff *skb;
1572         struct adapter *adap;
1573         struct cpl_pass_open_req6 *req;
1574         int ret;
1575 
1576         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1577         if (!skb)
1578                 return -ENOMEM;
1579 
1580         adap = netdev2adap(dev);
1581         req = __skb_put(skb, sizeof(*req));
1582         INIT_TP_WR(req, 0);
1583         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1584         req->local_port = sport;
1585         req->peer_port = htons(0);
1586         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1587         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1588         req->peer_ip_hi = cpu_to_be64(0);
1589         req->peer_ip_lo = cpu_to_be64(0);
1590         chan = rxq_to_chan(&adap->sge, queue);
1591         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1592         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1593                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1594         ret = t4_mgmt_tx(adap, skb);
1595         return net_xmit_eval(ret);
1596 }
1597 EXPORT_SYMBOL(cxgb4_create_server6);
1598 
1599 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1600                         unsigned int queue, bool ipv6)
1601 {
1602         struct sk_buff *skb;
1603         struct adapter *adap;
1604         struct cpl_close_listsvr_req *req;
1605         int ret;
1606 
1607         adap = netdev2adap(dev);
1608 
1609         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1610         if (!skb)
1611                 return -ENOMEM;
1612 
1613         req = __skb_put(skb, sizeof(*req));
1614         INIT_TP_WR(req, 0);
1615         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1616         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1617                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1618         ret = t4_mgmt_tx(adap, skb);
1619         return net_xmit_eval(ret);
1620 }
1621 EXPORT_SYMBOL(cxgb4_remove_server);
1622 
1623 /**
1624  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1625  *      @mtus: the HW MTU table
1626  *      @mtu: the target MTU
1627  *      @idx: index of selected entry in the MTU table
1628  *
1629  *      Returns the index and the value in the HW MTU table that is closest to
1630  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1631  *      table, in which case that smallest available value is selected.
1632  */
1633 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1634                             unsigned int *idx)
1635 {
1636         unsigned int i = 0;
1637 
1638         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1639                 ++i;
1640         if (idx)
1641                 *idx = i;
1642         return mtus[i];
1643 }
1644 EXPORT_SYMBOL(cxgb4_best_mtu);
1645 
1646 /**
1647  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1648  *     @mtus: the HW MTU table
1649  *     @header_size: Header Size
1650  *     @data_size_max: maximum Data Segment Size
1651  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1652  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1653  *
1654  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1655  *     MTU Table based solely on a Maximum MTU parameter, we break that
1656  *     parameter up into a Header Size and Maximum Data Segment Size, and
1657  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1658  *     the Hardware MTU Table which will result in a Data Segment Size with
1659  *     the requested alignment _and_ that MTU isn't "too far" from the
1660  *     closest MTU, then we'll return that rather than the closest MTU.
1661  */
1662 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1663                                     unsigned short header_size,
1664                                     unsigned short data_size_max,
1665                                     unsigned short data_size_align,
1666                                     unsigned int *mtu_idxp)
1667 {
1668         unsigned short max_mtu = header_size + data_size_max;
1669         unsigned short data_size_align_mask = data_size_align - 1;
1670         int mtu_idx, aligned_mtu_idx;
1671 
1672         /* Scan the MTU Table till we find an MTU which is larger than our
1673          * Maximum MTU or we reach the end of the table.  Along the way,
1674          * record the last MTU found, if any, which will result in a Data
1675          * Segment Length matching the requested alignment.
1676          */
1677         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1678                 unsigned short data_size = mtus[mtu_idx] - header_size;
1679 
1680                 /* If this MTU minus the Header Size would result in a
1681                  * Data Segment Size of the desired alignment, remember it.
1682                  */
1683                 if ((data_size & data_size_align_mask) == 0)
1684                         aligned_mtu_idx = mtu_idx;
1685 
1686                 /* If we're not at the end of the Hardware MTU Table and the
1687                  * next element is larger than our Maximum MTU, drop out of
1688                  * the loop.
1689                  */
1690                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1691                         break;
1692         }
1693 
1694         /* If we fell out of the loop because we ran to the end of the table,
1695          * then we just have to use the last [largest] entry.
1696          */
1697         if (mtu_idx == NMTUS)
1698                 mtu_idx--;
1699 
1700         /* If we found an MTU which resulted in the requested Data Segment
1701          * Length alignment and that's "not far" from the largest MTU which is
1702          * less than or equal to the maximum MTU, then use that.
1703          */
1704         if (aligned_mtu_idx >= 0 &&
1705             mtu_idx - aligned_mtu_idx <= 1)
1706                 mtu_idx = aligned_mtu_idx;
1707 
1708         /* If the caller has passed in an MTU Index pointer, pass the
1709          * MTU Index back.  Return the MTU value.
1710          */
1711         if (mtu_idxp)
1712                 *mtu_idxp = mtu_idx;
1713         return mtus[mtu_idx];
1714 }
1715 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1716 
1717 /**
1718  *      cxgb4_port_chan - get the HW channel of a port
1719  *      @dev: the net device for the port
1720  *
1721  *      Return the HW Tx channel of the given port.
1722  */
1723 unsigned int cxgb4_port_chan(const struct net_device *dev)
1724 {
1725         return netdev2pinfo(dev)->tx_chan;
1726 }
1727 EXPORT_SYMBOL(cxgb4_port_chan);
1728 
1729 /**
1730  *      cxgb4_port_e2cchan - get the HW c-channel of a port
1731  *      @dev: the net device for the port
1732  *
1733  *      Return the HW RX c-channel of the given port.
1734  */
1735 unsigned int cxgb4_port_e2cchan(const struct net_device *dev)
1736 {
1737         return netdev2pinfo(dev)->rx_cchan;
1738 }
1739 EXPORT_SYMBOL(cxgb4_port_e2cchan);
1740 
1741 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1742 {
1743         struct adapter *adap = netdev2adap(dev);
1744         u32 v1, v2, lp_count, hp_count;
1745 
1746         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1747         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1748         if (is_t4(adap->params.chip)) {
1749                 lp_count = LP_COUNT_G(v1);
1750                 hp_count = HP_COUNT_G(v1);
1751         } else {
1752                 lp_count = LP_COUNT_T5_G(v1);
1753                 hp_count = HP_COUNT_T5_G(v2);
1754         }
1755         return lpfifo ? lp_count : hp_count;
1756 }
1757 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1758 
1759 /**
1760  *      cxgb4_port_viid - get the VI id of a port
1761  *      @dev: the net device for the port
1762  *
1763  *      Return the VI id of the given port.
1764  */
1765 unsigned int cxgb4_port_viid(const struct net_device *dev)
1766 {
1767         return netdev2pinfo(dev)->viid;
1768 }
1769 EXPORT_SYMBOL(cxgb4_port_viid);
1770 
1771 /**
1772  *      cxgb4_port_idx - get the index of a port
1773  *      @dev: the net device for the port
1774  *
1775  *      Return the index of the given port.
1776  */
1777 unsigned int cxgb4_port_idx(const struct net_device *dev)
1778 {
1779         return netdev2pinfo(dev)->port_id;
1780 }
1781 EXPORT_SYMBOL(cxgb4_port_idx);
1782 
1783 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1784                          struct tp_tcp_stats *v6)
1785 {
1786         struct adapter *adap = pci_get_drvdata(pdev);
1787 
1788         spin_lock(&adap->stats_lock);
1789         t4_tp_get_tcp_stats(adap, v4, v6, false);
1790         spin_unlock(&adap->stats_lock);
1791 }
1792 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1793 
1794 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1795                       const unsigned int *pgsz_order)
1796 {
1797         struct adapter *adap = netdev2adap(dev);
1798 
1799         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1800         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1801                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1802                      HPZ3_V(pgsz_order[3]));
1803 }
1804 EXPORT_SYMBOL(cxgb4_iscsi_init);
1805 
1806 int cxgb4_flush_eq_cache(struct net_device *dev)
1807 {
1808         struct adapter *adap = netdev2adap(dev);
1809 
1810         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1811 }
1812 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1813 
1814 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1815 {
1816         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1817         __be64 indices;
1818         int ret;
1819 
1820         spin_lock(&adap->win0_lock);
1821         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1822                            sizeof(indices), (__be32 *)&indices,
1823                            T4_MEMORY_READ);
1824         spin_unlock(&adap->win0_lock);
1825         if (!ret) {
1826                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1827                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1828         }
1829         return ret;
1830 }
1831 
1832 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1833                         u16 size)
1834 {
1835         struct adapter *adap = netdev2adap(dev);
1836         u16 hw_pidx, hw_cidx;
1837         int ret;
1838 
1839         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1840         if (ret)
1841                 goto out;
1842 
1843         if (pidx != hw_pidx) {
1844                 u16 delta;
1845                 u32 val;
1846 
1847                 if (pidx >= hw_pidx)
1848                         delta = pidx - hw_pidx;
1849                 else
1850                         delta = size - hw_pidx + pidx;
1851 
1852                 if (is_t4(adap->params.chip))
1853                         val = PIDX_V(delta);
1854                 else
1855                         val = PIDX_T5_V(delta);
1856                 wmb();
1857                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1858                              QID_V(qid) | val);
1859         }
1860 out:
1861         return ret;
1862 }
1863 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1864 
1865 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1866 {
1867         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1868         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1869         u32 offset, memtype, memaddr;
1870         struct adapter *adap;
1871         u32 hma_size = 0;
1872         int ret;
1873 
1874         adap = netdev2adap(dev);
1875 
1876         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1877 
1878         /* Figure out where the offset lands in the Memory Type/Address scheme.
1879          * This code assumes that the memory is laid out starting at offset 0
1880          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1881          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1882          * MC0, and some have both MC0 and MC1.
1883          */
1884         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1885         edc0_size = EDRAM0_SIZE_G(size) << 20;
1886         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1887         edc1_size = EDRAM1_SIZE_G(size) << 20;
1888         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1889         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1890 
1891         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1892                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1893                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1894         }
1895         edc0_end = edc0_size;
1896         edc1_end = edc0_end + edc1_size;
1897         mc0_end = edc1_end + mc0_size;
1898 
1899         if (offset < edc0_end) {
1900                 memtype = MEM_EDC0;
1901                 memaddr = offset;
1902         } else if (offset < edc1_end) {
1903                 memtype = MEM_EDC1;
1904                 memaddr = offset - edc0_end;
1905         } else {
1906                 if (hma_size && (offset < (edc1_end + hma_size))) {
1907                         memtype = MEM_HMA;
1908                         memaddr = offset - edc1_end;
1909                 } else if (offset < mc0_end) {
1910                         memtype = MEM_MC0;
1911                         memaddr = offset - edc1_end;
1912                 } else if (is_t5(adap->params.chip)) {
1913                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1914                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1915                         mc1_end = mc0_end + mc1_size;
1916                         if (offset < mc1_end) {
1917                                 memtype = MEM_MC1;
1918                                 memaddr = offset - mc0_end;
1919                         } else {
1920                                 /* offset beyond the end of any memory */
1921                                 goto err;
1922                         }
1923                 } else {
1924                         /* T4/T6 only has a single memory channel */
1925                         goto err;
1926                 }
1927         }
1928 
1929         spin_lock(&adap->win0_lock);
1930         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1931         spin_unlock(&adap->win0_lock);
1932         return ret;
1933 
1934 err:
1935         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1936                 stag, offset);
1937         return -EINVAL;
1938 }
1939 EXPORT_SYMBOL(cxgb4_read_tpte);
1940 
1941 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1942 {
1943         u32 hi, lo;
1944         struct adapter *adap;
1945 
1946         adap = netdev2adap(dev);
1947         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1948         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1949 
1950         return ((u64)hi << 32) | (u64)lo;
1951 }
1952 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1953 
1954 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1955                          unsigned int qid,
1956                          enum cxgb4_bar2_qtype qtype,
1957                          int user,
1958                          u64 *pbar2_qoffset,
1959                          unsigned int *pbar2_qid)
1960 {
1961         return t4_bar2_sge_qregs(netdev2adap(dev),
1962                                  qid,
1963                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1964                                   ? T4_BAR2_QTYPE_EGRESS
1965                                   : T4_BAR2_QTYPE_INGRESS),
1966                                  user,
1967                                  pbar2_qoffset,
1968                                  pbar2_qid);
1969 }
1970 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1971 
1972 static struct pci_driver cxgb4_driver;
1973 
1974 static void check_neigh_update(struct neighbour *neigh)
1975 {
1976         const struct device *parent;
1977         const struct net_device *netdev = neigh->dev;
1978 
1979         if (is_vlan_dev(netdev))
1980                 netdev = vlan_dev_real_dev(netdev);
1981         parent = netdev->dev.parent;
1982         if (parent && parent->driver == &cxgb4_driver.driver)
1983                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1984 }
1985 
1986 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1987                        void *data)
1988 {
1989         switch (event) {
1990         case NETEVENT_NEIGH_UPDATE:
1991                 check_neigh_update(data);
1992                 break;
1993         case NETEVENT_REDIRECT:
1994         default:
1995                 break;
1996         }
1997         return 0;
1998 }
1999 
2000 static bool netevent_registered;
2001 static struct notifier_block cxgb4_netevent_nb = {
2002         .notifier_call = netevent_cb
2003 };
2004 
2005 static void drain_db_fifo(struct adapter *adap, int usecs)
2006 {
2007         u32 v1, v2, lp_count, hp_count;
2008 
2009         do {
2010                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2011                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2012                 if (is_t4(adap->params.chip)) {
2013                         lp_count = LP_COUNT_G(v1);
2014                         hp_count = HP_COUNT_G(v1);
2015                 } else {
2016                         lp_count = LP_COUNT_T5_G(v1);
2017                         hp_count = HP_COUNT_T5_G(v2);
2018                 }
2019 
2020                 if (lp_count == 0 && hp_count == 0)
2021                         break;
2022                 set_current_state(TASK_UNINTERRUPTIBLE);
2023                 schedule_timeout(usecs_to_jiffies(usecs));
2024         } while (1);
2025 }
2026 
2027 static void disable_txq_db(struct sge_txq *q)
2028 {
2029         unsigned long flags;
2030 
2031         spin_lock_irqsave(&q->db_lock, flags);
2032         q->db_disabled = 1;
2033         spin_unlock_irqrestore(&q->db_lock, flags);
2034 }
2035 
2036 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2037 {
2038         spin_lock_irq(&q->db_lock);
2039         if (q->db_pidx_inc) {
2040                 /* Make sure that all writes to the TX descriptors
2041                  * are committed before we tell HW about them.
2042                  */
2043                 wmb();
2044                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2045                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2046                 q->db_pidx_inc = 0;
2047         }
2048         q->db_disabled = 0;
2049         spin_unlock_irq(&q->db_lock);
2050 }
2051 
2052 static void disable_dbs(struct adapter *adap)
2053 {
2054         int i;
2055 
2056         for_each_ethrxq(&adap->sge, i)
2057                 disable_txq_db(&adap->sge.ethtxq[i].q);
2058         if (is_offload(adap)) {
2059                 struct sge_uld_txq_info *txq_info =
2060                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2061 
2062                 if (txq_info) {
2063                         for_each_ofldtxq(&adap->sge, i) {
2064                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2065 
2066                                 disable_txq_db(&txq->q);
2067                         }
2068                 }
2069         }
2070         for_each_port(adap, i)
2071                 disable_txq_db(&adap->sge.ctrlq[i].q);
2072 }
2073 
2074 static void enable_dbs(struct adapter *adap)
2075 {
2076         int i;
2077 
2078         for_each_ethrxq(&adap->sge, i)
2079                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2080         if (is_offload(adap)) {
2081                 struct sge_uld_txq_info *txq_info =
2082                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2083 
2084                 if (txq_info) {
2085                         for_each_ofldtxq(&adap->sge, i) {
2086                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2087 
2088                                 enable_txq_db(adap, &txq->q);
2089                         }
2090                 }
2091         }
2092         for_each_port(adap, i)
2093                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2094 }
2095 
2096 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2097 {
2098         enum cxgb4_uld type = CXGB4_ULD_RDMA;
2099 
2100         if (adap->uld && adap->uld[type].handle)
2101                 adap->uld[type].control(adap->uld[type].handle, cmd);
2102 }
2103 
2104 static void process_db_full(struct work_struct *work)
2105 {
2106         struct adapter *adap;
2107 
2108         adap = container_of(work, struct adapter, db_full_task);
2109 
2110         drain_db_fifo(adap, dbfifo_drain_delay);
2111         enable_dbs(adap);
2112         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2113         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2114                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2115                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2116                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2117         else
2118                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2119                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2120 }
2121 
2122 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2123 {
2124         u16 hw_pidx, hw_cidx;
2125         int ret;
2126 
2127         spin_lock_irq(&q->db_lock);
2128         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2129         if (ret)
2130                 goto out;
2131         if (q->db_pidx != hw_pidx) {
2132                 u16 delta;
2133                 u32 val;
2134 
2135                 if (q->db_pidx >= hw_pidx)
2136                         delta = q->db_pidx - hw_pidx;
2137                 else
2138                         delta = q->size - hw_pidx + q->db_pidx;
2139 
2140                 if (is_t4(adap->params.chip))
2141                         val = PIDX_V(delta);
2142                 else
2143                         val = PIDX_T5_V(delta);
2144                 wmb();
2145                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2146                              QID_V(q->cntxt_id) | val);
2147         }
2148 out:
2149         q->db_disabled = 0;
2150         q->db_pidx_inc = 0;
2151         spin_unlock_irq(&q->db_lock);
2152         if (ret)
2153                 CH_WARN(adap, "DB drop recovery failed.\n");
2154 }
2155 
2156 static void recover_all_queues(struct adapter *adap)
2157 {
2158         int i;
2159 
2160         for_each_ethrxq(&adap->sge, i)
2161                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2162         if (is_offload(adap)) {
2163                 struct sge_uld_txq_info *txq_info =
2164                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2165                 if (txq_info) {
2166                         for_each_ofldtxq(&adap->sge, i) {
2167                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2168 
2169                                 sync_txq_pidx(adap, &txq->q);
2170                         }
2171                 }
2172         }
2173         for_each_port(adap, i)
2174                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2175 }
2176 
2177 static void process_db_drop(struct work_struct *work)
2178 {
2179         struct adapter *adap;
2180 
2181         adap = container_of(work, struct adapter, db_drop_task);
2182 
2183         if (is_t4(adap->params.chip)) {
2184                 drain_db_fifo(adap, dbfifo_drain_delay);
2185                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2186                 drain_db_fifo(adap, dbfifo_drain_delay);
2187                 recover_all_queues(adap);
2188                 drain_db_fifo(adap, dbfifo_drain_delay);
2189                 enable_dbs(adap);
2190                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2191         } else if (is_t5(adap->params.chip)) {
2192                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2193                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2194                 u16 pidx_inc = dropped_db & 0x1fff;
2195                 u64 bar2_qoffset;
2196                 unsigned int bar2_qid;
2197                 int ret;
2198 
2199                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2200                                         0, &bar2_qoffset, &bar2_qid);
2201                 if (ret)
2202                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2203                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2204                 else
2205                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2206                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2207 
2208                 /* Re-enable BAR2 WC */
2209                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2210         }
2211 
2212         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2213                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2214 }
2215 
2216 void t4_db_full(struct adapter *adap)
2217 {
2218         if (is_t4(adap->params.chip)) {
2219                 disable_dbs(adap);
2220                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2221                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2222                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2223                 queue_work(adap->workq, &adap->db_full_task);
2224         }
2225 }
2226 
2227 void t4_db_dropped(struct adapter *adap)
2228 {
2229         if (is_t4(adap->params.chip)) {
2230                 disable_dbs(adap);
2231                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2232         }
2233         queue_work(adap->workq, &adap->db_drop_task);
2234 }
2235 
2236 void t4_register_netevent_notifier(void)
2237 {
2238         if (!netevent_registered) {
2239                 register_netevent_notifier(&cxgb4_netevent_nb);
2240                 netevent_registered = true;
2241         }
2242 }
2243 
2244 static void detach_ulds(struct adapter *adap)
2245 {
2246         unsigned int i;
2247 
2248         mutex_lock(&uld_mutex);
2249         list_del(&adap->list_node);
2250 
2251         for (i = 0; i < CXGB4_ULD_MAX; i++)
2252                 if (adap->uld && adap->uld[i].handle)
2253                         adap->uld[i].state_change(adap->uld[i].handle,
2254                                              CXGB4_STATE_DETACH);
2255 
2256         if (netevent_registered && list_empty(&adapter_list)) {
2257                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2258                 netevent_registered = false;
2259         }
2260         mutex_unlock(&uld_mutex);
2261 }
2262 
2263 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2264 {
2265         unsigned int i;
2266 
2267         mutex_lock(&uld_mutex);
2268         for (i = 0; i < CXGB4_ULD_MAX; i++)
2269                 if (adap->uld && adap->uld[i].handle)
2270                         adap->uld[i].state_change(adap->uld[i].handle,
2271                                                   new_state);
2272         mutex_unlock(&uld_mutex);
2273 }
2274 
2275 #if IS_ENABLED(CONFIG_IPV6)
2276 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2277                                    unsigned long event, void *data)
2278 {
2279         struct inet6_ifaddr *ifa = data;
2280         struct net_device *event_dev = ifa->idev->dev;
2281         const struct device *parent = NULL;
2282 #if IS_ENABLED(CONFIG_BONDING)
2283         struct adapter *adap;
2284 #endif
2285         if (is_vlan_dev(event_dev))
2286                 event_dev = vlan_dev_real_dev(event_dev);
2287 #if IS_ENABLED(CONFIG_BONDING)
2288         if (event_dev->flags & IFF_MASTER) {
2289                 list_for_each_entry(adap, &adapter_list, list_node) {
2290                         switch (event) {
2291                         case NETDEV_UP:
2292                                 cxgb4_clip_get(adap->port[0],
2293                                                (const u32 *)ifa, 1);
2294                                 break;
2295                         case NETDEV_DOWN:
2296                                 cxgb4_clip_release(adap->port[0],
2297                                                    (const u32 *)ifa, 1);
2298                                 break;
2299                         default:
2300                                 break;
2301                         }
2302                 }
2303                 return NOTIFY_OK;
2304         }
2305 #endif
2306 
2307         if (event_dev)
2308                 parent = event_dev->dev.parent;
2309 
2310         if (parent && parent->driver == &cxgb4_driver.driver) {
2311                 switch (event) {
2312                 case NETDEV_UP:
2313                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2314                         break;
2315                 case NETDEV_DOWN:
2316                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2317                         break;
2318                 default:
2319                         break;
2320                 }
2321         }
2322         return NOTIFY_OK;
2323 }
2324 
2325 static bool inet6addr_registered;
2326 static struct notifier_block cxgb4_inet6addr_notifier = {
2327         .notifier_call = cxgb4_inet6addr_handler
2328 };
2329 
2330 static void update_clip(const struct adapter *adap)
2331 {
2332         int i;
2333         struct net_device *dev;
2334         int ret;
2335 
2336         rcu_read_lock();
2337 
2338         for (i = 0; i < MAX_NPORTS; i++) {
2339                 dev = adap->port[i];
2340                 ret = 0;
2341 
2342                 if (dev)
2343                         ret = cxgb4_update_root_dev_clip(dev);
2344 
2345                 if (ret < 0)
2346                         break;
2347         }
2348         rcu_read_unlock();
2349 }
2350 #endif /* IS_ENABLED(CONFIG_IPV6) */
2351 
2352 /**
2353  *      cxgb_up - enable the adapter
2354  *      @adap: adapter being enabled
2355  *
2356  *      Called when the first port is enabled, this function performs the
2357  *      actions necessary to make an adapter operational, such as completing
2358  *      the initialization of HW modules, and enabling interrupts.
2359  *
2360  *      Must be called with the rtnl lock held.
2361  */
2362 static int cxgb_up(struct adapter *adap)
2363 {
2364         int err;
2365 
2366         mutex_lock(&uld_mutex);
2367         err = setup_sge_queues(adap);
2368         if (err)
2369                 goto rel_lock;
2370         err = setup_rss(adap);
2371         if (err)
2372                 goto freeq;
2373 
2374         if (adap->flags & CXGB4_USING_MSIX) {
2375                 name_msix_vecs(adap);
2376                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2377                                   adap->msix_info[0].desc, adap);
2378                 if (err)
2379                         goto irq_err;
2380                 err = request_msix_queue_irqs(adap);
2381                 if (err) {
2382                         free_irq(adap->msix_info[0].vec, adap);
2383                         goto irq_err;
2384                 }
2385         } else {
2386                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2387                                   (adap->flags & CXGB4_USING_MSI) ? 0
2388                                                                   : IRQF_SHARED,
2389                                   adap->port[0]->name, adap);
2390                 if (err)
2391                         goto irq_err;
2392         }
2393 
2394         enable_rx(adap);
2395         t4_sge_start(adap);
2396         t4_intr_enable(adap);
2397         adap->flags |= CXGB4_FULL_INIT_DONE;
2398         mutex_unlock(&uld_mutex);
2399 
2400         notify_ulds(adap, CXGB4_STATE_UP);
2401 #if IS_ENABLED(CONFIG_IPV6)
2402         update_clip(adap);
2403 #endif
2404         return err;
2405 
2406  irq_err:
2407         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2408  freeq:
2409         t4_free_sge_resources(adap);
2410  rel_lock:
2411         mutex_unlock(&uld_mutex);
2412         return err;
2413 }
2414 
2415 static void cxgb_down(struct adapter *adapter)
2416 {
2417         cancel_work_sync(&adapter->tid_release_task);
2418         cancel_work_sync(&adapter->db_full_task);
2419         cancel_work_sync(&adapter->db_drop_task);
2420         adapter->tid_release_task_busy = false;
2421         adapter->tid_release_head = NULL;
2422 
2423         t4_sge_stop(adapter);
2424         t4_free_sge_resources(adapter);
2425 
2426         adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2427 }
2428 
2429 /*
2430  * net_device operations
2431  */
2432 static int cxgb_open(struct net_device *dev)
2433 {
2434         int err;
2435         struct port_info *pi = netdev_priv(dev);
2436         struct adapter *adapter = pi->adapter;
2437 
2438         netif_carrier_off(dev);
2439 
2440         if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2441                 err = cxgb_up(adapter);
2442                 if (err < 0)
2443                         return err;
2444         }
2445 
2446         /* It's possible that the basic port information could have
2447          * changed since we first read it.
2448          */
2449         err = t4_update_port_info(pi);
2450         if (err < 0)
2451                 return err;
2452 
2453         err = link_start(dev);
2454         if (!err)
2455                 netif_tx_start_all_queues(dev);
2456         return err;
2457 }
2458 
2459 static int cxgb_close(struct net_device *dev)
2460 {
2461         struct port_info *pi = netdev_priv(dev);
2462         struct adapter *adapter = pi->adapter;
2463         int ret;
2464 
2465         netif_tx_stop_all_queues(dev);
2466         netif_carrier_off(dev);
2467         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2468                                   false, false, false);
2469 #ifdef CONFIG_CHELSIO_T4_DCB
2470         cxgb4_dcb_reset(dev);
2471         dcb_tx_queue_prio_enable(dev, false);
2472 #endif
2473         return ret;
2474 }
2475 
2476 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2477                 __be32 sip, __be16 sport, __be16 vlan,
2478                 unsigned int queue, unsigned char port, unsigned char mask)
2479 {
2480         int ret;
2481         struct filter_entry *f;
2482         struct adapter *adap;
2483         int i;
2484         u8 *val;
2485 
2486         adap = netdev2adap(dev);
2487 
2488         /* Adjust stid to correct filter index */
2489         stid -= adap->tids.sftid_base;
2490         stid += adap->tids.nftids;
2491 
2492         /* Check to make sure the filter requested is writable ...
2493          */
2494         f = &adap->tids.ftid_tab[stid];
2495         ret = writable_filter(f);
2496         if (ret)
2497                 return ret;
2498 
2499         /* Clear out any old resources being used by the filter before
2500          * we start constructing the new filter.
2501          */
2502         if (f->valid)
2503                 clear_filter(adap, f);
2504 
2505         /* Clear out filter specifications */
2506         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2507         f->fs.val.lport = cpu_to_be16(sport);
2508         f->fs.mask.lport  = ~0;
2509         val = (u8 *)&sip;
2510         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2511                 for (i = 0; i < 4; i++) {
2512                         f->fs.val.lip[i] = val[i];
2513                         f->fs.mask.lip[i] = ~0;
2514                 }
2515                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2516                         f->fs.val.iport = port;
2517                         f->fs.mask.iport = mask;
2518                 }
2519         }
2520 
2521         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2522                 f->fs.val.proto = IPPROTO_TCP;
2523                 f->fs.mask.proto = ~0;
2524         }
2525 
2526         f->fs.dirsteer = 1;
2527         f->fs.iq = queue;
2528         /* Mark filter as locked */
2529         f->locked = 1;
2530         f->fs.rpttid = 1;
2531 
2532         /* Save the actual tid. We need this to get the corresponding
2533          * filter entry structure in filter_rpl.
2534          */
2535         f->tid = stid + adap->tids.ftid_base;
2536         ret = set_filter_wr(adap, stid);
2537         if (ret) {
2538                 clear_filter(adap, f);
2539                 return ret;
2540         }
2541 
2542         return 0;
2543 }
2544 EXPORT_SYMBOL(cxgb4_create_server_filter);
2545 
2546 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2547                 unsigned int queue, bool ipv6)
2548 {
2549         struct filter_entry *f;
2550         struct adapter *adap;
2551 
2552         adap = netdev2adap(dev);
2553 
2554         /* Adjust stid to correct filter index */
2555         stid -= adap->tids.sftid_base;
2556         stid += adap->tids.nftids;
2557 
2558         f = &adap->tids.ftid_tab[stid];
2559         /* Unlock the filter */
2560         f->locked = 0;
2561 
2562         return delete_filter(adap, stid);
2563 }
2564 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2565 
2566 static void cxgb_get_stats(struct net_device *dev,
2567                            struct rtnl_link_stats64 *ns)
2568 {
2569         struct port_stats stats;
2570         struct port_info *p = netdev_priv(dev);
2571         struct adapter *adapter = p->adapter;
2572 
2573         /* Block retrieving statistics during EEH error
2574          * recovery. Otherwise, the recovery might fail
2575          * and the PCI device will be removed permanently
2576          */
2577         spin_lock(&adapter->stats_lock);
2578         if (!netif_device_present(dev)) {
2579                 spin_unlock(&adapter->stats_lock);
2580                 return;
2581         }
2582         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2583                                  &p->stats_base);
2584         spin_unlock(&adapter->stats_lock);
2585 
2586         ns->tx_bytes   = stats.tx_octets;
2587         ns->tx_packets = stats.tx_frames;
2588         ns->rx_bytes   = stats.rx_octets;
2589         ns->rx_packets = stats.rx_frames;
2590         ns->multicast  = stats.rx_mcast_frames;
2591 
2592         /* detailed rx_errors */
2593         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2594                                stats.rx_runt;
2595         ns->rx_over_errors   = 0;
2596         ns->rx_crc_errors    = stats.rx_fcs_err;
2597         ns->rx_frame_errors  = stats.rx_symbol_err;
2598         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2599                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2600                                stats.rx_trunc0 + stats.rx_trunc1 +
2601                                stats.rx_trunc2 + stats.rx_trunc3;
2602         ns->rx_missed_errors = 0;
2603 
2604         /* detailed tx_errors */
2605         ns->tx_aborted_errors   = 0;
2606         ns->tx_carrier_errors   = 0;
2607         ns->tx_fifo_errors      = 0;
2608         ns->tx_heartbeat_errors = 0;
2609         ns->tx_window_errors    = 0;
2610 
2611         ns->tx_errors = stats.tx_error_frames;
2612         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2613                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2614 }
2615 
2616 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2617 {
2618         unsigned int mbox;
2619         int ret = 0, prtad, devad;
2620         struct port_info *pi = netdev_priv(dev);
2621         struct adapter *adapter = pi->adapter;
2622         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2623 
2624         switch (cmd) {
2625         case SIOCGMIIPHY:
2626                 if (pi->mdio_addr < 0)
2627                         return -EOPNOTSUPP;
2628                 data->phy_id = pi->mdio_addr;
2629                 break;
2630         case SIOCGMIIREG:
2631         case SIOCSMIIREG:
2632                 if (mdio_phy_id_is_c45(data->phy_id)) {
2633                         prtad = mdio_phy_id_prtad(data->phy_id);
2634                         devad = mdio_phy_id_devad(data->phy_id);
2635                 } else if (data->phy_id < 32) {
2636                         prtad = data->phy_id;
2637                         devad = 0;
2638                         data->reg_num &= 0x1f;
2639                 } else
2640                         return -EINVAL;
2641 
2642                 mbox = pi->adapter->pf;
2643                 if (cmd == SIOCGMIIREG)
2644                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2645                                          data->reg_num, &data->val_out);
2646                 else
2647                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2648                                          data->reg_num, data->val_in);
2649                 break;
2650         case SIOCGHWTSTAMP:
2651                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2652                                     sizeof(pi->tstamp_config)) ?
2653                         -EFAULT : 0;
2654         case SIOCSHWTSTAMP:
2655                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2656                                    sizeof(pi->tstamp_config)))
2657                         return -EFAULT;
2658 
2659                 if (!is_t4(adapter->params.chip)) {
2660                         switch (pi->tstamp_config.tx_type) {
2661                         case HWTSTAMP_TX_OFF:
2662                         case HWTSTAMP_TX_ON:
2663                                 break;
2664                         default:
2665                                 return -ERANGE;
2666                         }
2667 
2668                         switch (pi->tstamp_config.rx_filter) {
2669                         case HWTSTAMP_FILTER_NONE:
2670                                 pi->rxtstamp = false;
2671                                 break;
2672                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2673                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2674                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2675                                                          PTP_TS_L4);
2676                                 break;
2677                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2678                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2679                                                          PTP_TS_L2_L4);
2680                                 break;
2681                         case HWTSTAMP_FILTER_ALL:
2682                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2683                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2684                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2685                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2686                                 pi->rxtstamp = true;
2687                                 break;
2688                         default:
2689                                 pi->tstamp_config.rx_filter =
2690                                         HWTSTAMP_FILTER_NONE;
2691                                 return -ERANGE;
2692                         }
2693 
2694                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2695                             (pi->tstamp_config.rx_filter ==
2696                                 HWTSTAMP_FILTER_NONE)) {
2697                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2698                                         pi->ptp_enable = false;
2699                         }
2700 
2701                         if (pi->tstamp_config.rx_filter !=
2702                                 HWTSTAMP_FILTER_NONE) {
2703                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2704                                                                  pi) >= 0)
2705                                         pi->ptp_enable = true;
2706                         }
2707                 } else {
2708                         /* For T4 Adapters */
2709                         switch (pi->tstamp_config.rx_filter) {
2710                         case HWTSTAMP_FILTER_NONE:
2711                         pi->rxtstamp = false;
2712                         break;
2713                         case HWTSTAMP_FILTER_ALL:
2714                         pi->rxtstamp = true;
2715                         break;
2716                         default:
2717                         pi->tstamp_config.rx_filter =
2718                         HWTSTAMP_FILTER_NONE;
2719                         return -ERANGE;
2720                         }
2721                 }
2722                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2723                                     sizeof(pi->tstamp_config)) ?
2724                         -EFAULT : 0;
2725         default:
2726                 return -EOPNOTSUPP;
2727         }
2728         return ret;
2729 }
2730 
2731 static void cxgb_set_rxmode(struct net_device *dev)
2732 {
2733         /* unfortunately we can't return errors to the stack */
2734         set_rxmode(dev, -1, false);
2735 }
2736 
2737 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2738 {
2739         int ret;
2740         struct port_info *pi = netdev_priv(dev);
2741 
2742         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2743                             -1, -1, -1, true);
2744         if (!ret)
2745                 dev->mtu = new_mtu;
2746         return ret;
2747 }
2748 
2749 #ifdef CONFIG_PCI_IOV
2750 static int cxgb4_mgmt_open(struct net_device *dev)
2751 {
2752         /* Turn carrier off since we don't have to transmit anything on this
2753          * interface.
2754          */
2755         netif_carrier_off(dev);
2756         return 0;
2757 }
2758 
2759 /* Fill MAC address that will be assigned by the FW */
2760 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2761 {
2762         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2763         unsigned int i, vf, nvfs;
2764         u16 a, b;
2765         int err;
2766         u8 *na;
2767 
2768         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2769                                                             PCI_CAP_ID_VPD);
2770         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2771         if (err)
2772                 return;
2773 
2774         na = adap->params.vpd.na;
2775         for (i = 0; i < ETH_ALEN; i++)
2776                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2777                               hex2val(na[2 * i + 1]));
2778 
2779         a = (hw_addr[0] << 8) | hw_addr[1];
2780         b = (hw_addr[1] << 8) | hw_addr[2];
2781         a ^= b;
2782         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2783         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2784         macaddr[0] = a >> 8;
2785         macaddr[1] = a & 0xff;
2786 
2787         for (i = 2; i < 5; i++)
2788                 macaddr[i] = hw_addr[i + 1];
2789 
2790         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2791                 vf < nvfs; vf++) {
2792                 macaddr[5] = adap->pf * nvfs + vf;
2793                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2794         }
2795 }
2796 
2797 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2798 {
2799         struct port_info *pi = netdev_priv(dev);
2800         struct adapter *adap = pi->adapter;
2801         int ret;
2802 
2803         /* verify MAC addr is valid */
2804         if (!is_valid_ether_addr(mac)) {
2805                 dev_err(pi->adapter->pdev_dev,
2806                         "Invalid Ethernet address %pM for VF %d\n",
2807                         mac, vf);
2808                 return -EINVAL;
2809         }
2810 
2811         dev_info(pi->adapter->pdev_dev,
2812                  "Setting MAC %pM on VF %d\n", mac, vf);
2813         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2814         if (!ret)
2815                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2816         return ret;
2817 }
2818 
2819 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2820                                     int vf, struct ifla_vf_info *ivi)
2821 {
2822         struct port_info *pi = netdev_priv(dev);
2823         struct adapter *adap = pi->adapter;
2824         struct vf_info *vfinfo;
2825 
2826         if (vf >= adap->num_vfs)
2827                 return -EINVAL;
2828         vfinfo = &adap->vfinfo[vf];
2829 
2830         ivi->vf = vf;
2831         ivi->max_tx_rate = vfinfo->tx_rate;
2832         ivi->min_tx_rate = 0;
2833         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2834         ivi->vlan = vfinfo->vlan;
2835         ivi->linkstate = vfinfo->link_state;
2836         return 0;
2837 }
2838 
2839 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2840                                        struct netdev_phys_item_id *ppid)
2841 {
2842         struct port_info *pi = netdev_priv(dev);
2843         unsigned int phy_port_id;
2844 
2845         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2846         ppid->id_len = sizeof(phy_port_id);
2847         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2848         return 0;
2849 }
2850 
2851 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2852                                   int min_tx_rate, int max_tx_rate)
2853 {
2854         struct port_info *pi = netdev_priv(dev);
2855         struct adapter *adap = pi->adapter;
2856         unsigned int link_ok, speed, mtu;
2857         u32 fw_pfvf, fw_class;
2858         int class_id = vf;
2859         int ret;
2860         u16 pktsize;
2861 
2862         if (vf >= adap->num_vfs)
2863                 return -EINVAL;
2864 
2865         if (min_tx_rate) {
2866                 dev_err(adap->pdev_dev,
2867                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2868                         min_tx_rate, vf);
2869                 return -EINVAL;
2870         }
2871 
2872         if (max_tx_rate == 0) {
2873                 /* unbind VF to to any Traffic Class */
2874                 fw_pfvf =
2875                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2876                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2877                 fw_class = 0xffffffff;
2878                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2879                                     &fw_pfvf, &fw_class);
2880                 if (ret) {
2881                         dev_err(adap->pdev_dev,
2882                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2883                                 ret, adap->pf, vf);
2884                         return -EINVAL;
2885                 }
2886                 dev_info(adap->pdev_dev,
2887                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2888                          adap->pf, vf);
2889                 adap->vfinfo[vf].tx_rate = 0;
2890                 return 0;
2891         }
2892 
2893         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2894         if (ret != FW_SUCCESS) {
2895                 dev_err(adap->pdev_dev,
2896                         "Failed to get link information for VF %d\n", vf);
2897                 return -EINVAL;
2898         }
2899 
2900         if (!link_ok) {
2901                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2902                 return -EINVAL;
2903         }
2904 
2905         if (max_tx_rate > speed) {
2906                 dev_err(adap->pdev_dev,
2907                         "Max tx rate %d for VF %d can't be > link-speed %u",
2908                         max_tx_rate, vf, speed);
2909                 return -EINVAL;
2910         }
2911 
2912         pktsize = mtu;
2913         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2914         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2915         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2916         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2917         /* configure Traffic Class for rate-limiting */
2918         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2919                               SCHED_CLASS_LEVEL_CL_RL,
2920                               SCHED_CLASS_MODE_CLASS,
2921                               SCHED_CLASS_RATEUNIT_BITS,
2922                               SCHED_CLASS_RATEMODE_ABS,
2923                               pi->tx_chan, class_id, 0,
2924                               max_tx_rate * 1000, 0, pktsize);
2925         if (ret) {
2926                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2927                         ret);
2928                 return -EINVAL;
2929         }
2930         dev_info(adap->pdev_dev,
2931                  "Class %d with MSS %u configured with rate %u\n",
2932                  class_id, pktsize, max_tx_rate);
2933 
2934         /* bind VF to configured Traffic Class */
2935         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2936                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2937         fw_class = class_id;
2938         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2939                             &fw_class);
2940         if (ret) {
2941                 dev_err(adap->pdev_dev,
2942                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2943                         ret, adap->pf, vf, class_id);
2944                 return -EINVAL;
2945         }
2946         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2947                  adap->pf, vf, class_id);
2948         adap->vfinfo[vf].tx_rate = max_tx_rate;
2949         return 0;
2950 }
2951 
2952 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2953                                   u16 vlan, u8 qos, __be16 vlan_proto)
2954 {
2955         struct port_info *pi = netdev_priv(dev);
2956         struct adapter *adap = pi->adapter;
2957         int ret;
2958 
2959         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2960                 return -EINVAL;
2961 
2962         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2963                 return -EPROTONOSUPPORT;
2964 
2965         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2966         if (!ret) {
2967                 adap->vfinfo[vf].vlan = vlan;
2968                 return 0;
2969         }
2970 
2971         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2972                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2973         return ret;
2974 }
2975 
2976 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2977                                         int link)
2978 {
2979         struct port_info *pi = netdev_priv(dev);
2980         struct adapter *adap = pi->adapter;
2981         u32 param, val;
2982         int ret = 0;
2983 
2984         if (vf >= adap->num_vfs)
2985                 return -EINVAL;
2986 
2987         switch (link) {
2988         case IFLA_VF_LINK_STATE_AUTO:
2989                 val = FW_VF_LINK_STATE_AUTO;
2990                 break;
2991 
2992         case IFLA_VF_LINK_STATE_ENABLE:
2993                 val = FW_VF_LINK_STATE_ENABLE;
2994                 break;
2995 
2996         case IFLA_VF_LINK_STATE_DISABLE:
2997                 val = FW_VF_LINK_STATE_DISABLE;
2998                 break;
2999 
3000         default:
3001                 return -EINVAL;
3002         }
3003 
3004         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3005                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
3006         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
3007                             &param, &val);
3008         if (ret) {
3009                 dev_err(adap->pdev_dev,
3010                         "Error %d in setting PF %d VF %d link state\n",
3011                         ret, adap->pf, vf);
3012                 return -EINVAL;
3013         }
3014 
3015         adap->vfinfo[vf].link_state = link;
3016         return ret;
3017 }
3018 #endif /* CONFIG_PCI_IOV */
3019 
3020 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3021 {
3022         int ret;
3023         struct sockaddr *addr = p;
3024         struct port_info *pi = netdev_priv(dev);
3025 
3026         if (!is_valid_ether_addr(addr->sa_data))
3027                 return -EADDRNOTAVAIL;
3028 
3029         ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
3030                                     addr->sa_data, true, &pi->smt_idx);
3031         if (ret < 0)
3032                 return ret;
3033 
3034         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3035         return 0;
3036 }
3037 
3038 #ifdef CONFIG_NET_POLL_CONTROLLER
3039 static void cxgb_netpoll(struct net_device *dev)
3040 {
3041         struct port_info *pi = netdev_priv(dev);
3042         struct adapter *adap = pi->adapter;
3043 
3044         if (adap->flags & CXGB4_USING_MSIX) {
3045                 int i;
3046                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3047 
3048                 for (i = pi->nqsets; i; i--, rx++)
3049                         t4_sge_intr_msix(0, &rx->rspq);
3050         } else
3051                 t4_intr_handler(adap)(0, adap);
3052 }
3053 #endif
3054 
3055 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
3056 {
3057         struct port_info *pi = netdev_priv(dev);
3058         struct adapter *adap = pi->adapter;
3059         struct sched_class *e;
3060         struct ch_sched_params p;
3061         struct ch_sched_queue qe;
3062         u32 req_rate;
3063         int err = 0;
3064 
3065         if (!can_sched(dev))
3066                 return -ENOTSUPP;
3067 
3068         if (index < 0 || index > pi->nqsets - 1)
3069                 return -EINVAL;
3070 
3071         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3072                 dev_err(adap->pdev_dev,
3073                         "Failed to rate limit on queue %d. Link Down?\n",
3074                         index);
3075                 return -EINVAL;
3076         }
3077 
3078         /* Convert from Mbps to Kbps */
3079         req_rate = rate * 1000;
3080 
3081         /* Max rate is 100 Gbps */
3082         if (req_rate > SCHED_MAX_RATE_KBPS) {
3083                 dev_err(adap->pdev_dev,
3084                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
3085                         rate, SCHED_MAX_RATE_KBPS / 1000);
3086                 return -ERANGE;
3087         }
3088 
3089         /* First unbind the queue from any existing class */
3090         memset(&qe, 0, sizeof(qe));
3091         qe.queue = index;
3092         qe.class = SCHED_CLS_NONE;
3093 
3094         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3095         if (err) {
3096                 dev_err(adap->pdev_dev,
3097                         "Unbinding Queue %d on port %d fail. Err: %d\n",
3098                         index, pi->port_id, err);
3099                 return err;
3100         }
3101 
3102         /* Queue already unbound */
3103         if (!req_rate)
3104                 return 0;
3105 
3106         /* Fetch any available unused or matching scheduling class */
3107         memset(&p, 0, sizeof(p));
3108         p.type = SCHED_CLASS_TYPE_PACKET;
3109         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
3110         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
3111         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3112         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3113         p.u.params.channel  = pi->tx_chan;
3114         p.u.params.class    = SCHED_CLS_NONE;
3115         p.u.params.minrate  = 0;
3116         p.u.params.maxrate  = req_rate;
3117         p.u.params.weight   = 0;
3118         p.u.params.pktsize  = dev->mtu;
3119 
3120         e = cxgb4_sched_class_alloc(dev, &p);
3121         if (!e)
3122                 return -ENOMEM;
3123 
3124         /* Bind the queue to a scheduling class */
3125         memset(&qe, 0, sizeof(qe));
3126         qe.queue = index;
3127         qe.class = e->idx;
3128 
3129         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3130         if (err)
3131                 dev_err(adap->pdev_dev,
3132                         "Queue rate limiting failed. Err: %d\n", err);
3133         return err;
3134 }
3135 
3136 static int cxgb_setup_tc_flower(struct net_device *dev,
3137                                 struct flow_cls_offload *cls_flower)
3138 {
3139         switch (cls_flower->command) {
3140         case FLOW_CLS_REPLACE:
3141                 return cxgb4_tc_flower_replace(dev, cls_flower);
3142         case FLOW_CLS_DESTROY:
3143                 return cxgb4_tc_flower_destroy(dev, cls_flower);
3144         case FLOW_CLS_STATS:
3145                 return cxgb4_tc_flower_stats(dev, cls_flower);
3146         default:
3147                 return -EOPNOTSUPP;
3148         }
3149 }
3150 
3151 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3152                                  struct tc_cls_u32_offload *cls_u32)
3153 {
3154         switch (cls_u32->command) {
3155         case TC_CLSU32_NEW_KNODE:
3156         case TC_CLSU32_REPLACE_KNODE:
3157                 return cxgb4_config_knode(dev, cls_u32);
3158         case TC_CLSU32_DELETE_KNODE:
3159                 return cxgb4_delete_knode(dev, cls_u32);
3160         default:
3161                 return -EOPNOTSUPP;
3162         }
3163 }
3164 
3165 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3166                                   void *cb_priv)
3167 {
3168         struct net_device *dev = cb_priv;
3169         struct port_info *pi = netdev2pinfo(dev);
3170         struct adapter *adap = netdev2adap(dev);
3171 
3172         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3173                 dev_err(adap->pdev_dev,
3174                         "Failed to setup tc on port %d. Link Down?\n",
3175                         pi->port_id);
3176                 return -EINVAL;
3177         }
3178 
3179         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3180                 return -EOPNOTSUPP;
3181 
3182         switch (type) {
3183         case TC_SETUP_CLSU32:
3184                 return cxgb_setup_tc_cls_u32(dev, type_data);
3185         case TC_SETUP_CLSFLOWER:
3186                 return cxgb_setup_tc_flower(dev, type_data);
3187         default:
3188                 return -EOPNOTSUPP;
3189         }
3190 }
3191 
3192 static LIST_HEAD(cxgb_block_cb_list);
3193 
3194 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3195                          void *type_data)
3196 {
3197         struct port_info *pi = netdev2pinfo(dev);
3198 
3199         switch (type) {
3200         case TC_SETUP_BLOCK:
3201                 return flow_block_cb_setup_simple(type_data,
3202                                                   &cxgb_block_cb_list,
3203                                                   cxgb_setup_tc_block_cb,
3204                                                   pi, dev, true);
3205         default:
3206                 return -EOPNOTSUPP;
3207         }
3208 }
3209 
3210 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3211                                 struct udp_tunnel_info *ti)
3212 {
3213         struct port_info *pi = netdev_priv(netdev);
3214         struct adapter *adapter = pi->adapter;
3215         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3216         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3217         int ret = 0, i;
3218 
3219         if (chip_ver < CHELSIO_T6)
3220                 return;
3221 
3222         switch (ti->type) {
3223         case UDP_TUNNEL_TYPE_VXLAN:
3224                 if (!adapter->vxlan_port_cnt ||
3225                     adapter->vxlan_port != ti->port)
3226                         return; /* Invalid VxLAN destination port */
3227 
3228                 adapter->vxlan_port_cnt--;
3229                 if (adapter->vxlan_port_cnt)
3230                         return;
3231 
3232                 adapter->vxlan_port = 0;
3233                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3234                 break;
3235         case UDP_TUNNEL_TYPE_GENEVE:
3236                 if (!adapter->geneve_port_cnt ||
3237                     adapter->geneve_port != ti->port)
3238                         return; /* Invalid GENEVE destination port */
3239 
3240                 adapter->geneve_port_cnt--;
3241                 if (adapter->geneve_port_cnt)
3242                         return;
3243 
3244                 adapter->geneve_port = 0;
3245                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3246                 break;
3247         default:
3248                 return;
3249         }
3250 
3251         /* Matchall mac entries can be deleted only after all tunnel ports
3252          * are brought down or removed.
3253          */
3254         if (!adapter->rawf_cnt)
3255                 return;
3256         for_each_port(adapter, i) {
3257                 pi = adap2pinfo(adapter, i);
3258                 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3259                                            match_all_mac, match_all_mac,
3260                                            adapter->rawf_start +
3261                                             pi->port_id,
3262                                            1, pi->port_id, false);
3263                 if (ret < 0) {
3264                         netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3265                                     i);
3266                         return;
3267                 }
3268         }
3269 }
3270 
3271 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3272                                 struct udp_tunnel_info *ti)
3273 {
3274         struct port_info *pi = netdev_priv(netdev);
3275         struct adapter *adapter = pi->adapter;
3276         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3277         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3278         int i, ret;
3279 
3280         if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3281                 return;
3282 
3283         switch (ti->type) {
3284         case UDP_TUNNEL_TYPE_VXLAN:
3285                 /* Callback for adding vxlan port can be called with the same
3286                  * port for both IPv4 and IPv6. We should not disable the
3287                  * offloading when the same port for both protocols is added
3288                  * and later one of them is removed.
3289                  */
3290                 if (adapter->vxlan_port_cnt &&
3291                     adapter->vxlan_port == ti->port) {
3292                         adapter->vxlan_port_cnt++;
3293                         return;
3294                 }
3295 
3296                 /* We will support only one VxLAN port */
3297                 if (adapter->vxlan_port_cnt) {
3298                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3299                                     be16_to_cpu(adapter->vxlan_port),
3300                                     be16_to_cpu(ti->port));
3301                         return;
3302                 }
3303 
3304                 adapter->vxlan_port = ti->port;
3305                 adapter->vxlan_port_cnt = 1;
3306 
3307                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3308                              VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3309                 break;
3310         case UDP_TUNNEL_TYPE_GENEVE:
3311                 if (adapter->geneve_port_cnt &&
3312                     adapter->geneve_port == ti->port) {
3313                         adapter->geneve_port_cnt++;
3314                         return;
3315                 }
3316 
3317                 /* We will support only one GENEVE port */
3318                 if (adapter->geneve_port_cnt) {
3319                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3320                                     be16_to_cpu(adapter->geneve_port),
3321                                     be16_to_cpu(ti->port));
3322                         return;
3323                 }
3324 
3325                 adapter->geneve_port = ti->port;
3326                 adapter->geneve_port_cnt = 1;
3327 
3328                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3329                              GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3330                 break;
3331         default:
3332                 return;
3333         }
3334 
3335         /* Create a 'match all' mac filter entry for inner mac,
3336          * if raw mac interface is supported. Once the linux kernel provides
3337          * driver entry points for adding/deleting the inner mac addresses,
3338          * we will remove this 'match all' entry and fallback to adding
3339          * exact match filters.
3340          */
3341         for_each_port(adapter, i) {
3342                 pi = adap2pinfo(adapter, i);
3343 
3344                 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3345                                             match_all_mac,
3346                                             match_all_mac,
3347                                             adapter->rawf_start +
3348                                             pi->port_id,
3349                                             1, pi->port_id, false);
3350                 if (ret < 0) {
3351                         netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3352                                     be16_to_cpu(ti->port));
3353                         cxgb_del_udp_tunnel(netdev, ti);
3354                         return;
3355                 }
3356         }
3357 }
3358 
3359 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3360                                              struct net_device *dev,
3361                                              netdev_features_t features)
3362 {
3363         struct port_info *pi = netdev_priv(dev);
3364         struct adapter *adapter = pi->adapter;
3365 
3366         if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3367                 return features;
3368 
3369         /* Check if hw supports offload for this packet */
3370         if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3371                 return features;
3372 
3373         /* Offload is not supported for this encapsulated packet */
3374         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3375 }
3376 
3377 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3378                                            netdev_features_t features)
3379 {
3380         /* Disable GRO, if RX_CSUM is disabled */
3381         if (!(features & NETIF_F_RXCSUM))
3382                 features &= ~NETIF_F_GRO;
3383 
3384         return features;
3385 }
3386 
3387 static const struct net_device_ops cxgb4_netdev_ops = {
3388         .ndo_open             = cxgb_open,
3389         .ndo_stop             = cxgb_close,
3390         .ndo_start_xmit       = t4_start_xmit,
3391         .ndo_select_queue     = cxgb_select_queue,
3392         .ndo_get_stats64      = cxgb_get_stats,
3393         .ndo_set_rx_mode      = cxgb_set_rxmode,
3394         .ndo_set_mac_address  = cxgb_set_mac_addr,
3395         .ndo_set_features     = cxgb_set_features,
3396         .ndo_validate_addr    = eth_validate_addr,
3397         .ndo_do_ioctl         = cxgb_ioctl,
3398         .ndo_change_mtu       = cxgb_change_mtu,
3399 #ifdef CONFIG_NET_POLL_CONTROLLER
3400         .ndo_poll_controller  = cxgb_netpoll,
3401 #endif
3402 #ifdef CONFIG_CHELSIO_T4_FCOE
3403         .ndo_fcoe_enable      = cxgb_fcoe_enable,
3404         .ndo_fcoe_disable     = cxgb_fcoe_disable,
3405 #endif /* CONFIG_CHELSIO_T4_FCOE */
3406         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
3407         .ndo_setup_tc         = cxgb_setup_tc,
3408         .ndo_udp_tunnel_add   = cxgb_add_udp_tunnel,
3409         .ndo_udp_tunnel_del   = cxgb_del_udp_tunnel,
3410         .ndo_features_check   = cxgb_features_check,
3411         .ndo_fix_features     = cxgb_fix_features,
3412 };
3413 
3414 #ifdef CONFIG_PCI_IOV
3415 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3416         .ndo_open               = cxgb4_mgmt_open,
3417         .ndo_set_vf_mac         = cxgb4_mgmt_set_vf_mac,
3418         .ndo_get_vf_config      = cxgb4_mgmt_get_vf_config,
3419         .ndo_set_vf_rate        = cxgb4_mgmt_set_vf_rate,
3420         .ndo_get_phys_port_id   = cxgb4_mgmt_get_phys_port_id,
3421         .ndo_set_vf_vlan        = cxgb4_mgmt_set_vf_vlan,
3422         .ndo_set_vf_link_state  = cxgb4_mgmt_set_vf_link_state,
3423 };
3424 #endif
3425 
3426 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3427                                    struct ethtool_drvinfo *info)
3428 {
3429         struct adapter *adapter = netdev2adap(dev);
3430 
3431         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3432         strlcpy(info->version, cxgb4_driver_version,
3433                 sizeof(info->version));
3434         strlcpy(info->bus_info, pci_name(adapter->pdev),
3435                 sizeof(info->bus_info));
3436 }
3437 
3438 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3439         .get_drvinfo       = cxgb4_mgmt_get_drvinfo,
3440 };
3441 
3442 static void notify_fatal_err(struct work_struct *work)
3443 {
3444         struct adapter *adap;
3445 
3446         adap = container_of(work, struct adapter, fatal_err_notify_task);
3447         notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3448 }
3449 
3450 void t4_fatal_err(struct adapter *adap)
3451 {
3452         int port;
3453 
3454         if (pci_channel_offline(adap->pdev))
3455                 return;
3456 
3457         /* Disable the SGE since ULDs are going to free resources that
3458          * could be exposed to the adapter.  RDMA MWs for example...
3459          */
3460         t4_shutdown_adapter(adap);
3461         for_each_port(adap, port) {
3462                 struct net_device *dev = adap->port[port];
3463 
3464                 /* If we get here in very early initialization the network
3465                  * devices may not have been set up yet.
3466                  */
3467                 if (!dev)
3468                         continue;
3469 
3470                 netif_tx_stop_all_queues(dev);
3471                 netif_carrier_off(dev);
3472         }
3473         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3474         queue_work(adap->workq, &adap->fatal_err_notify_task);
3475 }
3476 
3477 static void setup_memwin(struct adapter *adap)
3478 {
3479         u32 nic_win_base = t4_get_util_window(adap);
3480 
3481         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3482 }
3483 
3484 static void setup_memwin_rdma(struct adapter *adap)
3485 {
3486         if (adap->vres.ocq.size) {
3487                 u32 start;
3488                 unsigned int sz_kb;
3489 
3490                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3491                 start &= PCI_BASE_ADDRESS_MEM_MASK;
3492                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3493                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3494                 t4_write_reg(adap,
3495                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3496                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3497                 t4_write_reg(adap,
3498                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3499                              adap->vres.ocq.start);
3500                 t4_read_reg(adap,
3501                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3502         }
3503 }
3504 
3505 /* HMA Definitions */
3506 
3507 /* The maximum number of address that can be send in a single FW cmd */
3508 #define HMA_MAX_ADDR_IN_CMD     5
3509 
3510 #define HMA_PAGE_SIZE           PAGE_SIZE
3511 
3512 #define HMA_MAX_NO_FW_ADDRESS   (16 << 10)  /* FW supports 16K addresses */
3513 
3514 #define HMA_PAGE_ORDER                                  \
3515         ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ?      \
3516         ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3517 
3518 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3519  * configuration(in units of MB).
3520  */
3521 #define HMA_MIN_TOTAL_SIZE      1
3522 #define HMA_MAX_TOTAL_SIZE                              \
3523         (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) *           \
3524           HMA_MAX_NO_FW_ADDRESS) >> 20)
3525 
3526 static void adap_free_hma_mem(struct adapter *adapter)
3527 {
3528         struct scatterlist *iter;
3529         struct page *page;
3530         int i;
3531 
3532         if (!adapter->hma.sgt)
3533                 return;
3534 
3535         if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3536                 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3537                              adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3538                 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3539         }
3540 
3541         for_each_sg(adapter->hma.sgt->sgl, iter,
3542                     adapter->hma.sgt->orig_nents, i) {
3543                 page = sg_page(iter);
3544                 if (page)
3545                         __free_pages(page, HMA_PAGE_ORDER);
3546         }
3547 
3548         kfree(adapter->hma.phy_addr);
3549         sg_free_table(adapter->hma.sgt);
3550         kfree(adapter->hma.sgt);
3551         adapter->hma.sgt = NULL;
3552 }
3553 
3554 static int adap_config_hma(struct adapter *adapter)
3555 {
3556         struct scatterlist *sgl, *iter;
3557         struct sg_table *sgt;
3558         struct page *newpage;
3559         unsigned int i, j, k;
3560         u32 param, hma_size;
3561         unsigned int ncmds;
3562         size_t page_size;
3563         u32 page_order;
3564         int node, ret;
3565 
3566         /* HMA is supported only for T6+ cards.
3567          * Avoid initializing HMA in kdump kernels.
3568          */
3569         if (is_kdump_kernel() ||
3570             CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3571                 return 0;
3572 
3573         /* Get the HMA region size required by fw */
3574         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3575                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3576         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3577                               1, &param, &hma_size);
3578         /* An error means card has its own memory or HMA is not supported by
3579          * the firmware. Return without any errors.
3580          */
3581         if (ret || !hma_size)
3582                 return 0;
3583 
3584         if (hma_size < HMA_MIN_TOTAL_SIZE ||
3585             hma_size > HMA_MAX_TOTAL_SIZE) {
3586                 dev_err(adapter->pdev_dev,
3587                         "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3588                         hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3589                 return -EINVAL;
3590         }
3591 
3592         page_size = HMA_PAGE_SIZE;
3593         page_order = HMA_PAGE_ORDER;
3594         adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3595         if (unlikely(!adapter->hma.sgt)) {
3596                 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3597                 return -ENOMEM;
3598         }
3599         sgt = adapter->hma.sgt;
3600         /* FW returned value will be in MB's
3601          */
3602         sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3603         if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3604                 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3605                 kfree(adapter->hma.sgt);
3606                 adapter->hma.sgt = NULL;
3607                 return -ENOMEM;
3608         }
3609 
3610         sgl = adapter->hma.sgt->sgl;
3611         node = dev_to_node(adapter->pdev_dev);
3612         for_each_sg(sgl, iter, sgt->orig_nents, i) {
3613                 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3614                                            __GFP_ZERO, page_order);
3615                 if (!newpage) {
3616                         dev_err(adapter->pdev_dev,
3617                                 "Not enough memory for HMA page allocation\n");
3618                         ret = -ENOMEM;
3619                         goto free_hma;
3620                 }
3621                 sg_set_page(iter, newpage, page_size << page_order, 0);
3622         }
3623 
3624         sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3625                                 DMA_BIDIRECTIONAL);
3626         if (!sgt->nents) {
3627                 dev_err(adapter->pdev_dev,
3628                         "Not enough memory for HMA DMA mapping");
3629                 ret = -ENOMEM;
3630                 goto free_hma;
3631         }
3632         adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3633 
3634         adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3635                                         GFP_KERNEL);
3636         if (unlikely(!adapter->hma.phy_addr))
3637                 goto free_hma;
3638 
3639         for_each_sg(sgl, iter, sgt->nents, i) {
3640                 newpage = sg_page(iter);
3641                 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3642         }
3643 
3644         ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3645         /* Pass on the addresses to firmware */
3646         for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3647                 struct fw_hma_cmd hma_cmd;
3648                 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3649                 u8 soc = 0, eoc = 0;
3650                 u8 hma_mode = 1; /* Presently we support only Page table mode */
3651 
3652                 soc = (i == 0) ? 1 : 0;
3653                 eoc = (i == ncmds - 1) ? 1 : 0;
3654 
3655                 /* For last cmd, set naddr corresponding to remaining
3656                  * addresses
3657                  */
3658                 if (i == ncmds - 1) {
3659                         naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3660                         naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3661                 }
3662                 memset(&hma_cmd, 0, sizeof(hma_cmd));
3663                 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3664                                        FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3665                 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3666 
3667                 hma_cmd.mode_to_pcie_params =
3668                         htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3669                               FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3670 
3671                 /* HMA cmd size specified in MB's */
3672                 hma_cmd.naddr_size =
3673                         htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3674                               FW_HMA_CMD_NADDR_V(naddr));
3675 
3676                 /* Total Page size specified in units of 4K */
3677                 hma_cmd.addr_size_pkd =
3678                         htonl(FW_HMA_CMD_ADDR_SIZE_V
3679                                 ((page_size << page_order) >> 12));
3680 
3681                 /* Fill the 5 addresses */
3682                 for (j = 0; j < naddr; j++) {
3683                         hma_cmd.phy_address[j] =
3684                                 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3685                 }
3686                 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3687                                  sizeof(hma_cmd), &hma_cmd);
3688                 if (ret) {
3689                         dev_err(adapter->pdev_dev,
3690                                 "HMA FW command failed with err %d\n", ret);
3691                         goto free_hma;
3692                 }
3693         }
3694 
3695         if (!ret)
3696                 dev_info(adapter->pdev_dev,
3697                          "Reserved %uMB host memory for HMA\n", hma_size);
3698         return ret;
3699 
3700 free_hma:
3701         adap_free_hma_mem(adapter);
3702         return ret;
3703 }
3704 
3705 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3706 {
3707         u32 v;
3708         int ret;
3709 
3710         /* Now that we've successfully configured and initialized the adapter
3711          * can ask the Firmware what resources it has provisioned for us.
3712          */
3713         ret = t4_get_pfres(adap);
3714         if (ret) {
3715                 dev_err(adap->pdev_dev,
3716                         "Unable to retrieve resource provisioning information\n");
3717                 return ret;
3718         }
3719 
3720         /* get device capabilities */
3721         memset(c, 0, sizeof(*c));
3722         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3723                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
3724         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3725         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3726         if (ret < 0)
3727                 return ret;
3728 
3729         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3730                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3731         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3732         if (ret < 0)
3733                 return ret;
3734 
3735         ret = t4_config_glbl_rss(adap, adap->pf,
3736                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3737                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3738                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3739         if (ret < 0)
3740                 return ret;
3741 
3742         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3743                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3744                           FW_CMD_CAP_PF);
3745         if (ret < 0)
3746                 return ret;
3747 
3748         t4_sge_init(adap);
3749 
3750         /* tweak some settings */
3751         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3752         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3753         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3754         v = t4_read_reg(adap, TP_PIO_DATA_A);
3755         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3756 
3757         /* first 4 Tx modulation queues point to consecutive Tx channels */
3758         adap->params.tp.tx_modq_map = 0xE4;
3759         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3760                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3761 
3762         /* associate each Tx modulation queue with consecutive Tx channels */
3763         v = 0x84218421;
3764         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3765                           &v, 1, TP_TX_SCHED_HDR_A);
3766         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3767                           &v, 1, TP_TX_SCHED_FIFO_A);
3768         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3769                           &v, 1, TP_TX_SCHED_PCMD_A);
3770 
3771 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3772         if (is_offload(adap)) {
3773                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3774                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3775                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3776                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3777                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3778                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3779                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3780                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3781                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3782                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3783         }
3784 
3785         /* get basic stuff going */
3786         return t4_early_init(adap, adap->pf);
3787 }
3788 
3789 /*
3790  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3791  */
3792 #define MAX_ATIDS 8192U
3793 
3794 /*
3795  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3796  *
3797  * If the firmware we're dealing with has Configuration File support, then
3798  * we use that to perform all configuration
3799  */
3800 
3801 /*
3802  * Tweak configuration based on module parameters, etc.  Most of these have
3803  * defaults assigned to them by Firmware Configuration Files (if we're using
3804  * them) but need to be explicitly set if we're using hard-coded
3805  * initialization.  But even in the case of using Firmware Configuration
3806  * Files, we'd like to expose the ability to change these via module
3807  * parameters so these are essentially common tweaks/settings for
3808  * Configuration Files and hard-coded initialization ...
3809  */
3810 static int adap_init0_tweaks(struct adapter *adapter)
3811 {
3812         /*
3813          * Fix up various Host-Dependent Parameters like Page Size, Cache
3814          * Line Size, etc.  The firmware default is for a 4KB Page Size and
3815          * 64B Cache Line Size ...
3816          */
3817         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3818 
3819         /*
3820          * Process module parameters which affect early initialization.
3821          */
3822         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3823                 dev_err(&adapter->pdev->dev,
3824                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
3825                         rx_dma_offset);
3826                 rx_dma_offset = 2;
3827         }
3828         t4_set_reg_field(adapter, SGE_CONTROL_A,
3829                          PKTSHIFT_V(PKTSHIFT_M),
3830                          PKTSHIFT_V(rx_dma_offset));
3831 
3832         /*
3833          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3834          * adds the pseudo header itself.
3835          */
3836         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3837                                CSUM_HAS_PSEUDO_HDR_F, 0);
3838 
3839         return 0;
3840 }
3841 
3842 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3843  * unto themselves and they contain their own firmware to perform their
3844  * tasks ...
3845  */
3846 static int phy_aq1202_version(const u8 *phy_fw_data,
3847                               size_t phy_fw_size)
3848 {
3849         int offset;
3850 
3851         /* At offset 0x8 you're looking for the primary image's
3852          * starting offset which is 3 Bytes wide
3853          *
3854          * At offset 0xa of the primary image, you look for the offset
3855          * of the DRAM segment which is 3 Bytes wide.
3856          *
3857          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3858          * wide
3859          */
3860         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3861         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3862         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3863 
3864         offset = le24(phy_fw_data + 0x8) << 12;
3865         offset = le24(phy_fw_data + offset + 0xa);
3866         return be16(phy_fw_data + offset + 0x27e);
3867 
3868         #undef be16
3869         #undef le16
3870         #undef le24
3871 }
3872 
3873 static struct info_10gbt_phy_fw {
3874         unsigned int phy_fw_id;         /* PCI Device ID */
3875         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
3876         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3877         int phy_flash;                  /* Has FLASH for PHY Firmware */
3878 } phy_info_array[] = {
3879         {
3880                 PHY_AQ1202_DEVICEID,
3881                 PHY_AQ1202_FIRMWARE,
3882                 phy_aq1202_version,
3883                 1,
3884         },
3885         {
3886                 PHY_BCM84834_DEVICEID,
3887                 PHY_BCM84834_FIRMWARE,
3888                 NULL,
3889                 0,
3890         },
3891         { 0, NULL, NULL },
3892 };
3893 
3894 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3895 {
3896         int i;
3897 
3898         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3899                 if (phy_info_array[i].phy_fw_id == devid)
3900                         return &phy_info_array[i];
3901         }
3902         return NULL;
3903 }
3904 
3905 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
3906  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
3907  * we return a negative error number.  If we transfer new firmware we return 1
3908  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
3909  */
3910 static int adap_init0_phy(struct adapter *adap)
3911 {
3912         const struct firmware *phyf;
3913         int ret;
3914         struct info_10gbt_phy_fw *phy_info;
3915 
3916         /* Use the device ID to determine which PHY file to flash.
3917          */
3918         phy_info = find_phy_info(adap->pdev->device);
3919         if (!phy_info) {
3920                 dev_warn(adap->pdev_dev,
3921                          "No PHY Firmware file found for this PHY\n");
3922                 return -EOPNOTSUPP;
3923         }
3924 
3925         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3926          * use that. The adapter firmware provides us with a memory buffer
3927          * where we can load a PHY firmware file from the host if we want to
3928          * override the PHY firmware File in flash.
3929          */
3930         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3931                                       adap->pdev_dev);
3932         if (ret < 0) {
3933                 /* For adapters without FLASH attached to PHY for their
3934                  * firmware, it's obviously a fatal error if we can't get the
3935                  * firmware to the adapter.  For adapters with PHY firmware
3936                  * FLASH storage, it's worth a warning if we can't find the
3937                  * PHY Firmware but we'll neuter the error ...
3938                  */
3939                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3940                         "/lib/firmware/%s, error %d\n",
3941                         phy_info->phy_fw_file, -ret);
3942                 if (phy_info->phy_flash) {
3943                         int cur_phy_fw_ver = 0;
3944 
3945                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3946                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3947                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
3948                         ret = 0;
3949                 }
3950 
3951                 return ret;
3952         }
3953 
3954         /* Load PHY Firmware onto adapter.
3955          */
3956         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3957                              phy_info->phy_fw_version,
3958                              (u8 *)phyf->data, phyf->size);
3959         if (ret < 0)
3960                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3961                         -ret);
3962         else if (ret > 0) {
3963                 int new_phy_fw_ver = 0;
3964 
3965                 if (phy_info->phy_fw_version)
3966                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3967                                                                   phyf->size);
3968                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3969                          "Firmware /lib/firmware/%s, version %#x\n",
3970                          phy_info->phy_fw_file, new_phy_fw_ver);
3971         }
3972 
3973         release_firmware(phyf);
3974 
3975         return ret;
3976 }
3977 
3978 /*
3979  * Attempt to initialize the adapter via a Firmware Configuration File.
3980  */
3981 static int adap_init0_config(struct adapter *adapter, int reset)
3982 {
3983         char *fw_config_file, fw_config_file_path[256];
3984         u32 finiver, finicsum, cfcsum, param, val;
3985         struct fw_caps_config_cmd caps_cmd;
3986         unsigned long mtype = 0, maddr = 0;
3987         const struct firmware *cf;
3988         char *config_name = NULL;
3989         int config_issued = 0;
3990         int ret;
3991 
3992         /*
3993          * Reset device if necessary.
3994          */
3995         if (reset) {
3996                 ret = t4_fw_reset(adapter, adapter->mbox,
3997                                   PIORSTMODE_F | PIORST_F);
3998                 if (ret < 0)
3999                         goto bye;
4000         }
4001 
4002         /* If this is a 10Gb/s-BT adapter make sure the chip-external
4003          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
4004          * to be performed after any global adapter RESET above since some
4005          * PHYs only have local RAM copies of the PHY firmware.
4006          */
4007         if (is_10gbt_device(adapter->pdev->device)) {
4008                 ret = adap_init0_phy(adapter);
4009                 if (ret < 0)
4010                         goto bye;
4011         }
4012         /*
4013          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4014          * then use that.  Otherwise, use the configuration file stored
4015          * in the adapter flash ...
4016          */
4017         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
4018         case CHELSIO_T4:
4019                 fw_config_file = FW4_CFNAME;
4020                 break;
4021         case CHELSIO_T5:
4022                 fw_config_file = FW5_CFNAME;
4023                 break;
4024         case CHELSIO_T6:
4025                 fw_config_file = FW6_CFNAME;
4026                 break;
4027         default:
4028                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4029                        adapter->pdev->device);
4030                 ret = -EINVAL;
4031                 goto bye;
4032         }
4033 
4034         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
4035         if (ret < 0) {
4036                 config_name = "On FLASH";
4037                 mtype = FW_MEMTYPE_CF_FLASH;
4038                 maddr = t4_flash_cfg_addr(adapter);
4039         } else {
4040                 u32 params[7], val[7];
4041 
4042                 sprintf(fw_config_file_path,
4043                         "/lib/firmware/%s", fw_config_file);
4044                 config_name = fw_config_file_path;
4045 
4046                 if (cf->size >= FLASH_CFG_MAX_SIZE)
4047                         ret = -ENOMEM;
4048                 else {
4049                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4050                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4051                         ret = t4_query_params(adapter, adapter->mbox,
4052                                               adapter->pf, 0, 1, params, val);
4053                         if (ret == 0) {
4054                                 /*
4055                                  * For t4_memory_rw() below addresses and
4056                                  * sizes have to be in terms of multiples of 4
4057                                  * bytes.  So, if the Configuration File isn't
4058                                  * a multiple of 4 bytes in length we'll have
4059                                  * to write that out separately since we can't
4060                                  * guarantee that the bytes following the
4061                                  * residual byte in the buffer returned by
4062                                  * request_firmware() are zeroed out ...
4063                                  */
4064                                 size_t resid = cf->size & 0x3;
4065                                 size_t size = cf->size & ~0x3;
4066                                 __be32 *data = (__be32 *)cf->data;
4067 
4068                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
4069                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
4070 
4071                                 spin_lock(&adapter->win0_lock);
4072                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
4073                                                    size, data, T4_MEMORY_WRITE);
4074                                 if (ret == 0 && resid != 0) {
4075                                         union {
4076                                                 __be32 word;
4077                                                 char buf[4];
4078                                         } last;
4079                                         int i;
4080 
4081                                         last.word = data[size >> 2];
4082                                         for (i = resid; i < 4; i++)
4083                                                 last.buf[i] = 0;
4084                                         ret = t4_memory_rw(adapter, 0, mtype,
4085                                                            maddr + size,
4086                                                            4, &last.word,
4087                                                            T4_MEMORY_WRITE);
4088                                 }
4089                                 spin_unlock(&adapter->win0_lock);
4090                         }
4091                 }
4092 
4093                 release_firmware(cf);
4094                 if (ret)
4095                         goto bye;
4096         }
4097 
4098         val = 0;
4099 
4100         /* Ofld + Hash filter is supported. Older fw will fail this request and
4101          * it is fine.
4102          */
4103         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4104                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD));
4105         ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
4106                             1, &param, &val);
4107 
4108         /* FW doesn't know about Hash filter + ofld support,
4109          * it's not a problem, don't return an error.
4110          */
4111         if (ret < 0) {
4112                 dev_warn(adapter->pdev_dev,
4113                          "Hash filter with ofld is not supported by FW\n");
4114         }
4115 
4116         /*
4117          * Issue a Capability Configuration command to the firmware to get it
4118          * to parse the Configuration File.  We don't use t4_fw_config_file()
4119          * because we want the ability to modify various features after we've
4120          * processed the configuration file ...
4121          */
4122         memset(&caps_cmd, 0, sizeof(caps_cmd));
4123         caps_cmd.op_to_write =
4124                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4125                       FW_CMD_REQUEST_F |
4126                       FW_CMD_READ_F);
4127         caps_cmd.cfvalid_to_len16 =
4128                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4129                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4130                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4131                       FW_LEN16(caps_cmd));
4132         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4133                          &caps_cmd);
4134 
4135         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4136          * Configuration File in FLASH), our last gasp effort is to use the
4137          * Firmware Configuration File which is embedded in the firmware.  A
4138          * very few early versions of the firmware didn't have one embedded
4139          * but we can ignore those.
4140          */
4141         if (ret == -ENOENT) {
4142                 memset(&caps_cmd, 0, sizeof(caps_cmd));
4143                 caps_cmd.op_to_write =
4144                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4145                                         FW_CMD_REQUEST_F |
4146                                         FW_CMD_READ_F);
4147                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4148                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4149                                 sizeof(caps_cmd), &caps_cmd);
4150                 config_name = "Firmware Default";
4151         }
4152 
4153         config_issued = 1;
4154         if (ret < 0)
4155                 goto bye;
4156 
4157         finiver = ntohl(caps_cmd.finiver);
4158         finicsum = ntohl(caps_cmd.finicsum);
4159         cfcsum = ntohl(caps_cmd.cfcsum);
4160         if (finicsum != cfcsum)
4161                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4162                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4163                          finicsum, cfcsum);
4164 
4165         /*
4166          * And now tell the firmware to use the configuration we just loaded.
4167          */
4168         caps_cmd.op_to_write =
4169                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4170                       FW_CMD_REQUEST_F |
4171                       FW_CMD_WRITE_F);
4172         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4173         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4174                          NULL);
4175         if (ret < 0)
4176                 goto bye;
4177 
4178         /*
4179          * Tweak configuration based on system architecture, module
4180          * parameters, etc.
4181          */
4182         ret = adap_init0_tweaks(adapter);
4183         if (ret < 0)
4184                 goto bye;
4185 
4186         /* We will proceed even if HMA init fails. */
4187         ret = adap_config_hma(adapter);
4188         if (ret)
4189                 dev_err(adapter->pdev_dev,
4190                         "HMA configuration failed with error %d\n", ret);
4191 
4192         if (is_t6(adapter->params.chip)) {
4193                 ret = setup_ppod_edram(adapter);
4194                 if (!ret)
4195                         dev_info(adapter->pdev_dev, "Successfully enabled "
4196                                  "ppod edram feature\n");
4197         }
4198 
4199         /*
4200          * And finally tell the firmware to initialize itself using the
4201          * parameters from the Configuration File.
4202          */
4203         ret = t4_fw_initialize(adapter, adapter->mbox);
4204         if (ret < 0)
4205                 goto bye;
4206 
4207         /* Emit Firmware Configuration File information and return
4208          * successfully.
4209          */
4210         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4211                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4212                  config_name, finiver, cfcsum);
4213         return 0;
4214 
4215         /*
4216          * Something bad happened.  Return the error ...  (If the "error"
4217          * is that there's no Configuration File on the adapter we don't
4218          * want to issue a warning since this is fairly common.)
4219          */
4220 bye:
4221         if (config_issued && ret != -ENOENT)
4222                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4223                          config_name, -ret);
4224         return ret;
4225 }
4226 
4227 static struct fw_info fw_info_array[] = {
4228         {
4229                 .chip = CHELSIO_T4,
4230                 .fs_name = FW4_CFNAME,
4231                 .fw_mod_name = FW4_FNAME,
4232                 .fw_hdr = {
4233                         .chip = FW_HDR_CHIP_T4,
4234                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4235                         .intfver_nic = FW_INTFVER(T4, NIC),
4236                         .intfver_vnic = FW_INTFVER(T4, VNIC),
4237                         .intfver_ri = FW_INTFVER(T4, RI),
4238                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4239                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
4240                 },
4241         }, {
4242                 .chip = CHELSIO_T5,
4243                 .fs_name = FW5_CFNAME,
4244                 .fw_mod_name = FW5_FNAME,
4245                 .fw_hdr = {
4246                         .chip = FW_HDR_CHIP_T5,
4247                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4248                         .intfver_nic = FW_INTFVER(T5, NIC),
4249                         .intfver_vnic = FW_INTFVER(T5, VNIC),
4250                         .intfver_ri = FW_INTFVER(T5, RI),
4251                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4252                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
4253                 },
4254         }, {
4255                 .chip = CHELSIO_T6,
4256                 .fs_name = FW6_CFNAME,
4257                 .fw_mod_name = FW6_FNAME,
4258                 .fw_hdr = {
4259                         .chip = FW_HDR_CHIP_T6,
4260                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4261                         .intfver_nic = FW_INTFVER(T6, NIC),
4262                         .intfver_vnic = FW_INTFVER(T6, VNIC),
4263                         .intfver_ofld = FW_INTFVER(T6, OFLD),
4264                         .intfver_ri = FW_INTFVER(T6, RI),
4265                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4266                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4267                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4268                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
4269                 },
4270         }
4271 
4272 };
4273 
4274 static struct fw_info *find_fw_info(int chip)
4275 {
4276         int i;
4277 
4278         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4279                 if (fw_info_array[i].chip == chip)
4280                         return &fw_info_array[i];
4281         }
4282         return NULL;
4283 }
4284 
4285 /*
4286  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4287  */
4288 static int adap_init0(struct adapter *adap)
4289 {
4290         int ret;
4291         u32 v, port_vec;
4292         enum dev_state state;
4293         u32 params[7], val[7];
4294         struct fw_caps_config_cmd caps_cmd;
4295         int reset = 1;
4296 
4297         /* Grab Firmware Device Log parameters as early as possible so we have
4298          * access to it for debugging, etc.
4299          */
4300         ret = t4_init_devlog_params(adap);
4301         if (ret < 0)
4302                 return ret;
4303 
4304         /* Contact FW, advertising Master capability */
4305         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4306                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4307         if (ret < 0) {
4308                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4309                         ret);
4310                 return ret;
4311         }
4312         if (ret == adap->mbox)
4313                 adap->flags |= CXGB4_MASTER_PF;
4314 
4315         /*
4316          * If we're the Master PF Driver and the device is uninitialized,
4317          * then let's consider upgrading the firmware ...  (We always want
4318          * to check the firmware version number in order to A. get it for
4319          * later reporting and B. to warn if the currently loaded firmware
4320          * is excessively mismatched relative to the driver.)
4321          */
4322 
4323         t4_get_version_info(adap);
4324         ret = t4_check_fw_version(adap);
4325         /* If firmware is too old (not supported by driver) force an update. */
4326         if (ret)
4327                 state = DEV_STATE_UNINIT;
4328         if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4329                 struct fw_info *fw_info;
4330                 struct fw_hdr *card_fw;
4331                 const struct firmware *fw;
4332                 const u8 *fw_data = NULL;
4333                 unsigned int fw_size = 0;
4334 
4335                 /* This is the firmware whose headers the driver was compiled
4336                  * against
4337                  */
4338                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4339                 if (fw_info == NULL) {
4340                         dev_err(adap->pdev_dev,
4341                                 "unable to get firmware info for chip %d.\n",
4342                                 CHELSIO_CHIP_VERSION(adap->params.chip));
4343                         return -EINVAL;
4344                 }
4345 
4346                 /* allocate memory to read the header of the firmware on the
4347                  * card
4348                  */
4349                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4350                 if (!card_fw) {
4351                         ret = -ENOMEM;
4352                         goto bye;
4353                 }
4354 
4355                 /* Get FW from from /lib/firmware/ */
4356                 ret = request_firmware(&fw, fw_info->fw_mod_name,
4357                                        adap->pdev_dev);
4358                 if (ret < 0) {
4359                         dev_err(adap->pdev_dev,
4360                                 "unable to load firmware image %s, error %d\n",
4361                                 fw_info->fw_mod_name, ret);
4362                 } else {
4363                         fw_data = fw->data;
4364                         fw_size = fw->size;
4365                 }
4366 
4367                 /* upgrade FW logic */
4368                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4369                                  state, &reset);
4370 
4371                 /* Cleaning up */
4372                 release_firmware(fw);
4373                 kvfree(card_fw);
4374 
4375                 if (ret < 0)
4376                         goto bye;
4377         }
4378 
4379         /* If the firmware is initialized already, emit a simply note to that
4380          * effect. Otherwise, it's time to try initializing the adapter.
4381          */
4382         if (state == DEV_STATE_INIT) {
4383                 ret = adap_config_hma(adap);
4384                 if (ret)
4385                         dev_err(adap->pdev_dev,
4386                                 "HMA configuration failed with error %d\n",
4387                                 ret);
4388                 dev_info(adap->pdev_dev, "Coming up as %s: "\
4389                          "Adapter already initialized\n",
4390                          adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4391         } else {
4392                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4393                          "Initializing adapter\n");
4394 
4395                 /* Find out whether we're dealing with a version of the
4396                  * firmware which has configuration file support.
4397                  */
4398                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4399                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4400                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4401                                       params, val);
4402 
4403                 /* If the firmware doesn't support Configuration Files,
4404                  * return an error.
4405                  */
4406                 if (ret < 0) {
4407                         dev_err(adap->pdev_dev, "firmware doesn't support "
4408                                 "Firmware Configuration Files\n");
4409                         goto bye;
4410                 }
4411 
4412                 /* The firmware provides us with a memory buffer where we can
4413                  * load a Configuration File from the host if we want to
4414                  * override the Configuration File in flash.
4415                  */
4416                 ret = adap_init0_config(adap, reset);
4417                 if (ret == -ENOENT) {
4418                         dev_err(adap->pdev_dev, "no Configuration File "
4419                                 "present on adapter.\n");
4420                         goto bye;
4421                 }
4422                 if (ret < 0) {
4423                         dev_err(adap->pdev_dev, "could not initialize "
4424                                 "adapter, error %d\n", -ret);
4425                         goto bye;
4426                 }
4427         }
4428 
4429         /* Now that we've successfully configured and initialized the adapter
4430          * (or found it already initialized), we can ask the Firmware what
4431          * resources it has provisioned for us.
4432          */
4433         ret = t4_get_pfres(adap);
4434         if (ret) {
4435                 dev_err(adap->pdev_dev,
4436                         "Unable to retrieve resource provisioning information\n");
4437                 goto bye;
4438         }
4439 
4440         /* Grab VPD parameters.  This should be done after we establish a
4441          * connection to the firmware since some of the VPD parameters
4442          * (notably the Core Clock frequency) are retrieved via requests to
4443          * the firmware.  On the other hand, we need these fairly early on
4444          * so we do this right after getting ahold of the firmware.
4445          *
4446          * We need to do this after initializing the adapter because someone
4447          * could have FLASHed a new VPD which won't be read by the firmware
4448          * until we do the RESET ...
4449          */
4450         ret = t4_get_vpd_params(adap, &adap->params.vpd);
4451         if (ret < 0)
4452                 goto bye;
4453 
4454         /* Find out what ports are available to us.  Note that we need to do
4455          * this before calling adap_init0_no_config() since it needs nports
4456          * and portvec ...
4457          */
4458         v =
4459             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4460             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4461         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4462         if (ret < 0)
4463                 goto bye;
4464 
4465         adap->params.nports = hweight32(port_vec);
4466         adap->params.portvec = port_vec;
4467 
4468         /* Give the SGE code a chance to pull in anything that it needs ...
4469          * Note that this must be called after we retrieve our VPD parameters
4470          * in order to know how to convert core ticks to seconds, etc.
4471          */
4472         ret = t4_sge_init(adap);
4473         if (ret < 0)
4474                 goto bye;
4475 
4476         /* Grab the SGE Doorbell Queue Timer values.  If successful, that
4477          * indicates that the Firmware and Hardware support this.
4478          */
4479         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4480                     FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4481         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4482                               1, params, val);
4483 
4484         if (!ret) {
4485                 adap->sge.dbqtimer_tick = val[0];
4486                 ret = t4_read_sge_dbqtimers(adap,
4487                                             ARRAY_SIZE(adap->sge.dbqtimer_val),
4488                                             adap->sge.dbqtimer_val);
4489         }
4490 
4491         if (!ret)
4492                 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4493 
4494         if (is_bypass_device(adap->pdev->device))
4495                 adap->params.bypass = 1;
4496 
4497         /*
4498          * Grab some of our basic fundamental operating parameters.
4499          */
4500 #define FW_PARAM_DEV(param) \
4501         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4502         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
4503 
4504 #define FW_PARAM_PFVF(param) \
4505         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4506         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
4507         FW_PARAMS_PARAM_Y_V(0) | \
4508         FW_PARAMS_PARAM_Z_V(0)
4509 
4510         params[0] = FW_PARAM_PFVF(EQ_START);
4511         params[1] = FW_PARAM_PFVF(L2T_START);
4512         params[2] = FW_PARAM_PFVF(L2T_END);
4513         params[3] = FW_PARAM_PFVF(FILTER_START);
4514         params[4] = FW_PARAM_PFVF(FILTER_END);
4515         params[5] = FW_PARAM_PFVF(IQFLINT_START);
4516         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4517         if (ret < 0)
4518                 goto bye;
4519         adap->sge.egr_start = val[0];
4520         adap->l2t_start = val[1];
4521         adap->l2t_end = val[2];
4522         adap->tids.ftid_base = val[3];
4523         adap->tids.nftids = val[4] - val[3] + 1;
4524         adap->sge.ingr_start = val[5];
4525 
4526         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4527                 /* Read the raw mps entries. In T6, the last 2 tcam entries
4528                  * are reserved for raw mac addresses (rawf = 2, one per port).
4529                  */
4530                 params[0] = FW_PARAM_PFVF(RAWF_START);
4531                 params[1] = FW_PARAM_PFVF(RAWF_END);
4532                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4533                                       params, val);
4534                 if (ret == 0) {
4535                         adap->rawf_start = val[0];
4536                         adap->rawf_cnt = val[1] - val[0] + 1;
4537                 }
4538         }
4539 
4540         /* qids (ingress/egress) returned from firmware can be anywhere
4541          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4542          * Hence driver needs to allocate memory for this range to
4543          * store the queue info. Get the highest IQFLINT/EQ index returned
4544          * in FW_EQ_*_CMD.alloc command.
4545          */
4546         params[0] = FW_PARAM_PFVF(EQ_END);
4547         params[1] = FW_PARAM_PFVF(IQFLINT_END);
4548         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4549         if (ret < 0)
4550                 goto bye;
4551         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4552         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4553 
4554         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4555                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
4556         if (!adap->sge.egr_map) {
4557                 ret = -ENOMEM;
4558                 goto bye;
4559         }
4560 
4561         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4562                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4563         if (!adap->sge.ingr_map) {
4564                 ret = -ENOMEM;
4565                 goto bye;
4566         }
4567 
4568         /* Allocate the memory for the vaious egress queue bitmaps
4569          * ie starving_fl, txq_maperr and blocked_fl.
4570          */
4571         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4572                                         sizeof(long), GFP_KERNEL);
4573         if (!adap->sge.starving_fl) {
4574                 ret = -ENOMEM;
4575                 goto bye;
4576         }
4577 
4578         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4579                                        sizeof(long), GFP_KERNEL);
4580         if (!adap->sge.txq_maperr) {
4581                 ret = -ENOMEM;
4582                 goto bye;
4583         }
4584 
4585 #ifdef CONFIG_DEBUG_FS
4586         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4587                                        sizeof(long), GFP_KERNEL);
4588         if (!adap->sge.blocked_fl) {
4589                 ret = -ENOMEM;
4590                 goto bye;
4591         }
4592 #endif
4593 
4594         params[0] = FW_PARAM_PFVF(CLIP_START);
4595         params[1] = FW_PARAM_PFVF(CLIP_END);
4596         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4597         if (ret < 0)
4598                 goto bye;
4599         adap->clipt_start = val[0];
4600         adap->clipt_end = val[1];
4601 
4602         /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4603          * Classes supported by the hardware/firmware so we hard code it here
4604          * for now.
4605          */
4606         adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4607 
4608         /* query params related to active filter region */
4609         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4610         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4611         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4612         /* If Active filter size is set we enable establishing
4613          * offload connection through firmware work request
4614          */
4615         if ((val[0] != val[1]) && (ret >= 0)) {
4616                 adap->flags |= CXGB4_FW_OFLD_CONN;
4617                 adap->tids.aftid_base = val[0];
4618                 adap->tids.aftid_end = val[1];
4619         }
4620 
4621         /* If we're running on newer firmware, let it know that we're
4622          * prepared to deal with encapsulated CPL messages.  Older
4623          * firmware won't understand this and we'll just get
4624          * unencapsulated messages ...
4625          */
4626         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4627         val[0] = 1;
4628         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4629 
4630         /*
4631          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4632          * capability.  Earlier versions of the firmware didn't have the
4633          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4634          * permission to use ULPTX MEMWRITE DSGL.
4635          */
4636         if (is_t4(adap->params.chip)) {
4637                 adap->params.ulptx_memwrite_dsgl = false;
4638         } else {
4639                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4640                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4641                                       1, params, val);
4642                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4643         }
4644 
4645         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4646         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4647         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4648                               1, params, val);
4649         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4650 
4651         /* See if FW supports FW_FILTER2 work request */
4652         if (is_t4(adap->params.chip)) {
4653                 adap->params.filter2_wr_support = 0;
4654         } else {
4655                 params[0] = FW_PARAM_DEV(FILTER2_WR);
4656                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4657                                       1, params, val);
4658                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4659         }
4660 
4661         /* Check if FW supports returning vin and smt index.
4662          * If this is not supported, driver will interpret
4663          * these values from viid.
4664          */
4665         params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4666         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4667                               1, params, val);
4668         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4669 
4670         /*
4671          * Get device capabilities so we can determine what resources we need
4672          * to manage.
4673          */
4674         memset(&caps_cmd, 0, sizeof(caps_cmd));
4675         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4676                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
4677         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4678         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4679                          &caps_cmd);
4680         if (ret < 0)
4681                 goto bye;
4682 
4683         /* hash filter has some mandatory register settings to be tested and for
4684          * that it needs to test whether offload is enabled or not, hence
4685          * checking and setting it here.
4686          */
4687         if (caps_cmd.ofldcaps)
4688                 adap->params.offload = 1;
4689 
4690         if (caps_cmd.ofldcaps ||
4691             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
4692                 /* query offload-related parameters */
4693                 params[0] = FW_PARAM_DEV(NTID);
4694                 params[1] = FW_PARAM_PFVF(SERVER_START);
4695                 params[2] = FW_PARAM_PFVF(SERVER_END);
4696                 params[3] = FW_PARAM_PFVF(TDDP_START);
4697                 params[4] = FW_PARAM_PFVF(TDDP_END);
4698                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4699                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4700                                       params, val);
4701                 if (ret < 0)
4702                         goto bye;
4703                 adap->tids.ntids = val[0];
4704                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4705                 adap->tids.stid_base = val[1];
4706                 adap->tids.nstids = val[2] - val[1] + 1;
4707                 /*
4708                  * Setup server filter region. Divide the available filter
4709                  * region into two parts. Regular filters get 1/3rd and server
4710                  * filters get 2/3rd part. This is only enabled if workarond
4711                  * path is enabled.
4712                  * 1. For regular filters.
4713                  * 2. Server filter: This are special filters which are used
4714                  * to redirect SYN packets to offload queue.
4715                  */
4716                 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4717                         adap->tids.sftid_base = adap->tids.ftid_base +
4718                                         DIV_ROUND_UP(adap->tids.nftids, 3);
4719                         adap->tids.nsftids = adap->tids.nftids -
4720                                          DIV_ROUND_UP(adap->tids.nftids, 3);
4721                         adap->tids.nftids = adap->tids.sftid_base -
4722                                                 adap->tids.ftid_base;
4723                 }
4724                 adap->vres.ddp.start = val[3];
4725                 adap->vres.ddp.size = val[4] - val[3] + 1;
4726                 adap->params.ofldq_wr_cred = val[5];
4727 
4728                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4729                         init_hash_filter(adap);
4730                 } else {
4731                         adap->num_ofld_uld += 1;
4732                 }
4733         }
4734         if (caps_cmd.rdmacaps) {
4735                 params[0] = FW_PARAM_PFVF(STAG_START);
4736                 params[1] = FW_PARAM_PFVF(STAG_END);
4737                 params[2] = FW_PARAM_PFVF(RQ_START);
4738                 params[3] = FW_PARAM_PFVF(RQ_END);
4739                 params[4] = FW_PARAM_PFVF(PBL_START);
4740                 params[5] = FW_PARAM_PFVF(PBL_END);
4741                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4742                                       params, val);
4743                 if (ret < 0)
4744                         goto bye;
4745                 adap->vres.stag.start = val[0];
4746                 adap->vres.stag.size = val[1] - val[0] + 1;
4747                 adap->vres.rq.start = val[2];
4748                 adap->vres.rq.size = val[3] - val[2] + 1;
4749                 adap->vres.pbl.start = val[4];
4750                 adap->vres.pbl.size = val[5] - val[4] + 1;
4751 
4752                 params[0] = FW_PARAM_PFVF(SRQ_START);
4753                 params[1] = FW_PARAM_PFVF(SRQ_END);
4754                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4755                                       params, val);
4756                 if (!ret) {
4757                         adap->vres.srq.start = val[0];
4758                         adap->vres.srq.size = val[1] - val[0] + 1;
4759                 }
4760                 if (adap->vres.srq.size) {
4761                         adap->srq = t4_init_srq(adap->vres.srq.size);
4762                         if (!adap->srq)
4763                                 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4764                 }
4765 
4766                 params[0] = FW_PARAM_PFVF(SQRQ_START);
4767                 params[1] = FW_PARAM_PFVF(SQRQ_END);
4768                 params[2] = FW_PARAM_PFVF(CQ_START);
4769                 params[3] = FW_PARAM_PFVF(CQ_END);
4770                 params[4] = FW_PARAM_PFVF(OCQ_START);
4771                 params[5] = FW_PARAM_PFVF(OCQ_END);
4772                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4773                                       val);
4774                 if (ret < 0)
4775                         goto bye;
4776                 adap->vres.qp.start = val[0];
4777                 adap->vres.qp.size = val[1] - val[0] + 1;
4778                 adap->vres.cq.start = val[2];
4779                 adap->vres.cq.size = val[3] - val[2] + 1;
4780                 adap->vres.ocq.start = val[4];
4781                 adap->vres.ocq.size = val[5] - val[4] + 1;
4782 
4783                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4784                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4785                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4786                                       val);
4787                 if (ret < 0) {
4788                         adap->params.max_ordird_qp = 8;
4789                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4790                         ret = 0;
4791                 } else {
4792                         adap->params.max_ordird_qp = val[0];
4793                         adap->params.max_ird_adapter = val[1];
4794                 }
4795                 dev_info(adap->pdev_dev,
4796                          "max_ordird_qp %d max_ird_adapter %d\n",
4797                          adap->params.max_ordird_qp,
4798                          adap->params.max_ird_adapter);
4799 
4800                 /* Enable write_with_immediate if FW supports it */
4801                 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4802                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4803                                       val);
4804                 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
4805 
4806                 /* Enable write_cmpl if FW supports it */
4807                 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4808                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4809                                       val);
4810                 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
4811                 adap->num_ofld_uld += 2;
4812         }
4813         if (caps_cmd.iscsicaps) {
4814                 params[0] = FW_PARAM_PFVF(ISCSI_START);
4815                 params[1] = FW_PARAM_PFVF(ISCSI_END);
4816                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4817                                       params, val);
4818                 if (ret < 0)
4819                         goto bye;
4820                 adap->vres.iscsi.start = val[0];
4821                 adap->vres.iscsi.size = val[1] - val[0] + 1;
4822                 if (is_t6(adap->params.chip)) {
4823                         params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START);
4824                         params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END);
4825                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4826                                               params, val);
4827                         if (!ret) {
4828                                 adap->vres.ppod_edram.start = val[0];
4829                                 adap->vres.ppod_edram.size =
4830                                         val[1] - val[0] + 1;
4831 
4832                                 dev_info(adap->pdev_dev,
4833                                          "ppod edram start 0x%x end 0x%x size 0x%x\n",
4834                                          val[0], val[1],
4835                                          adap->vres.ppod_edram.size);
4836                         }
4837                 }
4838                 /* LIO target and cxgb4i initiaitor */
4839                 adap->num_ofld_uld += 2;
4840         }
4841         if (caps_cmd.cryptocaps) {
4842                 if (ntohs(caps_cmd.cryptocaps) &
4843                     FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4844                         params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4845                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4846                                               2, params, val);
4847                         if (ret < 0) {
4848                                 if (ret != -EINVAL)
4849                                         goto bye;
4850                         } else {
4851                                 adap->vres.ncrypto_fc = val[0];
4852                         }
4853                         adap->num_ofld_uld += 1;
4854                 }
4855                 if (ntohs(caps_cmd.cryptocaps) &
4856                     FW_CAPS_CONFIG_TLS_INLINE) {
4857                         params[0] = FW_PARAM_PFVF(TLS_START);
4858                         params[1] = FW_PARAM_PFVF(TLS_END);
4859                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4860                                               2, params, val);
4861                         if (ret < 0)
4862                                 goto bye;
4863                         adap->vres.key.start = val[0];
4864                         adap->vres.key.size = val[1] - val[0] + 1;
4865                         adap->num_uld += 1;
4866                 }
4867                 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
4868         }
4869 #undef FW_PARAM_PFVF
4870 #undef FW_PARAM_DEV
4871 
4872         /* The MTU/MSS Table is initialized by now, so load their values.  If
4873          * we're initializing the adapter, then we'll make any modifications
4874          * we want to the MTU/MSS Table and also initialize the congestion
4875          * parameters.
4876          */
4877         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4878         if (state != DEV_STATE_INIT) {
4879                 int i;
4880 
4881                 /* The default MTU Table contains values 1492 and 1500.
4882                  * However, for TCP, it's better to have two values which are
4883                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4884                  * This allows us to have a TCP Data Payload which is a
4885                  * multiple of 8 regardless of what combination of TCP Options
4886                  * are in use (always a multiple of 4 bytes) which is
4887                  * important for performance reasons.  For instance, if no
4888                  * options are in use, then we have a 20-byte IP header and a
4889                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
4890                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4891                  * which is not a multiple of 8.  So using an MSS of 1488 in
4892                  * this case results in a TCP Data Payload of 1448 bytes which
4893                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
4894                  * Stamps have been negotiated, then an MTU of 1500 bytes
4895                  * results in a TCP Data Payload of 1448 bytes which, as
4896                  * above, is a multiple of 8 bytes ...
4897                  */
4898                 for (i = 0; i < NMTUS; i++)
4899                         if (adap->params.mtus[i] == 1492) {
4900                                 adap->params.mtus[i] = 1488;
4901                                 break;
4902                         }
4903 
4904                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4905                              adap->params.b_wnd);
4906         }
4907         t4_init_sge_params(adap);
4908         adap->flags |= CXGB4_FW_OK;
4909         t4_init_tp_params(adap, true);
4910         return 0;
4911 
4912         /*
4913          * Something bad happened.  If a command timed out or failed with EIO
4914          * FW does not operate within its spec or something catastrophic
4915          * happened to HW/FW, stop issuing commands.
4916          */
4917 bye:
4918         adap_free_hma_mem(adap);
4919         kfree(adap->sge.egr_map);
4920         kfree(adap->sge.ingr_map);
4921         kfree(adap->sge.starving_fl);
4922         kfree(adap->sge.txq_maperr);
4923 #ifdef CONFIG_DEBUG_FS
4924         kfree(adap->sge.blocked_fl);
4925 #endif
4926         if (ret != -ETIMEDOUT && ret != -EIO)
4927                 t4_fw_bye(adap, adap->mbox);
4928         return ret;
4929 }
4930 
4931 /* EEH callbacks */
4932 
4933 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4934                                          pci_channel_state_t state)
4935 {
4936         int i;
4937         struct adapter *adap = pci_get_drvdata(pdev);
4938 
4939         if (!adap)
4940                 goto out;
4941 
4942         rtnl_lock();
4943         adap->flags &= ~CXGB4_FW_OK;
4944         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4945         spin_lock(&adap->stats_lock);
4946         for_each_port(adap, i) {
4947                 struct net_device *dev = adap->port[i];
4948                 if (dev) {
4949                         netif_device_detach(dev);
4950                         netif_carrier_off(dev);
4951                 }
4952         }
4953         spin_unlock(&adap->stats_lock);
4954         disable_interrupts(adap);
4955         if (adap->flags & CXGB4_FULL_INIT_DONE)
4956                 cxgb_down(adap);
4957         rtnl_unlock();
4958         if ((adap->flags & CXGB4_DEV_ENABLED)) {
4959                 pci_disable_device(pdev);
4960                 adap->flags &= ~CXGB4_DEV_ENABLED;
4961         }
4962 out:    return state == pci_channel_io_perm_failure ?
4963                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4964 }
4965 
4966 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4967 {
4968         int i, ret;
4969         struct fw_caps_config_cmd c;
4970         struct adapter *adap = pci_get_drvdata(pdev);
4971 
4972         if (!adap) {
4973                 pci_restore_state(pdev);
4974                 pci_save_state(pdev);
4975                 return PCI_ERS_RESULT_RECOVERED;
4976         }
4977 
4978         if (!(adap->flags & CXGB4_DEV_ENABLED)) {
4979                 if (pci_enable_device(pdev)) {
4980                         dev_err(&pdev->dev, "Cannot reenable PCI "
4981                                             "device after reset\n");
4982                         return PCI_ERS_RESULT_DISCONNECT;
4983                 }
4984                 adap->flags |= CXGB4_DEV_ENABLED;
4985         }
4986 
4987         pci_set_master(pdev);
4988         pci_restore_state(pdev);
4989         pci_save_state(pdev);
4990 
4991         if (t4_wait_dev_ready(adap->regs) < 0)
4992                 return PCI_ERS_RESULT_DISCONNECT;
4993         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4994                 return PCI_ERS_RESULT_DISCONNECT;
4995         adap->flags |= CXGB4_FW_OK;
4996         if (adap_init1(adap, &c))
4997                 return PCI_ERS_RESULT_DISCONNECT;
4998 
4999         for_each_port(adap, i) {
5000                 struct port_info *pi = adap2pinfo(adap, i);
5001                 u8 vivld = 0, vin = 0;
5002 
5003                 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
5004                                   NULL, NULL, &vivld, &vin);
5005                 if (ret < 0)
5006                         return PCI_ERS_RESULT_DISCONNECT;
5007                 pi->viid = ret;
5008                 pi->xact_addr_filt = -1;
5009                 /* If fw supports returning the VIN as part of FW_VI_CMD,
5010                  * save the returned values.
5011                  */
5012                 if (adap->params.viid_smt_extn_support) {
5013                         pi->vivld = vivld;
5014                         pi->vin = vin;
5015                 } else {
5016                         /* Retrieve the values from VIID */
5017                         pi->vivld = FW_VIID_VIVLD_G(pi->viid);
5018                         pi->vin = FW_VIID_VIN_G(pi->viid);
5019                 }
5020         }
5021 
5022         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5023                      adap->params.b_wnd);
5024         setup_memwin(adap);
5025         if (cxgb_up(adap))
5026                 return PCI_ERS_RESULT_DISCONNECT;
5027         return PCI_ERS_RESULT_RECOVERED;
5028 }
5029 
5030 static void eeh_resume(struct pci_dev *pdev)
5031 {
5032         int i;
5033         struct adapter *adap = pci_get_drvdata(pdev);
5034 
5035         if (!adap)
5036                 return;
5037 
5038         rtnl_lock();
5039         for_each_port(adap, i) {
5040                 struct net_device *dev = adap->port[i];
5041                 if (dev) {
5042                         if (netif_running(dev)) {
5043                                 link_start(dev);
5044                                 cxgb_set_rxmode(dev);
5045                         }
5046                         netif_device_attach(dev);
5047                 }
5048         }
5049         rtnl_unlock();
5050 }
5051 
5052 static const struct pci_error_handlers cxgb4_eeh = {
5053         .error_detected = eeh_err_detected,
5054         .slot_reset     = eeh_slot_reset,
5055         .resume         = eeh_resume,
5056 };
5057 
5058 /* Return true if the Link Configuration supports "High Speeds" (those greater
5059  * than 1Gb/s).
5060  */
5061 static inline bool is_x_10g_port(const struct link_config *lc)
5062 {
5063         unsigned int speeds, high_speeds;
5064 
5065         speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
5066         high_speeds = speeds &
5067                         ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
5068 
5069         return high_speeds != 0;
5070 }
5071 
5072 /*
5073  * Perform default configuration of DMA queues depending on the number and type
5074  * of ports we found and the number of available CPUs.  Most settings can be
5075  * modified by the admin prior to actual use.
5076  */
5077 static int cfg_queues(struct adapter *adap)
5078 {
5079         struct sge *s = &adap->sge;
5080         int i, n10g = 0, qidx = 0;
5081         int niqflint, neq, avail_eth_qsets;
5082         int max_eth_qsets = 32;
5083 #ifndef CONFIG_CHELSIO_T4_DCB
5084         int q10g = 0;
5085 #endif
5086 
5087         /* Reduce memory usage in kdump environment, disable all offload.
5088          */
5089         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
5090                 adap->params.offload = 0;
5091                 adap->params.crypto = 0;
5092         }
5093 
5094         /* Calculate the number of Ethernet Queue Sets available based on
5095          * resources provisioned for us.  We always have an Asynchronous
5096          * Firmware Event Ingress Queue.  If we're operating in MSI or Legacy
5097          * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
5098          * Ingress Queue.  Meanwhile, we need two Egress Queues for each
5099          * Queue Set: one for the Free List and one for the Ethernet TX Queue.
5100          *
5101          * Note that we should also take into account all of the various
5102          * Offload Queues.  But, in any situation where we're operating in
5103          * a Resource Constrained Provisioning environment, doing any Offload
5104          * at all is problematic ...
5105          */
5106         niqflint = adap->params.pfres.niqflint - 1;
5107         if (!(adap->flags & CXGB4_USING_MSIX))
5108                 niqflint--;
5109         neq = adap->params.pfres.neq / 2;
5110         avail_eth_qsets = min(niqflint, neq);
5111 
5112         if (avail_eth_qsets > max_eth_qsets)
5113                 avail_eth_qsets = max_eth_qsets;
5114 
5115         if (avail_eth_qsets < adap->params.nports) {
5116                 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
5117                         avail_eth_qsets, adap->params.nports);
5118                 return -ENOMEM;
5119         }
5120 
5121         /* Count the number of 10Gb/s or better ports */
5122         for_each_port(adap, i)
5123                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5124 
5125 #ifdef CONFIG_CHELSIO_T4_DCB
5126         /* For Data Center Bridging support we need to be able to support up
5127          * to 8 Traffic Priorities; each of which will be assigned to its
5128          * own TX Queue in order to prevent Head-Of-Line Blocking.
5129          */
5130         if (adap->params.nports * 8 > avail_eth_qsets) {
5131                 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5132                         avail_eth_qsets, adap->params.nports * 8);
5133                 return -ENOMEM;
5134         }
5135 
5136         for_each_port(adap, i) {
5137                 struct port_info *pi = adap2pinfo(adap, i);
5138 
5139                 pi->first_qset = qidx;
5140                 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5141                 qidx += pi->nqsets;
5142         }
5143 #else /* !CONFIG_CHELSIO_T4_DCB */
5144         /*
5145          * We default to 1 queue per non-10G port and up to # of cores queues
5146          * per 10G port.
5147          */
5148         if (n10g)
5149                 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5150         if (q10g > netif_get_num_default_rss_queues())
5151                 q10g = netif_get_num_default_rss_queues();
5152 
5153         if (is_kdump_kernel())
5154                 q10g = 1;
5155 
5156         for_each_port(adap, i) {
5157                 struct port_info *pi = adap2pinfo(adap, i);
5158 
5159                 pi->first_qset = qidx;
5160                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5161                 qidx += pi->nqsets;
5162         }
5163 #endif /* !CONFIG_CHELSIO_T4_DCB */
5164 
5165         s->ethqsets = qidx;
5166         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
5167 
5168         if (is_uld(adap)) {
5169                 /*
5170                  * For offload we use 1 queue/channel if all ports are up to 1G,
5171                  * otherwise we divide all available queues amongst the channels
5172                  * capped by the number of available cores.
5173                  */
5174                 if (n10g) {
5175                         i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
5176                         s->ofldqsets = roundup(i, adap->params.nports);
5177                 } else {
5178                         s->ofldqsets = adap->params.nports;
5179                 }
5180         }
5181 
5182         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5183                 struct sge_eth_rxq *r = &s->ethrxq[i];
5184 
5185                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5186                 r->fl.size = 72;
5187         }
5188 
5189         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5190                 s->ethtxq[i].q.size = 1024;
5191 
5192         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5193                 s->ctrlq[i].q.size = 512;
5194 
5195         if (!is_t4(adap->params.chip))
5196                 s->ptptxq.q.size = 8;
5197 
5198         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5199         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5200 
5201         return 0;
5202 }
5203 
5204 /*
5205  * Reduce the number of Ethernet queues across all ports to at most n.
5206  * n provides at least one queue per port.
5207  */
5208 static void reduce_ethqs(struct adapter *adap, int n)
5209 {
5210         int i;
5211         struct port_info *pi;
5212 
5213         while (n < adap->sge.ethqsets)
5214                 for_each_port(adap, i) {
5215                         pi = adap2pinfo(adap, i);
5216                         if (pi->nqsets > 1) {
5217                                 pi->nqsets--;
5218                                 adap->sge.ethqsets--;
5219                                 if (adap->sge.ethqsets <= n)
5220                                         break;
5221                         }
5222                 }
5223 
5224         n = 0;
5225         for_each_port(adap, i) {
5226                 pi = adap2pinfo(adap, i);
5227                 pi->first_qset = n;
5228                 n += pi->nqsets;
5229         }
5230 }
5231 
5232 static int get_msix_info(struct adapter *adap)
5233 {
5234         struct uld_msix_info *msix_info;
5235         unsigned int max_ingq = 0;
5236 
5237         if (is_offload(adap))
5238                 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5239         if (is_pci_uld(adap))
5240                 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5241 
5242         if (!max_ingq)
5243                 goto out;
5244 
5245         msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5246         if (!msix_info)
5247                 return -ENOMEM;
5248 
5249         adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5250                                                  sizeof(long), GFP_KERNEL);
5251         if (!adap->msix_bmap_ulds.msix_bmap) {
5252                 kfree(msix_info);
5253                 return -ENOMEM;
5254         }
5255         spin_lock_init(&adap->msix_bmap_ulds.lock);
5256         adap->msix_info_ulds = msix_info;
5257 out:
5258         return 0;
5259 }
5260 
5261 static void free_msix_info(struct adapter *adap)
5262 {
5263         if (!(adap->num_uld && adap->num_ofld_uld))
5264                 return;
5265 
5266         kfree(adap->msix_info_ulds);
5267         kfree(adap->msix_bmap_ulds.msix_bmap);
5268 }
5269 
5270 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5271 #define EXTRA_VECS 2
5272 
5273 static int enable_msix(struct adapter *adap)
5274 {
5275         int ofld_need = 0, uld_need = 0;
5276         int i, j, want, need, allocated;
5277         struct sge *s = &adap->sge;
5278         unsigned int nchan = adap->params.nports;
5279         struct msix_entry *entries;
5280         int max_ingq = MAX_INGQ;
5281 
5282         if (is_pci_uld(adap))
5283                 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5284         if (is_offload(adap))
5285                 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
5286         entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5287                                 GFP_KERNEL);
5288         if (!entries)
5289                 return -ENOMEM;
5290 
5291         /* map for msix */
5292         if (get_msix_info(adap)) {
5293                 adap->params.offload = 0;
5294                 adap->params.crypto = 0;
5295         }
5296 
5297         for (i = 0; i < max_ingq + 1; ++i)
5298                 entries[i].entry = i;
5299 
5300         want = s->max_ethqsets + EXTRA_VECS;
5301         if (is_offload(adap)) {
5302                 want += adap->num_ofld_uld * s->ofldqsets;
5303                 ofld_need = adap->num_ofld_uld * nchan;
5304         }
5305         if (is_pci_uld(adap)) {
5306                 want += adap->num_uld * s->ofldqsets;
5307                 uld_need = adap->num_uld * nchan;
5308         }
5309 #ifdef CONFIG_CHELSIO_T4_DCB
5310         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5311          * each port.
5312          */
5313         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5314 #else
5315         need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5316 #endif
5317         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5318         if (allocated < 0) {
5319                 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5320                          " not using MSI-X\n");
5321                 kfree(entries);
5322                 return allocated;
5323         }
5324 
5325         /* Distribute available vectors to the various queue groups.
5326          * Every group gets its minimum requirement and NIC gets top
5327          * priority for leftovers.
5328          */
5329         i = allocated - EXTRA_VECS - ofld_need - uld_need;
5330         if (i < s->max_ethqsets) {
5331                 s->max_ethqsets = i;
5332                 if (i < s->ethqsets)
5333                         reduce_ethqs(adap, i);
5334         }
5335         if (is_uld(adap)) {
5336                 if (allocated < want)
5337                         s->nqs_per_uld = nchan;
5338                 else
5339                         s->nqs_per_uld = s->ofldqsets;
5340         }
5341 
5342         for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
5343                 adap->msix_info[i].vec = entries[i].vector;
5344         if (is_uld(adap)) {
5345                 for (j = 0 ; i < allocated; ++i, j++) {
5346                         adap->msix_info_ulds[j].vec = entries[i].vector;
5347                         adap->msix_info_ulds[j].idx = i;
5348                 }
5349                 adap->msix_bmap_ulds.mapsize = j;
5350         }
5351         dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
5352                  "nic %d per uld %d\n",
5353                  allocated, s->max_ethqsets, s->nqs_per_uld);
5354 
5355         kfree(entries);
5356         return 0;
5357 }
5358 
5359 #undef EXTRA_VECS
5360 
5361 static int init_rss(struct adapter *adap)
5362 {
5363         unsigned int i;
5364         int err;
5365 
5366         err = t4_init_rss_mode(adap, adap->mbox);
5367         if (err)
5368                 return err;
5369 
5370         for_each_port(adap, i) {
5371                 struct port_info *pi = adap2pinfo(adap, i);
5372 
5373                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5374                 if (!pi->rss)
5375                         return -ENOMEM;
5376         }
5377         return 0;
5378 }
5379 
5380 /* Dump basic information about the adapter */
5381 static void print_adapter_info(struct adapter *adapter)
5382 {
5383         /* Hardware/Firmware/etc. Version/Revision IDs */
5384         t4_dump_version_info(adapter);
5385 
5386         /* Software/Hardware configuration */
5387         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5388                  is_offload(adapter) ? "R" : "",
5389                  ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5390                   (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5391                  is_offload(adapter) ? "Offload" : "non-Offload");
5392 }
5393 
5394 static void print_port_info(const struct net_device *dev)
5395 {
5396         char buf[80];
5397         char *bufp = buf;
5398         const struct port_info *pi = netdev_priv(dev);
5399         const struct adapter *adap = pi->adapter;
5400 
5401         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5402                 bufp += sprintf(bufp, "100M/");
5403         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5404                 bufp += sprintf(bufp, "1G/");
5405         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5406                 bufp += sprintf(bufp, "10G/");
5407         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5408                 bufp += sprintf(bufp, "25G/");
5409         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5410                 bufp += sprintf(bufp, "40G/");
5411         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5412                 bufp += sprintf(bufp, "50G/");
5413         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5414                 bufp += sprintf(bufp, "100G/");
5415         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5416                 bufp += sprintf(bufp, "200G/");
5417         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5418                 bufp += sprintf(bufp, "400G/");
5419         if (bufp != buf)
5420                 --bufp;
5421         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5422 
5423         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5424                     dev->name, adap->params.vpd.id, adap->name, buf);
5425 }
5426 
5427 /*
5428  * Free the following resources:
5429  * - memory used for tables
5430  * - MSI/MSI-X
5431  * - net devices
5432  * - resources FW is holding for us
5433  */
5434 static void free_some_resources(struct adapter *adapter)
5435 {
5436         unsigned int i;
5437 
5438         kvfree(adapter->smt);
5439         kvfree(adapter->l2t);
5440         kvfree(adapter->srq);
5441         t4_cleanup_sched(adapter);
5442         kvfree(adapter->tids.tid_tab);
5443         cxgb4_cleanup_tc_flower(adapter);
5444         cxgb4_cleanup_tc_u32(adapter);
5445         kfree(adapter->sge.egr_map);
5446         kfree(adapter->sge.ingr_map);
5447         kfree(adapter->sge.starving_fl);
5448         kfree(adapter->sge.txq_maperr);
5449 #ifdef CONFIG_DEBUG_FS
5450         kfree(adapter->sge.blocked_fl);
5451 #endif
5452         disable_msi(adapter);
5453 
5454         for_each_port(adapter, i)
5455                 if (adapter->port[i]) {
5456                         struct port_info *pi = adap2pinfo(adapter, i);
5457 
5458                         if (pi->viid != 0)
5459                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5460                                            0, pi->viid);
5461                         kfree(adap2pinfo(adapter, i)->rss);
5462                         free_netdev(adapter->port[i]);
5463                 }
5464         if (adapter->flags & CXGB4_FW_OK)
5465                 t4_fw_bye(adapter, adapter->pf);
5466 }
5467 
5468 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5469 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5470                    NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5471 #define SEGMENT_SIZE 128
5472 
5473 static int t4_get_chip_type(struct adapter *adap, int ver)
5474 {
5475         u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5476 
5477         switch (ver) {
5478         case CHELSIO_T4:
5479                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5480         case CHELSIO_T5:
5481                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5482         case CHELSIO_T6:
5483                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5484         default:
5485                 break;
5486         }
5487         return -EINVAL;
5488 }
5489 
5490 #ifdef CONFIG_PCI_IOV
5491 static void cxgb4_mgmt_setup(struct net_device *dev)
5492 {
5493         dev->type = ARPHRD_NONE;
5494         dev->mtu = 0;
5495         dev->hard_header_len = 0;
5496         dev->addr_len = 0;
5497         dev->tx_queue_len = 0;
5498         dev->flags |= IFF_NOARP;
5499         dev->priv_flags |= IFF_NO_QUEUE;
5500 
5501         /* Initialize the device structure. */
5502         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5503         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5504 }
5505 
5506 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5507 {
5508         struct adapter *adap = pci_get_drvdata(pdev);
5509         int err = 0;
5510         int current_vfs = pci_num_vf(pdev);
5511         u32 pcie_fw;
5512 
5513         pcie_fw = readl(adap->regs + PCIE_FW_A);
5514         /* Check if fw is initialized */
5515         if (!(pcie_fw & PCIE_FW_INIT_F)) {
5516                 dev_warn(&pdev->dev, "Device not initialized\n");
5517                 return -EOPNOTSUPP;
5518         }
5519 
5520         /* If any of the VF's is already assigned to Guest OS, then
5521          * SRIOV for the same cannot be modified
5522          */
5523         if (current_vfs && pci_vfs_assigned(pdev)) {
5524                 dev_err(&pdev->dev,
5525                         "Cannot modify SR-IOV while VFs are assigned\n");
5526                 return current_vfs;
5527         }
5528         /* Note that the upper-level code ensures that we're never called with
5529          * a non-zero "num_vfs" when we already have VFs instantiated.  But
5530          * it never hurts to code defensively.
5531          */
5532         if (num_vfs != 0 && current_vfs != 0)
5533                 return -EBUSY;
5534 
5535         /* Nothing to do for no change. */
5536         if (num_vfs == current_vfs)
5537                 return num_vfs;
5538 
5539         /* Disable SRIOV when zero is passed. */
5540         if (!num_vfs) {
5541                 pci_disable_sriov(pdev);
5542                 /* free VF Management Interface */
5543                 unregister_netdev(adap->port[0]);
5544                 free_netdev(adap->port[0]);
5545                 adap->port[0] = NULL;
5546 
5547                 /* free VF resources */
5548                 adap->num_vfs = 0;
5549                 kfree(adap->vfinfo);
5550                 adap->vfinfo = NULL;
5551                 return 0;
5552         }
5553 
5554         if (!current_vfs) {
5555                 struct fw_pfvf_cmd port_cmd, port_rpl;
5556                 struct net_device *netdev;
5557                 unsigned int pmask, port;
5558                 struct pci_dev *pbridge;
5559                 struct port_info *pi;
5560                 char name[IFNAMSIZ];
5561                 u32 devcap2;
5562                 u16 flags;
5563 
5564                 /* If we want to instantiate Virtual Functions, then our
5565                  * parent bridge's PCI-E needs to support Alternative Routing
5566                  * ID (ARI) because our VFs will show up at function offset 8
5567                  * and above.
5568                  */
5569                 pbridge = pdev->bus->self;
5570                 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
5571                 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
5572 
5573                 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5574                     !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5575                         /* Our parent bridge does not support ARI so issue a
5576                          * warning and skip instantiating the VFs.  They
5577                          * won't be reachable.
5578                          */
5579                         dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5580                                  pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5581                                  PCI_FUNC(pbridge->devfn));
5582                         return -ENOTSUPP;
5583                 }
5584                 memset(&port_cmd, 0, sizeof(port_cmd));
5585                 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5586                                                  FW_CMD_REQUEST_F |
5587                                                  FW_CMD_READ_F |
5588                                                  FW_PFVF_CMD_PFN_V(adap->pf) |
5589                                                  FW_PFVF_CMD_VFN_V(0));
5590                 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5591                 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5592                                  &port_rpl);
5593                 if (err)
5594                         return err;
5595                 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5596                 port = ffs(pmask) - 1;
5597                 /* Allocate VF Management Interface. */
5598                 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5599                          adap->pf);
5600                 netdev = alloc_netdev(sizeof(struct port_info),
5601                                       name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5602                 if (!netdev)
5603                         return -ENOMEM;
5604 
5605                 pi = netdev_priv(netdev);
5606                 pi->adapter = adap;
5607                 pi->lport = port;
5608                 pi->tx_chan = port;
5609                 SET_NETDEV_DEV(netdev, &pdev->dev);
5610 
5611                 adap->port[0] = netdev;
5612                 pi->port_id = 0;
5613 
5614                 err = register_netdev(adap->port[0]);
5615                 if (err) {
5616                         pr_info("Unable to register VF mgmt netdev %s\n", name);
5617                         free_netdev(adap->port[0]);
5618                         adap->port[0] = NULL;
5619                         return err;
5620                 }
5621                 /* Allocate and set up VF Information. */
5622                 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5623                                        sizeof(struct vf_info), GFP_KERNEL);
5624                 if (!adap->vfinfo) {
5625                         unregister_netdev(adap->port[0]);
5626                         free_netdev(adap->port[0]);
5627                         adap->port[0] = NULL;
5628                         return -ENOMEM;
5629                 }
5630                 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5631         }
5632         /* Instantiate the requested number of VFs. */
5633         err = pci_enable_sriov(pdev, num_vfs);
5634         if (err) {
5635                 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5636                 if (!current_vfs) {
5637                         unregister_netdev(adap->port[0]);
5638                         free_netdev(adap->port[0]);
5639                         adap->port[0] = NULL;
5640                         kfree(adap->vfinfo);
5641                         adap->vfinfo = NULL;
5642                 }
5643                 return err;
5644         }
5645 
5646         adap->num_vfs = num_vfs;
5647         return num_vfs;
5648 }
5649 #endif /* CONFIG_PCI_IOV */
5650 
5651 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5652 {
5653         struct net_device *netdev;
5654         struct adapter *adapter;
5655         static int adap_idx = 1;
5656         int s_qpp, qpp, num_seg;
5657         struct port_info *pi;
5658         bool highdma = false;
5659         enum chip_type chip;
5660         void __iomem *regs;
5661         int func, chip_ver;
5662         u16 device_id;
5663         int i, err;
5664         u32 whoami;
5665 
5666         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5667 
5668         err = pci_request_regions(pdev, KBUILD_MODNAME);
5669         if (err) {
5670                 /* Just info, some other driver may have claimed the device. */
5671                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5672                 return err;
5673         }
5674 
5675         err = pci_enable_device(pdev);
5676         if (err) {
5677                 dev_err(&pdev->dev, "cannot enable PCI device\n");
5678                 goto out_release_regions;
5679         }
5680 
5681         regs = pci_ioremap_bar(pdev, 0);
5682         if (!regs) {
5683                 dev_err(&pdev->dev, "cannot map device registers\n");
5684                 err = -ENOMEM;
5685                 goto out_disable_device;
5686         }
5687 
5688         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5689         if (!adapter) {
5690                 err = -ENOMEM;
5691                 goto out_unmap_bar0;
5692         }
5693 
5694         adapter->regs = regs;
5695         err = t4_wait_dev_ready(regs);
5696         if (err < 0)
5697                 goto out_free_adapter;
5698 
5699         /* We control everything through one PF */
5700         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5701         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5702         chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5703         if ((int)chip < 0) {
5704                 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5705                 err = chip;
5706                 goto out_free_adapter;
5707         }
5708         chip_ver = CHELSIO_CHIP_VERSION(chip);
5709         func = chip_ver <= CHELSIO_T5 ?
5710                SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5711 
5712         adapter->pdev = pdev;
5713         adapter->pdev_dev = &pdev->dev;
5714         adapter->name = pci_name(pdev);
5715         adapter->mbox = func;
5716         adapter->pf = func;
5717         adapter->params.chip = chip;
5718         adapter->adap_idx = adap_idx;
5719         adapter->msg_enable = DFLT_MSG_ENABLE;
5720         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5721                                     (sizeof(struct mbox_cmd) *
5722                                      T4_OS_LOG_MBOX_CMDS),
5723                                     GFP_KERNEL);
5724         if (!adapter->mbox_log) {
5725                 err = -ENOMEM;
5726                 goto out_free_adapter;
5727         }
5728         spin_lock_init(&adapter->mbox_lock);
5729         INIT_LIST_HEAD(&adapter->mlist.list);
5730         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
5731         pci_set_drvdata(pdev, adapter);
5732 
5733         if (func != ent->driver_data) {
5734                 pci_disable_device(pdev);
5735                 pci_save_state(pdev);        /* to restore SR-IOV later */
5736                 return 0;
5737         }
5738 
5739         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5740                 highdma = true;
5741                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5742                 if (err) {
5743                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5744                                 "coherent allocations\n");
5745                         goto out_free_adapter;
5746                 }
5747         } else {
5748                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5749                 if (err) {
5750                         dev_err(&pdev->dev, "no usable DMA configuration\n");
5751                         goto out_free_adapter;
5752                 }
5753         }
5754 
5755         pci_enable_pcie_error_reporting(pdev);
5756         pci_set_master(pdev);
5757         pci_save_state(pdev);
5758         adap_idx++;
5759         adapter->workq = create_singlethread_workqueue("cxgb4");
5760         if (!adapter->workq) {
5761                 err = -ENOMEM;
5762                 goto out_free_adapter;
5763         }
5764 
5765         /* PCI device has been enabled */
5766         adapter->flags |= CXGB4_DEV_ENABLED;
5767         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5768 
5769         /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5770          * Ingress Packet Data to Free List Buffers in order to allow for
5771          * chipset performance optimizations between the Root Complex and
5772          * Memory Controllers.  (Messages to the associated Ingress Queue
5773          * notifying new Packet Placement in the Free Lists Buffers will be
5774          * send without the Relaxed Ordering Attribute thus guaranteeing that
5775          * all preceding PCIe Transaction Layer Packets will be processed
5776          * first.)  But some Root Complexes have various issues with Upstream
5777          * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5778          * The PCIe devices which under the Root Complexes will be cleared the
5779          * Relaxed Ordering bit in the configuration space, So we check our
5780          * PCIe configuration space to see if it's flagged with advice against
5781          * using Relaxed Ordering.
5782          */
5783         if (!pcie_relaxed_ordering_enabled(pdev))
5784                 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
5785 
5786         spin_lock_init(&adapter->stats_lock);
5787         spin_lock_init(&adapter->tid_release_lock);
5788         spin_lock_init(&adapter->win0_lock);
5789 
5790         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5791         INIT_WORK(&adapter->db_full_task, process_db_full);
5792         INIT_WORK(&adapter->db_drop_task, process_db_drop);
5793         INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
5794 
5795         err = t4_prep_adapter(adapter);
5796         if (err)
5797                 goto out_free_adapter;
5798 
5799         if (is_kdump_kernel()) {
5800                 /* Collect hardware state and append to /proc/vmcore */
5801                 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5802                 if (err) {
5803                         dev_warn(adapter->pdev_dev,
5804                                  "Fail collecting vmcore device dump, err: %d. Continuing\n",
5805                                  err);
5806                         err = 0;
5807                 }
5808         }
5809 
5810         if (!is_t4(adapter->params.chip)) {
5811                 s_qpp = (QUEUESPERPAGEPF0_S +
5812                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
5813                         adapter->pf);
5814                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5815                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
5816                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5817 
5818                 /* Each segment size is 128B. Write coalescing is enabled only
5819                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5820                  * queue is less no of segments that can be accommodated in
5821                  * a page size.
5822                  */
5823                 if (qpp > num_seg) {
5824                         dev_err(&pdev->dev,
5825                                 "Incorrect number of egress queues per page\n");
5826                         err = -EINVAL;
5827                         goto out_free_adapter;
5828                 }
5829                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5830                 pci_resource_len(pdev, 2));
5831                 if (!adapter->bar2) {
5832                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
5833                         err = -ENOMEM;
5834                         goto out_free_adapter;
5835                 }
5836         }
5837 
5838         setup_memwin(adapter);
5839         err = adap_init0(adapter);
5840 #ifdef CONFIG_DEBUG_FS
5841         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5842 #endif
5843         setup_memwin_rdma(adapter);
5844         if (err)
5845                 goto out_unmap_bar;
5846 
5847         /* configure SGE_STAT_CFG_A to read WC stats */
5848         if (!is_t4(adapter->params.chip))
5849                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5850                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5851                               T6_STATMODE_V(0)));
5852 
5853         /* Initialize hash mac addr list */
5854         INIT_LIST_HEAD(&adapter->mac_hlist);
5855 
5856         for_each_port(adapter, i) {
5857                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5858                                            MAX_ETH_QSETS);
5859                 if (!netdev) {
5860                         err = -ENOMEM;
5861                         goto out_free_dev;
5862                 }
5863 
5864                 SET_NETDEV_DEV(netdev, &pdev->dev);
5865 
5866                 adapter->port[i] = netdev;
5867                 pi = netdev_priv(netdev);
5868                 pi->adapter = adapter;
5869                 pi->xact_addr_filt = -1;
5870                 pi->port_id = i;
5871                 netdev->irq = pdev->irq;
5872 
5873                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5874                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5875                         NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
5876                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5877                         NETIF_F_HW_TC;
5878 
5879                 if (chip_ver > CHELSIO_T5) {
5880                         netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5881                                                    NETIF_F_IPV6_CSUM |
5882                                                    NETIF_F_RXCSUM |
5883                                                    NETIF_F_GSO_UDP_TUNNEL |
5884                                                    NETIF_F_GSO_UDP_TUNNEL_CSUM |
5885                                                    NETIF_F_TSO | NETIF_F_TSO6;
5886 
5887                         netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5888                                                NETIF_F_GSO_UDP_TUNNEL_CSUM |
5889                                                NETIF_F_HW_TLS_RECORD;
5890                 }
5891 
5892                 if (highdma)
5893                         netdev->hw_features |= NETIF_F_HIGHDMA;
5894                 netdev->features |= netdev->hw_features;
5895                 netdev->vlan_features = netdev->features & VLAN_FEAT;
5896 
5897                 netdev->priv_flags |= IFF_UNICAST_FLT;
5898 
5899                 /* MTU range: 81 - 9600 */
5900                 netdev->min_mtu = 81;              /* accommodate SACK */
5901                 netdev->max_mtu = MAX_MTU;
5902 
5903                 netdev->netdev_ops = &cxgb4_netdev_ops;
5904 #ifdef CONFIG_CHELSIO_T4_DCB
5905                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5906                 cxgb4_dcb_state_init(netdev);
5907                 cxgb4_dcb_version_init(netdev);
5908 #endif
5909                 cxgb4_set_ethtool_ops(netdev);
5910         }
5911 
5912         cxgb4_init_ethtool_dump(adapter);
5913 
5914         pci_set_drvdata(pdev, adapter);
5915 
5916         if (adapter->flags & CXGB4_FW_OK) {
5917                 err = t4_port_init(adapter, func, func, 0);
5918                 if (err)
5919                         goto out_free_dev;
5920         } else if (adapter->params.nports == 1) {
5921                 /* If we don't have a connection to the firmware -- possibly
5922                  * because of an error -- grab the raw VPD parameters so we
5923                  * can set the proper MAC Address on the debug network
5924                  * interface that we've created.
5925                  */
5926                 u8 hw_addr[ETH_ALEN];
5927                 u8 *na = adapter->params.vpd.na;
5928 
5929                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5930                 if (!err) {
5931                         for (i = 0; i < ETH_ALEN; i++)
5932                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5933                                               hex2val(na[2 * i + 1]));
5934                         t4_set_hw_addr(adapter, 0, hw_addr);
5935                 }
5936         }
5937 
5938         if (!(adapter->flags & CXGB4_FW_OK))
5939                 goto fw_attach_fail;
5940 
5941         /* Configure queues and allocate tables now, they can be needed as
5942          * soon as the first register_netdev completes.
5943          */
5944         err = cfg_queues(adapter);
5945         if (err)
5946                 goto out_free_dev;
5947 
5948         adapter->smt = t4_init_smt();
5949         if (!adapter->smt) {
5950                 /* We tolerate a lack of SMT, giving up some functionality */
5951                 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5952         }
5953 
5954         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5955         if (!adapter->l2t) {
5956                 /* We tolerate a lack of L2T, giving up some functionality */
5957                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5958                 adapter->params.offload = 0;
5959         }
5960 
5961 #if IS_ENABLED(CONFIG_IPV6)
5962         if (chip_ver <= CHELSIO_T5 &&
5963             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5964                 /* CLIP functionality is not present in hardware,
5965                  * hence disable all offload features
5966                  */
5967                 dev_warn(&pdev->dev,
5968                          "CLIP not enabled in hardware, continuing\n");
5969                 adapter->params.offload = 0;
5970         } else {
5971                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5972                                                   adapter->clipt_end);
5973                 if (!adapter->clipt) {
5974                         /* We tolerate a lack of clip_table, giving up
5975                          * some functionality
5976                          */
5977                         dev_warn(&pdev->dev,
5978                                  "could not allocate Clip table, continuing\n");
5979                         adapter->params.offload = 0;
5980                 }
5981         }
5982 #endif
5983 
5984         for_each_port(adapter, i) {
5985                 pi = adap2pinfo(adapter, i);
5986                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5987                 if (!pi->sched_tbl)
5988                         dev_warn(&pdev->dev,
5989                                  "could not activate scheduling on port %d\n",
5990                                  i);
5991         }
5992 
5993         if (tid_init(&adapter->tids) < 0) {
5994                 dev_warn(&pdev->dev, "could not allocate TID table, "
5995                          "continuing\n");
5996                 adapter->params.offload = 0;
5997         } else {
5998                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5999                 if (!adapter->tc_u32)
6000                         dev_warn(&pdev->dev,
6001                                  "could not offload tc u32, continuing\n");
6002 
6003                 if (cxgb4_init_tc_flower(adapter))
6004                         dev_warn(&pdev->dev,
6005                                  "could not offload tc flower, continuing\n");
6006         }
6007 
6008         if (is_offload(adapter) || is_hashfilter(adapter)) {
6009                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
6010                         u32 hash_base, hash_reg;
6011 
6012                         if (chip_ver <= CHELSIO_T5) {
6013                                 hash_reg = LE_DB_TID_HASHBASE_A;
6014                                 hash_base = t4_read_reg(adapter, hash_reg);
6015                                 adapter->tids.hash_base = hash_base / 4;
6016                         } else {
6017                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
6018                                 hash_base = t4_read_reg(adapter, hash_reg);
6019                                 adapter->tids.hash_base = hash_base;
6020                         }
6021                 }
6022         }
6023 
6024         /* See what interrupts we'll be using */
6025         if (msi > 1 && enable_msix(adapter) == 0)
6026                 adapter->flags |= CXGB4_USING_MSIX;
6027         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
6028                 adapter->flags |= CXGB4_USING_MSI;
6029                 if (msi > 1)
6030                         free_msix_info(adapter);
6031         }
6032 
6033         /* check for PCI Express bandwidth capabiltites */
6034         pcie_print_link_status(pdev);
6035 
6036         cxgb4_init_mps_ref_entries(adapter);
6037 
6038         err = init_rss(adapter);
6039         if (err)
6040                 goto out_free_dev;
6041 
6042         err = setup_fw_sge_queues(adapter);
6043         if (err) {
6044                 dev_err(adapter->pdev_dev,
6045                         "FW sge queue allocation failed, err %d", err);
6046                 goto out_free_dev;
6047         }
6048 
6049 fw_attach_fail:
6050         /*
6051          * The card is now ready to go.  If any errors occur during device
6052          * registration we do not fail the whole card but rather proceed only
6053          * with the ports we manage to register successfully.  However we must
6054          * register at least one net device.
6055          */
6056         for_each_port(adapter, i) {
6057                 pi = adap2pinfo(adapter, i);
6058                 adapter->port[i]->dev_port = pi->lport;
6059                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6060                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6061 
6062                 netif_carrier_off(adapter->port[i]);
6063 
6064                 err = register_netdev(adapter->port[i]);
6065                 if (err)
6066                         break;
6067                 adapter->chan_map[pi->tx_chan] = i;
6068                 print_port_info(adapter->port[i]);
6069         }
6070         if (i == 0) {
6071                 dev_err(&pdev->dev, "could not register any net devices\n");
6072                 goto out_free_dev;
6073         }
6074         if (err) {
6075                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6076                 err = 0;
6077         }
6078 
6079         if (cxgb4_debugfs_root) {
6080                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6081                                                            cxgb4_debugfs_root);
6082                 setup_debugfs(adapter);
6083         }
6084 
6085         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6086         pdev->needs_freset = 1;
6087 
6088         if (is_uld(adapter)) {
6089                 mutex_lock(&uld_mutex);
6090                 list_add_tail(&adapter->list_node, &adapter_list);
6091                 mutex_unlock(&uld_mutex);
6092         }
6093 
6094         if (!is_t4(adapter->params.chip))
6095                 cxgb4_ptp_init(adapter);
6096 
6097         if (IS_REACHABLE(CONFIG_THERMAL) &&
6098             !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
6099                 cxgb4_thermal_init(adapter);
6100 
6101         print_adapter_info(adapter);
6102         return 0;
6103 
6104  out_free_dev:
6105         t4_free_sge_resources(adapter);
6106         free_some_resources(adapter);
6107         if (adapter->flags & CXGB4_USING_MSIX)
6108                 free_msix_info(adapter);
6109         if (adapter->num_uld || adapter->num_ofld_uld)
6110                 t4_uld_mem_free(adapter);
6111  out_unmap_bar:
6112         if (!is_t4(adapter->params.chip))
6113                 iounmap(adapter->bar2);
6114  out_free_adapter:
6115         if (adapter->workq)
6116                 destroy_workqueue(adapter->workq);
6117 
6118         kfree(adapter->mbox_log);
6119         kfree(adapter);
6120  out_unmap_bar0:
6121         iounmap(regs);
6122  out_disable_device:
6123         pci_disable_pcie_error_reporting(pdev);
6124         pci_disable_device(pdev);
6125  out_release_regions:
6126         pci_release_regions(pdev);
6127         return err;
6128 }
6129 
6130 static void remove_one(struct pci_dev *pdev)
6131 {
6132         struct adapter *adapter = pci_get_drvdata(pdev);
6133         struct hash_mac_addr *entry, *tmp;
6134 
6135         if (!adapter) {
6136                 pci_release_regions(pdev);
6137                 return;
6138         }
6139 
6140         /* If we allocated filters, free up state associated with any
6141          * valid filters ...
6142          */
6143         clear_all_filters(adapter);
6144 
6145         adapter->flags |= CXGB4_SHUTTING_DOWN;
6146 
6147         if (adapter->pf == 4) {
6148                 int i;
6149 
6150                 /* Tear down per-adapter Work Queue first since it can contain
6151                  * references to our adapter data structure.
6152                  */
6153                 destroy_workqueue(adapter->workq);
6154 
6155                 if (is_uld(adapter)) {
6156                         detach_ulds(adapter);
6157                         t4_uld_clean_up(adapter);
6158                 }
6159 
6160                 adap_free_hma_mem(adapter);
6161 
6162                 disable_interrupts(adapter);
6163 
6164                 cxgb4_free_mps_ref_entries(adapter);
6165 
6166                 for_each_port(adapter, i)
6167                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6168                                 unregister_netdev(adapter->port[i]);
6169 
6170                 debugfs_remove_recursive(adapter->debugfs_root);
6171 
6172                 if (!is_t4(adapter->params.chip))
6173                         cxgb4_ptp_stop(adapter);
6174                 if (IS_REACHABLE(CONFIG_THERMAL))
6175                         cxgb4_thermal_remove(adapter);
6176 
6177                 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6178                         cxgb_down(adapter);
6179 
6180                 if (adapter->flags & CXGB4_USING_MSIX)
6181                         free_msix_info(adapter);
6182                 if (adapter->num_uld || adapter->num_ofld_uld)
6183                         t4_uld_mem_free(adapter);
6184                 free_some_resources(adapter);
6185                 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6186                                          list) {
6187                         list_del(&entry->list);
6188                         kfree(entry);
6189                 }
6190 
6191 #if IS_ENABLED(CONFIG_IPV6)
6192                 t4_cleanup_clip_tbl(adapter);
6193 #endif
6194                 if (!is_t4(adapter->params.chip))
6195                         iounmap(adapter->bar2);
6196         }
6197 #ifdef CONFIG_PCI_IOV
6198         else {
6199                 cxgb4_iov_configure(adapter->pdev, 0);
6200         }
6201 #endif
6202         iounmap(adapter->regs);
6203         pci_disable_pcie_error_reporting(pdev);
6204         if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6205                 pci_disable_device(pdev);
6206                 adapter->flags &= ~CXGB4_DEV_ENABLED;
6207         }
6208         pci_release_regions(pdev);
6209         kfree(adapter->mbox_log);
6210         synchronize_rcu();
6211         kfree(adapter);
6212 }
6213 
6214 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6215  * delivery.  This is essentially a stripped down version of the PCI remove()
6216  * function where we do the minimal amount of work necessary to shutdown any
6217  * further activity.
6218  */
6219 static void shutdown_one(struct pci_dev *pdev)
6220 {
6221         struct adapter *adapter = pci_get_drvdata(pdev);
6222 
6223         /* As with remove_one() above (see extended comment), we only want do
6224          * do cleanup on PCI Devices which went all the way through init_one()
6225          * ...
6226          */
6227         if (!adapter) {
6228                 pci_release_regions(pdev);
6229                 return;
6230         }
6231 
6232         adapter->flags |= CXGB4_SHUTTING_DOWN;
6233 
6234         if (adapter->pf == 4) {
6235                 int i;
6236 
6237                 for_each_port(adapter, i)
6238                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6239                                 cxgb_close(adapter->port[i]);
6240 
6241                 if (is_uld(adapter)) {
6242                         detach_ulds(adapter);
6243                         t4_uld_clean_up(adapter);
6244                 }
6245 
6246                 disable_interrupts(adapter);
6247                 disable_msi(adapter);
6248 
6249                 t4_sge_stop(adapter);
6250                 if (adapter->flags & CXGB4_FW_OK)
6251                         t4_fw_bye(adapter, adapter->mbox);
6252         }
6253 }
6254 
6255 static struct pci_driver cxgb4_driver = {
6256         .name     = KBUILD_MODNAME,
6257         .id_table = cxgb4_pci_tbl,
6258         .probe    = init_one,
6259         .remove   = remove_one,
6260         .shutdown = shutdown_one,
6261 #ifdef CONFIG_PCI_IOV
6262         .sriov_configure = cxgb4_iov_configure,
6263 #endif
6264         .err_handler = &cxgb4_eeh,
6265 };
6266 
6267 static int __init cxgb4_init_module(void)
6268 {
6269         int ret;
6270 
6271         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6272 
6273         ret = pci_register_driver(&cxgb4_driver);
6274         if (ret < 0)
6275                 goto err_pci;
6276 
6277 #if IS_ENABLED(CONFIG_IPV6)
6278         if (!inet6addr_registered) {
6279                 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6280                 if (ret)
6281                         pci_unregister_driver(&cxgb4_driver);
6282                 else
6283                         inet6addr_registered = true;
6284         }
6285 #endif
6286 
6287         if (ret == 0)
6288                 return ret;
6289 
6290 err_pci:
6291         debugfs_remove(cxgb4_debugfs_root);
6292 
6293         return ret;
6294 }
6295 
6296 static void __exit cxgb4_cleanup_module(void)
6297 {
6298 #if IS_ENABLED(CONFIG_IPV6)
6299         if (inet6addr_registered) {
6300                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6301                 inet6addr_registered = false;
6302         }
6303 #endif
6304         pci_unregister_driver(&cxgb4_driver);
6305         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6306 }
6307 
6308 module_init(cxgb4_init_module);
6309 module_exit(cxgb4_cleanup_module);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

DEFINITIONS
