1 /* Copyright © 2005 Agere Systems Inc.
2 * All rights reserved.
3 * http://www.agere.com
4 *
5 * SOFTWARE LICENSE
6 *
7 * This software is provided subject to the following terms and conditions,
8 * which you should read carefully before using the software. Using this
9 * software indicates your acceptance of these terms and conditions. If you do
10 * not agree with these terms and conditions, do not use the software.
11 *
12 * Copyright © 2005 Agere Systems Inc.
13 * All rights reserved.
14 *
15 * Redistribution and use in source or binary forms, with or without
16 * modifications, are permitted provided that the following conditions are met:
17 *
18 * . Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following Disclaimer as comments in the code as
20 * well as in the documentation and/or other materials provided with the
21 * distribution.
22 *
23 * . Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following Disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 *
27 * . Neither the name of Agere Systems Inc. nor the names of the contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * Disclaimer
32 *
33 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
34 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
35 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
36 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
37 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
38 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
43 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
44 * DAMAGE.
45 *
46 */
47
48 #define DRIVER_NAME "et131x"
49 #define DRIVER_VERSION "v2.0"
50
51 /* EEPROM registers */
52
53 /* LBCIF Register Groups (addressed via 32-bit offsets) */
54 #define LBCIF_DWORD0_GROUP 0xAC
55 #define LBCIF_DWORD1_GROUP 0xB0
56
57 /* LBCIF Registers (addressed via 8-bit offsets) */
58 #define LBCIF_ADDRESS_REGISTER 0xAC
59 #define LBCIF_DATA_REGISTER 0xB0
60 #define LBCIF_CONTROL_REGISTER 0xB1
61 #define LBCIF_STATUS_REGISTER 0xB2
62
63 /* LBCIF Control Register Bits */
64 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
65 #define LBCIF_CONTROL_PAGE_WRITE 0x02
66 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
67 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
68 #define LBCIF_CONTROL_I2C_WRITE 0x40
69 #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
70
71 /* LBCIF Status Register Bits */
72 #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
73 #define LBCIF_STATUS_I2C_IDLE 0x02
74 #define LBCIF_STATUS_ACK_ERROR 0x04
75 #define LBCIF_STATUS_GENERAL_ERROR 0x08
76 #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
77 #define LBCIF_STATUS_EEPROM_PRESENT 0x80
78
79 /* START OF GLOBAL REGISTER ADDRESS MAP */
80 /* 10bit registers
81 *
82 * Tx queue start address reg in global address map at address 0x0000
83 * tx queue end address reg in global address map at address 0x0004
84 * rx queue start address reg in global address map at address 0x0008
85 * rx queue end address reg in global address map at address 0x000C
86 */
87
88 /* structure for power management control status reg in global address map
89 * located at address 0x0010
90 * jagcore_rx_rdy bit 9
91 * jagcore_tx_rdy bit 8
92 * phy_lped_en bit 7
93 * phy_sw_coma bit 6
94 * rxclk_gate bit 5
95 * txclk_gate bit 4
96 * sysclk_gate bit 3
97 * jagcore_rx_en bit 2
98 * jagcore_tx_en bit 1
99 * gigephy_en bit 0
100 */
101 #define ET_PM_PHY_SW_COMA 0x40
102 #define ET_PMCSR_INIT 0x38
103
104 /* Interrupt status reg at address 0x0018
105 */
106 #define ET_INTR_TXDMA_ISR 0x00000008
107 #define ET_INTR_TXDMA_ERR 0x00000010
108 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
109 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
110 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
111 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
112 #define ET_INTR_RXDMA_ERR 0x00000200
113 #define ET_INTR_WATCHDOG 0x00004000
114 #define ET_INTR_WOL 0x00008000
115 #define ET_INTR_PHY 0x00010000
116 #define ET_INTR_TXMAC 0x00020000
117 #define ET_INTR_RXMAC 0x00040000
118 #define ET_INTR_MAC_STAT 0x00080000
119 #define ET_INTR_SLV_TIMEOUT 0x00100000
120
121 /* Interrupt mask register at address 0x001C
122 * Interrupt alias clear mask reg at address 0x0020
123 * Interrupt status alias reg at address 0x0024
124 *
125 * Same masks as above
126 */
127
128 /* Software reset reg at address 0x0028
129 * 0: txdma_sw_reset
130 * 1: rxdma_sw_reset
131 * 2: txmac_sw_reset
132 * 3: rxmac_sw_reset
133 * 4: mac_sw_reset
134 * 5: mac_stat_sw_reset
135 * 6: mmc_sw_reset
136 *31: selfclr_disable
137 */
138 #define ET_RESET_ALL 0x007F
139
140 /* SLV Timer reg at address 0x002C (low 24 bits)
141 */
142
143 /* MSI Configuration reg at address 0x0030
144 */
145 #define ET_MSI_VECTOR 0x0000001F
146 #define ET_MSI_TC 0x00070000
147
148 /* Loopback reg located at address 0x0034
149 */
150 #define ET_LOOP_MAC 0x00000001
151 #define ET_LOOP_DMA 0x00000002
152
153 /* GLOBAL Module of JAGCore Address Mapping
154 * Located at address 0x0000
155 */
156 struct global_regs { /* Location: */
157 u32 txq_start_addr; /* 0x0000 */
158 u32 txq_end_addr; /* 0x0004 */
159 u32 rxq_start_addr; /* 0x0008 */
160 u32 rxq_end_addr; /* 0x000C */
161 u32 pm_csr; /* 0x0010 */
162 u32 unused; /* 0x0014 */
163 u32 int_status; /* 0x0018 */
164 u32 int_mask; /* 0x001C */
165 u32 int_alias_clr_en; /* 0x0020 */
166 u32 int_status_alias; /* 0x0024 */
167 u32 sw_reset; /* 0x0028 */
168 u32 slv_timer; /* 0x002C */
169 u32 msi_config; /* 0x0030 */
170 u32 loopback; /* 0x0034 */
171 u32 watchdog_timer; /* 0x0038 */
172 };
173
174 /* START OF TXDMA REGISTER ADDRESS MAP */
175 /* txdma control status reg at address 0x1000
176 */
177 #define ET_TXDMA_CSR_HALT 0x00000001
178 #define ET_TXDMA_DROP_TLP 0x00000002
179 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_CACHE_SHIFT 4
181 #define ET_TXDMA_SNGL_EPKT 0x00000100
182 #define ET_TXDMA_CLASS 0x00001E00
183
184 /* structure for txdma packet ring base address hi reg in txdma address map
185 * located at address 0x1004
186 * Defined earlier (u32)
187 */
188
189 /* structure for txdma packet ring base address low reg in txdma address map
190 * located at address 0x1008
191 * Defined earlier (u32)
192 */
193
194 /* structure for txdma packet ring number of descriptor reg in txdma address
195 * map. Located at address 0x100C
196 *
197 * 31-10: unused
198 * 9-0: pr ndes
199 */
200 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
201 #define ET_DMA12_WRAP 0x1000
202 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
203 #define ET_DMA10_WRAP 0x0400
204 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
205 #define ET_DMA4_WRAP 0x0010
206
207 #define INDEX12(x) ((x) & ET_DMA12_MASK)
208 #define INDEX10(x) ((x) & ET_DMA10_MASK)
209 #define INDEX4(x) ((x) & ET_DMA4_MASK)
210
211 /* 10bit DMA with wrap
212 * txdma tx queue write address reg in txdma address map at 0x1010
213 * txdma tx queue write address external reg in txdma address map at 0x1014
214 * txdma tx queue read address reg in txdma address map at 0x1018
215 *
216 * u32
217 * txdma status writeback address hi reg in txdma address map at0x101C
218 * txdma status writeback address lo reg in txdma address map at 0x1020
219 *
220 * 10bit DMA with wrap
221 * txdma service request reg in txdma address map at 0x1024
222 * structure for txdma service complete reg in txdma address map at 0x1028
223 *
224 * 4bit DMA with wrap
225 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
226 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
227 *
228 * txdma error reg in txdma address map at address 0x1034
229 * 0: PyldResend
230 * 1: PyldRewind
231 * 4: DescrResend
232 * 5: DescrRewind
233 * 8: WrbkResend
234 * 9: WrbkRewind
235 */
236
237 /* Tx DMA Module of JAGCore Address Mapping
238 * Located at address 0x1000
239 */
240 struct txdma_regs { /* Location: */
241 u32 csr; /* 0x1000 */
242 u32 pr_base_hi; /* 0x1004 */
243 u32 pr_base_lo; /* 0x1008 */
244 u32 pr_num_des; /* 0x100C */
245 u32 txq_wr_addr; /* 0x1010 */
246 u32 txq_wr_addr_ext; /* 0x1014 */
247 u32 txq_rd_addr; /* 0x1018 */
248 u32 dma_wb_base_hi; /* 0x101C */
249 u32 dma_wb_base_lo; /* 0x1020 */
250 u32 service_request; /* 0x1024 */
251 u32 service_complete; /* 0x1028 */
252 u32 cache_rd_index; /* 0x102C */
253 u32 cache_wr_index; /* 0x1030 */
254 u32 tx_dma_error; /* 0x1034 */
255 u32 desc_abort_cnt; /* 0x1038 */
256 u32 payload_abort_cnt; /* 0x103c */
257 u32 writeback_abort_cnt; /* 0x1040 */
258 u32 desc_timeout_cnt; /* 0x1044 */
259 u32 payload_timeout_cnt; /* 0x1048 */
260 u32 writeback_timeout_cnt; /* 0x104c */
261 u32 desc_error_cnt; /* 0x1050 */
262 u32 payload_error_cnt; /* 0x1054 */
263 u32 writeback_error_cnt; /* 0x1058 */
264 u32 dropped_tlp_cnt; /* 0x105c */
265 u32 new_service_complete; /* 0x1060 */
266 u32 ethernet_packet_cnt; /* 0x1064 */
267 };
268
269 /* END OF TXDMA REGISTER ADDRESS MAP */
270
271 /* START OF RXDMA REGISTER ADDRESS MAP */
272 /* structure for control status reg in rxdma address map
273 * Located at address 0x2000
274 *
275 * CSR
276 * 0: halt
277 * 1-3: tc
278 * 4: fbr_big_endian
279 * 5: psr_big_endian
280 * 6: pkt_big_endian
281 * 7: dma_big_endian
282 * 8-9: fbr0_size
283 * 10: fbr0_enable
284 * 11-12: fbr1_size
285 * 13: fbr1_enable
286 * 14: unused
287 * 15: pkt_drop_disable
288 * 16: pkt_done_flush
289 * 17: halt_status
290 * 18-31: unused
291 */
292 #define ET_RXDMA_CSR_HALT 0x0001
293 #define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
294 #define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
295 #define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
296 #define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
297 #define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
298 #define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
299 #define ET_RXDMA_CSR_HALT_STATUS 0x00020000
300
301 /* structure for dma writeback lo reg in rxdma address map
302 * located at address 0x2004
303 * Defined earlier (u32)
304 */
305
306 /* structure for dma writeback hi reg in rxdma address map
307 * located at address 0x2008
308 * Defined earlier (u32)
309 */
310
311 /* structure for number of packets done reg in rxdma address map
312 * located at address 0x200C
313 *
314 * 31-8: unused
315 * 7-0: num done
316 */
317
318 /* structure for max packet time reg in rxdma address map
319 * located at address 0x2010
320 *
321 * 31-18: unused
322 * 17-0: time done
323 */
324
325 /* structure for rx queue read address reg in rxdma address map
326 * located at address 0x2014
327 * Defined earlier (u32)
328 */
329
330 /* structure for rx queue read address external reg in rxdma address map
331 * located at address 0x2018
332 * Defined earlier (u32)
333 */
334
335 /* structure for rx queue write address reg in rxdma address map
336 * located at address 0x201C
337 * Defined earlier (u32)
338 */
339
340 /* structure for packet status ring base address lo reg in rxdma address map
341 * located at address 0x2020
342 * Defined earlier (u32)
343 */
344
345 /* structure for packet status ring base address hi reg in rxdma address map
346 * located at address 0x2024
347 * Defined earlier (u32)
348 */
349
350 /* structure for packet status ring number of descriptors reg in rxdma address
351 * map. Located at address 0x2028
352 *
353 * 31-12: unused
354 * 11-0: psr ndes
355 */
356 #define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
357
358 /* structure for packet status ring available offset reg in rxdma address map
359 * located at address 0x202C
360 *
361 * 31-13: unused
362 * 12: psr avail wrap
363 * 11-0: psr avail
364 */
365
366 /* structure for packet status ring full offset reg in rxdma address map
367 * located at address 0x2030
368 *
369 * 31-13: unused
370 * 12: psr full wrap
371 * 11-0: psr full
372 */
373
374 /* structure for packet status ring access index reg in rxdma address map
375 * located at address 0x2034
376 *
377 * 31-5: unused
378 * 4-0: psr_ai
379 */
380
381 /* structure for packet status ring minimum descriptors reg in rxdma address
382 * map. Located at address 0x2038
383 *
384 * 31-12: unused
385 * 11-0: psr_min
386 */
387
388 /* structure for free buffer ring base lo address reg in rxdma address map
389 * located at address 0x203C
390 * Defined earlier (u32)
391 */
392
393 /* structure for free buffer ring base hi address reg in rxdma address map
394 * located at address 0x2040
395 * Defined earlier (u32)
396 */
397
398 /* structure for free buffer ring number of descriptors reg in rxdma address
399 * map. Located at address 0x2044
400 *
401 * 31-10: unused
402 * 9-0: fbr ndesc
403 */
404
405 /* structure for free buffer ring 0 available offset reg in rxdma address map
406 * located at address 0x2048
407 * Defined earlier (u32)
408 */
409
410 /* structure for free buffer ring 0 full offset reg in rxdma address map
411 * located at address 0x204C
412 * Defined earlier (u32)
413 */
414
415 /* structure for free buffer cache 0 full offset reg in rxdma address map
416 * located at address 0x2050
417 *
418 * 31-5: unused
419 * 4-0: fbc rdi
420 */
421
422 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
423 * located at address 0x2054
424 *
425 * 31-10: unused
426 * 9-0: fbr min
427 */
428
429 /* structure for free buffer ring 1 base address lo reg in rxdma address map
430 * located at address 0x2058 - 0x205C
431 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
432 */
433
434 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
435 * map. Located at address 0x2060
436 * Defined earlier (RXDMA_FBR_NUM_DES_t)
437 */
438
439 /* structure for free buffer ring 1 available offset reg in rxdma address map
440 * located at address 0x2064
441 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
442 */
443
444 /* structure for free buffer ring 1 full offset reg in rxdma address map
445 * located at address 0x2068
446 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
447 */
448
449 /* structure for free buffer cache 1 read index reg in rxdma address map
450 * located at address 0x206C
451 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
452 */
453
454 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
455 * located at address 0x2070
456 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
457 */
458
459 /* Rx DMA Module of JAGCore Address Mapping
460 * Located at address 0x2000
461 */
462 struct rxdma_regs { /* Location: */
463 u32 csr; /* 0x2000 */
464 u32 dma_wb_base_lo; /* 0x2004 */
465 u32 dma_wb_base_hi; /* 0x2008 */
466 u32 num_pkt_done; /* 0x200C */
467 u32 max_pkt_time; /* 0x2010 */
468 u32 rxq_rd_addr; /* 0x2014 */
469 u32 rxq_rd_addr_ext; /* 0x2018 */
470 u32 rxq_wr_addr; /* 0x201C */
471 u32 psr_base_lo; /* 0x2020 */
472 u32 psr_base_hi; /* 0x2024 */
473 u32 psr_num_des; /* 0x2028 */
474 u32 psr_avail_offset; /* 0x202C */
475 u32 psr_full_offset; /* 0x2030 */
476 u32 psr_access_index; /* 0x2034 */
477 u32 psr_min_des; /* 0x2038 */
478 u32 fbr0_base_lo; /* 0x203C */
479 u32 fbr0_base_hi; /* 0x2040 */
480 u32 fbr0_num_des; /* 0x2044 */
481 u32 fbr0_avail_offset; /* 0x2048 */
482 u32 fbr0_full_offset; /* 0x204C */
483 u32 fbr0_rd_index; /* 0x2050 */
484 u32 fbr0_min_des; /* 0x2054 */
485 u32 fbr1_base_lo; /* 0x2058 */
486 u32 fbr1_base_hi; /* 0x205C */
487 u32 fbr1_num_des; /* 0x2060 */
488 u32 fbr1_avail_offset; /* 0x2064 */
489 u32 fbr1_full_offset; /* 0x2068 */
490 u32 fbr1_rd_index; /* 0x206C */
491 u32 fbr1_min_des; /* 0x2070 */
492 };
493
494 /* END OF RXDMA REGISTER ADDRESS MAP */
495
496 /* START OF TXMAC REGISTER ADDRESS MAP */
497 /* structure for control reg in txmac address map
498 * located at address 0x3000
499 *
500 * bits
501 * 31-8: unused
502 * 7: cklseg_disable
503 * 6: ckbcnt_disable
504 * 5: cksegnum
505 * 4: async_disable
506 * 3: fc_disable
507 * 2: mcif_disable
508 * 1: mif_disable
509 * 0: txmac_en
510 */
511 #define ET_TX_CTRL_FC_DISABLE 0x0008
512 #define ET_TX_CTRL_TXMAC_ENABLE 0x0001
513
514 /* structure for shadow pointer reg in txmac address map
515 * located at address 0x3004
516 * 31-27: reserved
517 * 26-16: txq rd ptr
518 * 15-11: reserved
519 * 10-0: txq wr ptr
520 */
521
522 /* structure for error count reg in txmac address map
523 * located at address 0x3008
524 *
525 * 31-12: unused
526 * 11-8: reserved
527 * 7-4: txq_underrun
528 * 3-0: fifo_underrun
529 */
530
531 /* structure for max fill reg in txmac address map
532 * located at address 0x300C
533 * 31-12: unused
534 * 11-0: max fill
535 */
536
537 /* structure for cf parameter reg in txmac address map
538 * located at address 0x3010
539 * 31-16: cfep
540 * 15-0: cfpt
541 */
542
543 /* structure for tx test reg in txmac address map
544 * located at address 0x3014
545 * 31-17: unused
546 * 16: reserved
547 * 15: txtest_en
548 * 14-11: unused
549 * 10-0: txq test pointer
550 */
551
552 /* structure for error reg in txmac address map
553 * located at address 0x3018
554 *
555 * 31-9: unused
556 * 8: fifo_underrun
557 * 7-6: unused
558 * 5: ctrl2_err
559 * 4: txq_underrun
560 * 3: bcnt_err
561 * 2: lseg_err
562 * 1: segnum_err
563 * 0: seg0_err
564 */
565
566 /* structure for error interrupt reg in txmac address map
567 * located at address 0x301C
568 *
569 * 31-9: unused
570 * 8: fifo_underrun
571 * 7-6: unused
572 * 5: ctrl2_err
573 * 4: txq_underrun
574 * 3: bcnt_err
575 * 2: lseg_err
576 * 1: segnum_err
577 * 0: seg0_err
578 */
579
580 /* structure for error interrupt reg in txmac address map
581 * located at address 0x3020
582 *
583 * 31-2: unused
584 * 1: bp_req
585 * 0: bp_xonxoff
586 */
587
588 /* Tx MAC Module of JAGCore Address Mapping
589 */
590 struct txmac_regs { /* Location: */
591 u32 ctl; /* 0x3000 */
592 u32 shadow_ptr; /* 0x3004 */
593 u32 err_cnt; /* 0x3008 */
594 u32 max_fill; /* 0x300C */
595 u32 cf_param; /* 0x3010 */
596 u32 tx_test; /* 0x3014 */
597 u32 err; /* 0x3018 */
598 u32 err_int; /* 0x301C */
599 u32 bp_ctrl; /* 0x3020 */
600 };
601
602 /* END OF TXMAC REGISTER ADDRESS MAP */
603
604 /* START OF RXMAC REGISTER ADDRESS MAP */
605
606 /* structure for rxmac control reg in rxmac address map
607 * located at address 0x4000
608 *
609 * 31-7: reserved
610 * 6: rxmac_int_disable
611 * 5: async_disable
612 * 4: mif_disable
613 * 3: wol_disable
614 * 2: pkt_filter_disable
615 * 1: mcif_disable
616 * 0: rxmac_en
617 */
618 #define ET_RX_CTRL_WOL_DISABLE 0x0008
619 #define ET_RX_CTRL_RXMAC_ENABLE 0x0001
620
621 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
622 * located at address 0x4004
623 * 31-16: crc
624 * 15-12: reserved
625 * 11: ignore_pp
626 * 10: ignore_mp
627 * 9: clr_intr
628 * 8: ignore_link_chg
629 * 7: ignore_uni
630 * 6: ignore_multi
631 * 5: ignore_broad
632 * 4-0: valid_crc 4-0
633 */
634
635 /* structure for CRC 1 and CRC 2 reg in rxmac address map
636 * located at address 0x4008
637 *
638 * 31-16: crc2
639 * 15-0: crc1
640 */
641
642 /* structure for CRC 3 and CRC 4 reg in rxmac address map
643 * located at address 0x400C
644 *
645 * 31-16: crc4
646 * 15-0: crc3
647 */
648
649 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
650 * located at address 0x4010
651 *
652 * 31-24: sa3
653 * 23-16: sa4
654 * 15-8: sa5
655 * 7-0: sa6
656 */
657 #define ET_RX_WOL_LO_SA3_SHIFT 24
658 #define ET_RX_WOL_LO_SA4_SHIFT 16
659 #define ET_RX_WOL_LO_SA5_SHIFT 8
660
661 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
662 * located at address 0x4014
663 *
664 * 31-16: reserved
665 * 15-8: sa1
666 * 7-0: sa2
667 */
668 #define ET_RX_WOL_HI_SA1_SHIFT 8
669
670 /* structure for Wake On Lan mask reg in rxmac address map
671 * located at address 0x4018 - 0x4064
672 * Defined earlier (u32)
673 */
674
675 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
676 * located at address 0x4068
677 *
678 * 31-24: addr1_3
679 * 23-16: addr1_4
680 * 15-8: addr1_5
681 * 7-0: addr1_6
682 */
683 #define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
684 #define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
685 #define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
686
687 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
688 * located at address 0x406C
689 *
690 * 31-24: addr2_3
691 * 23-16: addr2_4
692 * 15-8: addr2_5
693 * 7-0: addr2_6
694 */
695 #define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
696 #define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
697 #define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
698
699 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
700 * located at address 0x4070
701 *
702 * 31-24: addr2_1
703 * 23-16: addr2_2
704 * 15-8: addr1_1
705 * 7-0: addr1_2
706 */
707 #define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
708 #define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
709 #define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
710
711 /* structure for Multicast Hash reg in rxmac address map
712 * located at address 0x4074 - 0x4080
713 * Defined earlier (u32)
714 */
715
716 /* structure for Packet Filter Control reg in rxmac address map
717 * located at address 0x4084
718 *
719 * 31-23: unused
720 * 22-16: min_pkt_size
721 * 15-4: unused
722 * 3: filter_frag_en
723 * 2: filter_uni_en
724 * 1: filter_multi_en
725 * 0: filter_broad_en
726 */
727 #define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16
728 #define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
729 #define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
730 #define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002
731 #define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001
732
733 /* structure for Memory Controller Interface Control Max Segment reg in rxmac
734 * address map. Located at address 0x4088
735 *
736 * 31-10: reserved
737 * 9-2: max_size
738 * 1: fc_en
739 * 0: seg_en
740 */
741 #define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2
742 #define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
743 #define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
744
745 /* structure for Memory Controller Interface Water Mark reg in rxmac address
746 * map. Located at address 0x408C
747 *
748 * 31-26: unused
749 * 25-16: mark_hi
750 * 15-10: unused
751 * 9-0: mark_lo
752 */
753
754 /* structure for Rx Queue Dialog reg in rxmac address map.
755 * located at address 0x4090
756 *
757 * 31-26: reserved
758 * 25-16: rd_ptr
759 * 15-10: reserved
760 * 9-0: wr_ptr
761 */
762
763 /* structure for space available reg in rxmac address map.
764 * located at address 0x4094
765 *
766 * 31-17: reserved
767 * 16: space_avail_en
768 * 15-10: reserved
769 * 9-0: space_avail
770 */
771
772 /* structure for management interface reg in rxmac address map.
773 * located at address 0x4098
774 *
775 * 31-18: reserved
776 * 17: drop_pkt_en
777 * 16-0: drop_pkt_mask
778 */
779
780 /* structure for Error reg in rxmac address map.
781 * located at address 0x409C
782 *
783 * 31-4: unused
784 * 3: mif
785 * 2: async
786 * 1: pkt_filter
787 * 0: mcif
788 */
789
790 /* Rx MAC Module of JAGCore Address Mapping
791 */
792 struct rxmac_regs { /* Location: */
793 u32 ctrl; /* 0x4000 */
794 u32 crc0; /* 0x4004 */
795 u32 crc12; /* 0x4008 */
796 u32 crc34; /* 0x400C */
797 u32 sa_lo; /* 0x4010 */
798 u32 sa_hi; /* 0x4014 */
799 u32 mask0_word0; /* 0x4018 */
800 u32 mask0_word1; /* 0x401C */
801 u32 mask0_word2; /* 0x4020 */
802 u32 mask0_word3; /* 0x4024 */
803 u32 mask1_word0; /* 0x4028 */
804 u32 mask1_word1; /* 0x402C */
805 u32 mask1_word2; /* 0x4030 */
806 u32 mask1_word3; /* 0x4034 */
807 u32 mask2_word0; /* 0x4038 */
808 u32 mask2_word1; /* 0x403C */
809 u32 mask2_word2; /* 0x4040 */
810 u32 mask2_word3; /* 0x4044 */
811 u32 mask3_word0; /* 0x4048 */
812 u32 mask3_word1; /* 0x404C */
813 u32 mask3_word2; /* 0x4050 */
814 u32 mask3_word3; /* 0x4054 */
815 u32 mask4_word0; /* 0x4058 */
816 u32 mask4_word1; /* 0x405C */
817 u32 mask4_word2; /* 0x4060 */
818 u32 mask4_word3; /* 0x4064 */
819 u32 uni_pf_addr1; /* 0x4068 */
820 u32 uni_pf_addr2; /* 0x406C */
821 u32 uni_pf_addr3; /* 0x4070 */
822 u32 multi_hash1; /* 0x4074 */
823 u32 multi_hash2; /* 0x4078 */
824 u32 multi_hash3; /* 0x407C */
825 u32 multi_hash4; /* 0x4080 */
826 u32 pf_ctrl; /* 0x4084 */
827 u32 mcif_ctrl_max_seg; /* 0x4088 */
828 u32 mcif_water_mark; /* 0x408C */
829 u32 rxq_diag; /* 0x4090 */
830 u32 space_avail; /* 0x4094 */
831
832 u32 mif_ctrl; /* 0x4098 */
833 u32 err_reg; /* 0x409C */
834 };
835
836 /* END OF RXMAC REGISTER ADDRESS MAP */
837
838 /* START OF MAC REGISTER ADDRESS MAP */
839 /* structure for configuration #1 reg in mac address map.
840 * located at address 0x5000
841 *
842 * 31: soft reset
843 * 30: sim reset
844 * 29-20: reserved
845 * 19: reset rx mc
846 * 18: reset tx mc
847 * 17: reset rx func
848 * 16: reset tx fnc
849 * 15-9: reserved
850 * 8: loopback
851 * 7-6: reserved
852 * 5: rx flow
853 * 4: tx flow
854 * 3: syncd rx en
855 * 2: rx enable
856 * 1: syncd tx en
857 * 0: tx enable
858 */
859 #define ET_MAC_CFG1_SOFT_RESET 0x80000000
860 #define ET_MAC_CFG1_SIM_RESET 0x40000000
861 #define ET_MAC_CFG1_RESET_RXMC 0x00080000
862 #define ET_MAC_CFG1_RESET_TXMC 0x00040000
863 #define ET_MAC_CFG1_RESET_RXFUNC 0x00020000
864 #define ET_MAC_CFG1_RESET_TXFUNC 0x00010000
865 #define ET_MAC_CFG1_LOOPBACK 0x00000100
866 #define ET_MAC_CFG1_RX_FLOW 0x00000020
867 #define ET_MAC_CFG1_TX_FLOW 0x00000010
868 #define ET_MAC_CFG1_RX_ENABLE 0x00000004
869 #define ET_MAC_CFG1_TX_ENABLE 0x00000001
870 #define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */
871
872 /* structure for configuration #2 reg in mac address map.
873 * located at address 0x5004
874 * 31-16: reserved
875 * 15-12: preamble
876 * 11-10: reserved
877 * 9-8: if mode
878 * 7-6: reserved
879 * 5: huge frame
880 * 4: length check
881 * 3: undefined
882 * 2: pad crc
883 * 1: crc enable
884 * 0: full duplex
885 */
886 #define ET_MAC_CFG2_PREAMBLE_SHIFT 12
887 #define ET_MAC_CFG2_IFMODE_MASK 0x0300
888 #define ET_MAC_CFG2_IFMODE_1000 0x0200
889 #define ET_MAC_CFG2_IFMODE_100 0x0100
890 #define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020
891 #define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010
892 #define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004
893 #define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002
894 #define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001
895
896 /* structure for Interpacket gap reg in mac address map.
897 * located at address 0x5008
898 *
899 * 31: reserved
900 * 30-24: non B2B ipg 1
901 * 23: undefined
902 * 22-16: non B2B ipg 2
903 * 15-8: Min ifg enforce
904 * 7-0: B2B ipg
905 *
906 * structure for half duplex reg in mac address map.
907 * located at address 0x500C
908 * 31-24: reserved
909 * 23-20: Alt BEB trunc
910 * 19: Alt BEB enable
911 * 18: BP no backoff
912 * 17: no backoff
913 * 16: excess defer
914 * 15-12: re-xmit max
915 * 11-10: reserved
916 * 9-0: collision window
917 */
918
919 /* structure for Maximum Frame Length reg in mac address map.
920 * located at address 0x5010: bits 0-15 hold the length.
921 */
922
923 /* structure for Reserve 1 reg in mac address map.
924 * located at address 0x5014 - 0x5018
925 * Defined earlier (u32)
926 */
927
928 /* structure for Test reg in mac address map.
929 * located at address 0x501C
930 * test: bits 0-2, rest unused
931 */
932
933 /* structure for MII Management Configuration reg in mac address map.
934 * located at address 0x5020
935 *
936 * 31: reset MII mgmt
937 * 30-6: unused
938 * 5: scan auto increment
939 * 4: preamble suppress
940 * 3: undefined
941 * 2-0: mgmt clock reset
942 */
943 #define ET_MAC_MIIMGMT_CLK_RST 0x0007
944
945 /* structure for MII Management Command reg in mac address map.
946 * located at address 0x5024
947 * bit 1: scan cycle
948 * bit 0: read cycle
949 */
950
951 /* structure for MII Management Address reg in mac address map.
952 * located at address 0x5028
953 * 31-13: reserved
954 * 12-8: phy addr
955 * 7-5: reserved
956 * 4-0: register
957 */
958 #define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg))
959
960 /* structure for MII Management Control reg in mac address map.
961 * located at address 0x502C
962 * 31-16: reserved
963 * 15-0: phy control
964 */
965
966 /* structure for MII Management Status reg in mac address map.
967 * located at address 0x5030
968 * 31-16: reserved
969 * 15-0: phy control
970 */
971 #define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
972
973 /* structure for MII Management Indicators reg in mac address map.
974 * located at address 0x5034
975 * 31-3: reserved
976 * 2: not valid
977 * 1: scanning
978 * 0: busy
979 */
980 #define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
981 #define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
982
983 /* structure for Interface Control reg in mac address map.
984 * located at address 0x5038
985 *
986 * 31: reset if module
987 * 30-28: reserved
988 * 27: tbi mode
989 * 26: ghd mode
990 * 25: lhd mode
991 * 24: phy mode
992 * 23: reset per mii
993 * 22-17: reserved
994 * 16: speed
995 * 15: reset pe100x
996 * 14-11: reserved
997 * 10: force quiet
998 * 9: no cipher
999 * 8: disable link fail
1000 * 7: reset gpsi
1001 * 6-1: reserved
1002 * 0: enable jabber protection
1003 */
1004 #define ET_MAC_IFCTRL_GHDMODE (1 << 26)
1005 #define ET_MAC_IFCTRL_PHYMODE (1 << 24)
1006
1007 /* structure for Interface Status reg in mac address map.
1008 * located at address 0x503C
1009 *
1010 * 31-10: reserved
1011 * 9: excess_defer
1012 * 8: clash
1013 * 7: phy_jabber
1014 * 6: phy_link_ok
1015 * 5: phy_full_duplex
1016 * 4: phy_speed
1017 * 3: pe100x_link_fail
1018 * 2: pe10t_loss_carrier
1019 * 1: pe10t_sqe_error
1020 * 0: pe10t_jabber
1021 */
1022
1023 /* structure for Mac Station Address, Part 1 reg in mac address map.
1024 * located at address 0x5040
1025 *
1026 * 31-24: Octet6
1027 * 23-16: Octet5
1028 * 15-8: Octet4
1029 * 7-0: Octet3
1030 */
1031 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1032 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1033 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1034
1035 /* structure for Mac Station Address, Part 2 reg in mac address map.
1036 * located at address 0x5044
1037 *
1038 * 31-24: Octet2
1039 * 23-16: Octet1
1040 * 15-0: reserved
1041 */
1042 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1043 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1044
1045 /* MAC Module of JAGCore Address Mapping
1046 */
1047 struct mac_regs { /* Location: */
1048 u32 cfg1; /* 0x5000 */
1049 u32 cfg2; /* 0x5004 */
1050 u32 ipg; /* 0x5008 */
1051 u32 hfdp; /* 0x500C */
1052 u32 max_fm_len; /* 0x5010 */
1053 u32 rsv1; /* 0x5014 */
1054 u32 rsv2; /* 0x5018 */
1055 u32 mac_test; /* 0x501C */
1056 u32 mii_mgmt_cfg; /* 0x5020 */
1057 u32 mii_mgmt_cmd; /* 0x5024 */
1058 u32 mii_mgmt_addr; /* 0x5028 */
1059 u32 mii_mgmt_ctrl; /* 0x502C */
1060 u32 mii_mgmt_stat; /* 0x5030 */
1061 u32 mii_mgmt_indicator; /* 0x5034 */
1062 u32 if_ctrl; /* 0x5038 */
1063 u32 if_stat; /* 0x503C */
1064 u32 station_addr_1; /* 0x5040 */
1065 u32 station_addr_2; /* 0x5044 */
1066 };
1067
1068 /* END OF MAC REGISTER ADDRESS MAP */
1069
1070 /* START OF MAC STAT REGISTER ADDRESS MAP */
1071 /* structure for Carry Register One and it's Mask Register reg located in mac
1072 * stat address map address 0x6130 and 0x6138.
1073 *
1074 * 31: tr64
1075 * 30: tr127
1076 * 29: tr255
1077 * 28: tr511
1078 * 27: tr1k
1079 * 26: trmax
1080 * 25: trmgv
1081 * 24-17: unused
1082 * 16: rbyt
1083 * 15: rpkt
1084 * 14: rfcs
1085 * 13: rmca
1086 * 12: rbca
1087 * 11: rxcf
1088 * 10: rxpf
1089 * 9: rxuo
1090 * 8: raln
1091 * 7: rflr
1092 * 6: rcde
1093 * 5: rcse
1094 * 4: rund
1095 * 3: rovr
1096 * 2: rfrg
1097 * 1: rjbr
1098 * 0: rdrp
1099 */
1100
1101 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1102 * located at address 0x613C
1103 *
1104 * 31-20: unused
1105 * 19: tjbr
1106 * 18: tfcs
1107 * 17: txcf
1108 * 16: tovr
1109 * 15: tund
1110 * 14: trfg
1111 * 13: tbyt
1112 * 12: tpkt
1113 * 11: tmca
1114 * 10: tbca
1115 * 9: txpf
1116 * 8: tdfr
1117 * 7: tedf
1118 * 6: tscl
1119 * 5: tmcl
1120 * 4: tlcl
1121 * 3: txcl
1122 * 2: tncl
1123 * 1: tpfh
1124 * 0: tdrp
1125 */
1126
1127 /* MAC STATS Module of JAGCore Address Mapping
1128 */
1129 struct macstat_regs { /* Location: */
1130 u32 pad[32]; /* 0x6000 - 607C */
1131
1132 /* counters */
1133 u32 txrx_0_64_byte_frames; /* 0x6080 */
1134 u32 txrx_65_127_byte_frames; /* 0x6084 */
1135 u32 txrx_128_255_byte_frames; /* 0x6088 */
1136 u32 txrx_256_511_byte_frames; /* 0x608C */
1137 u32 txrx_512_1023_byte_frames; /* 0x6090 */
1138 u32 txrx_1024_1518_byte_frames; /* 0x6094 */
1139 u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
1140 u32 rx_bytes; /* 0x609C */
1141 u32 rx_packets; /* 0x60A0 */
1142 u32 rx_fcs_errs; /* 0x60A4 */
1143 u32 rx_multicast_packets; /* 0x60A8 */
1144 u32 rx_broadcast_packets; /* 0x60AC */
1145 u32 rx_control_frames; /* 0x60B0 */
1146 u32 rx_pause_frames; /* 0x60B4 */
1147 u32 rx_unknown_opcodes; /* 0x60B8 */
1148 u32 rx_align_errs; /* 0x60BC */
1149 u32 rx_frame_len_errs; /* 0x60C0 */
1150 u32 rx_code_errs; /* 0x60C4 */
1151 u32 rx_carrier_sense_errs; /* 0x60C8 */
1152 u32 rx_undersize_packets; /* 0x60CC */
1153 u32 rx_oversize_packets; /* 0x60D0 */
1154 u32 rx_fragment_packets; /* 0x60D4 */
1155 u32 rx_jabbers; /* 0x60D8 */
1156 u32 rx_drops; /* 0x60DC */
1157 u32 tx_bytes; /* 0x60E0 */
1158 u32 tx_packets; /* 0x60E4 */
1159 u32 tx_multicast_packets; /* 0x60E8 */
1160 u32 tx_broadcast_packets; /* 0x60EC */
1161 u32 tx_pause_frames; /* 0x60F0 */
1162 u32 tx_deferred; /* 0x60F4 */
1163 u32 tx_excessive_deferred; /* 0x60F8 */
1164 u32 tx_single_collisions; /* 0x60FC */
1165 u32 tx_multiple_collisions; /* 0x6100 */
1166 u32 tx_late_collisions; /* 0x6104 */
1167 u32 tx_excessive_collisions; /* 0x6108 */
1168 u32 tx_total_collisions; /* 0x610C */
1169 u32 tx_pause_honored_frames; /* 0x6110 */
1170 u32 tx_drops; /* 0x6114 */
1171 u32 tx_jabbers; /* 0x6118 */
1172 u32 tx_fcs_errs; /* 0x611C */
1173 u32 tx_control_frames; /* 0x6120 */
1174 u32 tx_oversize_frames; /* 0x6124 */
1175 u32 tx_undersize_frames; /* 0x6128 */
1176 u32 tx_fragments; /* 0x612C */
1177 u32 carry_reg1; /* 0x6130 */
1178 u32 carry_reg2; /* 0x6134 */
1179 u32 carry_reg1_mask; /* 0x6138 */
1180 u32 carry_reg2_mask; /* 0x613C */
1181 };
1182
1183 /* END OF MAC STAT REGISTER ADDRESS MAP */
1184
1185 /* START OF MMC REGISTER ADDRESS MAP */
1186 /* Main Memory Controller Control reg in mmc address map.
1187 * located at address 0x7000
1188 */
1189 #define ET_MMC_ENABLE 1
1190 #define ET_MMC_ARB_DISABLE 2
1191 #define ET_MMC_RXMAC_DISABLE 4
1192 #define ET_MMC_TXMAC_DISABLE 8
1193 #define ET_MMC_TXDMA_DISABLE 16
1194 #define ET_MMC_RXDMA_DISABLE 32
1195 #define ET_MMC_FORCE_CE 64
1196
1197 /* Main Memory Controller Host Memory Access Address reg in mmc
1198 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1199 */
1200 #define ET_SRAM_REQ_ACCESS 1
1201 #define ET_SRAM_WR_ACCESS 2
1202 #define ET_SRAM_IS_CTRL 4
1203
1204 /* structure for Main Memory Controller Host Memory Access Data reg in mmc
1205 * address map. Located at address 0x7008 - 0x7014
1206 * Defined earlier (u32)
1207 */
1208
1209 /* Memory Control Module of JAGCore Address Mapping
1210 */
1211 struct mmc_regs { /* Location: */
1212 u32 mmc_ctrl; /* 0x7000 */
1213 u32 sram_access; /* 0x7004 */
1214 u32 sram_word1; /* 0x7008 */
1215 u32 sram_word2; /* 0x700C */
1216 u32 sram_word3; /* 0x7010 */
1217 u32 sram_word4; /* 0x7014 */
1218 };
1219
1220 /* END OF MMC REGISTER ADDRESS MAP */
1221
1222 /* JAGCore Address Mapping
1223 */
1224 struct address_map {
1225 struct global_regs global;
1226 /* unused section of global address map */
1227 u8 unused_global[4096 - sizeof(struct global_regs)];
1228 struct txdma_regs txdma;
1229 /* unused section of txdma address map */
1230 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1231 struct rxdma_regs rxdma;
1232 /* unused section of rxdma address map */
1233 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1234 struct txmac_regs txmac;
1235 /* unused section of txmac address map */
1236 u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1237 struct rxmac_regs rxmac;
1238 /* unused section of rxmac address map */
1239 u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1240 struct mac_regs mac;
1241 /* unused section of mac address map */
1242 u8 unused_mac[4096 - sizeof(struct mac_regs)];
1243 struct macstat_regs macstat;
1244 /* unused section of mac stat address map */
1245 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1246 struct mmc_regs mmc;
1247 /* unused section of mmc address map */
1248 u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1249 /* unused section of address map */
1250 u8 unused_[1015808];
1251 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1252 u8 unused__[524288]; /* unused section of address map */
1253 };
1254
1255 /* Defines for generic MII registers 0x00 -> 0x0F can be found in
1256 * include/linux/mii.h
1257 */
1258 /* some defines for modem registers that seem to be 'reserved' */
1259 #define PHY_INDEX_REG 0x10
1260 #define PHY_DATA_REG 0x11
1261 #define PHY_MPHY_CONTROL_REG 0x12
1262
1263 /* defines for specified registers */
1264 #define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1265 /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
1266 #define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
1267 #define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
1268 #define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
1269 #define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
1270 #define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
1271 #define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
1272 #define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
1273 #define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
1274 /* TRU_VMI_LINK_CONTROL_REG 29 */
1275 /* TRU_VMI_TIMING_CONTROL_REG */
1276
1277 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1278 #define ET_1000BT_MSTR_SLV 0x4000
1279
1280 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1281
1282 /* MI Register 19: Loopback Control Reg(0x13)
1283 * 15: mii_en
1284 * 14: pcs_en
1285 * 13: pmd_en
1286 * 12: all_digital_en
1287 * 11: replica_en
1288 * 10: line_driver_en
1289 * 9-0: reserved
1290 */
1291
1292 /* MI Register 20: Reserved Reg(0x14) */
1293
1294 /* MI Register 21: Management Interface Control Reg(0x15)
1295 * 15-11: reserved
1296 * 10-4: mi_error_count
1297 * 3: reserved
1298 * 2: ignore_10g_fr
1299 * 1: reserved
1300 * 0: preamble_suppress_en
1301 */
1302
1303 /* MI Register 22: PHY Configuration Reg(0x16)
1304 * 15: crs_tx_en
1305 * 14: reserved
1306 * 13-12: tx_fifo_depth
1307 * 11-10: speed_downshift
1308 * 9: pbi_detect
1309 * 8: tbi_rate
1310 * 7: alternate_np
1311 * 6: group_mdio_en
1312 * 5: tx_clock_en
1313 * 4: sys_clock_en
1314 * 3: reserved
1315 * 2-0: mac_if_mode
1316 */
1317 #define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
1318
1319 #define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
1320 #define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
1321 #define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
1322 #define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
1323
1324 /* MI Register 23: PHY CONTROL Reg(0x17)
1325 * 15: reserved
1326 * 14: tdr_en
1327 * 13: reserved
1328 * 12-11: downshift_attempts
1329 * 10-6: reserved
1330 * 5: jabber_10baseT
1331 * 4: sqe_10baseT
1332 * 3: tp_loopback_10baseT
1333 * 2: preamble_gen_en
1334 * 1: reserved
1335 * 0: force_int
1336 */
1337
1338 /* MI Register 24: Interrupt Mask Reg(0x18)
1339 * 15-10: reserved
1340 * 9: mdio_sync_lost
1341 * 8: autoneg_status
1342 * 7: hi_bit_err
1343 * 6: np_rx
1344 * 5: err_counter_full
1345 * 4: fifo_over_underflow
1346 * 3: rx_status
1347 * 2: link_status
1348 * 1: automatic_speed
1349 * 0: int_en
1350 */
1351
1352 /* MI Register 25: Interrupt Status Reg(0x19)
1353 * 15-10: reserved
1354 * 9: mdio_sync_lost
1355 * 8: autoneg_status
1356 * 7: hi_bit_err
1357 * 6: np_rx
1358 * 5: err_counter_full
1359 * 4: fifo_over_underflow
1360 * 3: rx_status
1361 * 2: link_status
1362 * 1: automatic_speed
1363 * 0: int_en
1364 */
1365
1366 /* MI Register 26: PHY Status Reg(0x1A)
1367 * 15: reserved
1368 * 14-13: autoneg_fault
1369 * 12: autoneg_status
1370 * 11: mdi_x_status
1371 * 10: polarity_status
1372 * 9-8: speed_status
1373 * 7: duplex_status
1374 * 6: link_status
1375 * 5: tx_status
1376 * 4: rx_status
1377 * 3: collision_status
1378 * 2: autoneg_en
1379 * 1: pause_en
1380 * 0: asymmetric_dir
1381 */
1382 #define ET_PHY_AUTONEG_STATUS 0x1000
1383 #define ET_PHY_POLARITY_STATUS 0x0400
1384 #define ET_PHY_SPEED_STATUS 0x0300
1385 #define ET_PHY_DUPLEX_STATUS 0x0080
1386 #define ET_PHY_LSTATUS 0x0040
1387 #define ET_PHY_AUTONEG_ENABLE 0x0020
1388
1389 /* MI Register 27: LED Control Reg 1(0x1B)
1390 * 15-14: reserved
1391 * 13-12: led_dup_indicate
1392 * 11-10: led_10baseT
1393 * 9-8: led_collision
1394 * 7-4: reserved
1395 * 3-2: pulse_dur
1396 * 1: pulse_stretch1
1397 * 0: pulse_stretch0
1398 */
1399
1400 /* MI Register 28: LED Control Reg 2(0x1C)
1401 * 15-12: led_link
1402 * 11-8: led_tx_rx
1403 * 7-4: led_100BaseTX
1404 * 3-0: led_1000BaseT
1405 */
1406 #define ET_LED2_LED_LINK 0xF000
1407 #define ET_LED2_LED_TXRX 0x0F00
1408 #define ET_LED2_LED_100TX 0x00F0
1409 #define ET_LED2_LED_1000T 0x000F
1410
1411 /* defines for LED control reg 2 values */
1412 #define LED_VAL_1000BT 0x0
1413 #define LED_VAL_100BTX 0x1
1414 #define LED_VAL_10BT 0x2
1415 #define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
1416 #define LED_VAL_LINKON 0x4
1417 #define LED_VAL_TX 0x5
1418 #define LED_VAL_RX 0x6
1419 #define LED_VAL_TXRX 0x7 /* TX or RX */
1420 #define LED_VAL_DUPLEXFULL 0x8
1421 #define LED_VAL_COLLISION 0x9
1422 #define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
1423 #define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
1424 #define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
1425 #define LED_VAL_BLINK 0xD
1426 #define LED_VAL_ON 0xE
1427 #define LED_VAL_OFF 0xF
1428
1429 #define LED_LINK_SHIFT 12
1430 #define LED_TXRX_SHIFT 8
1431 #define LED_100TX_SHIFT 4
1432
1433 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */