This source file includes following definitions.
- ravb_read
- ravb_write
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11 #ifndef __RAVB_H__
12 #define __RAVB_H__
13
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
22
23 #define BE_TX_RING_SIZE 64
24 #define BE_RX_RING_SIZE 1024
25 #define NC_TX_RING_SIZE 64
26 #define NC_RX_RING_SIZE 64
27 #define BE_TX_RING_MIN 64
28 #define BE_RX_RING_MIN 64
29 #define BE_TX_RING_MAX 1024
30 #define BE_RX_RING_MAX 2048
31
32 #define PKT_BUF_SZ 1538
33
34
35 #define RAVB_ALIGN 128
36
37
38 #define RAVB_TXTSTAMP_VALID 0x00000001
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010
40
41 #define RAVB_RXTSTAMP_VALID 0x00000001
42 #define RAVB_RXTSTAMP_TYPE 0x00000006
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010
46
47 enum ravb_reg {
48
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
52 CSR = 0x000C,
53 CDAR0 = 0x0010,
54 CDAR1 = 0x0014,
55 CDAR2 = 0x0018,
56 CDAR3 = 0x001C,
57 CDAR4 = 0x0020,
58 CDAR5 = 0x0024,
59 CDAR6 = 0x0028,
60 CDAR7 = 0x002C,
61 CDAR8 = 0x0030,
62 CDAR9 = 0x0034,
63 CDAR10 = 0x0038,
64 CDAR11 = 0x003C,
65 CDAR12 = 0x0040,
66 CDAR13 = 0x0044,
67 CDAR14 = 0x0048,
68 CDAR15 = 0x004C,
69 CDAR16 = 0x0050,
70 CDAR17 = 0x0054,
71 CDAR18 = 0x0058,
72 CDAR19 = 0x005C,
73 CDAR20 = 0x0060,
74 CDAR21 = 0x0064,
75 ESR = 0x0088,
76 APSR = 0x008C,
77 RCR = 0x0090,
78 RQC0 = 0x0094,
79 RQC1 = 0x0098,
80 RQC2 = 0x009C,
81 RQC3 = 0x00A0,
82 RQC4 = 0x00A4,
83 RPC = 0x00B0,
84 UFCW = 0x00BC,
85 UFCS = 0x00C0,
86 UFCV0 = 0x00C4,
87 UFCV1 = 0x00C8,
88 UFCV2 = 0x00CC,
89 UFCV3 = 0x00D0,
90 UFCV4 = 0x00D4,
91 UFCD0 = 0x00E0,
92 UFCD1 = 0x00E4,
93 UFCD2 = 0x00E8,
94 UFCD3 = 0x00EC,
95 UFCD4 = 0x00F0,
96 SFO = 0x00FC,
97 SFP0 = 0x0100,
98 SFP1 = 0x0104,
99 SFP2 = 0x0108,
100 SFP3 = 0x010C,
101 SFP4 = 0x0110,
102 SFP5 = 0x0114,
103 SFP6 = 0x0118,
104 SFP7 = 0x011C,
105 SFP8 = 0x0120,
106 SFP9 = 0x0124,
107 SFP10 = 0x0128,
108 SFP11 = 0x012C,
109 SFP12 = 0x0130,
110 SFP13 = 0x0134,
111 SFP14 = 0x0138,
112 SFP15 = 0x013C,
113 SFP16 = 0x0140,
114 SFP17 = 0x0144,
115 SFP18 = 0x0148,
116 SFP19 = 0x014C,
117 SFP20 = 0x0150,
118 SFP21 = 0x0154,
119 SFP22 = 0x0158,
120 SFP23 = 0x015C,
121 SFP24 = 0x0160,
122 SFP25 = 0x0164,
123 SFP26 = 0x0168,
124 SFP27 = 0x016C,
125 SFP28 = 0x0170,
126 SFP29 = 0x0174,
127 SFP30 = 0x0178,
128 SFP31 = 0x017C,
129 SFM0 = 0x01C0,
130 SFM1 = 0x01C4,
131 TGC = 0x0300,
132 TCCR = 0x0304,
133 TSR = 0x0308,
134 TFA0 = 0x0310,
135 TFA1 = 0x0314,
136 TFA2 = 0x0318,
137 CIVR0 = 0x0320,
138 CIVR1 = 0x0324,
139 CDVR0 = 0x0328,
140 CDVR1 = 0x032C,
141 CUL0 = 0x0330,
142 CUL1 = 0x0334,
143 CLL0 = 0x0338,
144 CLL1 = 0x033C,
145 DIC = 0x0350,
146 DIS = 0x0354,
147 EIC = 0x0358,
148 EIS = 0x035C,
149 RIC0 = 0x0360,
150 RIS0 = 0x0364,
151 RIC1 = 0x0368,
152 RIS1 = 0x036C,
153 RIC2 = 0x0370,
154 RIS2 = 0x0374,
155 TIC = 0x0378,
156 TIS = 0x037C,
157 ISS = 0x0380,
158 CIE = 0x0384,
159 GCCR = 0x0390,
160 GMTT = 0x0394,
161 GPTC = 0x0398,
162 GTI = 0x039C,
163 GTO0 = 0x03A0,
164 GTO1 = 0x03A4,
165 GTO2 = 0x03A8,
166 GIC = 0x03AC,
167 GIS = 0x03B0,
168 GCPT = 0x03B4,
169 GCT0 = 0x03B8,
170 GCT1 = 0x03BC,
171 GCT2 = 0x03C0,
172 GIE = 0x03CC,
173 GID = 0x03D0,
174 DIL = 0x0440,
175 RIE0 = 0x0460,
176 RID0 = 0x0464,
177 RIE2 = 0x0470,
178 RID2 = 0x0474,
179 TIE = 0x0478,
180 TID = 0x047c,
181
182
183 ECMR = 0x0500,
184 RFLR = 0x0508,
185 ECSR = 0x0510,
186 ECSIPR = 0x0518,
187 PIR = 0x0520,
188 PSR = 0x0528,
189 PIPR = 0x052c,
190 MPR = 0x0558,
191 PFTCR = 0x055c,
192 PFRCR = 0x0560,
193 GECMR = 0x05b0,
194 MAHR = 0x05c0,
195 MALR = 0x05c8,
196 TROCR = 0x0700,
197 CEFCR = 0x0740,
198 FRECR = 0x0748,
199 TSFRCR = 0x0750,
200 TLFRCR = 0x0758,
201 RFCR = 0x0760,
202 MAFCR = 0x0778,
203 };
204
205
206
207
208 enum CCC_BIT {
209 CCC_OPC = 0x00000003,
210 CCC_OPC_RESET = 0x00000000,
211 CCC_OPC_CONFIG = 0x00000001,
212 CCC_OPC_OPERATION = 0x00000002,
213 CCC_GAC = 0x00000080,
214 CCC_DTSR = 0x00000100,
215 CCC_CSEL = 0x00030000,
216 CCC_CSEL_HPB = 0x00010000,
217 CCC_CSEL_ETH_TX = 0x00020000,
218 CCC_CSEL_GMII_REF = 0x00030000,
219 CCC_LBME = 0x01000000,
220 };
221
222
223 enum CSR_BIT {
224 CSR_OPS = 0x0000000F,
225 CSR_OPS_RESET = 0x00000001,
226 CSR_OPS_CONFIG = 0x00000002,
227 CSR_OPS_OPERATION = 0x00000004,
228 CSR_OPS_STANDBY = 0x00000008,
229 CSR_DTS = 0x00000100,
230 CSR_TPO0 = 0x00010000,
231 CSR_TPO1 = 0x00020000,
232 CSR_TPO2 = 0x00040000,
233 CSR_TPO3 = 0x00080000,
234 CSR_RPO = 0x00100000,
235 };
236
237
238 enum ESR_BIT {
239 ESR_EQN = 0x0000001F,
240 ESR_ET = 0x00000F00,
241 ESR_EIL = 0x00001000,
242 };
243
244
245 enum APSR_BIT {
246 APSR_MEMS = 0x00000002,
247 APSR_CMSW = 0x00000010,
248 APSR_DM = 0x00006000,
249 APSR_DM_RDM = 0x00002000,
250 APSR_DM_TDM = 0x00004000,
251 };
252
253
254 enum RCR_BIT {
255 RCR_EFFS = 0x00000001,
256 RCR_ENCF = 0x00000002,
257 RCR_ESF = 0x0000000C,
258 RCR_ETS0 = 0x00000010,
259 RCR_ETS2 = 0x00000020,
260 RCR_RFCL = 0x1FFF0000,
261 };
262
263
264 enum RQC_BIT {
265 RQC_RSM0 = 0x00000003,
266 RQC_UFCC0 = 0x00000030,
267 RQC_RSM1 = 0x00000300,
268 RQC_UFCC1 = 0x00003000,
269 RQC_RSM2 = 0x00030000,
270 RQC_UFCC2 = 0x00300000,
271 RQC_RSM3 = 0x03000000,
272 RQC_UFCC3 = 0x30000000,
273 };
274
275
276 enum RPC_BIT {
277 RPC_PCNT = 0x00000700,
278 RPC_DCNT = 0x00FF0000,
279 };
280
281
282 enum UFCW_BIT {
283 UFCW_WL0 = 0x0000003F,
284 UFCW_WL1 = 0x00003F00,
285 UFCW_WL2 = 0x003F0000,
286 UFCW_WL3 = 0x3F000000,
287 };
288
289
290 enum UFCS_BIT {
291 UFCS_SL0 = 0x0000003F,
292 UFCS_SL1 = 0x00003F00,
293 UFCS_SL2 = 0x003F0000,
294 UFCS_SL3 = 0x3F000000,
295 };
296
297
298 enum UFCV_BIT {
299 UFCV_CV0 = 0x0000003F,
300 UFCV_CV1 = 0x00003F00,
301 UFCV_CV2 = 0x003F0000,
302 UFCV_CV3 = 0x3F000000,
303 };
304
305
306 enum UFCD_BIT {
307 UFCD_DV0 = 0x0000003F,
308 UFCD_DV1 = 0x00003F00,
309 UFCD_DV2 = 0x003F0000,
310 UFCD_DV3 = 0x3F000000,
311 };
312
313
314 enum SFO_BIT {
315 SFO_FBP = 0x0000003F,
316 };
317
318
319 enum RTC_BIT {
320 RTC_MFL0 = 0x00000FFF,
321 RTC_MFL1 = 0x0FFF0000,
322 };
323
324
325 enum TGC_BIT {
326 TGC_TSM0 = 0x00000001,
327 TGC_TSM1 = 0x00000002,
328 TGC_TSM2 = 0x00000004,
329 TGC_TSM3 = 0x00000008,
330 TGC_TQP = 0x00000030,
331 TGC_TQP_NONAVB = 0x00000000,
332 TGC_TQP_AVBMODE1 = 0x00000010,
333 TGC_TQP_AVBMODE2 = 0x00000030,
334 TGC_TBD0 = 0x00000300,
335 TGC_TBD1 = 0x00003000,
336 TGC_TBD2 = 0x00030000,
337 TGC_TBD3 = 0x00300000,
338 };
339
340
341 enum TCCR_BIT {
342 TCCR_TSRQ0 = 0x00000001,
343 TCCR_TSRQ1 = 0x00000002,
344 TCCR_TSRQ2 = 0x00000004,
345 TCCR_TSRQ3 = 0x00000008,
346 TCCR_TFEN = 0x00000100,
347 TCCR_TFR = 0x00000200,
348 };
349
350
351 enum TSR_BIT {
352 TSR_CCS0 = 0x00000003,
353 TSR_CCS1 = 0x0000000C,
354 TSR_TFFL = 0x00000700,
355 };
356
357
358 enum TFA2_BIT {
359 TFA2_TSV = 0x0000FFFF,
360 TFA2_TST = 0x03FF0000,
361 };
362
363
364 enum DIC_BIT {
365 DIC_DPE1 = 0x00000002,
366 DIC_DPE2 = 0x00000004,
367 DIC_DPE3 = 0x00000008,
368 DIC_DPE4 = 0x00000010,
369 DIC_DPE5 = 0x00000020,
370 DIC_DPE6 = 0x00000040,
371 DIC_DPE7 = 0x00000080,
372 DIC_DPE8 = 0x00000100,
373 DIC_DPE9 = 0x00000200,
374 DIC_DPE10 = 0x00000400,
375 DIC_DPE11 = 0x00000800,
376 DIC_DPE12 = 0x00001000,
377 DIC_DPE13 = 0x00002000,
378 DIC_DPE14 = 0x00004000,
379 DIC_DPE15 = 0x00008000,
380 };
381
382
383 enum DIS_BIT {
384 DIS_DPF1 = 0x00000002,
385 DIS_DPF2 = 0x00000004,
386 DIS_DPF3 = 0x00000008,
387 DIS_DPF4 = 0x00000010,
388 DIS_DPF5 = 0x00000020,
389 DIS_DPF6 = 0x00000040,
390 DIS_DPF7 = 0x00000080,
391 DIS_DPF8 = 0x00000100,
392 DIS_DPF9 = 0x00000200,
393 DIS_DPF10 = 0x00000400,
394 DIS_DPF11 = 0x00000800,
395 DIS_DPF12 = 0x00001000,
396 DIS_DPF13 = 0x00002000,
397 DIS_DPF14 = 0x00004000,
398 DIS_DPF15 = 0x00008000,
399 };
400
401
402 enum EIC_BIT {
403 EIC_MREE = 0x00000001,
404 EIC_MTEE = 0x00000002,
405 EIC_QEE = 0x00000004,
406 EIC_SEE = 0x00000008,
407 EIC_CLLE0 = 0x00000010,
408 EIC_CLLE1 = 0x00000020,
409 EIC_CULE0 = 0x00000040,
410 EIC_CULE1 = 0x00000080,
411 EIC_TFFE = 0x00000100,
412 };
413
414
415 enum EIS_BIT {
416 EIS_MREF = 0x00000001,
417 EIS_MTEF = 0x00000002,
418 EIS_QEF = 0x00000004,
419 EIS_SEF = 0x00000008,
420 EIS_CLLF0 = 0x00000010,
421 EIS_CLLF1 = 0x00000020,
422 EIS_CULF0 = 0x00000040,
423 EIS_CULF1 = 0x00000080,
424 EIS_TFFF = 0x00000100,
425 EIS_QFS = 0x00010000,
426 EIS_RESERVED = (GENMASK(31, 17) | GENMASK(15, 11)),
427 };
428
429
430 enum RIC0_BIT {
431 RIC0_FRE0 = 0x00000001,
432 RIC0_FRE1 = 0x00000002,
433 RIC0_FRE2 = 0x00000004,
434 RIC0_FRE3 = 0x00000008,
435 RIC0_FRE4 = 0x00000010,
436 RIC0_FRE5 = 0x00000020,
437 RIC0_FRE6 = 0x00000040,
438 RIC0_FRE7 = 0x00000080,
439 RIC0_FRE8 = 0x00000100,
440 RIC0_FRE9 = 0x00000200,
441 RIC0_FRE10 = 0x00000400,
442 RIC0_FRE11 = 0x00000800,
443 RIC0_FRE12 = 0x00001000,
444 RIC0_FRE13 = 0x00002000,
445 RIC0_FRE14 = 0x00004000,
446 RIC0_FRE15 = 0x00008000,
447 RIC0_FRE16 = 0x00010000,
448 RIC0_FRE17 = 0x00020000,
449 };
450
451
452 enum RIS0_BIT {
453 RIS0_FRF0 = 0x00000001,
454 RIS0_FRF1 = 0x00000002,
455 RIS0_FRF2 = 0x00000004,
456 RIS0_FRF3 = 0x00000008,
457 RIS0_FRF4 = 0x00000010,
458 RIS0_FRF5 = 0x00000020,
459 RIS0_FRF6 = 0x00000040,
460 RIS0_FRF7 = 0x00000080,
461 RIS0_FRF8 = 0x00000100,
462 RIS0_FRF9 = 0x00000200,
463 RIS0_FRF10 = 0x00000400,
464 RIS0_FRF11 = 0x00000800,
465 RIS0_FRF12 = 0x00001000,
466 RIS0_FRF13 = 0x00002000,
467 RIS0_FRF14 = 0x00004000,
468 RIS0_FRF15 = 0x00008000,
469 RIS0_FRF16 = 0x00010000,
470 RIS0_FRF17 = 0x00020000,
471 RIS0_RESERVED = GENMASK(31, 18),
472 };
473
474
475 enum RIC1_BIT {
476 RIC1_RFWE = 0x80000000,
477 };
478
479
480 enum RIS1_BIT {
481 RIS1_RFWF = 0x80000000,
482 };
483
484
485 enum RIC2_BIT {
486 RIC2_QFE0 = 0x00000001,
487 RIC2_QFE1 = 0x00000002,
488 RIC2_QFE2 = 0x00000004,
489 RIC2_QFE3 = 0x00000008,
490 RIC2_QFE4 = 0x00000010,
491 RIC2_QFE5 = 0x00000020,
492 RIC2_QFE6 = 0x00000040,
493 RIC2_QFE7 = 0x00000080,
494 RIC2_QFE8 = 0x00000100,
495 RIC2_QFE9 = 0x00000200,
496 RIC2_QFE10 = 0x00000400,
497 RIC2_QFE11 = 0x00000800,
498 RIC2_QFE12 = 0x00001000,
499 RIC2_QFE13 = 0x00002000,
500 RIC2_QFE14 = 0x00004000,
501 RIC2_QFE15 = 0x00008000,
502 RIC2_QFE16 = 0x00010000,
503 RIC2_QFE17 = 0x00020000,
504 RIC2_RFFE = 0x80000000,
505 };
506
507
508 enum RIS2_BIT {
509 RIS2_QFF0 = 0x00000001,
510 RIS2_QFF1 = 0x00000002,
511 RIS2_QFF2 = 0x00000004,
512 RIS2_QFF3 = 0x00000008,
513 RIS2_QFF4 = 0x00000010,
514 RIS2_QFF5 = 0x00000020,
515 RIS2_QFF6 = 0x00000040,
516 RIS2_QFF7 = 0x00000080,
517 RIS2_QFF8 = 0x00000100,
518 RIS2_QFF9 = 0x00000200,
519 RIS2_QFF10 = 0x00000400,
520 RIS2_QFF11 = 0x00000800,
521 RIS2_QFF12 = 0x00001000,
522 RIS2_QFF13 = 0x00002000,
523 RIS2_QFF14 = 0x00004000,
524 RIS2_QFF15 = 0x00008000,
525 RIS2_QFF16 = 0x00010000,
526 RIS2_QFF17 = 0x00020000,
527 RIS2_RFFF = 0x80000000,
528 RIS2_RESERVED = GENMASK(30, 18),
529 };
530
531
532 enum TIC_BIT {
533 TIC_FTE0 = 0x00000001,
534 TIC_FTE1 = 0x00000002,
535 TIC_TFUE = 0x00000100,
536 TIC_TFWE = 0x00000200,
537 };
538
539
540 enum TIS_BIT {
541 TIS_FTF0 = 0x00000001,
542 TIS_FTF1 = 0x00000002,
543 TIS_TFUF = 0x00000100,
544 TIS_TFWF = 0x00000200,
545 TIS_RESERVED = (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
546 };
547
548
549 enum ISS_BIT {
550 ISS_FRS = 0x00000001,
551 ISS_FTS = 0x00000004,
552 ISS_ES = 0x00000040,
553 ISS_MS = 0x00000080,
554 ISS_TFUS = 0x00000100,
555 ISS_TFWS = 0x00000200,
556 ISS_RFWS = 0x00001000,
557 ISS_CGIS = 0x00002000,
558 ISS_DPS1 = 0x00020000,
559 ISS_DPS2 = 0x00040000,
560 ISS_DPS3 = 0x00080000,
561 ISS_DPS4 = 0x00100000,
562 ISS_DPS5 = 0x00200000,
563 ISS_DPS6 = 0x00400000,
564 ISS_DPS7 = 0x00800000,
565 ISS_DPS8 = 0x01000000,
566 ISS_DPS9 = 0x02000000,
567 ISS_DPS10 = 0x04000000,
568 ISS_DPS11 = 0x08000000,
569 ISS_DPS12 = 0x10000000,
570 ISS_DPS13 = 0x20000000,
571 ISS_DPS14 = 0x40000000,
572 ISS_DPS15 = 0x80000000,
573 };
574
575
576 enum CIE_BIT {
577 CIE_CRIE = 0x00000001,
578 CIE_CTIE = 0x00000100,
579 CIE_RQFM = 0x00010000,
580 CIE_CL0M = 0x00020000,
581 CIE_RFWL = 0x00040000,
582 CIE_RFFL = 0x00080000,
583 };
584
585
586 enum GCCR_BIT {
587 GCCR_TCR = 0x00000003,
588 GCCR_TCR_NOREQ = 0x00000000,
589 GCCR_TCR_RESET = 0x00000001,
590 GCCR_TCR_CAPTURE = 0x00000003,
591 GCCR_LTO = 0x00000004,
592 GCCR_LTI = 0x00000008,
593 GCCR_LPTC = 0x00000010,
594 GCCR_LMTT = 0x00000020,
595 GCCR_TCSS = 0x00000300,
596 GCCR_TCSS_GPTP = 0x00000000,
597 GCCR_TCSS_ADJGPTP = 0x00000100,
598 GCCR_TCSS_AVTP = 0x00000200,
599 };
600
601
602 enum GTI_BIT {
603 GTI_TIV = 0x0FFFFFFF,
604 };
605
606 #define GTI_TIV_MAX GTI_TIV
607 #define GTI_TIV_MIN 0x20
608
609
610 enum GIC_BIT {
611 GIC_PTCE = 0x00000001,
612 GIC_PTME = 0x00000004,
613 };
614
615
616 enum GIS_BIT {
617 GIS_PTCF = 0x00000001,
618 GIS_PTMF = 0x00000004,
619 GIS_RESERVED = GENMASK(15, 10),
620 };
621
622
623 enum GIE_BIT {
624 GIE_PTCS = 0x00000001,
625 GIE_PTOS = 0x00000002,
626 GIE_PTMS0 = 0x00000004,
627 GIE_PTMS1 = 0x00000008,
628 GIE_PTMS2 = 0x00000010,
629 GIE_PTMS3 = 0x00000020,
630 GIE_PTMS4 = 0x00000040,
631 GIE_PTMS5 = 0x00000080,
632 GIE_PTMS6 = 0x00000100,
633 GIE_PTMS7 = 0x00000200,
634 GIE_ATCS0 = 0x00010000,
635 GIE_ATCS1 = 0x00020000,
636 GIE_ATCS2 = 0x00040000,
637 GIE_ATCS3 = 0x00080000,
638 GIE_ATCS4 = 0x00100000,
639 GIE_ATCS5 = 0x00200000,
640 GIE_ATCS6 = 0x00400000,
641 GIE_ATCS7 = 0x00800000,
642 GIE_ATCS8 = 0x01000000,
643 GIE_ATCS9 = 0x02000000,
644 GIE_ATCS10 = 0x04000000,
645 GIE_ATCS11 = 0x08000000,
646 GIE_ATCS12 = 0x10000000,
647 GIE_ATCS13 = 0x20000000,
648 GIE_ATCS14 = 0x40000000,
649 GIE_ATCS15 = 0x80000000,
650 };
651
652
653 enum GID_BIT {
654 GID_PTCD = 0x00000001,
655 GID_PTOD = 0x00000002,
656 GID_PTMD0 = 0x00000004,
657 GID_PTMD1 = 0x00000008,
658 GID_PTMD2 = 0x00000010,
659 GID_PTMD3 = 0x00000020,
660 GID_PTMD4 = 0x00000040,
661 GID_PTMD5 = 0x00000080,
662 GID_PTMD6 = 0x00000100,
663 GID_PTMD7 = 0x00000200,
664 GID_ATCD0 = 0x00010000,
665 GID_ATCD1 = 0x00020000,
666 GID_ATCD2 = 0x00040000,
667 GID_ATCD3 = 0x00080000,
668 GID_ATCD4 = 0x00100000,
669 GID_ATCD5 = 0x00200000,
670 GID_ATCD6 = 0x00400000,
671 GID_ATCD7 = 0x00800000,
672 GID_ATCD8 = 0x01000000,
673 GID_ATCD9 = 0x02000000,
674 GID_ATCD10 = 0x04000000,
675 GID_ATCD11 = 0x08000000,
676 GID_ATCD12 = 0x10000000,
677 GID_ATCD13 = 0x20000000,
678 GID_ATCD14 = 0x40000000,
679 GID_ATCD15 = 0x80000000,
680 };
681
682
683 enum RIE0_BIT {
684 RIE0_FRS0 = 0x00000001,
685 RIE0_FRS1 = 0x00000002,
686 RIE0_FRS2 = 0x00000004,
687 RIE0_FRS3 = 0x00000008,
688 RIE0_FRS4 = 0x00000010,
689 RIE0_FRS5 = 0x00000020,
690 RIE0_FRS6 = 0x00000040,
691 RIE0_FRS7 = 0x00000080,
692 RIE0_FRS8 = 0x00000100,
693 RIE0_FRS9 = 0x00000200,
694 RIE0_FRS10 = 0x00000400,
695 RIE0_FRS11 = 0x00000800,
696 RIE0_FRS12 = 0x00001000,
697 RIE0_FRS13 = 0x00002000,
698 RIE0_FRS14 = 0x00004000,
699 RIE0_FRS15 = 0x00008000,
700 RIE0_FRS16 = 0x00010000,
701 RIE0_FRS17 = 0x00020000,
702 };
703
704
705 enum RID0_BIT {
706 RID0_FRD0 = 0x00000001,
707 RID0_FRD1 = 0x00000002,
708 RID0_FRD2 = 0x00000004,
709 RID0_FRD3 = 0x00000008,
710 RID0_FRD4 = 0x00000010,
711 RID0_FRD5 = 0x00000020,
712 RID0_FRD6 = 0x00000040,
713 RID0_FRD7 = 0x00000080,
714 RID0_FRD8 = 0x00000100,
715 RID0_FRD9 = 0x00000200,
716 RID0_FRD10 = 0x00000400,
717 RID0_FRD11 = 0x00000800,
718 RID0_FRD12 = 0x00001000,
719 RID0_FRD13 = 0x00002000,
720 RID0_FRD14 = 0x00004000,
721 RID0_FRD15 = 0x00008000,
722 RID0_FRD16 = 0x00010000,
723 RID0_FRD17 = 0x00020000,
724 };
725
726
727 enum RIE2_BIT {
728 RIE2_QFS0 = 0x00000001,
729 RIE2_QFS1 = 0x00000002,
730 RIE2_QFS2 = 0x00000004,
731 RIE2_QFS3 = 0x00000008,
732 RIE2_QFS4 = 0x00000010,
733 RIE2_QFS5 = 0x00000020,
734 RIE2_QFS6 = 0x00000040,
735 RIE2_QFS7 = 0x00000080,
736 RIE2_QFS8 = 0x00000100,
737 RIE2_QFS9 = 0x00000200,
738 RIE2_QFS10 = 0x00000400,
739 RIE2_QFS11 = 0x00000800,
740 RIE2_QFS12 = 0x00001000,
741 RIE2_QFS13 = 0x00002000,
742 RIE2_QFS14 = 0x00004000,
743 RIE2_QFS15 = 0x00008000,
744 RIE2_QFS16 = 0x00010000,
745 RIE2_QFS17 = 0x00020000,
746 RIE2_RFFS = 0x80000000,
747 };
748
749
750 enum RID2_BIT {
751 RID2_QFD0 = 0x00000001,
752 RID2_QFD1 = 0x00000002,
753 RID2_QFD2 = 0x00000004,
754 RID2_QFD3 = 0x00000008,
755 RID2_QFD4 = 0x00000010,
756 RID2_QFD5 = 0x00000020,
757 RID2_QFD6 = 0x00000040,
758 RID2_QFD7 = 0x00000080,
759 RID2_QFD8 = 0x00000100,
760 RID2_QFD9 = 0x00000200,
761 RID2_QFD10 = 0x00000400,
762 RID2_QFD11 = 0x00000800,
763 RID2_QFD12 = 0x00001000,
764 RID2_QFD13 = 0x00002000,
765 RID2_QFD14 = 0x00004000,
766 RID2_QFD15 = 0x00008000,
767 RID2_QFD16 = 0x00010000,
768 RID2_QFD17 = 0x00020000,
769 RID2_RFFD = 0x80000000,
770 };
771
772
773 enum TIE_BIT {
774 TIE_FTS0 = 0x00000001,
775 TIE_FTS1 = 0x00000002,
776 TIE_FTS2 = 0x00000004,
777 TIE_FTS3 = 0x00000008,
778 TIE_TFUS = 0x00000100,
779 TIE_TFWS = 0x00000200,
780 TIE_MFUS = 0x00000400,
781 TIE_MFWS = 0x00000800,
782 TIE_TDPS0 = 0x00010000,
783 TIE_TDPS1 = 0x00020000,
784 TIE_TDPS2 = 0x00040000,
785 TIE_TDPS3 = 0x00080000,
786 };
787
788
789 enum TID_BIT {
790 TID_FTD0 = 0x00000001,
791 TID_FTD1 = 0x00000002,
792 TID_FTD2 = 0x00000004,
793 TID_FTD3 = 0x00000008,
794 TID_TFUD = 0x00000100,
795 TID_TFWD = 0x00000200,
796 TID_MFUD = 0x00000400,
797 TID_MFWD = 0x00000800,
798 TID_TDPD0 = 0x00010000,
799 TID_TDPD1 = 0x00020000,
800 TID_TDPD2 = 0x00040000,
801 TID_TDPD3 = 0x00080000,
802 };
803
804
805 enum ECMR_BIT {
806 ECMR_PRM = 0x00000001,
807 ECMR_DM = 0x00000002,
808 ECMR_TE = 0x00000020,
809 ECMR_RE = 0x00000040,
810 ECMR_MPDE = 0x00000200,
811 ECMR_TXF = 0x00010000,
812 ECMR_RXF = 0x00020000,
813 ECMR_PFR = 0x00040000,
814 ECMR_ZPF = 0x00080000,
815 ECMR_RZPF = 0x00100000,
816 ECMR_DPAD = 0x00200000,
817 ECMR_RCSC = 0x00800000,
818 ECMR_TRCCM = 0x04000000,
819 };
820
821
822 enum ECSR_BIT {
823 ECSR_ICD = 0x00000001,
824 ECSR_MPD = 0x00000002,
825 ECSR_LCHNG = 0x00000004,
826 ECSR_PHYI = 0x00000008,
827 };
828
829
830 enum ECSIPR_BIT {
831 ECSIPR_ICDIP = 0x00000001,
832 ECSIPR_MPDIP = 0x00000002,
833 ECSIPR_LCHNGIP = 0x00000004,
834 };
835
836
837 enum PIR_BIT {
838 PIR_MDC = 0x00000001,
839 PIR_MMD = 0x00000002,
840 PIR_MDO = 0x00000004,
841 PIR_MDI = 0x00000008,
842 };
843
844
845 enum PSR_BIT {
846 PSR_LMON = 0x00000001,
847 };
848
849
850 enum PIPR_BIT {
851 PIPR_PHYIP = 0x00000001,
852 };
853
854
855 enum MPR_BIT {
856 MPR_MP = 0x0000ffff,
857 };
858
859
860 enum GECMR_BIT {
861 GECMR_SPEED = 0x00000001,
862 GECMR_SPEED_100 = 0x00000000,
863 GECMR_SPEED_1000 = 0x00000001,
864 };
865
866
867 struct ravb_desc {
868 __le16 ds;
869 u8 cc;
870 u8 die_dt;
871 __le32 dptr;
872 };
873
874 #define DPTR_ALIGN 4
875
876 enum DIE_DT {
877
878 DT_FMID = 0x40,
879 DT_FSTART = 0x50,
880 DT_FEND = 0x60,
881 DT_FSINGLE = 0x70,
882
883 DT_LINK = 0x80,
884 DT_LINKFIX = 0x90,
885 DT_EOS = 0xa0,
886
887 DT_FEMPTY = 0xc0,
888 DT_FEMPTY_IS = 0xd0,
889 DT_FEMPTY_IC = 0xe0,
890 DT_FEMPTY_ND = 0xf0,
891 DT_LEMPTY = 0x20,
892 DT_EEMPTY = 0x30,
893 };
894
895 struct ravb_rx_desc {
896 __le16 ds_cc;
897 u8 msc;
898 u8 die_dt;
899 __le32 dptr;
900 };
901
902 struct ravb_ex_rx_desc {
903 __le16 ds_cc;
904 u8 msc;
905 u8 die_dt;
906 __le32 dptr;
907 __le32 ts_n;
908 __le32 ts_sl;
909 __le16 ts_sh;
910 __le16 res;
911 };
912
913 enum RX_DS_CC_BIT {
914 RX_DS = 0x0fff,
915 RX_TR = 0x1000,
916 RX_EI = 0x2000,
917 RX_PS = 0xc000,
918 };
919
920
921 enum MSC_BIT {
922 MSC_CRC = 0x01,
923 MSC_RFE = 0x02,
924 MSC_RTSF = 0x04,
925 MSC_RTLF = 0x08,
926 MSC_FRE = 0x10,
927 MSC_CRL = 0x20,
928 MSC_CEEF = 0x40,
929 MSC_MC = 0x80,
930 };
931
932 struct ravb_tx_desc {
933 __le16 ds_tagl;
934 u8 tagh_tsr;
935 u8 die_dt;
936 __le32 dptr;
937 };
938
939 enum TX_DS_TAGL_BIT {
940 TX_DS = 0x0fff,
941 TX_TAGL = 0xf000,
942 };
943
944 enum TX_TAGH_TSR_BIT {
945 TX_TAGH = 0x3f,
946 TX_TSR = 0x40,
947 };
948 enum RAVB_QUEUE {
949 RAVB_BE = 0,
950 RAVB_NC,
951 };
952
953 #define DBAT_ENTRY_NUM 22
954 #define RX_QUEUE_OFFSET 4
955 #define NUM_RX_QUEUE 2
956 #define NUM_TX_QUEUE 2
957
958 #define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16))
959
960
961 #define NUM_TX_DESC_GEN2 2
962 #define NUM_TX_DESC_GEN3 1
963
964 struct ravb_tstamp_skb {
965 struct list_head list;
966 struct sk_buff *skb;
967 u16 tag;
968 };
969
970 struct ravb_ptp_perout {
971 u32 target;
972 u32 period;
973 };
974
975 #define N_EXT_TS 1
976 #define N_PER_OUT 1
977
978 struct ravb_ptp {
979 struct ptp_clock *clock;
980 struct ptp_clock_info info;
981 u32 default_addend;
982 u32 current_addend;
983 int extts[N_EXT_TS];
984 struct ravb_ptp_perout perout[N_PER_OUT];
985 };
986
987 enum ravb_chip_id {
988 RCAR_GEN2,
989 RCAR_GEN3,
990 };
991
992 struct ravb_private {
993 struct net_device *ndev;
994 struct platform_device *pdev;
995 void __iomem *addr;
996 struct clk *clk;
997 struct mdiobb_ctrl mdiobb;
998 u32 num_rx_ring[NUM_RX_QUEUE];
999 u32 num_tx_ring[NUM_TX_QUEUE];
1000 u32 desc_bat_size;
1001 dma_addr_t desc_bat_dma;
1002 struct ravb_desc *desc_bat;
1003 dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1004 dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1005 struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
1006 struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1007 void *tx_align[NUM_TX_QUEUE];
1008 struct sk_buff **rx_skb[NUM_RX_QUEUE];
1009 struct sk_buff **tx_skb[NUM_TX_QUEUE];
1010 u32 rx_over_errors;
1011 u32 rx_fifo_errors;
1012 struct net_device_stats stats[NUM_RX_QUEUE];
1013 u32 tstamp_tx_ctrl;
1014 u32 tstamp_rx_ctrl;
1015 struct list_head ts_skb_list;
1016 u32 ts_skb_tag;
1017 struct ravb_ptp ptp;
1018 spinlock_t lock;
1019 u32 cur_rx[NUM_RX_QUEUE];
1020 u32 dirty_rx[NUM_RX_QUEUE];
1021 u32 cur_tx[NUM_TX_QUEUE];
1022 u32 dirty_tx[NUM_TX_QUEUE];
1023 struct napi_struct napi[NUM_RX_QUEUE];
1024 struct work_struct work;
1025
1026 struct mii_bus *mii_bus;
1027 int link;
1028 phy_interface_t phy_interface;
1029 int msg_enable;
1030 int speed;
1031 int emac_irq;
1032 enum ravb_chip_id chip_id;
1033 int rx_irqs[NUM_RX_QUEUE];
1034 int tx_irqs[NUM_TX_QUEUE];
1035
1036 unsigned no_avb_link:1;
1037 unsigned avb_link_active_low:1;
1038 unsigned wol_enabled:1;
1039 int num_tx_desc;
1040 };
1041
1042 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1043 {
1044 struct ravb_private *priv = netdev_priv(ndev);
1045
1046 return ioread32(priv->addr + reg);
1047 }
1048
1049 static inline void ravb_write(struct net_device *ndev, u32 data,
1050 enum ravb_reg reg)
1051 {
1052 struct ravb_private *priv = netdev_priv(ndev);
1053
1054 iowrite32(data, priv->addr + reg);
1055 }
1056
1057 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1058 u32 set);
1059 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1060
1061 void ravb_ptp_interrupt(struct net_device *ndev);
1062 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1063 void ravb_ptp_stop(struct net_device *ndev);
1064
1065 #endif