This source file includes following definitions.
- cpts_can_timestamp
- cpts_rx_timestamp
- cpts_tx_timestamp
- cpts_create
- cpts_release
- cpts_register
- cpts_unregister
- cpts_can_timestamp
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7
8 #ifndef _TI_CPTS_H_
9 #define _TI_CPTS_H_
10
11 #if IS_ENABLED(CONFIG_TI_CPTS)
12
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/clocksource.h>
16 #include <linux/device.h>
17 #include <linux/list.h>
18 #include <linux/of.h>
19 #include <linux/ptp_clock_kernel.h>
20 #include <linux/skbuff.h>
21 #include <linux/ptp_classify.h>
22 #include <linux/timecounter.h>
23
24 struct cpsw_cpts {
25 u32 idver;
26 u32 control;
27 u32 rftclk_sel;
28 u32 ts_push;
29 u32 ts_load_val;
30 u32 ts_load_en;
31 u32 res2[2];
32 u32 intstat_raw;
33 u32 intstat_masked;
34 u32 int_enable;
35 u32 res3;
36 u32 event_pop;
37 u32 event_low;
38 u32 event_high;
39 };
40
41
42 #define TX_IDENT_SHIFT (16)
43 #define TX_IDENT_MASK (0xffff)
44 #define RTL_VER_SHIFT (11)
45 #define RTL_VER_MASK (0x1f)
46 #define MAJOR_VER_SHIFT (8)
47 #define MAJOR_VER_MASK (0x7)
48 #define MINOR_VER_SHIFT (0)
49 #define MINOR_VER_MASK (0xff)
50
51
52 #define HW4_TS_PUSH_EN (1<<11)
53 #define HW3_TS_PUSH_EN (1<<10)
54 #define HW2_TS_PUSH_EN (1<<9)
55 #define HW1_TS_PUSH_EN (1<<8)
56 #define INT_TEST (1<<1)
57 #define CPTS_EN (1<<0)
58
59
60
61
62
63 #define TS_PUSH (1<<0)
64 #define TS_LOAD_EN (1<<0)
65 #define TS_PEND_RAW (1<<0)
66 #define TS_PEND (1<<0)
67 #define TS_PEND_EN (1<<0)
68 #define EVENT_POP (1<<0)
69
70
71 #define PORT_NUMBER_SHIFT (24)
72 #define PORT_NUMBER_MASK (0x1f)
73 #define EVENT_TYPE_SHIFT (20)
74 #define EVENT_TYPE_MASK (0xf)
75 #define MESSAGE_TYPE_SHIFT (16)
76 #define MESSAGE_TYPE_MASK (0xf)
77 #define SEQUENCE_ID_SHIFT (0)
78 #define SEQUENCE_ID_MASK (0xffff)
79
80 enum {
81 CPTS_EV_PUSH,
82 CPTS_EV_ROLL,
83 CPTS_EV_HALF,
84 CPTS_EV_HW,
85 CPTS_EV_RX,
86 CPTS_EV_TX,
87 };
88
89 #define CPTS_FIFO_DEPTH 16
90 #define CPTS_MAX_EVENTS 32
91
92 struct cpts_event {
93 struct list_head list;
94 unsigned long tmo;
95 u32 high;
96 u32 low;
97 };
98
99 struct cpts {
100 struct device *dev;
101 struct cpsw_cpts __iomem *reg;
102 int tx_enable;
103 int rx_enable;
104 struct ptp_clock_info info;
105 struct ptp_clock *clock;
106 spinlock_t lock;
107 u32 cc_mult;
108 struct cyclecounter cc;
109 struct timecounter tc;
110 int phc_index;
111 struct clk *refclk;
112 struct list_head events;
113 struct list_head pool;
114 struct cpts_event pool_data[CPTS_MAX_EVENTS];
115 unsigned long ov_check_period;
116 struct sk_buff_head txq;
117 };
118
119 void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
120 void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
121 int cpts_register(struct cpts *cpts);
122 void cpts_unregister(struct cpts *cpts);
123 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
124 struct device_node *node);
125 void cpts_release(struct cpts *cpts);
126
127 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
128 {
129 unsigned int class = ptp_classify_raw(skb);
130
131 if (class == PTP_CLASS_NONE)
132 return false;
133
134 return true;
135 }
136
137 #else
138 struct cpts;
139
140 static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
141 {
142 }
143 static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
144 {
145 }
146
147 static inline
148 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
149 struct device_node *node)
150 {
151 return NULL;
152 }
153
154 static inline void cpts_release(struct cpts *cpts)
155 {
156 }
157
158 static inline int
159 cpts_register(struct cpts *cpts)
160 {
161 return 0;
162 }
163
164 static inline void cpts_unregister(struct cpts *cpts)
165 {
166 }
167
168 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
169 {
170 return false;
171 }
172 #endif
173
174
175 #endif