drivers/net/ethernet/ti/cpsw

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
slave_read
slave_write
cpsw_get_slave_port
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Texas Instruments Ethernet Switch Driver
   4  */
   5 
   6 #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
   7 #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
   8 
   9 #include "davinci_cpdma.h"
  10 
  11 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  12                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  13                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  14                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  15                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  16                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  17                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  18                          NETIF_MSG_RX_STATUS)
  19 
  20 #define cpsw_info(priv, type, format, ...)              \
  21 do {                                                            \
  22         if (netif_msg_##type(priv) && net_ratelimit())          \
  23                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  24 } while (0)
  25 
  26 #define cpsw_err(priv, type, format, ...)               \
  27 do {                                                            \
  28         if (netif_msg_##type(priv) && net_ratelimit())          \
  29                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  30 } while (0)
  31 
  32 #define cpsw_dbg(priv, type, format, ...)               \
  33 do {                                                            \
  34         if (netif_msg_##type(priv) && net_ratelimit())          \
  35                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  36 } while (0)
  37 
  38 #define cpsw_notice(priv, type, format, ...)            \
  39 do {                                                            \
  40         if (netif_msg_##type(priv) && net_ratelimit())          \
  41                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  42 } while (0)
  43 
  44 #define ALE_ALL_PORTS           0x7
  45 
  46 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  47 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  48 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  49 
  50 #define CPSW_VERSION_1          0x19010a
  51 #define CPSW_VERSION_2          0x19010c
  52 #define CPSW_VERSION_3          0x19010f
  53 #define CPSW_VERSION_4          0x190112
  54 
  55 #define HOST_PORT_NUM           0
  56 #define CPSW_ALE_PORTS_NUM      3
  57 #define SLIVER_SIZE             0x40
  58 
  59 #define CPSW1_HOST_PORT_OFFSET  0x028
  60 #define CPSW1_SLAVE_OFFSET      0x050
  61 #define CPSW1_SLAVE_SIZE        0x040
  62 #define CPSW1_CPDMA_OFFSET      0x100
  63 #define CPSW1_STATERAM_OFFSET   0x200
  64 #define CPSW1_HW_STATS          0x400
  65 #define CPSW1_CPTS_OFFSET       0x500
  66 #define CPSW1_ALE_OFFSET        0x600
  67 #define CPSW1_SLIVER_OFFSET     0x700
  68 
  69 #define CPSW2_HOST_PORT_OFFSET  0x108
  70 #define CPSW2_SLAVE_OFFSET      0x200
  71 #define CPSW2_SLAVE_SIZE        0x100
  72 #define CPSW2_CPDMA_OFFSET      0x800
  73 #define CPSW2_HW_STATS          0x900
  74 #define CPSW2_STATERAM_OFFSET   0xa00
  75 #define CPSW2_CPTS_OFFSET       0xc00
  76 #define CPSW2_ALE_OFFSET        0xd00
  77 #define CPSW2_SLIVER_OFFSET     0xd80
  78 #define CPSW2_BD_OFFSET         0x2000
  79 
  80 #define CPDMA_RXTHRESH          0x0c0
  81 #define CPDMA_RXFREE            0x0e0
  82 #define CPDMA_TXHDP             0x00
  83 #define CPDMA_RXHDP             0x20
  84 #define CPDMA_TXCP              0x40
  85 #define CPDMA_RXCP              0x60
  86 
  87 #define CPSW_POLL_WEIGHT        64
  88 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
  89 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
  90 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
  91                                  ETH_FCS_LEN +\
  92                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
  93 
  94 #define RX_PRIORITY_MAPPING     0x76543210
  95 #define TX_PRIORITY_MAPPING     0x33221100
  96 #define CPDMA_TX_PRIORITY_MAP   0x76543210
  97 
  98 #define CPSW_VLAN_AWARE         BIT(1)
  99 #define CPSW_RX_VLAN_ENCAP      BIT(2)
 100 #define CPSW_ALE_VLAN_AWARE     1
 101 
 102 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 103 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 104 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 105 
 106 #define CPSW_INTPACEEN          (0x3f << 16)
 107 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 108 #define CPSW_CMINTMAX_CNT       63
 109 #define CPSW_CMINTMIN_CNT       2
 110 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 111 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 112 
 113 #define IRQ_NUM                 2
 114 #define CPSW_MAX_QUEUES         8
 115 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 116 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
 117 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
 118 #define CPSW_FIFO_RATE_EN_SHIFT         20
 119 #define CPSW_TC_NUM                     4
 120 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
 121 #define CPSW_PCT_MASK                   0x7f
 122 
 123 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
 124 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
 125 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
 126 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
 127 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
 128 enum {
 129         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
 130         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
 131         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
 132         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
 133 };
 134 
 135 struct cpsw_wr_regs {
 136         u32     id_ver;
 137         u32     soft_reset;
 138         u32     control;
 139         u32     int_control;
 140         u32     rx_thresh_en;
 141         u32     rx_en;
 142         u32     tx_en;
 143         u32     misc_en;
 144         u32     mem_allign1[8];
 145         u32     rx_thresh_stat;
 146         u32     rx_stat;
 147         u32     tx_stat;
 148         u32     misc_stat;
 149         u32     mem_allign2[8];
 150         u32     rx_imax;
 151         u32     tx_imax;
 152 
 153 };
 154 
 155 struct cpsw_ss_regs {
 156         u32     id_ver;
 157         u32     control;
 158         u32     soft_reset;
 159         u32     stat_port_en;
 160         u32     ptype;
 161         u32     soft_idle;
 162         u32     thru_rate;
 163         u32     gap_thresh;
 164         u32     tx_start_wds;
 165         u32     flow_control;
 166         u32     vlan_ltype;
 167         u32     ts_ltype;
 168         u32     dlr_ltype;
 169 };
 170 
 171 /* CPSW_PORT_V1 */
 172 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 173 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 174 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 175 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 176 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 177 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 178 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 179 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 180 
 181 /* CPSW_PORT_V2 */
 182 #define CPSW2_CONTROL       0x00 /* Control Register */
 183 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 184 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 185 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 186 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 187 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 188 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 189 
 190 /* CPSW_PORT_V1 and V2 */
 191 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 192 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 193 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 194 
 195 /* CPSW_PORT_V2 only */
 196 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 197 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 198 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 199 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 200 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 201 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 202 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 203 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 204 
 205 /* Bit definitions for the CPSW2_CONTROL register */
 206 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
 207 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
 208 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
 209 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
 210 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
 211 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
 212 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
 213 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
 214 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
 215 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
 216 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
 217 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
 218 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
 219 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
 220 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
 221 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
 222 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
 223 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
 224 
 225 #define CTRL_V2_TS_BITS \
 226         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 227          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
 228 
 229 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 230 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 231 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 232 
 233 
 234 #define CTRL_V3_TS_BITS \
 235         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 236          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 237          TS_LTYPE1_EN | VLAN_LTYPE1_EN)
 238 
 239 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 240 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 241 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 242 
 243 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 244 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 245 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 246 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 247 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 248 
 249 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 250 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 251 
 252 /* Bit definitions for the CPSW1_TS_CTL register */
 253 #define CPSW_V1_TS_RX_EN                BIT(0)
 254 #define CPSW_V1_TS_TX_EN                BIT(4)
 255 #define CPSW_V1_MSG_TYPE_OFS            16
 256 
 257 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 258 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 259 
 260 #define CPSW_MAX_BLKS_TX                15
 261 #define CPSW_MAX_BLKS_TX_SHIFT          4
 262 #define CPSW_MAX_BLKS_RX                5
 263 
 264 struct cpsw_host_regs {
 265         u32     max_blks;
 266         u32     blk_cnt;
 267         u32     tx_in_ctl;
 268         u32     port_vlan;
 269         u32     tx_pri_map;
 270         u32     cpdma_tx_pri_map;
 271         u32     cpdma_rx_chan_map;
 272 };
 273 
 274 struct cpsw_slave_data {
 275         struct device_node *slave_node;
 276         struct device_node *phy_node;
 277         char            phy_id[MII_BUS_ID_SIZE];
 278         int             phy_if;
 279         u8              mac_addr[ETH_ALEN];
 280         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 281         struct phy      *ifphy;
 282 };
 283 
 284 struct cpsw_platform_data {
 285         struct cpsw_slave_data  *slave_data;
 286         u32     ss_reg_ofs;     /* Subsystem control register offset */
 287         u32     channels;       /* number of cpdma channels (symmetric) */
 288         u32     slaves;         /* number of slave cpgmac ports */
 289         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 290         u32     ale_entries;    /* ale table size */
 291         u32     bd_ram_size;  /*buffer descriptor ram size */
 292         u32     mac_control;    /* Mac control register */
 293         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 294         bool    dual_emac;      /* Enable Dual EMAC mode */
 295 };
 296 
 297 struct cpsw_slave {
 298         void __iomem                    *regs;
 299         int                             slave_num;
 300         u32                             mac_control;
 301         struct cpsw_slave_data          *data;
 302         struct phy_device               *phy;
 303         struct net_device               *ndev;
 304         u32                             port_vlan;
 305         struct cpsw_sl                  *mac_sl;
 306 };
 307 
 308 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 309 {
 310         return readl_relaxed(slave->regs + offset);
 311 }
 312 
 313 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 314 {
 315         writel_relaxed(val, slave->regs + offset);
 316 }
 317 
 318 struct cpsw_vector {
 319         struct cpdma_chan *ch;
 320         int budget;
 321 };
 322 
 323 struct cpsw_common {
 324         struct device                   *dev;
 325         struct cpsw_platform_data       data;
 326         struct napi_struct              napi_rx;
 327         struct napi_struct              napi_tx;
 328         struct cpsw_ss_regs __iomem     *regs;
 329         struct cpsw_wr_regs __iomem     *wr_regs;
 330         u8 __iomem                      *hw_stats;
 331         struct cpsw_host_regs __iomem   *host_port_regs;
 332         u32                             version;
 333         u32                             coal_intvl;
 334         u32                             bus_freq_mhz;
 335         int                             rx_packet_max;
 336         int                             descs_pool_size;
 337         struct cpsw_slave               *slaves;
 338         struct cpdma_ctlr               *dma;
 339         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 340         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 341         struct cpsw_ale                 *ale;
 342         bool                            quirk_irq;
 343         bool                            rx_irq_disabled;
 344         bool                            tx_irq_disabled;
 345         u32 irqs_table[IRQ_NUM];
 346         struct cpts                     *cpts;
 347         int                             rx_ch_num, tx_ch_num;
 348         int                             speed;
 349         int                             usage_count;
 350         struct page_pool                *page_pool[CPSW_MAX_QUEUES];
 351 };
 352 
 353 struct cpsw_priv {
 354         struct net_device               *ndev;
 355         struct device                   *dev;
 356         u32                             msg_enable;
 357         u8                              mac_addr[ETH_ALEN];
 358         bool                            rx_pause;
 359         bool                            tx_pause;
 360         bool                            mqprio_hw;
 361         int                             fifo_bw[CPSW_TC_NUM];
 362         int                             shp_cfg_speed;
 363         int                             tx_ts_enabled;
 364         int                             rx_ts_enabled;
 365         struct bpf_prog                 *xdp_prog;
 366         struct xdp_rxq_info             xdp_rxq[CPSW_MAX_QUEUES];
 367         struct xdp_attachment_info      xdpi;
 368 
 369         u32 emac_port;
 370         struct cpsw_common *cpsw;
 371 };
 372 
 373 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 374 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 375 
 376 #define cpsw_slave_index(cpsw, priv)                            \
 377                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 378                 cpsw->data.active_slave)
 379 
 380 static inline int cpsw_get_slave_port(u32 slave_num)
 381 {
 382         return slave_num + 1;
 383 }
 384 
 385 struct addr_sync_ctx {
 386         struct net_device *ndev;
 387         const u8 *addr;         /* address to be synched */
 388         int consumed;           /* number of address instances */
 389         int flush;              /* flush flag */
 390 };
 391 
 392 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
 393                      int ale_ageout, phys_addr_t desc_mem_phys,
 394                      int descs_pool_size);
 395 void cpsw_split_res(struct cpsw_common *cpsw);
 396 int cpsw_fill_rx_channels(struct cpsw_priv *priv);
 397 void cpsw_intr_enable(struct cpsw_common *cpsw);
 398 void cpsw_intr_disable(struct cpsw_common *cpsw);
 399 void cpsw_tx_handler(void *token, int len, int status);
 400 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw);
 401 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw);
 402 
 403 /* ethtool */
 404 u32 cpsw_get_msglevel(struct net_device *ndev);
 405 void cpsw_set_msglevel(struct net_device *ndev, u32 value);
 406 int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
 407 int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
 408 int cpsw_get_sset_count(struct net_device *ndev, int sset);
 409 void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
 410 void cpsw_get_ethtool_stats(struct net_device *ndev,
 411                             struct ethtool_stats *stats, u64 *data);
 412 void cpsw_get_pauseparam(struct net_device *ndev,
 413                          struct ethtool_pauseparam *pause);
 414 void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
 415 int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
 416 int cpsw_get_regs_len(struct net_device *ndev);
 417 void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
 418 int cpsw_ethtool_op_begin(struct net_device *ndev);
 419 void cpsw_ethtool_op_complete(struct net_device *ndev);
 420 void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
 421 int cpsw_get_link_ksettings(struct net_device *ndev,
 422                             struct ethtool_link_ksettings *ecmd);
 423 int cpsw_set_link_ksettings(struct net_device *ndev,
 424                             const struct ethtool_link_ksettings *ecmd);
 425 int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata);
 426 int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata);
 427 int cpsw_nway_reset(struct net_device *ndev);
 428 void cpsw_get_ringparam(struct net_device *ndev,
 429                         struct ethtool_ringparam *ering);
 430 int cpsw_set_ringparam(struct net_device *ndev,
 431                        struct ethtool_ringparam *ering);
 432 int cpsw_set_channels_common(struct net_device *ndev,
 433                              struct ethtool_channels *chs,
 434                              cpdma_handler_fn rx_handler);
 435 int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info);
 436 
 437 #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/ti/cpsw_priv.h

INCLUDED FROM

DEFINITIONS
