root/drivers/net/ethernet/micrel/ksz884x.c

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DEFINITIONS

This source file includes following definitions.
  1. hw_ack_intr
  2. hw_dis_intr
  3. hw_set_intr
  4. hw_ena_intr
  5. hw_dis_intr_bit
  6. hw_turn_off_intr
  7. hw_turn_on_intr
  8. hw_ena_intr_bit
  9. hw_read_intr
  10. hw_restore_intr
  11. hw_block_intr
  12. reset_desc
  13. release_desc
  14. get_rx_pkt
  15. set_rx_buf
  16. set_rx_len
  17. get_tx_pkt
  18. set_tx_buf
  19. set_tx_len
  20. sw_r_table
  21. sw_w_table_64
  22. sw_w_sta_mac_table
  23. sw_r_vlan_table
  24. port_r_mib_cnt
  25. port_r_mib_pkt
  26. port_r_cnt
  27. port_init_cnt
  28. port_chk
  29. port_cfg
  30. port_chk_shift
  31. port_cfg_shift
  32. port_r8
  33. port_r16
  34. port_w16
  35. sw_chk
  36. sw_cfg
  37. port_cfg_broad_storm
  38. port_chk_broad_storm
  39. sw_cfg_broad_storm
  40. sw_get_broad_storm
  41. sw_dis_broad_storm
  42. sw_ena_broad_storm
  43. sw_init_broad_storm
  44. hw_cfg_broad_storm
  45. sw_dis_prio_rate
  46. sw_init_prio_rate
  47. port_cfg_back_pressure
  48. port_cfg_force_flow_ctrl
  49. port_chk_back_pressure
  50. port_chk_force_flow_ctrl
  51. port_cfg_rx
  52. port_cfg_tx
  53. sw_cfg_fast_aging
  54. sw_flush_dyn_mac_table
  55. port_cfg_ins_tag
  56. port_cfg_rmv_tag
  57. port_chk_ins_tag
  58. port_chk_rmv_tag
  59. port_cfg_dis_non_vid
  60. port_cfg_in_filter
  61. port_chk_dis_non_vid
  62. port_chk_in_filter
  63. port_cfg_mirror_sniffer
  64. port_cfg_mirror_rx
  65. port_cfg_mirror_tx
  66. sw_cfg_mirror_rx_tx
  67. sw_init_mirror
  68. sw_cfg_unk_def_deliver
  69. sw_cfg_chk_unk_def_deliver
  70. sw_cfg_unk_def_port
  71. sw_chk_unk_def_port
  72. port_cfg_diffserv
  73. port_cfg_802_1p
  74. port_cfg_replace_vid
  75. port_cfg_prio
  76. port_chk_diffserv
  77. port_chk_802_1p
  78. port_chk_replace_vid
  79. port_chk_prio
  80. sw_dis_diffserv
  81. sw_dis_802_1p
  82. sw_cfg_replace_null_vid
  83. sw_cfg_replace_vid
  84. sw_cfg_port_based
  85. sw_dis_multi_queue
  86. sw_init_prio
  87. port_get_def_vid
  88. sw_init_vlan
  89. sw_cfg_port_base_vlan
  90. sw_get_addr
  91. sw_set_addr
  92. sw_set_global_ctrl
  93. port_set_stp_state
  94. sw_clr_sta_mac_table
  95. sw_init_stp
  96. sw_block_addr
  97. hw_r_phy_ctrl
  98. hw_w_phy_ctrl
  99. hw_r_phy_link_stat
  100. hw_r_phy_auto_neg
  101. hw_w_phy_auto_neg
  102. hw_r_phy_rem_cap
  103. hw_r_phy_crossover
  104. hw_w_phy_crossover
  105. hw_r_phy_polarity
  106. hw_w_phy_polarity
  107. hw_r_phy_link_md
  108. hw_w_phy_link_md
  109. hw_r_phy
  110. hw_w_phy
  111. drop_gpio
  112. raise_gpio
  113. state_gpio
  114. eeprom_clk
  115. spi_r
  116. spi_w
  117. spi_reg
  118. eeprom_read
  119. eeprom_write
  120. advertised_flow_ctrl
  121. set_flow_ctrl
  122. determine_flow_ctrl
  123. port_cfg_change
  124. port_get_link_speed
  125. port_set_link_speed
  126. port_force_link_speed
  127. port_set_power_saving
  128. hw_chk_wol_pme_status
  129. hw_clr_wol_pme_status
  130. hw_cfg_wol_pme
  131. hw_cfg_wol
  132. hw_set_wol_frame
  133. hw_add_wol_arp
  134. hw_add_wol_bcast
  135. hw_add_wol_mcast
  136. hw_add_wol_ucast
  137. hw_enable_wol
  138. hw_init
  139. hw_reset
  140. hw_setup
  141. hw_setup_intr
  142. ksz_check_desc_num
  143. hw_init_desc
  144. hw_set_desc_base
  145. hw_reset_pkts
  146. hw_resume_rx
  147. hw_start_rx
  148. hw_stop_rx
  149. hw_start_tx
  150. hw_stop_tx
  151. hw_disable
  152. hw_enable
  153. hw_alloc_pkt
  154. hw_send_pkt
  155. empty_addr
  156. hw_set_addr
  157. hw_read_addr
  158. hw_ena_add_addr
  159. hw_set_add_addr
  160. hw_add_addr
  161. hw_del_addr
  162. hw_clr_multicast
  163. hw_set_grp_addr
  164. hw_set_multicast
  165. hw_set_promiscuous
  166. sw_enable
  167. sw_setup
  168. ksz_start_timer
  169. ksz_stop_timer
  170. ksz_init_timer
  171. ksz_update_timer
  172. ksz_alloc_soft_desc
  173. ksz_alloc_desc
  174. free_dma_buf
  175. ksz_init_rx_buffers
  176. ksz_alloc_mem
  177. ksz_free_desc
  178. ksz_free_buffers
  179. ksz_free_mem
  180. get_mib_counters
  181. send_packet
  182. transmit_cleanup
  183. tx_done
  184. copy_old_skb
  185. netdev_tx_timeout
  186. csum_verified
  187. rx_proc
  188. dev_rcv_packets
  189. port_rcv_packets
  190. dev_rcv_special
  191. rx_proc_task
  192. tx_proc_task
  193. handle_rx_stop
  194. netdev_intr
  195. netdev_netpoll
  196. bridge_change
  197. netdev_close
  198. hw_cfg_huge_frame
  199. prepare_hardware
  200. set_media_state
  201. netdev_open
  202. netdev_query_statistics
  203. netdev_set_mac_address
  204. dev_set_promiscuous
  205. dev_set_multicast
  206. netdev_set_rx_mode
  207. netdev_change_mtu
  208. netdev_ioctl
  209. mdio_read
  210. mdio_write
  211. netdev_get_link_ksettings
  212. netdev_set_link_ksettings
  213. netdev_nway_reset
  214. netdev_get_link
  215. netdev_get_drvinfo
  216. netdev_get_regs_len
  217. netdev_get_regs
  218. netdev_get_wol
  219. netdev_set_wol
  220. netdev_get_msglevel
  221. netdev_set_msglevel
  222. netdev_get_eeprom_len
  223. netdev_get_eeprom
  224. netdev_set_eeprom
  225. netdev_get_pauseparam
  226. netdev_set_pauseparam
  227. netdev_get_ringparam
  228. netdev_get_strings
  229. netdev_get_sset_count
  230. netdev_get_ethtool_stats
  231. netdev_set_features
  232. update_link
  233. mib_read_work
  234. mib_monitor
  235. dev_monitor
  236. netdev_init
  237. netdev_free
  238. get_mac_addr
  239. read_other_addr
  240. pcidev_init
  241. pcidev_exit
  242. pcidev_resume
  243. pcidev_suspend

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
   4  *
   5  * Copyright (c) 2009-2010 Micrel, Inc.
   6  *      Tristram Ha <Tristram.Ha@micrel.com>
   7  */
   8 
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10 
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/ioport.h>
  16 #include <linux/pci.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/mii.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/ethtool.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/in.h>
  23 #include <linux/ip.h>
  24 #include <linux/if_vlan.h>
  25 #include <linux/crc32.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28 
  29 
  30 /* DMA Registers */
  31 
  32 #define KS_DMA_TX_CTRL                  0x0000
  33 #define DMA_TX_ENABLE                   0x00000001
  34 #define DMA_TX_CRC_ENABLE               0x00000002
  35 #define DMA_TX_PAD_ENABLE               0x00000004
  36 #define DMA_TX_LOOPBACK                 0x00000100
  37 #define DMA_TX_FLOW_ENABLE              0x00000200
  38 #define DMA_TX_CSUM_IP                  0x00010000
  39 #define DMA_TX_CSUM_TCP                 0x00020000
  40 #define DMA_TX_CSUM_UDP                 0x00040000
  41 #define DMA_TX_BURST_SIZE               0x3F000000
  42 
  43 #define KS_DMA_RX_CTRL                  0x0004
  44 #define DMA_RX_ENABLE                   0x00000001
  45 #define KS884X_DMA_RX_MULTICAST         0x00000002
  46 #define DMA_RX_PROMISCUOUS              0x00000004
  47 #define DMA_RX_ERROR                    0x00000008
  48 #define DMA_RX_UNICAST                  0x00000010
  49 #define DMA_RX_ALL_MULTICAST            0x00000020
  50 #define DMA_RX_BROADCAST                0x00000040
  51 #define DMA_RX_FLOW_ENABLE              0x00000200
  52 #define DMA_RX_CSUM_IP                  0x00010000
  53 #define DMA_RX_CSUM_TCP                 0x00020000
  54 #define DMA_RX_CSUM_UDP                 0x00040000
  55 #define DMA_RX_BURST_SIZE               0x3F000000
  56 
  57 #define DMA_BURST_SHIFT                 24
  58 #define DMA_BURST_DEFAULT               8
  59 
  60 #define KS_DMA_TX_START                 0x0008
  61 #define KS_DMA_RX_START                 0x000C
  62 #define DMA_START                       0x00000001
  63 
  64 #define KS_DMA_TX_ADDR                  0x0010
  65 #define KS_DMA_RX_ADDR                  0x0014
  66 
  67 #define DMA_ADDR_LIST_MASK              0xFFFFFFFC
  68 #define DMA_ADDR_LIST_SHIFT             2
  69 
  70 /* MTR0 */
  71 #define KS884X_MULTICAST_0_OFFSET       0x0020
  72 #define KS884X_MULTICAST_1_OFFSET       0x0021
  73 #define KS884X_MULTICAST_2_OFFSET       0x0022
  74 #define KS884x_MULTICAST_3_OFFSET       0x0023
  75 /* MTR1 */
  76 #define KS884X_MULTICAST_4_OFFSET       0x0024
  77 #define KS884X_MULTICAST_5_OFFSET       0x0025
  78 #define KS884X_MULTICAST_6_OFFSET       0x0026
  79 #define KS884X_MULTICAST_7_OFFSET       0x0027
  80 
  81 /* Interrupt Registers */
  82 
  83 /* INTEN */
  84 #define KS884X_INTERRUPTS_ENABLE        0x0028
  85 /* INTST */
  86 #define KS884X_INTERRUPTS_STATUS        0x002C
  87 
  88 #define KS884X_INT_RX_STOPPED           0x02000000
  89 #define KS884X_INT_TX_STOPPED           0x04000000
  90 #define KS884X_INT_RX_OVERRUN           0x08000000
  91 #define KS884X_INT_TX_EMPTY             0x10000000
  92 #define KS884X_INT_RX                   0x20000000
  93 #define KS884X_INT_TX                   0x40000000
  94 #define KS884X_INT_PHY                  0x80000000
  95 
  96 #define KS884X_INT_RX_MASK              \
  97         (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
  98 #define KS884X_INT_TX_MASK              \
  99         (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
 100 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
 101 
 102 /* MAC Additional Station Address */
 103 
 104 /* MAAL0 */
 105 #define KS_ADD_ADDR_0_LO                0x0080
 106 /* MAAH0 */
 107 #define KS_ADD_ADDR_0_HI                0x0084
 108 /* MAAL1 */
 109 #define KS_ADD_ADDR_1_LO                0x0088
 110 /* MAAH1 */
 111 #define KS_ADD_ADDR_1_HI                0x008C
 112 /* MAAL2 */
 113 #define KS_ADD_ADDR_2_LO                0x0090
 114 /* MAAH2 */
 115 #define KS_ADD_ADDR_2_HI                0x0094
 116 /* MAAL3 */
 117 #define KS_ADD_ADDR_3_LO                0x0098
 118 /* MAAH3 */
 119 #define KS_ADD_ADDR_3_HI                0x009C
 120 /* MAAL4 */
 121 #define KS_ADD_ADDR_4_LO                0x00A0
 122 /* MAAH4 */
 123 #define KS_ADD_ADDR_4_HI                0x00A4
 124 /* MAAL5 */
 125 #define KS_ADD_ADDR_5_LO                0x00A8
 126 /* MAAH5 */
 127 #define KS_ADD_ADDR_5_HI                0x00AC
 128 /* MAAL6 */
 129 #define KS_ADD_ADDR_6_LO                0x00B0
 130 /* MAAH6 */
 131 #define KS_ADD_ADDR_6_HI                0x00B4
 132 /* MAAL7 */
 133 #define KS_ADD_ADDR_7_LO                0x00B8
 134 /* MAAH7 */
 135 #define KS_ADD_ADDR_7_HI                0x00BC
 136 /* MAAL8 */
 137 #define KS_ADD_ADDR_8_LO                0x00C0
 138 /* MAAH8 */
 139 #define KS_ADD_ADDR_8_HI                0x00C4
 140 /* MAAL9 */
 141 #define KS_ADD_ADDR_9_LO                0x00C8
 142 /* MAAH9 */
 143 #define KS_ADD_ADDR_9_HI                0x00CC
 144 /* MAAL10 */
 145 #define KS_ADD_ADDR_A_LO                0x00D0
 146 /* MAAH10 */
 147 #define KS_ADD_ADDR_A_HI                0x00D4
 148 /* MAAL11 */
 149 #define KS_ADD_ADDR_B_LO                0x00D8
 150 /* MAAH11 */
 151 #define KS_ADD_ADDR_B_HI                0x00DC
 152 /* MAAL12 */
 153 #define KS_ADD_ADDR_C_LO                0x00E0
 154 /* MAAH12 */
 155 #define KS_ADD_ADDR_C_HI                0x00E4
 156 /* MAAL13 */
 157 #define KS_ADD_ADDR_D_LO                0x00E8
 158 /* MAAH13 */
 159 #define KS_ADD_ADDR_D_HI                0x00EC
 160 /* MAAL14 */
 161 #define KS_ADD_ADDR_E_LO                0x00F0
 162 /* MAAH14 */
 163 #define KS_ADD_ADDR_E_HI                0x00F4
 164 /* MAAL15 */
 165 #define KS_ADD_ADDR_F_LO                0x00F8
 166 /* MAAH15 */
 167 #define KS_ADD_ADDR_F_HI                0x00FC
 168 
 169 #define ADD_ADDR_HI_MASK                0x0000FFFF
 170 #define ADD_ADDR_ENABLE                 0x80000000
 171 #define ADD_ADDR_INCR                   8
 172 
 173 /* Miscellaneous Registers */
 174 
 175 /* MARL */
 176 #define KS884X_ADDR_0_OFFSET            0x0200
 177 #define KS884X_ADDR_1_OFFSET            0x0201
 178 /* MARM */
 179 #define KS884X_ADDR_2_OFFSET            0x0202
 180 #define KS884X_ADDR_3_OFFSET            0x0203
 181 /* MARH */
 182 #define KS884X_ADDR_4_OFFSET            0x0204
 183 #define KS884X_ADDR_5_OFFSET            0x0205
 184 
 185 /* OBCR */
 186 #define KS884X_BUS_CTRL_OFFSET          0x0210
 187 
 188 #define BUS_SPEED_125_MHZ               0x0000
 189 #define BUS_SPEED_62_5_MHZ              0x0001
 190 #define BUS_SPEED_41_66_MHZ             0x0002
 191 #define BUS_SPEED_25_MHZ                0x0003
 192 
 193 /* EEPCR */
 194 #define KS884X_EEPROM_CTRL_OFFSET       0x0212
 195 
 196 #define EEPROM_CHIP_SELECT              0x0001
 197 #define EEPROM_SERIAL_CLOCK             0x0002
 198 #define EEPROM_DATA_OUT                 0x0004
 199 #define EEPROM_DATA_IN                  0x0008
 200 #define EEPROM_ACCESS_ENABLE            0x0010
 201 
 202 /* MBIR */
 203 #define KS884X_MEM_INFO_OFFSET          0x0214
 204 
 205 #define RX_MEM_TEST_FAILED              0x0008
 206 #define RX_MEM_TEST_FINISHED            0x0010
 207 #define TX_MEM_TEST_FAILED              0x0800
 208 #define TX_MEM_TEST_FINISHED            0x1000
 209 
 210 /* GCR */
 211 #define KS884X_GLOBAL_CTRL_OFFSET       0x0216
 212 #define GLOBAL_SOFTWARE_RESET           0x0001
 213 
 214 #define KS8841_POWER_MANAGE_OFFSET      0x0218
 215 
 216 /* WFCR */
 217 #define KS8841_WOL_CTRL_OFFSET          0x021A
 218 #define KS8841_WOL_MAGIC_ENABLE         0x0080
 219 #define KS8841_WOL_FRAME3_ENABLE        0x0008
 220 #define KS8841_WOL_FRAME2_ENABLE        0x0004
 221 #define KS8841_WOL_FRAME1_ENABLE        0x0002
 222 #define KS8841_WOL_FRAME0_ENABLE        0x0001
 223 
 224 /* WF0 */
 225 #define KS8841_WOL_FRAME_CRC_OFFSET     0x0220
 226 #define KS8841_WOL_FRAME_BYTE0_OFFSET   0x0224
 227 #define KS8841_WOL_FRAME_BYTE2_OFFSET   0x0228
 228 
 229 /* IACR */
 230 #define KS884X_IACR_P                   0x04A0
 231 #define KS884X_IACR_OFFSET              KS884X_IACR_P
 232 
 233 /* IADR1 */
 234 #define KS884X_IADR1_P                  0x04A2
 235 #define KS884X_IADR2_P                  0x04A4
 236 #define KS884X_IADR3_P                  0x04A6
 237 #define KS884X_IADR4_P                  0x04A8
 238 #define KS884X_IADR5_P                  0x04AA
 239 
 240 #define KS884X_ACC_CTRL_SEL_OFFSET      KS884X_IACR_P
 241 #define KS884X_ACC_CTRL_INDEX_OFFSET    (KS884X_ACC_CTRL_SEL_OFFSET + 1)
 242 
 243 #define KS884X_ACC_DATA_0_OFFSET        KS884X_IADR4_P
 244 #define KS884X_ACC_DATA_1_OFFSET        (KS884X_ACC_DATA_0_OFFSET + 1)
 245 #define KS884X_ACC_DATA_2_OFFSET        KS884X_IADR5_P
 246 #define KS884X_ACC_DATA_3_OFFSET        (KS884X_ACC_DATA_2_OFFSET + 1)
 247 #define KS884X_ACC_DATA_4_OFFSET        KS884X_IADR2_P
 248 #define KS884X_ACC_DATA_5_OFFSET        (KS884X_ACC_DATA_4_OFFSET + 1)
 249 #define KS884X_ACC_DATA_6_OFFSET        KS884X_IADR3_P
 250 #define KS884X_ACC_DATA_7_OFFSET        (KS884X_ACC_DATA_6_OFFSET + 1)
 251 #define KS884X_ACC_DATA_8_OFFSET        KS884X_IADR1_P
 252 
 253 /* P1MBCR */
 254 #define KS884X_P1MBCR_P                 0x04D0
 255 #define KS884X_P1MBSR_P                 0x04D2
 256 #define KS884X_PHY1ILR_P                0x04D4
 257 #define KS884X_PHY1IHR_P                0x04D6
 258 #define KS884X_P1ANAR_P                 0x04D8
 259 #define KS884X_P1ANLPR_P                0x04DA
 260 
 261 /* P2MBCR */
 262 #define KS884X_P2MBCR_P                 0x04E0
 263 #define KS884X_P2MBSR_P                 0x04E2
 264 #define KS884X_PHY2ILR_P                0x04E4
 265 #define KS884X_PHY2IHR_P                0x04E6
 266 #define KS884X_P2ANAR_P                 0x04E8
 267 #define KS884X_P2ANLPR_P                0x04EA
 268 
 269 #define KS884X_PHY_1_CTRL_OFFSET        KS884X_P1MBCR_P
 270 #define PHY_CTRL_INTERVAL               (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
 271 
 272 #define KS884X_PHY_CTRL_OFFSET          0x00
 273 
 274 /* Mode Control Register */
 275 #define PHY_REG_CTRL                    0
 276 
 277 #define PHY_RESET                       0x8000
 278 #define PHY_LOOPBACK                    0x4000
 279 #define PHY_SPEED_100MBIT               0x2000
 280 #define PHY_AUTO_NEG_ENABLE             0x1000
 281 #define PHY_POWER_DOWN                  0x0800
 282 #define PHY_MII_DISABLE                 0x0400
 283 #define PHY_AUTO_NEG_RESTART            0x0200
 284 #define PHY_FULL_DUPLEX                 0x0100
 285 #define PHY_COLLISION_TEST              0x0080
 286 #define PHY_HP_MDIX                     0x0020
 287 #define PHY_FORCE_MDIX                  0x0010
 288 #define PHY_AUTO_MDIX_DISABLE           0x0008
 289 #define PHY_REMOTE_FAULT_DISABLE        0x0004
 290 #define PHY_TRANSMIT_DISABLE            0x0002
 291 #define PHY_LED_DISABLE                 0x0001
 292 
 293 #define KS884X_PHY_STATUS_OFFSET        0x02
 294 
 295 /* Mode Status Register */
 296 #define PHY_REG_STATUS                  1
 297 
 298 #define PHY_100BT4_CAPABLE              0x8000
 299 #define PHY_100BTX_FD_CAPABLE           0x4000
 300 #define PHY_100BTX_CAPABLE              0x2000
 301 #define PHY_10BT_FD_CAPABLE             0x1000
 302 #define PHY_10BT_CAPABLE                0x0800
 303 #define PHY_MII_SUPPRESS_CAPABLE        0x0040
 304 #define PHY_AUTO_NEG_ACKNOWLEDGE        0x0020
 305 #define PHY_REMOTE_FAULT                0x0010
 306 #define PHY_AUTO_NEG_CAPABLE            0x0008
 307 #define PHY_LINK_STATUS                 0x0004
 308 #define PHY_JABBER_DETECT               0x0002
 309 #define PHY_EXTENDED_CAPABILITY         0x0001
 310 
 311 #define KS884X_PHY_ID_1_OFFSET          0x04
 312 #define KS884X_PHY_ID_2_OFFSET          0x06
 313 
 314 /* PHY Identifier Registers */
 315 #define PHY_REG_ID_1                    2
 316 #define PHY_REG_ID_2                    3
 317 
 318 #define KS884X_PHY_AUTO_NEG_OFFSET      0x08
 319 
 320 /* Auto-Negotiation Advertisement Register */
 321 #define PHY_REG_AUTO_NEGOTIATION        4
 322 
 323 #define PHY_AUTO_NEG_NEXT_PAGE          0x8000
 324 #define PHY_AUTO_NEG_REMOTE_FAULT       0x2000
 325 /* Not supported. */
 326 #define PHY_AUTO_NEG_ASYM_PAUSE         0x0800
 327 #define PHY_AUTO_NEG_SYM_PAUSE          0x0400
 328 #define PHY_AUTO_NEG_100BT4             0x0200
 329 #define PHY_AUTO_NEG_100BTX_FD          0x0100
 330 #define PHY_AUTO_NEG_100BTX             0x0080
 331 #define PHY_AUTO_NEG_10BT_FD            0x0040
 332 #define PHY_AUTO_NEG_10BT               0x0020
 333 #define PHY_AUTO_NEG_SELECTOR           0x001F
 334 #define PHY_AUTO_NEG_802_3              0x0001
 335 
 336 #define PHY_AUTO_NEG_PAUSE  (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
 337 
 338 #define KS884X_PHY_REMOTE_CAP_OFFSET    0x0A
 339 
 340 /* Auto-Negotiation Link Partner Ability Register */
 341 #define PHY_REG_REMOTE_CAPABILITY       5
 342 
 343 #define PHY_REMOTE_NEXT_PAGE            0x8000
 344 #define PHY_REMOTE_ACKNOWLEDGE          0x4000
 345 #define PHY_REMOTE_REMOTE_FAULT         0x2000
 346 #define PHY_REMOTE_SYM_PAUSE            0x0400
 347 #define PHY_REMOTE_100BTX_FD            0x0100
 348 #define PHY_REMOTE_100BTX               0x0080
 349 #define PHY_REMOTE_10BT_FD              0x0040
 350 #define PHY_REMOTE_10BT                 0x0020
 351 
 352 /* P1VCT */
 353 #define KS884X_P1VCT_P                  0x04F0
 354 #define KS884X_P1PHYCTRL_P              0x04F2
 355 
 356 /* P2VCT */
 357 #define KS884X_P2VCT_P                  0x04F4
 358 #define KS884X_P2PHYCTRL_P              0x04F6
 359 
 360 #define KS884X_PHY_SPECIAL_OFFSET       KS884X_P1VCT_P
 361 #define PHY_SPECIAL_INTERVAL            (KS884X_P2VCT_P - KS884X_P1VCT_P)
 362 
 363 #define KS884X_PHY_LINK_MD_OFFSET       0x00
 364 
 365 #define PHY_START_CABLE_DIAG            0x8000
 366 #define PHY_CABLE_DIAG_RESULT           0x6000
 367 #define PHY_CABLE_STAT_NORMAL           0x0000
 368 #define PHY_CABLE_STAT_OPEN             0x2000
 369 #define PHY_CABLE_STAT_SHORT            0x4000
 370 #define PHY_CABLE_STAT_FAILED           0x6000
 371 #define PHY_CABLE_10M_SHORT             0x1000
 372 #define PHY_CABLE_FAULT_COUNTER         0x01FF
 373 
 374 #define KS884X_PHY_PHY_CTRL_OFFSET      0x02
 375 
 376 #define PHY_STAT_REVERSED_POLARITY      0x0020
 377 #define PHY_STAT_MDIX                   0x0010
 378 #define PHY_FORCE_LINK                  0x0008
 379 #define PHY_POWER_SAVING_DISABLE        0x0004
 380 #define PHY_REMOTE_LOOPBACK             0x0002
 381 
 382 /* SIDER */
 383 #define KS884X_SIDER_P                  0x0400
 384 #define KS884X_CHIP_ID_OFFSET           KS884X_SIDER_P
 385 #define KS884X_FAMILY_ID_OFFSET         (KS884X_CHIP_ID_OFFSET + 1)
 386 
 387 #define REG_FAMILY_ID                   0x88
 388 
 389 #define REG_CHIP_ID_41                  0x8810
 390 #define REG_CHIP_ID_42                  0x8800
 391 
 392 #define KS884X_CHIP_ID_MASK_41          0xFF10
 393 #define KS884X_CHIP_ID_MASK             0xFFF0
 394 #define KS884X_CHIP_ID_SHIFT            4
 395 #define KS884X_REVISION_MASK            0x000E
 396 #define KS884X_REVISION_SHIFT           1
 397 #define KS8842_START                    0x0001
 398 
 399 #define CHIP_IP_41_M                    0x8810
 400 #define CHIP_IP_42_M                    0x8800
 401 #define CHIP_IP_61_M                    0x8890
 402 #define CHIP_IP_62_M                    0x8880
 403 
 404 #define CHIP_IP_41_P                    0x8850
 405 #define CHIP_IP_42_P                    0x8840
 406 #define CHIP_IP_61_P                    0x88D0
 407 #define CHIP_IP_62_P                    0x88C0
 408 
 409 /* SGCR1 */
 410 #define KS8842_SGCR1_P                  0x0402
 411 #define KS8842_SWITCH_CTRL_1_OFFSET     KS8842_SGCR1_P
 412 
 413 #define SWITCH_PASS_ALL                 0x8000
 414 #define SWITCH_TX_FLOW_CTRL             0x2000
 415 #define SWITCH_RX_FLOW_CTRL             0x1000
 416 #define SWITCH_CHECK_LENGTH             0x0800
 417 #define SWITCH_AGING_ENABLE             0x0400
 418 #define SWITCH_FAST_AGING               0x0200
 419 #define SWITCH_AGGR_BACKOFF             0x0100
 420 #define SWITCH_PASS_PAUSE               0x0008
 421 #define SWITCH_LINK_AUTO_AGING          0x0001
 422 
 423 /* SGCR2 */
 424 #define KS8842_SGCR2_P                  0x0404
 425 #define KS8842_SWITCH_CTRL_2_OFFSET     KS8842_SGCR2_P
 426 
 427 #define SWITCH_VLAN_ENABLE              0x8000
 428 #define SWITCH_IGMP_SNOOP               0x4000
 429 #define IPV6_MLD_SNOOP_ENABLE           0x2000
 430 #define IPV6_MLD_SNOOP_OPTION           0x1000
 431 #define PRIORITY_SCHEME_SELECT          0x0800
 432 #define SWITCH_MIRROR_RX_TX             0x0100
 433 #define UNICAST_VLAN_BOUNDARY           0x0080
 434 #define MULTICAST_STORM_DISABLE         0x0040
 435 #define SWITCH_BACK_PRESSURE            0x0020
 436 #define FAIR_FLOW_CTRL                  0x0010
 437 #define NO_EXC_COLLISION_DROP           0x0008
 438 #define SWITCH_HUGE_PACKET              0x0004
 439 #define SWITCH_LEGAL_PACKET             0x0002
 440 #define SWITCH_BUF_RESERVE              0x0001
 441 
 442 /* SGCR3 */
 443 #define KS8842_SGCR3_P                  0x0406
 444 #define KS8842_SWITCH_CTRL_3_OFFSET     KS8842_SGCR3_P
 445 
 446 #define BROADCAST_STORM_RATE_LO         0xFF00
 447 #define SWITCH_REPEATER                 0x0080
 448 #define SWITCH_HALF_DUPLEX              0x0040
 449 #define SWITCH_FLOW_CTRL                0x0020
 450 #define SWITCH_10_MBIT                  0x0010
 451 #define SWITCH_REPLACE_NULL_VID         0x0008
 452 #define BROADCAST_STORM_RATE_HI         0x0007
 453 
 454 #define BROADCAST_STORM_RATE            0x07FF
 455 
 456 /* SGCR4 */
 457 #define KS8842_SGCR4_P                  0x0408
 458 
 459 /* SGCR5 */
 460 #define KS8842_SGCR5_P                  0x040A
 461 #define KS8842_SWITCH_CTRL_5_OFFSET     KS8842_SGCR5_P
 462 
 463 #define LED_MODE                        0x8200
 464 #define LED_SPEED_DUPLEX_ACT            0x0000
 465 #define LED_SPEED_DUPLEX_LINK_ACT       0x8000
 466 #define LED_DUPLEX_10_100               0x0200
 467 
 468 /* SGCR6 */
 469 #define KS8842_SGCR6_P                  0x0410
 470 #define KS8842_SWITCH_CTRL_6_OFFSET     KS8842_SGCR6_P
 471 
 472 #define KS8842_PRIORITY_MASK            3
 473 #define KS8842_PRIORITY_SHIFT           2
 474 
 475 /* SGCR7 */
 476 #define KS8842_SGCR7_P                  0x0412
 477 #define KS8842_SWITCH_CTRL_7_OFFSET     KS8842_SGCR7_P
 478 
 479 #define SWITCH_UNK_DEF_PORT_ENABLE      0x0008
 480 #define SWITCH_UNK_DEF_PORT_3           0x0004
 481 #define SWITCH_UNK_DEF_PORT_2           0x0002
 482 #define SWITCH_UNK_DEF_PORT_1           0x0001
 483 
 484 /* MACAR1 */
 485 #define KS8842_MACAR1_P                 0x0470
 486 #define KS8842_MACAR2_P                 0x0472
 487 #define KS8842_MACAR3_P                 0x0474
 488 #define KS8842_MAC_ADDR_1_OFFSET        KS8842_MACAR1_P
 489 #define KS8842_MAC_ADDR_0_OFFSET        (KS8842_MAC_ADDR_1_OFFSET + 1)
 490 #define KS8842_MAC_ADDR_3_OFFSET        KS8842_MACAR2_P
 491 #define KS8842_MAC_ADDR_2_OFFSET        (KS8842_MAC_ADDR_3_OFFSET + 1)
 492 #define KS8842_MAC_ADDR_5_OFFSET        KS8842_MACAR3_P
 493 #define KS8842_MAC_ADDR_4_OFFSET        (KS8842_MAC_ADDR_5_OFFSET + 1)
 494 
 495 /* TOSR1 */
 496 #define KS8842_TOSR1_P                  0x0480
 497 #define KS8842_TOSR2_P                  0x0482
 498 #define KS8842_TOSR3_P                  0x0484
 499 #define KS8842_TOSR4_P                  0x0486
 500 #define KS8842_TOSR5_P                  0x0488
 501 #define KS8842_TOSR6_P                  0x048A
 502 #define KS8842_TOSR7_P                  0x0490
 503 #define KS8842_TOSR8_P                  0x0492
 504 #define KS8842_TOS_1_OFFSET             KS8842_TOSR1_P
 505 #define KS8842_TOS_2_OFFSET             KS8842_TOSR2_P
 506 #define KS8842_TOS_3_OFFSET             KS8842_TOSR3_P
 507 #define KS8842_TOS_4_OFFSET             KS8842_TOSR4_P
 508 #define KS8842_TOS_5_OFFSET             KS8842_TOSR5_P
 509 #define KS8842_TOS_6_OFFSET             KS8842_TOSR6_P
 510 
 511 #define KS8842_TOS_7_OFFSET             KS8842_TOSR7_P
 512 #define KS8842_TOS_8_OFFSET             KS8842_TOSR8_P
 513 
 514 /* P1CR1 */
 515 #define KS8842_P1CR1_P                  0x0500
 516 #define KS8842_P1CR2_P                  0x0502
 517 #define KS8842_P1VIDR_P                 0x0504
 518 #define KS8842_P1CR3_P                  0x0506
 519 #define KS8842_P1IRCR_P                 0x0508
 520 #define KS8842_P1ERCR_P                 0x050A
 521 #define KS884X_P1SCSLMD_P               0x0510
 522 #define KS884X_P1CR4_P                  0x0512
 523 #define KS884X_P1SR_P                   0x0514
 524 
 525 /* P2CR1 */
 526 #define KS8842_P2CR1_P                  0x0520
 527 #define KS8842_P2CR2_P                  0x0522
 528 #define KS8842_P2VIDR_P                 0x0524
 529 #define KS8842_P2CR3_P                  0x0526
 530 #define KS8842_P2IRCR_P                 0x0528
 531 #define KS8842_P2ERCR_P                 0x052A
 532 #define KS884X_P2SCSLMD_P               0x0530
 533 #define KS884X_P2CR4_P                  0x0532
 534 #define KS884X_P2SR_P                   0x0534
 535 
 536 /* P3CR1 */
 537 #define KS8842_P3CR1_P                  0x0540
 538 #define KS8842_P3CR2_P                  0x0542
 539 #define KS8842_P3VIDR_P                 0x0544
 540 #define KS8842_P3CR3_P                  0x0546
 541 #define KS8842_P3IRCR_P                 0x0548
 542 #define KS8842_P3ERCR_P                 0x054A
 543 
 544 #define KS8842_PORT_1_CTRL_1            KS8842_P1CR1_P
 545 #define KS8842_PORT_2_CTRL_1            KS8842_P2CR1_P
 546 #define KS8842_PORT_3_CTRL_1            KS8842_P3CR1_P
 547 
 548 #define PORT_CTRL_ADDR(port, addr)              \
 549         (addr = KS8842_PORT_1_CTRL_1 + (port) * \
 550                 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
 551 
 552 #define KS8842_PORT_CTRL_1_OFFSET       0x00
 553 
 554 #define PORT_BROADCAST_STORM            0x0080
 555 #define PORT_DIFFSERV_ENABLE            0x0040
 556 #define PORT_802_1P_ENABLE              0x0020
 557 #define PORT_BASED_PRIORITY_MASK        0x0018
 558 #define PORT_BASED_PRIORITY_BASE        0x0003
 559 #define PORT_BASED_PRIORITY_SHIFT       3
 560 #define PORT_BASED_PRIORITY_0           0x0000
 561 #define PORT_BASED_PRIORITY_1           0x0008
 562 #define PORT_BASED_PRIORITY_2           0x0010
 563 #define PORT_BASED_PRIORITY_3           0x0018
 564 #define PORT_INSERT_TAG                 0x0004
 565 #define PORT_REMOVE_TAG                 0x0002
 566 #define PORT_PRIO_QUEUE_ENABLE          0x0001
 567 
 568 #define KS8842_PORT_CTRL_2_OFFSET       0x02
 569 
 570 #define PORT_INGRESS_VLAN_FILTER        0x4000
 571 #define PORT_DISCARD_NON_VID            0x2000
 572 #define PORT_FORCE_FLOW_CTRL            0x1000
 573 #define PORT_BACK_PRESSURE              0x0800
 574 #define PORT_TX_ENABLE                  0x0400
 575 #define PORT_RX_ENABLE                  0x0200
 576 #define PORT_LEARN_DISABLE              0x0100
 577 #define PORT_MIRROR_SNIFFER             0x0080
 578 #define PORT_MIRROR_RX                  0x0040
 579 #define PORT_MIRROR_TX                  0x0020
 580 #define PORT_USER_PRIORITY_CEILING      0x0008
 581 #define PORT_VLAN_MEMBERSHIP            0x0007
 582 
 583 #define KS8842_PORT_CTRL_VID_OFFSET     0x04
 584 
 585 #define PORT_DEFAULT_VID                0x0001
 586 
 587 #define KS8842_PORT_CTRL_3_OFFSET       0x06
 588 
 589 #define PORT_INGRESS_LIMIT_MODE         0x000C
 590 #define PORT_INGRESS_ALL                0x0000
 591 #define PORT_INGRESS_UNICAST            0x0004
 592 #define PORT_INGRESS_MULTICAST          0x0008
 593 #define PORT_INGRESS_BROADCAST          0x000C
 594 #define PORT_COUNT_IFG                  0x0002
 595 #define PORT_COUNT_PREAMBLE             0x0001
 596 
 597 #define KS8842_PORT_IN_RATE_OFFSET      0x08
 598 #define KS8842_PORT_OUT_RATE_OFFSET     0x0A
 599 
 600 #define PORT_PRIORITY_RATE              0x0F
 601 #define PORT_PRIORITY_RATE_SHIFT        4
 602 
 603 #define KS884X_PORT_LINK_MD             0x10
 604 
 605 #define PORT_CABLE_10M_SHORT            0x8000
 606 #define PORT_CABLE_DIAG_RESULT          0x6000
 607 #define PORT_CABLE_STAT_NORMAL          0x0000
 608 #define PORT_CABLE_STAT_OPEN            0x2000
 609 #define PORT_CABLE_STAT_SHORT           0x4000
 610 #define PORT_CABLE_STAT_FAILED          0x6000
 611 #define PORT_START_CABLE_DIAG           0x1000
 612 #define PORT_FORCE_LINK                 0x0800
 613 #define PORT_POWER_SAVING_DISABLE       0x0400
 614 #define PORT_PHY_REMOTE_LOOPBACK        0x0200
 615 #define PORT_CABLE_FAULT_COUNTER        0x01FF
 616 
 617 #define KS884X_PORT_CTRL_4_OFFSET       0x12
 618 
 619 #define PORT_LED_OFF                    0x8000
 620 #define PORT_TX_DISABLE                 0x4000
 621 #define PORT_AUTO_NEG_RESTART           0x2000
 622 #define PORT_REMOTE_FAULT_DISABLE       0x1000
 623 #define PORT_POWER_DOWN                 0x0800
 624 #define PORT_AUTO_MDIX_DISABLE          0x0400
 625 #define PORT_FORCE_MDIX                 0x0200
 626 #define PORT_LOOPBACK                   0x0100
 627 #define PORT_AUTO_NEG_ENABLE            0x0080
 628 #define PORT_FORCE_100_MBIT             0x0040
 629 #define PORT_FORCE_FULL_DUPLEX          0x0020
 630 #define PORT_AUTO_NEG_SYM_PAUSE         0x0010
 631 #define PORT_AUTO_NEG_100BTX_FD         0x0008
 632 #define PORT_AUTO_NEG_100BTX            0x0004
 633 #define PORT_AUTO_NEG_10BT_FD           0x0002
 634 #define PORT_AUTO_NEG_10BT              0x0001
 635 
 636 #define KS884X_PORT_STATUS_OFFSET       0x14
 637 
 638 #define PORT_HP_MDIX                    0x8000
 639 #define PORT_REVERSED_POLARITY          0x2000
 640 #define PORT_RX_FLOW_CTRL               0x0800
 641 #define PORT_TX_FLOW_CTRL               0x1000
 642 #define PORT_STATUS_SPEED_100MBIT       0x0400
 643 #define PORT_STATUS_FULL_DUPLEX         0x0200
 644 #define PORT_REMOTE_FAULT               0x0100
 645 #define PORT_MDIX_STATUS                0x0080
 646 #define PORT_AUTO_NEG_COMPLETE          0x0040
 647 #define PORT_STATUS_LINK_GOOD           0x0020
 648 #define PORT_REMOTE_SYM_PAUSE           0x0010
 649 #define PORT_REMOTE_100BTX_FD           0x0008
 650 #define PORT_REMOTE_100BTX              0x0004
 651 #define PORT_REMOTE_10BT_FD             0x0002
 652 #define PORT_REMOTE_10BT                0x0001
 653 
 654 /*
 655 #define STATIC_MAC_TABLE_ADDR           00-0000FFFF-FFFFFFFF
 656 #define STATIC_MAC_TABLE_FWD_PORTS      00-00070000-00000000
 657 #define STATIC_MAC_TABLE_VALID          00-00080000-00000000
 658 #define STATIC_MAC_TABLE_OVERRIDE       00-00100000-00000000
 659 #define STATIC_MAC_TABLE_USE_FID        00-00200000-00000000
 660 #define STATIC_MAC_TABLE_FID            00-03C00000-00000000
 661 */
 662 
 663 #define STATIC_MAC_TABLE_ADDR           0x0000FFFF
 664 #define STATIC_MAC_TABLE_FWD_PORTS      0x00070000
 665 #define STATIC_MAC_TABLE_VALID          0x00080000
 666 #define STATIC_MAC_TABLE_OVERRIDE       0x00100000
 667 #define STATIC_MAC_TABLE_USE_FID        0x00200000
 668 #define STATIC_MAC_TABLE_FID            0x03C00000
 669 
 670 #define STATIC_MAC_FWD_PORTS_SHIFT      16
 671 #define STATIC_MAC_FID_SHIFT            22
 672 
 673 /*
 674 #define VLAN_TABLE_VID                  00-00000000-00000FFF
 675 #define VLAN_TABLE_FID                  00-00000000-0000F000
 676 #define VLAN_TABLE_MEMBERSHIP           00-00000000-00070000
 677 #define VLAN_TABLE_VALID                00-00000000-00080000
 678 */
 679 
 680 #define VLAN_TABLE_VID                  0x00000FFF
 681 #define VLAN_TABLE_FID                  0x0000F000
 682 #define VLAN_TABLE_MEMBERSHIP           0x00070000
 683 #define VLAN_TABLE_VALID                0x00080000
 684 
 685 #define VLAN_TABLE_FID_SHIFT            12
 686 #define VLAN_TABLE_MEMBERSHIP_SHIFT     16
 687 
 688 /*
 689 #define DYNAMIC_MAC_TABLE_ADDR          00-0000FFFF-FFFFFFFF
 690 #define DYNAMIC_MAC_TABLE_FID           00-000F0000-00000000
 691 #define DYNAMIC_MAC_TABLE_SRC_PORT      00-00300000-00000000
 692 #define DYNAMIC_MAC_TABLE_TIMESTAMP     00-00C00000-00000000
 693 #define DYNAMIC_MAC_TABLE_ENTRIES       03-FF000000-00000000
 694 #define DYNAMIC_MAC_TABLE_MAC_EMPTY     04-00000000-00000000
 695 #define DYNAMIC_MAC_TABLE_RESERVED      78-00000000-00000000
 696 #define DYNAMIC_MAC_TABLE_NOT_READY     80-00000000-00000000
 697 */
 698 
 699 #define DYNAMIC_MAC_TABLE_ADDR          0x0000FFFF
 700 #define DYNAMIC_MAC_TABLE_FID           0x000F0000
 701 #define DYNAMIC_MAC_TABLE_SRC_PORT      0x00300000
 702 #define DYNAMIC_MAC_TABLE_TIMESTAMP     0x00C00000
 703 #define DYNAMIC_MAC_TABLE_ENTRIES       0xFF000000
 704 
 705 #define DYNAMIC_MAC_TABLE_ENTRIES_H     0x03
 706 #define DYNAMIC_MAC_TABLE_MAC_EMPTY     0x04
 707 #define DYNAMIC_MAC_TABLE_RESERVED      0x78
 708 #define DYNAMIC_MAC_TABLE_NOT_READY     0x80
 709 
 710 #define DYNAMIC_MAC_FID_SHIFT           16
 711 #define DYNAMIC_MAC_SRC_PORT_SHIFT      20
 712 #define DYNAMIC_MAC_TIMESTAMP_SHIFT     22
 713 #define DYNAMIC_MAC_ENTRIES_SHIFT       24
 714 #define DYNAMIC_MAC_ENTRIES_H_SHIFT     8
 715 
 716 /*
 717 #define MIB_COUNTER_VALUE               00-00000000-3FFFFFFF
 718 #define MIB_COUNTER_VALID               00-00000000-40000000
 719 #define MIB_COUNTER_OVERFLOW            00-00000000-80000000
 720 */
 721 
 722 #define MIB_COUNTER_VALUE               0x3FFFFFFF
 723 #define MIB_COUNTER_VALID               0x40000000
 724 #define MIB_COUNTER_OVERFLOW            0x80000000
 725 
 726 #define MIB_PACKET_DROPPED              0x0000FFFF
 727 
 728 #define KS_MIB_PACKET_DROPPED_TX_0      0x100
 729 #define KS_MIB_PACKET_DROPPED_TX_1      0x101
 730 #define KS_MIB_PACKET_DROPPED_TX        0x102
 731 #define KS_MIB_PACKET_DROPPED_RX_0      0x103
 732 #define KS_MIB_PACKET_DROPPED_RX_1      0x104
 733 #define KS_MIB_PACKET_DROPPED_RX        0x105
 734 
 735 /* Change default LED mode. */
 736 #define SET_DEFAULT_LED                 LED_SPEED_DUPLEX_ACT
 737 
 738 #define MAC_ADDR_ORDER(i)               (ETH_ALEN - 1 - (i))
 739 
 740 #define MAX_ETHERNET_BODY_SIZE          1500
 741 #define ETHERNET_HEADER_SIZE            (14 + VLAN_HLEN)
 742 
 743 #define MAX_ETHERNET_PACKET_SIZE        \
 744         (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
 745 
 746 #define REGULAR_RX_BUF_SIZE             (MAX_ETHERNET_PACKET_SIZE + 4)
 747 #define MAX_RX_BUF_SIZE                 (1912 + 4)
 748 
 749 #define ADDITIONAL_ENTRIES              16
 750 #define MAX_MULTICAST_LIST              32
 751 
 752 #define HW_MULTICAST_SIZE               8
 753 
 754 #define HW_TO_DEV_PORT(port)            (port - 1)
 755 
 756 enum {
 757         media_connected,
 758         media_disconnected
 759 };
 760 
 761 enum {
 762         OID_COUNTER_UNKOWN,
 763 
 764         OID_COUNTER_FIRST,
 765 
 766         /* total transmit errors */
 767         OID_COUNTER_XMIT_ERROR,
 768 
 769         /* total receive errors */
 770         OID_COUNTER_RCV_ERROR,
 771 
 772         OID_COUNTER_LAST
 773 };
 774 
 775 /*
 776  * Hardware descriptor definitions
 777  */
 778 
 779 #define DESC_ALIGNMENT                  16
 780 #define BUFFER_ALIGNMENT                8
 781 
 782 #define NUM_OF_RX_DESC                  64
 783 #define NUM_OF_TX_DESC                  64
 784 
 785 #define KS_DESC_RX_FRAME_LEN            0x000007FF
 786 #define KS_DESC_RX_FRAME_TYPE           0x00008000
 787 #define KS_DESC_RX_ERROR_CRC            0x00010000
 788 #define KS_DESC_RX_ERROR_RUNT           0x00020000
 789 #define KS_DESC_RX_ERROR_TOO_LONG       0x00040000
 790 #define KS_DESC_RX_ERROR_PHY            0x00080000
 791 #define KS884X_DESC_RX_PORT_MASK        0x00300000
 792 #define KS_DESC_RX_MULTICAST            0x01000000
 793 #define KS_DESC_RX_ERROR                0x02000000
 794 #define KS_DESC_RX_ERROR_CSUM_UDP       0x04000000
 795 #define KS_DESC_RX_ERROR_CSUM_TCP       0x08000000
 796 #define KS_DESC_RX_ERROR_CSUM_IP        0x10000000
 797 #define KS_DESC_RX_LAST                 0x20000000
 798 #define KS_DESC_RX_FIRST                0x40000000
 799 #define KS_DESC_RX_ERROR_COND           \
 800         (KS_DESC_RX_ERROR_CRC |         \
 801         KS_DESC_RX_ERROR_RUNT |         \
 802         KS_DESC_RX_ERROR_PHY |          \
 803         KS_DESC_RX_ERROR_TOO_LONG)
 804 
 805 #define KS_DESC_HW_OWNED                0x80000000
 806 
 807 #define KS_DESC_BUF_SIZE                0x000007FF
 808 #define KS884X_DESC_TX_PORT_MASK        0x00300000
 809 #define KS_DESC_END_OF_RING             0x02000000
 810 #define KS_DESC_TX_CSUM_GEN_UDP         0x04000000
 811 #define KS_DESC_TX_CSUM_GEN_TCP         0x08000000
 812 #define KS_DESC_TX_CSUM_GEN_IP          0x10000000
 813 #define KS_DESC_TX_LAST                 0x20000000
 814 #define KS_DESC_TX_FIRST                0x40000000
 815 #define KS_DESC_TX_INTERRUPT            0x80000000
 816 
 817 #define KS_DESC_PORT_SHIFT              20
 818 
 819 #define KS_DESC_RX_MASK                 (KS_DESC_BUF_SIZE)
 820 
 821 #define KS_DESC_TX_MASK                 \
 822         (KS_DESC_TX_INTERRUPT |         \
 823         KS_DESC_TX_FIRST |              \
 824         KS_DESC_TX_LAST |               \
 825         KS_DESC_TX_CSUM_GEN_IP |        \
 826         KS_DESC_TX_CSUM_GEN_TCP |       \
 827         KS_DESC_TX_CSUM_GEN_UDP |       \
 828         KS_DESC_BUF_SIZE)
 829 
 830 struct ksz_desc_rx_stat {
 831 #ifdef __BIG_ENDIAN_BITFIELD
 832         u32 hw_owned:1;
 833         u32 first_desc:1;
 834         u32 last_desc:1;
 835         u32 csum_err_ip:1;
 836         u32 csum_err_tcp:1;
 837         u32 csum_err_udp:1;
 838         u32 error:1;
 839         u32 multicast:1;
 840         u32 src_port:4;
 841         u32 err_phy:1;
 842         u32 err_too_long:1;
 843         u32 err_runt:1;
 844         u32 err_crc:1;
 845         u32 frame_type:1;
 846         u32 reserved1:4;
 847         u32 frame_len:11;
 848 #else
 849         u32 frame_len:11;
 850         u32 reserved1:4;
 851         u32 frame_type:1;
 852         u32 err_crc:1;
 853         u32 err_runt:1;
 854         u32 err_too_long:1;
 855         u32 err_phy:1;
 856         u32 src_port:4;
 857         u32 multicast:1;
 858         u32 error:1;
 859         u32 csum_err_udp:1;
 860         u32 csum_err_tcp:1;
 861         u32 csum_err_ip:1;
 862         u32 last_desc:1;
 863         u32 first_desc:1;
 864         u32 hw_owned:1;
 865 #endif
 866 };
 867 
 868 struct ksz_desc_tx_stat {
 869 #ifdef __BIG_ENDIAN_BITFIELD
 870         u32 hw_owned:1;
 871         u32 reserved1:31;
 872 #else
 873         u32 reserved1:31;
 874         u32 hw_owned:1;
 875 #endif
 876 };
 877 
 878 struct ksz_desc_rx_buf {
 879 #ifdef __BIG_ENDIAN_BITFIELD
 880         u32 reserved4:6;
 881         u32 end_of_ring:1;
 882         u32 reserved3:14;
 883         u32 buf_size:11;
 884 #else
 885         u32 buf_size:11;
 886         u32 reserved3:14;
 887         u32 end_of_ring:1;
 888         u32 reserved4:6;
 889 #endif
 890 };
 891 
 892 struct ksz_desc_tx_buf {
 893 #ifdef __BIG_ENDIAN_BITFIELD
 894         u32 intr:1;
 895         u32 first_seg:1;
 896         u32 last_seg:1;
 897         u32 csum_gen_ip:1;
 898         u32 csum_gen_tcp:1;
 899         u32 csum_gen_udp:1;
 900         u32 end_of_ring:1;
 901         u32 reserved4:1;
 902         u32 dest_port:4;
 903         u32 reserved3:9;
 904         u32 buf_size:11;
 905 #else
 906         u32 buf_size:11;
 907         u32 reserved3:9;
 908         u32 dest_port:4;
 909         u32 reserved4:1;
 910         u32 end_of_ring:1;
 911         u32 csum_gen_udp:1;
 912         u32 csum_gen_tcp:1;
 913         u32 csum_gen_ip:1;
 914         u32 last_seg:1;
 915         u32 first_seg:1;
 916         u32 intr:1;
 917 #endif
 918 };
 919 
 920 union desc_stat {
 921         struct ksz_desc_rx_stat rx;
 922         struct ksz_desc_tx_stat tx;
 923         u32 data;
 924 };
 925 
 926 union desc_buf {
 927         struct ksz_desc_rx_buf rx;
 928         struct ksz_desc_tx_buf tx;
 929         u32 data;
 930 };
 931 
 932 /**
 933  * struct ksz_hw_desc - Hardware descriptor data structure
 934  * @ctrl:       Descriptor control value.
 935  * @buf:        Descriptor buffer value.
 936  * @addr:       Physical address of memory buffer.
 937  * @next:       Pointer to next hardware descriptor.
 938  */
 939 struct ksz_hw_desc {
 940         union desc_stat ctrl;
 941         union desc_buf buf;
 942         u32 addr;
 943         u32 next;
 944 };
 945 
 946 /**
 947  * struct ksz_sw_desc - Software descriptor data structure
 948  * @ctrl:       Descriptor control value.
 949  * @buf:        Descriptor buffer value.
 950  * @buf_size:   Current buffers size value in hardware descriptor.
 951  */
 952 struct ksz_sw_desc {
 953         union desc_stat ctrl;
 954         union desc_buf buf;
 955         u32 buf_size;
 956 };
 957 
 958 /**
 959  * struct ksz_dma_buf - OS dependent DMA buffer data structure
 960  * @skb:        Associated socket buffer.
 961  * @dma:        Associated physical DMA address.
 962  * len:         Actual len used.
 963  */
 964 struct ksz_dma_buf {
 965         struct sk_buff *skb;
 966         dma_addr_t dma;
 967         int len;
 968 };
 969 
 970 /**
 971  * struct ksz_desc - Descriptor structure
 972  * @phw:        Hardware descriptor pointer to uncached physical memory.
 973  * @sw:         Cached memory to hold hardware descriptor values for
 974  *              manipulation.
 975  * @dma_buf:    Operating system dependent data structure to hold physical
 976  *              memory buffer allocation information.
 977  */
 978 struct ksz_desc {
 979         struct ksz_hw_desc *phw;
 980         struct ksz_sw_desc sw;
 981         struct ksz_dma_buf dma_buf;
 982 };
 983 
 984 #define DMA_BUFFER(desc)  ((struct ksz_dma_buf *)(&(desc)->dma_buf))
 985 
 986 /**
 987  * struct ksz_desc_info - Descriptor information data structure
 988  * @ring:       First descriptor in the ring.
 989  * @cur:        Current descriptor being manipulated.
 990  * @ring_virt:  First hardware descriptor in the ring.
 991  * @ring_phys:  The physical address of the first descriptor of the ring.
 992  * @size:       Size of hardware descriptor.
 993  * @alloc:      Number of descriptors allocated.
 994  * @avail:      Number of descriptors available for use.
 995  * @last:       Index for last descriptor released to hardware.
 996  * @next:       Index for next descriptor available for use.
 997  * @mask:       Mask for index wrapping.
 998  */
 999 struct ksz_desc_info {
1000         struct ksz_desc *ring;
1001         struct ksz_desc *cur;
1002         struct ksz_hw_desc *ring_virt;
1003         u32 ring_phys;
1004         int size;
1005         int alloc;
1006         int avail;
1007         int last;
1008         int next;
1009         int mask;
1010 };
1011 
1012 /*
1013  * KSZ8842 switch definitions
1014  */
1015 
1016 enum {
1017         TABLE_STATIC_MAC = 0,
1018         TABLE_VLAN,
1019         TABLE_DYNAMIC_MAC,
1020         TABLE_MIB
1021 };
1022 
1023 #define LEARNED_MAC_TABLE_ENTRIES       1024
1024 #define STATIC_MAC_TABLE_ENTRIES        8
1025 
1026 /**
1027  * struct ksz_mac_table - Static MAC table data structure
1028  * @mac_addr:   MAC address to filter.
1029  * @vid:        VID value.
1030  * @fid:        FID value.
1031  * @ports:      Port membership.
1032  * @override:   Override setting.
1033  * @use_fid:    FID use setting.
1034  * @valid:      Valid setting indicating the entry is being used.
1035  */
1036 struct ksz_mac_table {
1037         u8 mac_addr[ETH_ALEN];
1038         u16 vid;
1039         u8 fid;
1040         u8 ports;
1041         u8 override:1;
1042         u8 use_fid:1;
1043         u8 valid:1;
1044 };
1045 
1046 #define VLAN_TABLE_ENTRIES              16
1047 
1048 /**
1049  * struct ksz_vlan_table - VLAN table data structure
1050  * @vid:        VID value.
1051  * @fid:        FID value.
1052  * @member:     Port membership.
1053  */
1054 struct ksz_vlan_table {
1055         u16 vid;
1056         u8 fid;
1057         u8 member;
1058 };
1059 
1060 #define DIFFSERV_ENTRIES                64
1061 #define PRIO_802_1P_ENTRIES             8
1062 #define PRIO_QUEUES                     4
1063 
1064 #define SWITCH_PORT_NUM                 2
1065 #define TOTAL_PORT_NUM                  (SWITCH_PORT_NUM + 1)
1066 #define HOST_MASK                       (1 << SWITCH_PORT_NUM)
1067 #define PORT_MASK                       7
1068 
1069 #define MAIN_PORT                       0
1070 #define OTHER_PORT                      1
1071 #define HOST_PORT                       SWITCH_PORT_NUM
1072 
1073 #define PORT_COUNTER_NUM                0x20
1074 #define TOTAL_PORT_COUNTER_NUM          (PORT_COUNTER_NUM + 2)
1075 
1076 #define MIB_COUNTER_RX_LO_PRIORITY      0x00
1077 #define MIB_COUNTER_RX_HI_PRIORITY      0x01
1078 #define MIB_COUNTER_RX_UNDERSIZE        0x02
1079 #define MIB_COUNTER_RX_FRAGMENT         0x03
1080 #define MIB_COUNTER_RX_OVERSIZE         0x04
1081 #define MIB_COUNTER_RX_JABBER           0x05
1082 #define MIB_COUNTER_RX_SYMBOL_ERR       0x06
1083 #define MIB_COUNTER_RX_CRC_ERR          0x07
1084 #define MIB_COUNTER_RX_ALIGNMENT_ERR    0x08
1085 #define MIB_COUNTER_RX_CTRL_8808        0x09
1086 #define MIB_COUNTER_RX_PAUSE            0x0A
1087 #define MIB_COUNTER_RX_BROADCAST        0x0B
1088 #define MIB_COUNTER_RX_MULTICAST        0x0C
1089 #define MIB_COUNTER_RX_UNICAST          0x0D
1090 #define MIB_COUNTER_RX_OCTET_64         0x0E
1091 #define MIB_COUNTER_RX_OCTET_65_127     0x0F
1092 #define MIB_COUNTER_RX_OCTET_128_255    0x10
1093 #define MIB_COUNTER_RX_OCTET_256_511    0x11
1094 #define MIB_COUNTER_RX_OCTET_512_1023   0x12
1095 #define MIB_COUNTER_RX_OCTET_1024_1522  0x13
1096 #define MIB_COUNTER_TX_LO_PRIORITY      0x14
1097 #define MIB_COUNTER_TX_HI_PRIORITY      0x15
1098 #define MIB_COUNTER_TX_LATE_COLLISION   0x16
1099 #define MIB_COUNTER_TX_PAUSE            0x17
1100 #define MIB_COUNTER_TX_BROADCAST        0x18
1101 #define MIB_COUNTER_TX_MULTICAST        0x19
1102 #define MIB_COUNTER_TX_UNICAST          0x1A
1103 #define MIB_COUNTER_TX_DEFERRED         0x1B
1104 #define MIB_COUNTER_TX_TOTAL_COLLISION  0x1C
1105 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1106 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1107 #define MIB_COUNTER_TX_MULTI_COLLISION  0x1F
1108 
1109 #define MIB_COUNTER_RX_DROPPED_PACKET   0x20
1110 #define MIB_COUNTER_TX_DROPPED_PACKET   0x21
1111 
1112 /**
1113  * struct ksz_port_mib - Port MIB data structure
1114  * @cnt_ptr:    Current pointer to MIB counter index.
1115  * @link_down:  Indication the link has just gone down.
1116  * @state:      Connection status of the port.
1117  * @mib_start:  The starting counter index.  Some ports do not start at 0.
1118  * @counter:    64-bit MIB counter value.
1119  * @dropped:    Temporary buffer to remember last read packet dropped values.
1120  *
1121  * MIB counters needs to be read periodically so that counters do not get
1122  * overflowed and give incorrect values.  A right balance is needed to
1123  * satisfy this condition and not waste too much CPU time.
1124  *
1125  * It is pointless to read MIB counters when the port is disconnected.  The
1126  * @state provides the connection status so that MIB counters are read only
1127  * when the port is connected.  The @link_down indicates the port is just
1128  * disconnected so that all MIB counters are read one last time to update the
1129  * information.
1130  */
1131 struct ksz_port_mib {
1132         u8 cnt_ptr;
1133         u8 link_down;
1134         u8 state;
1135         u8 mib_start;
1136 
1137         u64 counter[TOTAL_PORT_COUNTER_NUM];
1138         u32 dropped[2];
1139 };
1140 
1141 /**
1142  * struct ksz_port_cfg - Port configuration data structure
1143  * @vid:        VID value.
1144  * @member:     Port membership.
1145  * @port_prio:  Port priority.
1146  * @rx_rate:    Receive priority rate.
1147  * @tx_rate:    Transmit priority rate.
1148  * @stp_state:  Current Spanning Tree Protocol state.
1149  */
1150 struct ksz_port_cfg {
1151         u16 vid;
1152         u8 member;
1153         u8 port_prio;
1154         u32 rx_rate[PRIO_QUEUES];
1155         u32 tx_rate[PRIO_QUEUES];
1156         int stp_state;
1157 };
1158 
1159 /**
1160  * struct ksz_switch - KSZ8842 switch data structure
1161  * @mac_table:  MAC table entries information.
1162  * @vlan_table: VLAN table entries information.
1163  * @port_cfg:   Port configuration information.
1164  * @diffserv:   DiffServ priority settings.  Possible values from 6-bit of ToS
1165  *              (bit7 ~ bit2) field.
1166  * @p_802_1p:   802.1P priority settings.  Possible values from 3-bit of 802.1p
1167  *              Tag priority field.
1168  * @br_addr:    Bridge address.  Used for STP.
1169  * @other_addr: Other MAC address.  Used for multiple network device mode.
1170  * @broad_per:  Broadcast storm percentage.
1171  * @member:     Current port membership.  Used for STP.
1172  */
1173 struct ksz_switch {
1174         struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1175         struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1176         struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1177 
1178         u8 diffserv[DIFFSERV_ENTRIES];
1179         u8 p_802_1p[PRIO_802_1P_ENTRIES];
1180 
1181         u8 br_addr[ETH_ALEN];
1182         u8 other_addr[ETH_ALEN];
1183 
1184         u8 broad_per;
1185         u8 member;
1186 };
1187 
1188 #define TX_RATE_UNIT                    10000
1189 
1190 /**
1191  * struct ksz_port_info - Port information data structure
1192  * @state:      Connection status of the port.
1193  * @tx_rate:    Transmit rate divided by 10000 to get Mbit.
1194  * @duplex:     Duplex mode.
1195  * @advertised: Advertised auto-negotiation setting.  Used to determine link.
1196  * @partner:    Auto-negotiation partner setting.  Used to determine link.
1197  * @port_id:    Port index to access actual hardware register.
1198  * @pdev:       Pointer to OS dependent network device.
1199  */
1200 struct ksz_port_info {
1201         uint state;
1202         uint tx_rate;
1203         u8 duplex;
1204         u8 advertised;
1205         u8 partner;
1206         u8 port_id;
1207         void *pdev;
1208 };
1209 
1210 #define MAX_TX_HELD_SIZE                52000
1211 
1212 /* Hardware features and bug fixes. */
1213 #define LINK_INT_WORKING                (1 << 0)
1214 #define SMALL_PACKET_TX_BUG             (1 << 1)
1215 #define HALF_DUPLEX_SIGNAL_BUG          (1 << 2)
1216 #define RX_HUGE_FRAME                   (1 << 4)
1217 #define STP_SUPPORT                     (1 << 8)
1218 
1219 /* Software overrides. */
1220 #define PAUSE_FLOW_CTRL                 (1 << 0)
1221 #define FAST_AGING                      (1 << 1)
1222 
1223 /**
1224  * struct ksz_hw - KSZ884X hardware data structure
1225  * @io:                 Virtual address assigned.
1226  * @ksz_switch:         Pointer to KSZ8842 switch.
1227  * @port_info:          Port information.
1228  * @port_mib:           Port MIB information.
1229  * @dev_count:          Number of network devices this hardware supports.
1230  * @dst_ports:          Destination ports in switch for transmission.
1231  * @id:                 Hardware ID.  Used for display only.
1232  * @mib_cnt:            Number of MIB counters this hardware has.
1233  * @mib_port_cnt:       Number of ports with MIB counters.
1234  * @tx_cfg:             Cached transmit control settings.
1235  * @rx_cfg:             Cached receive control settings.
1236  * @intr_mask:          Current interrupt mask.
1237  * @intr_set:           Current interrup set.
1238  * @intr_blocked:       Interrupt blocked.
1239  * @rx_desc_info:       Receive descriptor information.
1240  * @tx_desc_info:       Transmit descriptor information.
1241  * @tx_int_cnt:         Transmit interrupt count.  Used for TX optimization.
1242  * @tx_int_mask:        Transmit interrupt mask.  Used for TX optimization.
1243  * @tx_size:            Transmit data size.  Used for TX optimization.
1244  *                      The maximum is defined by MAX_TX_HELD_SIZE.
1245  * @perm_addr:          Permanent MAC address.
1246  * @override_addr:      Overridden MAC address.
1247  * @address:            Additional MAC address entries.
1248  * @addr_list_size:     Additional MAC address list size.
1249  * @mac_override:       Indication of MAC address overridden.
1250  * @promiscuous:        Counter to keep track of promiscuous mode set.
1251  * @all_multi:          Counter to keep track of all multicast mode set.
1252  * @multi_list:         Multicast address entries.
1253  * @multi_bits:         Cached multicast hash table settings.
1254  * @multi_list_size:    Multicast address list size.
1255  * @enabled:            Indication of hardware enabled.
1256  * @rx_stop:            Indication of receive process stop.
1257  * @features:           Hardware features to enable.
1258  * @overrides:          Hardware features to override.
1259  * @parent:             Pointer to parent, network device private structure.
1260  */
1261 struct ksz_hw {
1262         void __iomem *io;
1263 
1264         struct ksz_switch *ksz_switch;
1265         struct ksz_port_info port_info[SWITCH_PORT_NUM];
1266         struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1267         int dev_count;
1268         int dst_ports;
1269         int id;
1270         int mib_cnt;
1271         int mib_port_cnt;
1272 
1273         u32 tx_cfg;
1274         u32 rx_cfg;
1275         u32 intr_mask;
1276         u32 intr_set;
1277         uint intr_blocked;
1278 
1279         struct ksz_desc_info rx_desc_info;
1280         struct ksz_desc_info tx_desc_info;
1281 
1282         int tx_int_cnt;
1283         int tx_int_mask;
1284         int tx_size;
1285 
1286         u8 perm_addr[ETH_ALEN];
1287         u8 override_addr[ETH_ALEN];
1288         u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1289         u8 addr_list_size;
1290         u8 mac_override;
1291         u8 promiscuous;
1292         u8 all_multi;
1293         u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1294         u8 multi_bits[HW_MULTICAST_SIZE];
1295         u8 multi_list_size;
1296 
1297         u8 enabled;
1298         u8 rx_stop;
1299         u8 reserved2[1];
1300 
1301         uint features;
1302         uint overrides;
1303 
1304         void *parent;
1305 };
1306 
1307 enum {
1308         PHY_NO_FLOW_CTRL,
1309         PHY_FLOW_CTRL,
1310         PHY_TX_ONLY,
1311         PHY_RX_ONLY
1312 };
1313 
1314 /**
1315  * struct ksz_port - Virtual port data structure
1316  * @duplex:             Duplex mode setting.  1 for half duplex, 2 for full
1317  *                      duplex, and 0 for auto, which normally results in full
1318  *                      duplex.
1319  * @speed:              Speed setting.  10 for 10 Mbit, 100 for 100 Mbit, and
1320  *                      0 for auto, which normally results in 100 Mbit.
1321  * @force_link:         Force link setting.  0 for auto-negotiation, and 1 for
1322  *                      force.
1323  * @flow_ctrl:          Flow control setting.  PHY_NO_FLOW_CTRL for no flow
1324  *                      control, and PHY_FLOW_CTRL for flow control.
1325  *                      PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1326  *                      Mbit PHY.
1327  * @first_port:         Index of first port this port supports.
1328  * @mib_port_cnt:       Number of ports with MIB counters.
1329  * @port_cnt:           Number of ports this port supports.
1330  * @counter:            Port statistics counter.
1331  * @hw:                 Pointer to hardware structure.
1332  * @linked:             Pointer to port information linked to this port.
1333  */
1334 struct ksz_port {
1335         u8 duplex;
1336         u8 speed;
1337         u8 force_link;
1338         u8 flow_ctrl;
1339 
1340         int first_port;
1341         int mib_port_cnt;
1342         int port_cnt;
1343         u64 counter[OID_COUNTER_LAST];
1344 
1345         struct ksz_hw *hw;
1346         struct ksz_port_info *linked;
1347 };
1348 
1349 /**
1350  * struct ksz_timer_info - Timer information data structure
1351  * @timer:      Kernel timer.
1352  * @cnt:        Running timer counter.
1353  * @max:        Number of times to run timer; -1 for infinity.
1354  * @period:     Timer period in jiffies.
1355  */
1356 struct ksz_timer_info {
1357         struct timer_list timer;
1358         int cnt;
1359         int max;
1360         int period;
1361 };
1362 
1363 /**
1364  * struct ksz_shared_mem - OS dependent shared memory data structure
1365  * @dma_addr:   Physical DMA address allocated.
1366  * @alloc_size: Allocation size.
1367  * @phys:       Actual physical address used.
1368  * @alloc_virt: Virtual address allocated.
1369  * @virt:       Actual virtual address used.
1370  */
1371 struct ksz_shared_mem {
1372         dma_addr_t dma_addr;
1373         uint alloc_size;
1374         uint phys;
1375         u8 *alloc_virt;
1376         u8 *virt;
1377 };
1378 
1379 /**
1380  * struct ksz_counter_info - OS dependent counter information data structure
1381  * @counter:    Wait queue to wakeup after counters are read.
1382  * @time:       Next time in jiffies to read counter.
1383  * @read:       Indication of counters read in full or not.
1384  */
1385 struct ksz_counter_info {
1386         wait_queue_head_t counter;
1387         unsigned long time;
1388         int read;
1389 };
1390 
1391 /**
1392  * struct dev_info - Network device information data structure
1393  * @dev:                Pointer to network device.
1394  * @pdev:               Pointer to PCI device.
1395  * @hw:                 Hardware structure.
1396  * @desc_pool:          Physical memory used for descriptor pool.
1397  * @hwlock:             Spinlock to prevent hardware from accessing.
1398  * @lock:               Mutex lock to prevent device from accessing.
1399  * @dev_rcv:            Receive process function used.
1400  * @last_skb:           Socket buffer allocated for descriptor rx fragments.
1401  * @skb_index:          Buffer index for receiving fragments.
1402  * @skb_len:            Buffer length for receiving fragments.
1403  * @mib_read:           Workqueue to read MIB counters.
1404  * @mib_timer_info:     Timer to read MIB counters.
1405  * @counter:            Used for MIB reading.
1406  * @mtu:                Current MTU used.  The default is REGULAR_RX_BUF_SIZE;
1407  *                      the maximum is MAX_RX_BUF_SIZE.
1408  * @opened:             Counter to keep track of device open.
1409  * @rx_tasklet:         Receive processing tasklet.
1410  * @tx_tasklet:         Transmit processing tasklet.
1411  * @wol_enable:         Wake-on-LAN enable set by ethtool.
1412  * @wol_support:        Wake-on-LAN support used by ethtool.
1413  * @pme_wait:           Used for KSZ8841 power management.
1414  */
1415 struct dev_info {
1416         struct net_device *dev;
1417         struct pci_dev *pdev;
1418 
1419         struct ksz_hw hw;
1420         struct ksz_shared_mem desc_pool;
1421 
1422         spinlock_t hwlock;
1423         struct mutex lock;
1424 
1425         int (*dev_rcv)(struct dev_info *);
1426 
1427         struct sk_buff *last_skb;
1428         int skb_index;
1429         int skb_len;
1430 
1431         struct work_struct mib_read;
1432         struct ksz_timer_info mib_timer_info;
1433         struct ksz_counter_info counter[TOTAL_PORT_NUM];
1434 
1435         int mtu;
1436         int opened;
1437 
1438         struct tasklet_struct rx_tasklet;
1439         struct tasklet_struct tx_tasklet;
1440 
1441         int wol_enable;
1442         int wol_support;
1443         unsigned long pme_wait;
1444 };
1445 
1446 /**
1447  * struct dev_priv - Network device private data structure
1448  * @adapter:            Adapter device information.
1449  * @port:               Port information.
1450  * @monitor_time_info:  Timer to monitor ports.
1451  * @proc_sem:           Semaphore for proc accessing.
1452  * @id:                 Device ID.
1453  * @mii_if:             MII interface information.
1454  * @advertising:        Temporary variable to store advertised settings.
1455  * @msg_enable:         The message flags controlling driver output.
1456  * @media_state:        The connection status of the device.
1457  * @multicast:          The all multicast state of the device.
1458  * @promiscuous:        The promiscuous state of the device.
1459  */
1460 struct dev_priv {
1461         struct dev_info *adapter;
1462         struct ksz_port port;
1463         struct ksz_timer_info monitor_timer_info;
1464 
1465         struct semaphore proc_sem;
1466         int id;
1467 
1468         struct mii_if_info mii_if;
1469         u32 advertising;
1470 
1471         u32 msg_enable;
1472         int media_state;
1473         int multicast;
1474         int promiscuous;
1475 };
1476 
1477 #define DRV_NAME                "KSZ884X PCI"
1478 #define DEVICE_NAME             "KSZ884x PCI"
1479 #define DRV_VERSION             "1.0.0"
1480 #define DRV_RELDATE             "Feb 8, 2010"
1481 
1482 static char version[] =
1483         "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1484 
1485 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1486 
1487 /*
1488  * Interrupt processing primary routines
1489  */
1490 
1491 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1492 {
1493         writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1494 }
1495 
1496 static inline void hw_dis_intr(struct ksz_hw *hw)
1497 {
1498         hw->intr_blocked = hw->intr_mask;
1499         writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1500         hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1501 }
1502 
1503 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1504 {
1505         hw->intr_set = interrupt;
1506         writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1507 }
1508 
1509 static inline void hw_ena_intr(struct ksz_hw *hw)
1510 {
1511         hw->intr_blocked = 0;
1512         hw_set_intr(hw, hw->intr_mask);
1513 }
1514 
1515 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1516 {
1517         hw->intr_mask &= ~(bit);
1518 }
1519 
1520 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1521 {
1522         u32 read_intr;
1523 
1524         read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1525         hw->intr_set = read_intr & ~interrupt;
1526         writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1527         hw_dis_intr_bit(hw, interrupt);
1528 }
1529 
1530 /**
1531  * hw_turn_on_intr - turn on specified interrupts
1532  * @hw:         The hardware instance.
1533  * @bit:        The interrupt bits to be on.
1534  *
1535  * This routine turns on the specified interrupts in the interrupt mask so that
1536  * those interrupts will be enabled.
1537  */
1538 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1539 {
1540         hw->intr_mask |= bit;
1541 
1542         if (!hw->intr_blocked)
1543                 hw_set_intr(hw, hw->intr_mask);
1544 }
1545 
1546 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1547 {
1548         u32 read_intr;
1549 
1550         read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1551         hw->intr_set = read_intr | interrupt;
1552         writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1553 }
1554 
1555 static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1556 {
1557         *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1558         *status = *status & hw->intr_set;
1559 }
1560 
1561 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1562 {
1563         if (interrupt)
1564                 hw_ena_intr(hw);
1565 }
1566 
1567 /**
1568  * hw_block_intr - block hardware interrupts
1569  *
1570  * This function blocks all interrupts of the hardware and returns the current
1571  * interrupt enable mask so that interrupts can be restored later.
1572  *
1573  * Return the current interrupt enable mask.
1574  */
1575 static uint hw_block_intr(struct ksz_hw *hw)
1576 {
1577         uint interrupt = 0;
1578 
1579         if (!hw->intr_blocked) {
1580                 hw_dis_intr(hw);
1581                 interrupt = hw->intr_blocked;
1582         }
1583         return interrupt;
1584 }
1585 
1586 /*
1587  * Hardware descriptor routines
1588  */
1589 
1590 static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1591 {
1592         status.rx.hw_owned = 0;
1593         desc->phw->ctrl.data = cpu_to_le32(status.data);
1594 }
1595 
1596 static inline void release_desc(struct ksz_desc *desc)
1597 {
1598         desc->sw.ctrl.tx.hw_owned = 1;
1599         if (desc->sw.buf_size != desc->sw.buf.data) {
1600                 desc->sw.buf_size = desc->sw.buf.data;
1601                 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1602         }
1603         desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1604 }
1605 
1606 static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1607 {
1608         *desc = &info->ring[info->last];
1609         info->last++;
1610         info->last &= info->mask;
1611         info->avail--;
1612         (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1613 }
1614 
1615 static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1616 {
1617         desc->phw->addr = cpu_to_le32(addr);
1618 }
1619 
1620 static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1621 {
1622         desc->sw.buf.rx.buf_size = len;
1623 }
1624 
1625 static inline void get_tx_pkt(struct ksz_desc_info *info,
1626         struct ksz_desc **desc)
1627 {
1628         *desc = &info->ring[info->next];
1629         info->next++;
1630         info->next &= info->mask;
1631         info->avail--;
1632         (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1633 }
1634 
1635 static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1636 {
1637         desc->phw->addr = cpu_to_le32(addr);
1638 }
1639 
1640 static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1641 {
1642         desc->sw.buf.tx.buf_size = len;
1643 }
1644 
1645 /* Switch functions */
1646 
1647 #define TABLE_READ                      0x10
1648 #define TABLE_SEL_SHIFT                 2
1649 
1650 #define HW_DELAY(hw, reg)                       \
1651         do {                                    \
1652                 u16 dummy;                      \
1653                 dummy = readw(hw->io + reg);    \
1654         } while (0)
1655 
1656 /**
1657  * sw_r_table - read 4 bytes of data from switch table
1658  * @hw:         The hardware instance.
1659  * @table:      The table selector.
1660  * @addr:       The address of the table entry.
1661  * @data:       Buffer to store the read data.
1662  *
1663  * This routine reads 4 bytes of data from the table of the switch.
1664  * Hardware interrupts are disabled to minimize corruption of read data.
1665  */
1666 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1667 {
1668         u16 ctrl_addr;
1669         uint interrupt;
1670 
1671         ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1672 
1673         interrupt = hw_block_intr(hw);
1674 
1675         writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1676         HW_DELAY(hw, KS884X_IACR_OFFSET);
1677         *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1678 
1679         hw_restore_intr(hw, interrupt);
1680 }
1681 
1682 /**
1683  * sw_w_table_64 - write 8 bytes of data to the switch table
1684  * @hw:         The hardware instance.
1685  * @table:      The table selector.
1686  * @addr:       The address of the table entry.
1687  * @data_hi:    The high part of data to be written (bit63 ~ bit32).
1688  * @data_lo:    The low part of data to be written (bit31 ~ bit0).
1689  *
1690  * This routine writes 8 bytes of data to the table of the switch.
1691  * Hardware interrupts are disabled to minimize corruption of written data.
1692  */
1693 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1694         u32 data_lo)
1695 {
1696         u16 ctrl_addr;
1697         uint interrupt;
1698 
1699         ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1700 
1701         interrupt = hw_block_intr(hw);
1702 
1703         writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1704         writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1705 
1706         writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1707         HW_DELAY(hw, KS884X_IACR_OFFSET);
1708 
1709         hw_restore_intr(hw, interrupt);
1710 }
1711 
1712 /**
1713  * sw_w_sta_mac_table - write to the static MAC table
1714  * @hw:         The hardware instance.
1715  * @addr:       The address of the table entry.
1716  * @mac_addr:   The MAC address.
1717  * @ports:      The port members.
1718  * @override:   The flag to override the port receive/transmit settings.
1719  * @valid:      The flag to indicate entry is valid.
1720  * @use_fid:    The flag to indicate the FID is valid.
1721  * @fid:        The FID value.
1722  *
1723  * This routine writes an entry of the static MAC table of the switch.  It
1724  * calls sw_w_table_64() to write the data.
1725  */
1726 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1727         u8 ports, int override, int valid, int use_fid, u8 fid)
1728 {
1729         u32 data_hi;
1730         u32 data_lo;
1731 
1732         data_lo = ((u32) mac_addr[2] << 24) |
1733                 ((u32) mac_addr[3] << 16) |
1734                 ((u32) mac_addr[4] << 8) | mac_addr[5];
1735         data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1736         data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1737 
1738         if (override)
1739                 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1740         if (use_fid) {
1741                 data_hi |= STATIC_MAC_TABLE_USE_FID;
1742                 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1743         }
1744         if (valid)
1745                 data_hi |= STATIC_MAC_TABLE_VALID;
1746 
1747         sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1748 }
1749 
1750 /**
1751  * sw_r_vlan_table - read from the VLAN table
1752  * @hw:         The hardware instance.
1753  * @addr:       The address of the table entry.
1754  * @vid:        Buffer to store the VID.
1755  * @fid:        Buffer to store the VID.
1756  * @member:     Buffer to store the port membership.
1757  *
1758  * This function reads an entry of the VLAN table of the switch.  It calls
1759  * sw_r_table() to get the data.
1760  *
1761  * Return 0 if the entry is valid; otherwise -1.
1762  */
1763 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1764         u8 *member)
1765 {
1766         u32 data;
1767 
1768         sw_r_table(hw, TABLE_VLAN, addr, &data);
1769         if (data & VLAN_TABLE_VALID) {
1770                 *vid = (u16)(data & VLAN_TABLE_VID);
1771                 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1772                 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1773                         VLAN_TABLE_MEMBERSHIP_SHIFT);
1774                 return 0;
1775         }
1776         return -1;
1777 }
1778 
1779 /**
1780  * port_r_mib_cnt - read MIB counter
1781  * @hw:         The hardware instance.
1782  * @port:       The port index.
1783  * @addr:       The address of the counter.
1784  * @cnt:        Buffer to store the counter.
1785  *
1786  * This routine reads a MIB counter of the port.
1787  * Hardware interrupts are disabled to minimize corruption of read data.
1788  */
1789 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1790 {
1791         u32 data;
1792         u16 ctrl_addr;
1793         uint interrupt;
1794         int timeout;
1795 
1796         ctrl_addr = addr + PORT_COUNTER_NUM * port;
1797 
1798         interrupt = hw_block_intr(hw);
1799 
1800         ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1801         writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1802         HW_DELAY(hw, KS884X_IACR_OFFSET);
1803 
1804         for (timeout = 100; timeout > 0; timeout--) {
1805                 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1806 
1807                 if (data & MIB_COUNTER_VALID) {
1808                         if (data & MIB_COUNTER_OVERFLOW)
1809                                 *cnt += MIB_COUNTER_VALUE + 1;
1810                         *cnt += data & MIB_COUNTER_VALUE;
1811                         break;
1812                 }
1813         }
1814 
1815         hw_restore_intr(hw, interrupt);
1816 }
1817 
1818 /**
1819  * port_r_mib_pkt - read dropped packet counts
1820  * @hw:         The hardware instance.
1821  * @port:       The port index.
1822  * @cnt:        Buffer to store the receive and transmit dropped packet counts.
1823  *
1824  * This routine reads the dropped packet counts of the port.
1825  * Hardware interrupts are disabled to minimize corruption of read data.
1826  */
1827 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1828 {
1829         u32 cur;
1830         u32 data;
1831         u16 ctrl_addr;
1832         uint interrupt;
1833         int index;
1834 
1835         index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1836         do {
1837                 interrupt = hw_block_intr(hw);
1838 
1839                 ctrl_addr = (u16) index;
1840                 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1841                         << 8);
1842                 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1843                 HW_DELAY(hw, KS884X_IACR_OFFSET);
1844                 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1845 
1846                 hw_restore_intr(hw, interrupt);
1847 
1848                 data &= MIB_PACKET_DROPPED;
1849                 cur = *last;
1850                 if (data != cur) {
1851                         *last = data;
1852                         if (data < cur)
1853                                 data += MIB_PACKET_DROPPED + 1;
1854                         data -= cur;
1855                         *cnt += data;
1856                 }
1857                 ++last;
1858                 ++cnt;
1859                 index -= KS_MIB_PACKET_DROPPED_TX -
1860                         KS_MIB_PACKET_DROPPED_TX_0 + 1;
1861         } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1862 }
1863 
1864 /**
1865  * port_r_cnt - read MIB counters periodically
1866  * @hw:         The hardware instance.
1867  * @port:       The port index.
1868  *
1869  * This routine is used to read the counters of the port periodically to avoid
1870  * counter overflow.  The hardware should be acquired first before calling this
1871  * routine.
1872  *
1873  * Return non-zero when not all counters not read.
1874  */
1875 static int port_r_cnt(struct ksz_hw *hw, int port)
1876 {
1877         struct ksz_port_mib *mib = &hw->port_mib[port];
1878 
1879         if (mib->mib_start < PORT_COUNTER_NUM)
1880                 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1881                         port_r_mib_cnt(hw, port, mib->cnt_ptr,
1882                                 &mib->counter[mib->cnt_ptr]);
1883                         ++mib->cnt_ptr;
1884                 }
1885         if (hw->mib_cnt > PORT_COUNTER_NUM)
1886                 port_r_mib_pkt(hw, port, mib->dropped,
1887                         &mib->counter[PORT_COUNTER_NUM]);
1888         mib->cnt_ptr = 0;
1889         return 0;
1890 }
1891 
1892 /**
1893  * port_init_cnt - initialize MIB counter values
1894  * @hw:         The hardware instance.
1895  * @port:       The port index.
1896  *
1897  * This routine is used to initialize all counters to zero if the hardware
1898  * cannot do it after reset.
1899  */
1900 static void port_init_cnt(struct ksz_hw *hw, int port)
1901 {
1902         struct ksz_port_mib *mib = &hw->port_mib[port];
1903 
1904         mib->cnt_ptr = 0;
1905         if (mib->mib_start < PORT_COUNTER_NUM)
1906                 do {
1907                         port_r_mib_cnt(hw, port, mib->cnt_ptr,
1908                                 &mib->counter[mib->cnt_ptr]);
1909                         ++mib->cnt_ptr;
1910                 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1911         if (hw->mib_cnt > PORT_COUNTER_NUM)
1912                 port_r_mib_pkt(hw, port, mib->dropped,
1913                         &mib->counter[PORT_COUNTER_NUM]);
1914         memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1915         mib->cnt_ptr = 0;
1916 }
1917 
1918 /*
1919  * Port functions
1920  */
1921 
1922 /**
1923  * port_chk - check port register bits
1924  * @hw:         The hardware instance.
1925  * @port:       The port index.
1926  * @offset:     The offset of the port register.
1927  * @bits:       The data bits to check.
1928  *
1929  * This function checks whether the specified bits of the port register are set
1930  * or not.
1931  *
1932  * Return 0 if the bits are not set.
1933  */
1934 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1935 {
1936         u32 addr;
1937         u16 data;
1938 
1939         PORT_CTRL_ADDR(port, addr);
1940         addr += offset;
1941         data = readw(hw->io + addr);
1942         return (data & bits) == bits;
1943 }
1944 
1945 /**
1946  * port_cfg - set port register bits
1947  * @hw:         The hardware instance.
1948  * @port:       The port index.
1949  * @offset:     The offset of the port register.
1950  * @bits:       The data bits to set.
1951  * @set:        The flag indicating whether the bits are to be set or not.
1952  *
1953  * This routine sets or resets the specified bits of the port register.
1954  */
1955 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1956         int set)
1957 {
1958         u32 addr;
1959         u16 data;
1960 
1961         PORT_CTRL_ADDR(port, addr);
1962         addr += offset;
1963         data = readw(hw->io + addr);
1964         if (set)
1965                 data |= bits;
1966         else
1967                 data &= ~bits;
1968         writew(data, hw->io + addr);
1969 }
1970 
1971 /**
1972  * port_chk_shift - check port bit
1973  * @hw:         The hardware instance.
1974  * @port:       The port index.
1975  * @offset:     The offset of the register.
1976  * @shift:      Number of bits to shift.
1977  *
1978  * This function checks whether the specified port is set in the register or
1979  * not.
1980  *
1981  * Return 0 if the port is not set.
1982  */
1983 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1984 {
1985         u16 data;
1986         u16 bit = 1 << port;
1987 
1988         data = readw(hw->io + addr);
1989         data >>= shift;
1990         return (data & bit) == bit;
1991 }
1992 
1993 /**
1994  * port_cfg_shift - set port bit
1995  * @hw:         The hardware instance.
1996  * @port:       The port index.
1997  * @offset:     The offset of the register.
1998  * @shift:      Number of bits to shift.
1999  * @set:        The flag indicating whether the port is to be set or not.
2000  *
2001  * This routine sets or resets the specified port in the register.
2002  */
2003 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2004         int set)
2005 {
2006         u16 data;
2007         u16 bits = 1 << port;
2008 
2009         data = readw(hw->io + addr);
2010         bits <<= shift;
2011         if (set)
2012                 data |= bits;
2013         else
2014                 data &= ~bits;
2015         writew(data, hw->io + addr);
2016 }
2017 
2018 /**
2019  * port_r8 - read byte from port register
2020  * @hw:         The hardware instance.
2021  * @port:       The port index.
2022  * @offset:     The offset of the port register.
2023  * @data:       Buffer to store the data.
2024  *
2025  * This routine reads a byte from the port register.
2026  */
2027 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2028 {
2029         u32 addr;
2030 
2031         PORT_CTRL_ADDR(port, addr);
2032         addr += offset;
2033         *data = readb(hw->io + addr);
2034 }
2035 
2036 /**
2037  * port_r16 - read word from port register.
2038  * @hw:         The hardware instance.
2039  * @port:       The port index.
2040  * @offset:     The offset of the port register.
2041  * @data:       Buffer to store the data.
2042  *
2043  * This routine reads a word from the port register.
2044  */
2045 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2046 {
2047         u32 addr;
2048 
2049         PORT_CTRL_ADDR(port, addr);
2050         addr += offset;
2051         *data = readw(hw->io + addr);
2052 }
2053 
2054 /**
2055  * port_w16 - write word to port register.
2056  * @hw:         The hardware instance.
2057  * @port:       The port index.
2058  * @offset:     The offset of the port register.
2059  * @data:       Data to write.
2060  *
2061  * This routine writes a word to the port register.
2062  */
2063 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2064 {
2065         u32 addr;
2066 
2067         PORT_CTRL_ADDR(port, addr);
2068         addr += offset;
2069         writew(data, hw->io + addr);
2070 }
2071 
2072 /**
2073  * sw_chk - check switch register bits
2074  * @hw:         The hardware instance.
2075  * @addr:       The address of the switch register.
2076  * @bits:       The data bits to check.
2077  *
2078  * This function checks whether the specified bits of the switch register are
2079  * set or not.
2080  *
2081  * Return 0 if the bits are not set.
2082  */
2083 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2084 {
2085         u16 data;
2086 
2087         data = readw(hw->io + addr);
2088         return (data & bits) == bits;
2089 }
2090 
2091 /**
2092  * sw_cfg - set switch register bits
2093  * @hw:         The hardware instance.
2094  * @addr:       The address of the switch register.
2095  * @bits:       The data bits to set.
2096  * @set:        The flag indicating whether the bits are to be set or not.
2097  *
2098  * This function sets or resets the specified bits of the switch register.
2099  */
2100 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2101 {
2102         u16 data;
2103 
2104         data = readw(hw->io + addr);
2105         if (set)
2106                 data |= bits;
2107         else
2108                 data &= ~bits;
2109         writew(data, hw->io + addr);
2110 }
2111 
2112 /* Bandwidth */
2113 
2114 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2115 {
2116         port_cfg(hw, p,
2117                 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2118 }
2119 
2120 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2121 {
2122         return port_chk(hw, p,
2123                 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2124 }
2125 
2126 /* Driver set switch broadcast storm protection at 10% rate. */
2127 #define BROADCAST_STORM_PROTECTION_RATE 10
2128 
2129 /* 148,800 frames * 67 ms / 100 */
2130 #define BROADCAST_STORM_VALUE           9969
2131 
2132 /**
2133  * sw_cfg_broad_storm - configure broadcast storm threshold
2134  * @hw:         The hardware instance.
2135  * @percent:    Broadcast storm threshold in percent of transmit rate.
2136  *
2137  * This routine configures the broadcast storm threshold of the switch.
2138  */
2139 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2140 {
2141         u16 data;
2142         u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2143 
2144         if (value > BROADCAST_STORM_RATE)
2145                 value = BROADCAST_STORM_RATE;
2146 
2147         data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2148         data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2149         data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2150         writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2151 }
2152 
2153 /**
2154  * sw_get_board_storm - get broadcast storm threshold
2155  * @hw:         The hardware instance.
2156  * @percent:    Buffer to store the broadcast storm threshold percentage.
2157  *
2158  * This routine retrieves the broadcast storm threshold of the switch.
2159  */
2160 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2161 {
2162         int num;
2163         u16 data;
2164 
2165         data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2166         num = (data & BROADCAST_STORM_RATE_HI);
2167         num <<= 8;
2168         num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2169         num = DIV_ROUND_CLOSEST(num * 100, BROADCAST_STORM_VALUE);
2170         *percent = (u8) num;
2171 }
2172 
2173 /**
2174  * sw_dis_broad_storm - disable broadstorm
2175  * @hw:         The hardware instance.
2176  * @port:       The port index.
2177  *
2178  * This routine disables the broadcast storm limit function of the switch.
2179  */
2180 static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2181 {
2182         port_cfg_broad_storm(hw, port, 0);
2183 }
2184 
2185 /**
2186  * sw_ena_broad_storm - enable broadcast storm
2187  * @hw:         The hardware instance.
2188  * @port:       The port index.
2189  *
2190  * This routine enables the broadcast storm limit function of the switch.
2191  */
2192 static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2193 {
2194         sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2195         port_cfg_broad_storm(hw, port, 1);
2196 }
2197 
2198 /**
2199  * sw_init_broad_storm - initialize broadcast storm
2200  * @hw:         The hardware instance.
2201  *
2202  * This routine initializes the broadcast storm limit function of the switch.
2203  */
2204 static void sw_init_broad_storm(struct ksz_hw *hw)
2205 {
2206         int port;
2207 
2208         hw->ksz_switch->broad_per = 1;
2209         sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2210         for (port = 0; port < TOTAL_PORT_NUM; port++)
2211                 sw_dis_broad_storm(hw, port);
2212         sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2213 }
2214 
2215 /**
2216  * hw_cfg_broad_storm - configure broadcast storm
2217  * @hw:         The hardware instance.
2218  * @percent:    Broadcast storm threshold in percent of transmit rate.
2219  *
2220  * This routine configures the broadcast storm threshold of the switch.
2221  * It is called by user functions.  The hardware should be acquired first.
2222  */
2223 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2224 {
2225         if (percent > 100)
2226                 percent = 100;
2227 
2228         sw_cfg_broad_storm(hw, percent);
2229         sw_get_broad_storm(hw, &percent);
2230         hw->ksz_switch->broad_per = percent;
2231 }
2232 
2233 /**
2234  * sw_dis_prio_rate - disable switch priority rate
2235  * @hw:         The hardware instance.
2236  * @port:       The port index.
2237  *
2238  * This routine disables the priority rate function of the switch.
2239  */
2240 static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2241 {
2242         u32 addr;
2243 
2244         PORT_CTRL_ADDR(port, addr);
2245         addr += KS8842_PORT_IN_RATE_OFFSET;
2246         writel(0, hw->io + addr);
2247 }
2248 
2249 /**
2250  * sw_init_prio_rate - initialize switch prioirty rate
2251  * @hw:         The hardware instance.
2252  *
2253  * This routine initializes the priority rate function of the switch.
2254  */
2255 static void sw_init_prio_rate(struct ksz_hw *hw)
2256 {
2257         int port;
2258         int prio;
2259         struct ksz_switch *sw = hw->ksz_switch;
2260 
2261         for (port = 0; port < TOTAL_PORT_NUM; port++) {
2262                 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2263                         sw->port_cfg[port].rx_rate[prio] =
2264                         sw->port_cfg[port].tx_rate[prio] = 0;
2265                 }
2266                 sw_dis_prio_rate(hw, port);
2267         }
2268 }
2269 
2270 /* Communication */
2271 
2272 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2273 {
2274         port_cfg(hw, p,
2275                 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2276 }
2277 
2278 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2279 {
2280         port_cfg(hw, p,
2281                 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2282 }
2283 
2284 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2285 {
2286         return port_chk(hw, p,
2287                 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2288 }
2289 
2290 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2291 {
2292         return port_chk(hw, p,
2293                 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2294 }
2295 
2296 /* Spanning Tree */
2297 
2298 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2299 {
2300         port_cfg(hw, p,
2301                 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2302 }
2303 
2304 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2305 {
2306         port_cfg(hw, p,
2307                 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2308 }
2309 
2310 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2311 {
2312         sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2313 }
2314 
2315 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2316 {
2317         if (!(hw->overrides & FAST_AGING)) {
2318                 sw_cfg_fast_aging(hw, 1);
2319                 mdelay(1);
2320                 sw_cfg_fast_aging(hw, 0);
2321         }
2322 }
2323 
2324 /* VLAN */
2325 
2326 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2327 {
2328         port_cfg(hw, p,
2329                 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2330 }
2331 
2332 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2333 {
2334         port_cfg(hw, p,
2335                 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2336 }
2337 
2338 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2339 {
2340         return port_chk(hw, p,
2341                 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2342 }
2343 
2344 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2345 {
2346         return port_chk(hw, p,
2347                 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2348 }
2349 
2350 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2351 {
2352         port_cfg(hw, p,
2353                 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2354 }
2355 
2356 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2357 {
2358         port_cfg(hw, p,
2359                 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2360 }
2361 
2362 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2363 {
2364         return port_chk(hw, p,
2365                 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2366 }
2367 
2368 static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2369 {
2370         return port_chk(hw, p,
2371                 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2372 }
2373 
2374 /* Mirroring */
2375 
2376 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2377 {
2378         port_cfg(hw, p,
2379                 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2380 }
2381 
2382 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2383 {
2384         port_cfg(hw, p,
2385                 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2386 }
2387 
2388 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2389 {
2390         port_cfg(hw, p,
2391                 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2392 }
2393 
2394 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2395 {
2396         sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2397 }
2398 
2399 static void sw_init_mirror(struct ksz_hw *hw)
2400 {
2401         int port;
2402 
2403         for (port = 0; port < TOTAL_PORT_NUM; port++) {
2404                 port_cfg_mirror_sniffer(hw, port, 0);
2405                 port_cfg_mirror_rx(hw, port, 0);
2406                 port_cfg_mirror_tx(hw, port, 0);
2407         }
2408         sw_cfg_mirror_rx_tx(hw, 0);
2409 }
2410 
2411 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2412 {
2413         sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2414                 SWITCH_UNK_DEF_PORT_ENABLE, set);
2415 }
2416 
2417 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2418 {
2419         return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2420                 SWITCH_UNK_DEF_PORT_ENABLE);
2421 }
2422 
2423 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2424 {
2425         port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2426 }
2427 
2428 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2429 {
2430         return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2431 }
2432 
2433 /* Priority */
2434 
2435 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2436 {
2437         port_cfg(hw, p,
2438                 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2439 }
2440 
2441 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2442 {
2443         port_cfg(hw, p,
2444                 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2445 }
2446 
2447 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2448 {
2449         port_cfg(hw, p,
2450                 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2451 }
2452 
2453 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2454 {
2455         port_cfg(hw, p,
2456                 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2457 }
2458 
2459 static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2460 {
2461         return port_chk(hw, p,
2462                 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2463 }
2464 
2465 static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2466 {
2467         return port_chk(hw, p,
2468                 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2469 }
2470 
2471 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2472 {
2473         return port_chk(hw, p,
2474                 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2475 }
2476 
2477 static inline int port_chk_prio(struct ksz_hw *hw, int p)
2478 {
2479         return port_chk(hw, p,
2480                 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2481 }
2482 
2483 /**
2484  * sw_dis_diffserv - disable switch DiffServ priority
2485  * @hw:         The hardware instance.
2486  * @port:       The port index.
2487  *
2488  * This routine disables the DiffServ priority function of the switch.
2489  */
2490 static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2491 {
2492         port_cfg_diffserv(hw, port, 0);
2493 }
2494 
2495 /**
2496  * sw_dis_802_1p - disable switch 802.1p priority
2497  * @hw:         The hardware instance.
2498  * @port:       The port index.
2499  *
2500  * This routine disables the 802.1p priority function of the switch.
2501  */
2502 static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2503 {
2504         port_cfg_802_1p(hw, port, 0);
2505 }
2506 
2507 /**
2508  * sw_cfg_replace_null_vid -
2509  * @hw:         The hardware instance.
2510  * @set:        The flag to disable or enable.
2511  *
2512  */
2513 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2514 {
2515         sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2516 }
2517 
2518 /**
2519  * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2520  * @hw:         The hardware instance.
2521  * @port:       The port index.
2522  * @set:        The flag to disable or enable.
2523  *
2524  * This routine enables the 802.1p priority re-mapping function of the switch.
2525  * That allows 802.1p priority field to be replaced with the port's default
2526  * tag's priority value if the ingress packet's 802.1p priority has a higher
2527  * priority than port's default tag's priority.
2528  */
2529 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2530 {
2531         port_cfg_replace_vid(hw, port, set);
2532 }
2533 
2534 /**
2535  * sw_cfg_port_based - configure switch port based priority
2536  * @hw:         The hardware instance.
2537  * @port:       The port index.
2538  * @prio:       The priority to set.
2539  *
2540  * This routine configures the port based priority of the switch.
2541  */
2542 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2543 {
2544         u16 data;
2545 
2546         if (prio > PORT_BASED_PRIORITY_BASE)
2547                 prio = PORT_BASED_PRIORITY_BASE;
2548 
2549         hw->ksz_switch->port_cfg[port].port_prio = prio;
2550 
2551         port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2552         data &= ~PORT_BASED_PRIORITY_MASK;
2553         data |= prio << PORT_BASED_PRIORITY_SHIFT;
2554         port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2555 }
2556 
2557 /**
2558  * sw_dis_multi_queue - disable transmit multiple queues
2559  * @hw:         The hardware instance.
2560  * @port:       The port index.
2561  *
2562  * This routine disables the transmit multiple queues selection of the switch
2563  * port.  Only single transmit queue on the port.
2564  */
2565 static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2566 {
2567         port_cfg_prio(hw, port, 0);
2568 }
2569 
2570 /**
2571  * sw_init_prio - initialize switch priority
2572  * @hw:         The hardware instance.
2573  *
2574  * This routine initializes the switch QoS priority functions.
2575  */
2576 static void sw_init_prio(struct ksz_hw *hw)
2577 {
2578         int port;
2579         int tos;
2580         struct ksz_switch *sw = hw->ksz_switch;
2581 
2582         /*
2583          * Init all the 802.1p tag priority value to be assigned to different
2584          * priority queue.
2585          */
2586         sw->p_802_1p[0] = 0;
2587         sw->p_802_1p[1] = 0;
2588         sw->p_802_1p[2] = 1;
2589         sw->p_802_1p[3] = 1;
2590         sw->p_802_1p[4] = 2;
2591         sw->p_802_1p[5] = 2;
2592         sw->p_802_1p[6] = 3;
2593         sw->p_802_1p[7] = 3;
2594 
2595         /*
2596          * Init all the DiffServ priority value to be assigned to priority
2597          * queue 0.
2598          */
2599         for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2600                 sw->diffserv[tos] = 0;
2601 
2602         /* All QoS functions disabled. */
2603         for (port = 0; port < TOTAL_PORT_NUM; port++) {
2604                 sw_dis_multi_queue(hw, port);
2605                 sw_dis_diffserv(hw, port);
2606                 sw_dis_802_1p(hw, port);
2607                 sw_cfg_replace_vid(hw, port, 0);
2608 
2609                 sw->port_cfg[port].port_prio = 0;
2610                 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2611         }
2612         sw_cfg_replace_null_vid(hw, 0);
2613 }
2614 
2615 /**
2616  * port_get_def_vid - get port default VID.
2617  * @hw:         The hardware instance.
2618  * @port:       The port index.
2619  * @vid:        Buffer to store the VID.
2620  *
2621  * This routine retrieves the default VID of the port.
2622  */
2623 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2624 {
2625         u32 addr;
2626 
2627         PORT_CTRL_ADDR(port, addr);
2628         addr += KS8842_PORT_CTRL_VID_OFFSET;
2629         *vid = readw(hw->io + addr);
2630 }
2631 
2632 /**
2633  * sw_init_vlan - initialize switch VLAN
2634  * @hw:         The hardware instance.
2635  *
2636  * This routine initializes the VLAN function of the switch.
2637  */
2638 static void sw_init_vlan(struct ksz_hw *hw)
2639 {
2640         int port;
2641         int entry;
2642         struct ksz_switch *sw = hw->ksz_switch;
2643 
2644         /* Read 16 VLAN entries from device's VLAN table. */
2645         for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2646                 sw_r_vlan_table(hw, entry,
2647                         &sw->vlan_table[entry].vid,
2648                         &sw->vlan_table[entry].fid,
2649                         &sw->vlan_table[entry].member);
2650         }
2651 
2652         for (port = 0; port < TOTAL_PORT_NUM; port++) {
2653                 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2654                 sw->port_cfg[port].member = PORT_MASK;
2655         }
2656 }
2657 
2658 /**
2659  * sw_cfg_port_base_vlan - configure port-based VLAN membership
2660  * @hw:         The hardware instance.
2661  * @port:       The port index.
2662  * @member:     The port-based VLAN membership.
2663  *
2664  * This routine configures the port-based VLAN membership of the port.
2665  */
2666 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2667 {
2668         u32 addr;
2669         u8 data;
2670 
2671         PORT_CTRL_ADDR(port, addr);
2672         addr += KS8842_PORT_CTRL_2_OFFSET;
2673 
2674         data = readb(hw->io + addr);
2675         data &= ~PORT_VLAN_MEMBERSHIP;
2676         data |= (member & PORT_MASK);
2677         writeb(data, hw->io + addr);
2678 
2679         hw->ksz_switch->port_cfg[port].member = member;
2680 }
2681 
2682 /**
2683  * sw_get_addr - get the switch MAC address.
2684  * @hw:         The hardware instance.
2685  * @mac_addr:   Buffer to store the MAC address.
2686  *
2687  * This function retrieves the MAC address of the switch.
2688  */
2689 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2690 {
2691         int i;
2692 
2693         for (i = 0; i < 6; i += 2) {
2694                 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2695                 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2696         }
2697 }
2698 
2699 /**
2700  * sw_set_addr - configure switch MAC address
2701  * @hw:         The hardware instance.
2702  * @mac_addr:   The MAC address.
2703  *
2704  * This function configures the MAC address of the switch.
2705  */
2706 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2707 {
2708         int i;
2709 
2710         for (i = 0; i < 6; i += 2) {
2711                 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2712                 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2713         }
2714 }
2715 
2716 /**
2717  * sw_set_global_ctrl - set switch global control
2718  * @hw:         The hardware instance.
2719  *
2720  * This routine sets the global control of the switch function.
2721  */
2722 static void sw_set_global_ctrl(struct ksz_hw *hw)
2723 {
2724         u16 data;
2725 
2726         /* Enable switch MII flow control. */
2727         data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2728         data |= SWITCH_FLOW_CTRL;
2729         writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2730 
2731         data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2732 
2733         /* Enable aggressive back off algorithm in half duplex mode. */
2734         data |= SWITCH_AGGR_BACKOFF;
2735 
2736         /* Enable automatic fast aging when link changed detected. */
2737         data |= SWITCH_AGING_ENABLE;
2738         data |= SWITCH_LINK_AUTO_AGING;
2739 
2740         if (hw->overrides & FAST_AGING)
2741                 data |= SWITCH_FAST_AGING;
2742         else
2743                 data &= ~SWITCH_FAST_AGING;
2744         writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2745 
2746         data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2747 
2748         /* Enable no excessive collision drop. */
2749         data |= NO_EXC_COLLISION_DROP;
2750         writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2751 }
2752 
2753 enum {
2754         STP_STATE_DISABLED = 0,
2755         STP_STATE_LISTENING,
2756         STP_STATE_LEARNING,
2757         STP_STATE_FORWARDING,
2758         STP_STATE_BLOCKED,
2759         STP_STATE_SIMPLE
2760 };
2761 
2762 /**
2763  * port_set_stp_state - configure port spanning tree state
2764  * @hw:         The hardware instance.
2765  * @port:       The port index.
2766  * @state:      The spanning tree state.
2767  *
2768  * This routine configures the spanning tree state of the port.
2769  */
2770 static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2771 {
2772         u16 data;
2773 
2774         port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2775         switch (state) {
2776         case STP_STATE_DISABLED:
2777                 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2778                 data |= PORT_LEARN_DISABLE;
2779                 break;
2780         case STP_STATE_LISTENING:
2781 /*
2782  * No need to turn on transmit because of port direct mode.
2783  * Turning on receive is required if static MAC table is not setup.
2784  */
2785                 data &= ~PORT_TX_ENABLE;
2786                 data |= PORT_RX_ENABLE;
2787                 data |= PORT_LEARN_DISABLE;
2788                 break;
2789         case STP_STATE_LEARNING:
2790                 data &= ~PORT_TX_ENABLE;
2791                 data |= PORT_RX_ENABLE;
2792                 data &= ~PORT_LEARN_DISABLE;
2793                 break;
2794         case STP_STATE_FORWARDING:
2795                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2796                 data &= ~PORT_LEARN_DISABLE;
2797                 break;
2798         case STP_STATE_BLOCKED:
2799 /*
2800  * Need to setup static MAC table with override to keep receiving BPDU
2801  * messages.  See sw_init_stp routine.
2802  */
2803                 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2804                 data |= PORT_LEARN_DISABLE;
2805                 break;
2806         case STP_STATE_SIMPLE:
2807                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2808                 data |= PORT_LEARN_DISABLE;
2809                 break;
2810         }
2811         port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2812         hw->ksz_switch->port_cfg[port].stp_state = state;
2813 }
2814 
2815 #define STP_ENTRY                       0
2816 #define BROADCAST_ENTRY                 1
2817 #define BRIDGE_ADDR_ENTRY               2
2818 #define IPV6_ADDR_ENTRY                 3
2819 
2820 /**
2821  * sw_clr_sta_mac_table - clear static MAC table
2822  * @hw:         The hardware instance.
2823  *
2824  * This routine clears the static MAC table.
2825  */
2826 static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2827 {
2828         struct ksz_mac_table *entry;
2829         int i;
2830 
2831         for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2832                 entry = &hw->ksz_switch->mac_table[i];
2833                 sw_w_sta_mac_table(hw, i,
2834                         entry->mac_addr, entry->ports,
2835                         entry->override, 0,
2836                         entry->use_fid, entry->fid);
2837         }
2838 }
2839 
2840 /**
2841  * sw_init_stp - initialize switch spanning tree support
2842  * @hw:         The hardware instance.
2843  *
2844  * This routine initializes the spanning tree support of the switch.
2845  */
2846 static void sw_init_stp(struct ksz_hw *hw)
2847 {
2848         struct ksz_mac_table *entry;
2849 
2850         entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2851         entry->mac_addr[0] = 0x01;
2852         entry->mac_addr[1] = 0x80;
2853         entry->mac_addr[2] = 0xC2;
2854         entry->mac_addr[3] = 0x00;
2855         entry->mac_addr[4] = 0x00;
2856         entry->mac_addr[5] = 0x00;
2857         entry->ports = HOST_MASK;
2858         entry->override = 1;
2859         entry->valid = 1;
2860         sw_w_sta_mac_table(hw, STP_ENTRY,
2861                 entry->mac_addr, entry->ports,
2862                 entry->override, entry->valid,
2863                 entry->use_fid, entry->fid);
2864 }
2865 
2866 /**
2867  * sw_block_addr - block certain packets from the host port
2868  * @hw:         The hardware instance.
2869  *
2870  * This routine blocks certain packets from reaching to the host port.
2871  */
2872 static void sw_block_addr(struct ksz_hw *hw)
2873 {
2874         struct ksz_mac_table *entry;
2875         int i;
2876 
2877         for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2878                 entry = &hw->ksz_switch->mac_table[i];
2879                 entry->valid = 0;
2880                 sw_w_sta_mac_table(hw, i,
2881                         entry->mac_addr, entry->ports,
2882                         entry->override, entry->valid,
2883                         entry->use_fid, entry->fid);
2884         }
2885 }
2886 
2887 #define PHY_LINK_SUPPORT                \
2888         (PHY_AUTO_NEG_ASYM_PAUSE |      \
2889         PHY_AUTO_NEG_SYM_PAUSE |        \
2890         PHY_AUTO_NEG_100BT4 |           \
2891         PHY_AUTO_NEG_100BTX_FD |        \
2892         PHY_AUTO_NEG_100BTX |           \
2893         PHY_AUTO_NEG_10BT_FD |          \
2894         PHY_AUTO_NEG_10BT)
2895 
2896 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2897 {
2898         *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2899 }
2900 
2901 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2902 {
2903         writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2904 }
2905 
2906 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2907 {
2908         *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2909 }
2910 
2911 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2912 {
2913         *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2914 }
2915 
2916 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2917 {
2918         writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2919 }
2920 
2921 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2922 {
2923         *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2924 }
2925 
2926 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2927 {
2928         *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2929 }
2930 
2931 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2932 {
2933         writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2934 }
2935 
2936 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2937 {
2938         *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2939 }
2940 
2941 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2942 {
2943         writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2944 }
2945 
2946 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2947 {
2948         *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2949 }
2950 
2951 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2952 {
2953         writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2954 }
2955 
2956 /**
2957  * hw_r_phy - read data from PHY register
2958  * @hw:         The hardware instance.
2959  * @port:       Port to read.
2960  * @reg:        PHY register to read.
2961  * @val:        Buffer to store the read data.
2962  *
2963  * This routine reads data from the PHY register.
2964  */
2965 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2966 {
2967         int phy;
2968 
2969         phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2970         *val = readw(hw->io + phy);
2971 }
2972 
2973 /**
2974  * port_w_phy - write data to PHY register
2975  * @hw:         The hardware instance.
2976  * @port:       Port to write.
2977  * @reg:        PHY register to write.
2978  * @val:        Word data to write.
2979  *
2980  * This routine writes data to the PHY register.
2981  */
2982 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2983 {
2984         int phy;
2985 
2986         phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2987         writew(val, hw->io + phy);
2988 }
2989 
2990 /*
2991  * EEPROM access functions
2992  */
2993 
2994 #define AT93C_CODE                      0
2995 #define AT93C_WR_OFF                    0x00
2996 #define AT93C_WR_ALL                    0x10
2997 #define AT93C_ER_ALL                    0x20
2998 #define AT93C_WR_ON                     0x30
2999 
3000 #define AT93C_WRITE                     1
3001 #define AT93C_READ                      2
3002 #define AT93C_ERASE                     3
3003 
3004 #define EEPROM_DELAY                    4
3005 
3006 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3007 {
3008         u16 data;
3009 
3010         data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3011         data &= ~gpio;
3012         writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3013 }
3014 
3015 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3016 {
3017         u16 data;
3018 
3019         data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3020         data |= gpio;
3021         writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3022 }
3023 
3024 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3025 {
3026         u16 data;
3027 
3028         data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3029         return (u8)(data & gpio);
3030 }
3031 
3032 static void eeprom_clk(struct ksz_hw *hw)
3033 {
3034         raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3035         udelay(EEPROM_DELAY);
3036         drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3037         udelay(EEPROM_DELAY);
3038 }
3039 
3040 static u16 spi_r(struct ksz_hw *hw)
3041 {
3042         int i;
3043         u16 temp = 0;
3044 
3045         for (i = 15; i >= 0; i--) {
3046                 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3047                 udelay(EEPROM_DELAY);
3048 
3049                 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3050 
3051                 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3052                 udelay(EEPROM_DELAY);
3053         }
3054         return temp;
3055 }
3056 
3057 static void spi_w(struct ksz_hw *hw, u16 data)
3058 {
3059         int i;
3060 
3061         for (i = 15; i >= 0; i--) {
3062                 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3063                         drop_gpio(hw, EEPROM_DATA_OUT);
3064                 eeprom_clk(hw);
3065         }
3066 }
3067 
3068 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3069 {
3070         int i;
3071 
3072         /* Initial start bit */
3073         raise_gpio(hw, EEPROM_DATA_OUT);
3074         eeprom_clk(hw);
3075 
3076         /* AT93C operation */
3077         for (i = 1; i >= 0; i--) {
3078                 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3079                         drop_gpio(hw, EEPROM_DATA_OUT);
3080                 eeprom_clk(hw);
3081         }
3082 
3083         /* Address location */
3084         for (i = 5; i >= 0; i--) {
3085                 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3086                         drop_gpio(hw, EEPROM_DATA_OUT);
3087                 eeprom_clk(hw);
3088         }
3089 }
3090 
3091 #define EEPROM_DATA_RESERVED            0
3092 #define EEPROM_DATA_MAC_ADDR_0          1
3093 #define EEPROM_DATA_MAC_ADDR_1          2
3094 #define EEPROM_DATA_MAC_ADDR_2          3
3095 #define EEPROM_DATA_SUBSYS_ID           4
3096 #define EEPROM_DATA_SUBSYS_VEN_ID       5
3097 #define EEPROM_DATA_PM_CAP              6
3098 
3099 /* User defined EEPROM data */
3100 #define EEPROM_DATA_OTHER_MAC_ADDR      9
3101 
3102 /**
3103  * eeprom_read - read from AT93C46 EEPROM
3104  * @hw:         The hardware instance.
3105  * @reg:        The register offset.
3106  *
3107  * This function reads a word from the AT93C46 EEPROM.
3108  *
3109  * Return the data value.
3110  */
3111 static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3112 {
3113         u16 data;
3114 
3115         raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3116 
3117         spi_reg(hw, AT93C_READ, reg);
3118         data = spi_r(hw);
3119 
3120         drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3121 
3122         return data;
3123 }
3124 
3125 /**
3126  * eeprom_write - write to AT93C46 EEPROM
3127  * @hw:         The hardware instance.
3128  * @reg:        The register offset.
3129  * @data:       The data value.
3130  *
3131  * This procedure writes a word to the AT93C46 EEPROM.
3132  */
3133 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3134 {
3135         int timeout;
3136 
3137         raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3138 
3139         /* Enable write. */
3140         spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3141         drop_gpio(hw, EEPROM_CHIP_SELECT);
3142         udelay(1);
3143 
3144         /* Erase the register. */
3145         raise_gpio(hw, EEPROM_CHIP_SELECT);
3146         spi_reg(hw, AT93C_ERASE, reg);
3147         drop_gpio(hw, EEPROM_CHIP_SELECT);
3148         udelay(1);
3149 
3150         /* Check operation complete. */
3151         raise_gpio(hw, EEPROM_CHIP_SELECT);
3152         timeout = 8;
3153         mdelay(2);
3154         do {
3155                 mdelay(1);
3156         } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3157         drop_gpio(hw, EEPROM_CHIP_SELECT);
3158         udelay(1);
3159 
3160         /* Write the register. */
3161         raise_gpio(hw, EEPROM_CHIP_SELECT);
3162         spi_reg(hw, AT93C_WRITE, reg);
3163         spi_w(hw, data);
3164         drop_gpio(hw, EEPROM_CHIP_SELECT);
3165         udelay(1);
3166 
3167         /* Check operation complete. */
3168         raise_gpio(hw, EEPROM_CHIP_SELECT);
3169         timeout = 8;
3170         mdelay(2);
3171         do {
3172                 mdelay(1);
3173         } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3174         drop_gpio(hw, EEPROM_CHIP_SELECT);
3175         udelay(1);
3176 
3177         /* Disable write. */
3178         raise_gpio(hw, EEPROM_CHIP_SELECT);
3179         spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3180 
3181         drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3182 }
3183 
3184 /*
3185  * Link detection routines
3186  */
3187 
3188 static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3189 {
3190         ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3191         switch (port->flow_ctrl) {
3192         case PHY_FLOW_CTRL:
3193                 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3194                 break;
3195         /* Not supported. */
3196         case PHY_TX_ONLY:
3197         case PHY_RX_ONLY:
3198         default:
3199                 break;
3200         }
3201         return ctrl;
3202 }
3203 
3204 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3205 {
3206         u32 rx_cfg;
3207         u32 tx_cfg;
3208 
3209         rx_cfg = hw->rx_cfg;
3210         tx_cfg = hw->tx_cfg;
3211         if (rx)
3212                 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3213         else
3214                 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3215         if (tx)
3216                 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3217         else
3218                 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3219         if (hw->enabled) {
3220                 if (rx_cfg != hw->rx_cfg)
3221                         writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3222                 if (tx_cfg != hw->tx_cfg)
3223                         writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3224         }
3225 }
3226 
3227 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3228         u16 local, u16 remote)
3229 {
3230         int rx;
3231         int tx;
3232 
3233         if (hw->overrides & PAUSE_FLOW_CTRL)
3234                 return;
3235 
3236         rx = tx = 0;
3237         if (port->force_link)
3238                 rx = tx = 1;
3239         if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3240                 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3241                         rx = tx = 1;
3242                 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3243                                 (local & PHY_AUTO_NEG_PAUSE) ==
3244                                 PHY_AUTO_NEG_ASYM_PAUSE) {
3245                         tx = 1;
3246                 }
3247         } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3248                 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3249                         rx = 1;
3250         }
3251         if (!hw->ksz_switch)
3252                 set_flow_ctrl(hw, rx, tx);
3253 }
3254 
3255 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3256         struct ksz_port_info *info, u16 link_status)
3257 {
3258         if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3259                         !(hw->overrides & PAUSE_FLOW_CTRL)) {
3260                 u32 cfg = hw->tx_cfg;
3261 
3262                 /* Disable flow control in the half duplex mode. */
3263                 if (1 == info->duplex)
3264                         hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3265                 if (hw->enabled && cfg != hw->tx_cfg)
3266                         writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3267         }
3268 }
3269 
3270 /**
3271  * port_get_link_speed - get current link status
3272  * @port:       The port instance.
3273  *
3274  * This routine reads PHY registers to determine the current link status of the
3275  * switch ports.
3276  */
3277 static void port_get_link_speed(struct ksz_port *port)
3278 {
3279         uint interrupt;
3280         struct ksz_port_info *info;
3281         struct ksz_port_info *linked = NULL;
3282         struct ksz_hw *hw = port->hw;
3283         u16 data;
3284         u16 status;
3285         u8 local;
3286         u8 remote;
3287         int i;
3288         int p;
3289         int change = 0;
3290 
3291         interrupt = hw_block_intr(hw);
3292 
3293         for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3294                 info = &hw->port_info[p];
3295                 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3296                 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3297 
3298                 /*
3299                  * Link status is changing all the time even when there is no
3300                  * cable connection!
3301                  */
3302                 remote = status & (PORT_AUTO_NEG_COMPLETE |
3303                         PORT_STATUS_LINK_GOOD);
3304                 local = (u8) data;
3305 
3306                 /* No change to status. */
3307                 if (local == info->advertised && remote == info->partner)
3308                         continue;
3309 
3310                 info->advertised = local;
3311                 info->partner = remote;
3312                 if (status & PORT_STATUS_LINK_GOOD) {
3313 
3314                         /* Remember the first linked port. */
3315                         if (!linked)
3316                                 linked = info;
3317 
3318                         info->tx_rate = 10 * TX_RATE_UNIT;
3319                         if (status & PORT_STATUS_SPEED_100MBIT)
3320                                 info->tx_rate = 100 * TX_RATE_UNIT;
3321 
3322                         info->duplex = 1;
3323                         if (status & PORT_STATUS_FULL_DUPLEX)
3324                                 info->duplex = 2;
3325 
3326                         if (media_connected != info->state) {
3327                                 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3328                                         &data);
3329                                 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3330                                         &status);
3331                                 determine_flow_ctrl(hw, port, data, status);
3332                                 if (hw->ksz_switch) {
3333                                         port_cfg_back_pressure(hw, p,
3334                                                 (1 == info->duplex));
3335                                 }
3336                                 change |= 1 << i;
3337                                 port_cfg_change(hw, port, info, status);
3338                         }
3339                         info->state = media_connected;
3340                 } else {
3341                         if (media_disconnected != info->state) {
3342                                 change |= 1 << i;
3343 
3344                                 /* Indicate the link just goes down. */
3345                                 hw->port_mib[p].link_down = 1;
3346                         }
3347                         info->state = media_disconnected;
3348                 }
3349                 hw->port_mib[p].state = (u8) info->state;
3350         }
3351 
3352         if (linked && media_disconnected == port->linked->state)
3353                 port->linked = linked;
3354 
3355         hw_restore_intr(hw, interrupt);
3356 }
3357 
3358 #define PHY_RESET_TIMEOUT               10
3359 
3360 /**
3361  * port_set_link_speed - set port speed
3362  * @port:       The port instance.
3363  *
3364  * This routine sets the link speed of the switch ports.
3365  */
3366 static void port_set_link_speed(struct ksz_port *port)
3367 {
3368         struct ksz_hw *hw = port->hw;
3369         u16 data;
3370         u16 cfg;
3371         u8 status;
3372         int i;
3373         int p;
3374 
3375         for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3376                 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3377                 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3378 
3379                 cfg = 0;
3380                 if (status & PORT_STATUS_LINK_GOOD)
3381                         cfg = data;
3382 
3383                 data |= PORT_AUTO_NEG_ENABLE;
3384                 data = advertised_flow_ctrl(port, data);
3385 
3386                 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3387                         PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3388 
3389                 /* Check if manual configuration is specified by the user. */
3390                 if (port->speed || port->duplex) {
3391                         if (10 == port->speed)
3392                                 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3393                                         PORT_AUTO_NEG_100BTX);
3394                         else if (100 == port->speed)
3395                                 data &= ~(PORT_AUTO_NEG_10BT_FD |
3396                                         PORT_AUTO_NEG_10BT);
3397                         if (1 == port->duplex)
3398                                 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3399                                         PORT_AUTO_NEG_10BT_FD);
3400                         else if (2 == port->duplex)
3401                                 data &= ~(PORT_AUTO_NEG_100BTX |
3402                                         PORT_AUTO_NEG_10BT);
3403                 }
3404                 if (data != cfg) {
3405                         data |= PORT_AUTO_NEG_RESTART;
3406                         port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3407                 }
3408         }
3409 }
3410 
3411 /**
3412  * port_force_link_speed - force port speed
3413  * @port:       The port instance.
3414  *
3415  * This routine forces the link speed of the switch ports.
3416  */
3417 static void port_force_link_speed(struct ksz_port *port)
3418 {
3419         struct ksz_hw *hw = port->hw;
3420         u16 data;
3421         int i;
3422         int phy;
3423         int p;
3424 
3425         for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3426                 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3427                 hw_r_phy_ctrl(hw, phy, &data);
3428 
3429                 data &= ~PHY_AUTO_NEG_ENABLE;
3430 
3431                 if (10 == port->speed)
3432                         data &= ~PHY_SPEED_100MBIT;
3433                 else if (100 == port->speed)
3434                         data |= PHY_SPEED_100MBIT;
3435                 if (1 == port->duplex)
3436                         data &= ~PHY_FULL_DUPLEX;
3437                 else if (2 == port->duplex)
3438                         data |= PHY_FULL_DUPLEX;
3439                 hw_w_phy_ctrl(hw, phy, data);
3440         }
3441 }
3442 
3443 static void port_set_power_saving(struct ksz_port *port, int enable)
3444 {
3445         struct ksz_hw *hw = port->hw;
3446         int i;
3447         int p;
3448 
3449         for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3450                 port_cfg(hw, p,
3451                         KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3452 }
3453 
3454 /*
3455  * KSZ8841 power management functions
3456  */
3457 
3458 /**
3459  * hw_chk_wol_pme_status - check PMEN pin
3460  * @hw:         The hardware instance.
3461  *
3462  * This function is used to check PMEN pin is asserted.
3463  *
3464  * Return 1 if PMEN pin is asserted; otherwise, 0.
3465  */
3466 static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3467 {
3468         struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3469         struct pci_dev *pdev = hw_priv->pdev;
3470         u16 data;
3471 
3472         if (!pdev->pm_cap)
3473                 return 0;
3474         pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3475         return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3476 }
3477 
3478 /**
3479  * hw_clr_wol_pme_status - clear PMEN pin
3480  * @hw:         The hardware instance.
3481  *
3482  * This routine is used to clear PME_Status to deassert PMEN pin.
3483  */
3484 static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3485 {
3486         struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3487         struct pci_dev *pdev = hw_priv->pdev;
3488         u16 data;
3489 
3490         if (!pdev->pm_cap)
3491                 return;
3492 
3493         /* Clear PME_Status to deassert PMEN pin. */
3494         pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3495         data |= PCI_PM_CTRL_PME_STATUS;
3496         pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3497 }
3498 
3499 /**
3500  * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3501  * @hw:         The hardware instance.
3502  * @set:        The flag indicating whether to enable or disable.
3503  *
3504  * This routine is used to enable or disable Wake-on-LAN.
3505  */
3506 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3507 {
3508         struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3509         struct pci_dev *pdev = hw_priv->pdev;
3510         u16 data;
3511 
3512         if (!pdev->pm_cap)
3513                 return;
3514         pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3515         data &= ~PCI_PM_CTRL_STATE_MASK;
3516         if (set)
3517                 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3518         else
3519                 data &= ~PCI_PM_CTRL_PME_ENABLE;
3520         pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3521 }
3522 
3523 /**
3524  * hw_cfg_wol - configure Wake-on-LAN features
3525  * @hw:         The hardware instance.
3526  * @frame:      The pattern frame bit.
3527  * @set:        The flag indicating whether to enable or disable.
3528  *
3529  * This routine is used to enable or disable certain Wake-on-LAN features.
3530  */
3531 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3532 {
3533         u16 data;
3534 
3535         data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3536         if (set)
3537                 data |= frame;
3538         else
3539                 data &= ~frame;
3540         writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3541 }
3542 
3543 /**
3544  * hw_set_wol_frame - program Wake-on-LAN pattern
3545  * @hw:         The hardware instance.
3546  * @i:          The frame index.
3547  * @mask_size:  The size of the mask.
3548  * @mask:       Mask to ignore certain bytes in the pattern.
3549  * @frame_size: The size of the frame.
3550  * @pattern:    The frame data.
3551  *
3552  * This routine is used to program Wake-on-LAN pattern.
3553  */
3554 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3555         const u8 *mask, uint frame_size, const u8 *pattern)
3556 {
3557         int bits;
3558         int from;
3559         int len;
3560         int to;
3561         u32 crc;
3562         u8 data[64];
3563         u8 val = 0;
3564 
3565         if (frame_size > mask_size * 8)
3566                 frame_size = mask_size * 8;
3567         if (frame_size > 64)
3568                 frame_size = 64;
3569 
3570         i *= 0x10;
3571         writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3572         writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3573 
3574         bits = len = from = to = 0;
3575         do {
3576                 if (bits) {
3577                         if ((val & 1))
3578                                 data[to++] = pattern[from];
3579                         val >>= 1;
3580                         ++from;
3581                         --bits;
3582                 } else {
3583                         val = mask[len];
3584                         writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3585                                 + len);
3586                         ++len;
3587                         if (val)
3588                                 bits = 8;
3589                         else
3590                                 from += 8;
3591                 }
3592         } while (from < (int) frame_size);
3593         if (val) {
3594                 bits = mask[len - 1];
3595                 val <<= (from % 8);
3596                 bits &= ~val;
3597                 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3598                         1);
3599         }
3600         crc = ether_crc(to, data);
3601         writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3602 }
3603 
3604 /**
3605  * hw_add_wol_arp - add ARP pattern
3606  * @hw:         The hardware instance.
3607  * @ip_addr:    The IPv4 address assigned to the device.
3608  *
3609  * This routine is used to add ARP pattern for waking up the host.
3610  */
3611 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3612 {
3613         static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3614         u8 pattern[42] = {
3615                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3616                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3617                 0x08, 0x06,
3618                 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3619                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3620                 0x00, 0x00, 0x00, 0x00,
3621                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3622                 0x00, 0x00, 0x00, 0x00 };
3623 
3624         memcpy(&pattern[38], ip_addr, 4);
3625         hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3626 }
3627 
3628 /**
3629  * hw_add_wol_bcast - add broadcast pattern
3630  * @hw:         The hardware instance.
3631  *
3632  * This routine is used to add broadcast pattern for waking up the host.
3633  */
3634 static void hw_add_wol_bcast(struct ksz_hw *hw)
3635 {
3636         static const u8 mask[] = { 0x3F };
3637         static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3638 
3639         hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3640 }
3641 
3642 /**
3643  * hw_add_wol_mcast - add multicast pattern
3644  * @hw:         The hardware instance.
3645  *
3646  * This routine is used to add multicast pattern for waking up the host.
3647  *
3648  * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3649  * by IPv6 ping command.  Note that multicast packets are filtred through the
3650  * multicast hash table, so not all multicast packets can wake up the host.
3651  */
3652 static void hw_add_wol_mcast(struct ksz_hw *hw)
3653 {
3654         static const u8 mask[] = { 0x3F };
3655         u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3656 
3657         memcpy(&pattern[3], &hw->override_addr[3], 3);
3658         hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3659 }
3660 
3661 /**
3662  * hw_add_wol_ucast - add unicast pattern
3663  * @hw:         The hardware instance.
3664  *
3665  * This routine is used to add unicast pattern to wakeup the host.
3666  *
3667  * It is assumed the unicast packet is directed to the device, as the hardware
3668  * can only receive them in normal case.
3669  */
3670 static void hw_add_wol_ucast(struct ksz_hw *hw)
3671 {
3672         static const u8 mask[] = { 0x3F };
3673 
3674         hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3675 }
3676 
3677 /**
3678  * hw_enable_wol - enable Wake-on-LAN
3679  * @hw:         The hardware instance.
3680  * @wol_enable: The Wake-on-LAN settings.
3681  * @net_addr:   The IPv4 address assigned to the device.
3682  *
3683  * This routine is used to enable Wake-on-LAN depending on driver settings.
3684  */
3685 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3686 {
3687         hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3688         hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3689         hw_add_wol_ucast(hw);
3690         hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3691         hw_add_wol_mcast(hw);
3692         hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3693         hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3694         hw_add_wol_arp(hw, net_addr);
3695 }
3696 
3697 /**
3698  * hw_init - check driver is correct for the hardware
3699  * @hw:         The hardware instance.
3700  *
3701  * This function checks the hardware is correct for this driver and sets the
3702  * hardware up for proper initialization.
3703  *
3704  * Return number of ports or 0 if not right.
3705  */
3706 static int hw_init(struct ksz_hw *hw)
3707 {
3708         int rc = 0;
3709         u16 data;
3710         u16 revision;
3711 
3712         /* Set bus speed to 125MHz. */
3713         writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3714 
3715         /* Check KSZ884x chip ID. */
3716         data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3717 
3718         revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3719         data &= KS884X_CHIP_ID_MASK_41;
3720         if (REG_CHIP_ID_41 == data)
3721                 rc = 1;
3722         else if (REG_CHIP_ID_42 == data)
3723                 rc = 2;
3724         else
3725                 return 0;
3726 
3727         /* Setup hardware features or bug workarounds. */
3728         if (revision <= 1) {
3729                 hw->features |= SMALL_PACKET_TX_BUG;
3730                 if (1 == rc)
3731                         hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3732         }
3733         return rc;
3734 }
3735 
3736 /**
3737  * hw_reset - reset the hardware
3738  * @hw:         The hardware instance.
3739  *
3740  * This routine resets the hardware.
3741  */
3742 static void hw_reset(struct ksz_hw *hw)
3743 {
3744         writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3745 
3746         /* Wait for device to reset. */
3747         mdelay(10);
3748 
3749         /* Write 0 to clear device reset. */
3750         writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3751 }
3752 
3753 /**
3754  * hw_setup - setup the hardware
3755  * @hw:         The hardware instance.
3756  *
3757  * This routine setup the hardware for proper operation.
3758  */
3759 static void hw_setup(struct ksz_hw *hw)
3760 {
3761 #if SET_DEFAULT_LED
3762         u16 data;
3763 
3764         /* Change default LED mode. */
3765         data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3766         data &= ~LED_MODE;
3767         data |= SET_DEFAULT_LED;
3768         writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3769 #endif
3770 
3771         /* Setup transmit control. */
3772         hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3773                 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3774 
3775         /* Setup receive control. */
3776         hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3777                 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3778         hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3779 
3780         /* Hardware cannot handle UDP packet in IP fragments. */
3781         hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3782 
3783         if (hw->all_multi)
3784                 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3785         if (hw->promiscuous)
3786                 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3787 }
3788 
3789 /**
3790  * hw_setup_intr - setup interrupt mask
3791  * @hw:         The hardware instance.
3792  *
3793  * This routine setup the interrupt mask for proper operation.
3794  */
3795 static void hw_setup_intr(struct ksz_hw *hw)
3796 {
3797         hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3798 }
3799 
3800 static void ksz_check_desc_num(struct ksz_desc_info *info)
3801 {
3802 #define MIN_DESC_SHIFT  2
3803 
3804         int alloc = info->alloc;
3805         int shift;
3806 
3807         shift = 0;
3808         while (!(alloc & 1)) {
3809                 shift++;
3810                 alloc >>= 1;
3811         }
3812         if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3813                 pr_alert("Hardware descriptor numbers not right!\n");
3814                 while (alloc) {
3815                         shift++;
3816                         alloc >>= 1;
3817                 }
3818                 if (shift < MIN_DESC_SHIFT)
3819                         shift = MIN_DESC_SHIFT;
3820                 alloc = 1 << shift;
3821                 info->alloc = alloc;
3822         }
3823         info->mask = info->alloc - 1;
3824 }
3825 
3826 static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3827 {
3828         int i;
3829         u32 phys = desc_info->ring_phys;
3830         struct ksz_hw_desc *desc = desc_info->ring_virt;
3831         struct ksz_desc *cur = desc_info->ring;
3832         struct ksz_desc *previous = NULL;
3833 
3834         for (i = 0; i < desc_info->alloc; i++) {
3835                 cur->phw = desc++;
3836                 phys += desc_info->size;
3837                 previous = cur++;
3838                 previous->phw->next = cpu_to_le32(phys);
3839         }
3840         previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3841         previous->sw.buf.rx.end_of_ring = 1;
3842         previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3843 
3844         desc_info->avail = desc_info->alloc;
3845         desc_info->last = desc_info->next = 0;
3846 
3847         desc_info->cur = desc_info->ring;
3848 }
3849 
3850 /**
3851  * hw_set_desc_base - set descriptor base addresses
3852  * @hw:         The hardware instance.
3853  * @tx_addr:    The transmit descriptor base.
3854  * @rx_addr:    The receive descriptor base.
3855  *
3856  * This routine programs the descriptor base addresses after reset.
3857  */
3858 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3859 {
3860         /* Set base address of Tx/Rx descriptors. */
3861         writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3862         writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3863 }
3864 
3865 static void hw_reset_pkts(struct ksz_desc_info *info)
3866 {
3867         info->cur = info->ring;
3868         info->avail = info->alloc;
3869         info->last = info->next = 0;
3870 }
3871 
3872 static inline void hw_resume_rx(struct ksz_hw *hw)
3873 {
3874         writel(DMA_START, hw->io + KS_DMA_RX_START);
3875 }
3876 
3877 /**
3878  * hw_start_rx - start receiving
3879  * @hw:         The hardware instance.
3880  *
3881  * This routine starts the receive function of the hardware.
3882  */
3883 static void hw_start_rx(struct ksz_hw *hw)
3884 {
3885         writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3886 
3887         /* Notify when the receive stops. */
3888         hw->intr_mask |= KS884X_INT_RX_STOPPED;
3889 
3890         writel(DMA_START, hw->io + KS_DMA_RX_START);
3891         hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3892         hw->rx_stop++;
3893 
3894         /* Variable overflows. */
3895         if (0 == hw->rx_stop)
3896                 hw->rx_stop = 2;
3897 }
3898 
3899 /**
3900  * hw_stop_rx - stop receiving
3901  * @hw:         The hardware instance.
3902  *
3903  * This routine stops the receive function of the hardware.
3904  */
3905 static void hw_stop_rx(struct ksz_hw *hw)
3906 {
3907         hw->rx_stop = 0;
3908         hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3909         writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3910 }
3911 
3912 /**
3913  * hw_start_tx - start transmitting
3914  * @hw:         The hardware instance.
3915  *
3916  * This routine starts the transmit function of the hardware.
3917  */
3918 static void hw_start_tx(struct ksz_hw *hw)
3919 {
3920         writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3921 }
3922 
3923 /**
3924  * hw_stop_tx - stop transmitting
3925  * @hw:         The hardware instance.
3926  *
3927  * This routine stops the transmit function of the hardware.
3928  */
3929 static void hw_stop_tx(struct ksz_hw *hw)
3930 {
3931         writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3932 }
3933 
3934 /**
3935  * hw_disable - disable hardware
3936  * @hw:         The hardware instance.
3937  *
3938  * This routine disables the hardware.
3939  */
3940 static void hw_disable(struct ksz_hw *hw)
3941 {
3942         hw_stop_rx(hw);
3943         hw_stop_tx(hw);
3944         hw->enabled = 0;
3945 }
3946 
3947 /**
3948  * hw_enable - enable hardware
3949  * @hw:         The hardware instance.
3950  *
3951  * This routine enables the hardware.
3952  */
3953 static void hw_enable(struct ksz_hw *hw)
3954 {
3955         hw_start_tx(hw);
3956         hw_start_rx(hw);
3957         hw->enabled = 1;
3958 }
3959 
3960 /**
3961  * hw_alloc_pkt - allocate enough descriptors for transmission
3962  * @hw:         The hardware instance.
3963  * @length:     The length of the packet.
3964  * @physical:   Number of descriptors required.
3965  *
3966  * This function allocates descriptors for transmission.
3967  *
3968  * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3969  */
3970 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3971 {
3972         /* Always leave one descriptor free. */
3973         if (hw->tx_desc_info.avail <= 1)
3974                 return 0;
3975 
3976         /* Allocate a descriptor for transmission and mark it current. */
3977         get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3978         hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3979 
3980         /* Keep track of number of transmit descriptors used so far. */
3981         ++hw->tx_int_cnt;
3982         hw->tx_size += length;
3983 
3984         /* Cannot hold on too much data. */
3985         if (hw->tx_size >= MAX_TX_HELD_SIZE)
3986                 hw->tx_int_cnt = hw->tx_int_mask + 1;
3987 
3988         if (physical > hw->tx_desc_info.avail)
3989                 return 1;
3990 
3991         return hw->tx_desc_info.avail;
3992 }
3993 
3994 /**
3995  * hw_send_pkt - mark packet for transmission
3996  * @hw:         The hardware instance.
3997  *
3998  * This routine marks the packet for transmission in PCI version.
3999  */
4000 static void hw_send_pkt(struct ksz_hw *hw)
4001 {
4002         struct ksz_desc *cur = hw->tx_desc_info.cur;
4003 
4004         cur->sw.buf.tx.last_seg = 1;
4005 
4006         /* Interrupt only after specified number of descriptors used. */
4007         if (hw->tx_int_cnt > hw->tx_int_mask) {
4008                 cur->sw.buf.tx.intr = 1;
4009                 hw->tx_int_cnt = 0;
4010                 hw->tx_size = 0;
4011         }
4012 
4013         /* KSZ8842 supports port directed transmission. */
4014         cur->sw.buf.tx.dest_port = hw->dst_ports;
4015 
4016         release_desc(cur);
4017 
4018         writel(0, hw->io + KS_DMA_TX_START);
4019 }
4020 
4021 static int empty_addr(u8 *addr)
4022 {
4023         u32 *addr1 = (u32 *) addr;
4024         u16 *addr2 = (u16 *) &addr[4];
4025 
4026         return 0 == *addr1 && 0 == *addr2;
4027 }
4028 
4029 /**
4030  * hw_set_addr - set MAC address
4031  * @hw:         The hardware instance.
4032  *
4033  * This routine programs the MAC address of the hardware when the address is
4034  * overridden.
4035  */
4036 static void hw_set_addr(struct ksz_hw *hw)
4037 {
4038         int i;
4039 
4040         for (i = 0; i < ETH_ALEN; i++)
4041                 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4042                         hw->io + KS884X_ADDR_0_OFFSET + i);
4043 
4044         sw_set_addr(hw, hw->override_addr);
4045 }
4046 
4047 /**
4048  * hw_read_addr - read MAC address
4049  * @hw:         The hardware instance.
4050  *
4051  * This routine retrieves the MAC address of the hardware.
4052  */
4053 static void hw_read_addr(struct ksz_hw *hw)
4054 {
4055         int i;
4056 
4057         for (i = 0; i < ETH_ALEN; i++)
4058                 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4059                         KS884X_ADDR_0_OFFSET + i);
4060 
4061         if (!hw->mac_override) {
4062                 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
4063                 if (empty_addr(hw->override_addr)) {
4064                         memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
4065                         memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4066                                ETH_ALEN);
4067                         hw->override_addr[5] += hw->id;
4068                         hw_set_addr(hw);
4069                 }
4070         }
4071 }
4072 
4073 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4074 {
4075         int i;
4076         u32 mac_addr_lo;
4077         u32 mac_addr_hi;
4078 
4079         mac_addr_hi = 0;
4080         for (i = 0; i < 2; i++) {
4081                 mac_addr_hi <<= 8;
4082                 mac_addr_hi |= mac_addr[i];
4083         }
4084         mac_addr_hi |= ADD_ADDR_ENABLE;
4085         mac_addr_lo = 0;
4086         for (i = 2; i < 6; i++) {
4087                 mac_addr_lo <<= 8;
4088                 mac_addr_lo |= mac_addr[i];
4089         }
4090         index *= ADD_ADDR_INCR;
4091 
4092         writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4093         writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4094 }
4095 
4096 static void hw_set_add_addr(struct ksz_hw *hw)
4097 {
4098         int i;
4099 
4100         for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4101                 if (empty_addr(hw->address[i]))
4102                         writel(0, hw->io + ADD_ADDR_INCR * i +
4103                                 KS_ADD_ADDR_0_HI);
4104                 else
4105                         hw_ena_add_addr(hw, i, hw->address[i]);
4106         }
4107 }
4108 
4109 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4110 {
4111         int i;
4112         int j = ADDITIONAL_ENTRIES;
4113 
4114         if (ether_addr_equal(hw->override_addr, mac_addr))
4115                 return 0;
4116         for (i = 0; i < hw->addr_list_size; i++) {
4117                 if (ether_addr_equal(hw->address[i], mac_addr))
4118                         return 0;
4119                 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4120                         j = i;
4121         }
4122         if (j < ADDITIONAL_ENTRIES) {
4123                 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4124                 hw_ena_add_addr(hw, j, hw->address[j]);
4125                 return 0;
4126         }
4127         return -1;
4128 }
4129 
4130 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4131 {
4132         int i;
4133 
4134         for (i = 0; i < hw->addr_list_size; i++) {
4135                 if (ether_addr_equal(hw->address[i], mac_addr)) {
4136                         eth_zero_addr(hw->address[i]);
4137                         writel(0, hw->io + ADD_ADDR_INCR * i +
4138                                 KS_ADD_ADDR_0_HI);
4139                         return 0;
4140                 }
4141         }
4142         return -1;
4143 }
4144 
4145 /**
4146  * hw_clr_multicast - clear multicast addresses
4147  * @hw:         The hardware instance.
4148  *
4149  * This routine removes all multicast addresses set in the hardware.
4150  */
4151 static void hw_clr_multicast(struct ksz_hw *hw)
4152 {
4153         int i;
4154 
4155         for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4156                 hw->multi_bits[i] = 0;
4157 
4158                 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4159         }
4160 }
4161 
4162 /**
4163  * hw_set_grp_addr - set multicast addresses
4164  * @hw:         The hardware instance.
4165  *
4166  * This routine programs multicast addresses for the hardware to accept those
4167  * addresses.
4168  */
4169 static void hw_set_grp_addr(struct ksz_hw *hw)
4170 {
4171         int i;
4172         int index;
4173         int position;
4174         int value;
4175 
4176         memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4177 
4178         for (i = 0; i < hw->multi_list_size; i++) {
4179                 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4180                 index = position >> 3;
4181                 value = 1 << (position & 7);
4182                 hw->multi_bits[index] |= (u8) value;
4183         }
4184 
4185         for (i = 0; i < HW_MULTICAST_SIZE; i++)
4186                 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4187                         i);
4188 }
4189 
4190 /**
4191  * hw_set_multicast - enable or disable all multicast receiving
4192  * @hw:         The hardware instance.
4193  * @multicast:  To turn on or off the all multicast feature.
4194  *
4195  * This routine enables/disables the hardware to accept all multicast packets.
4196  */
4197 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4198 {
4199         /* Stop receiving for reconfiguration. */
4200         hw_stop_rx(hw);
4201 
4202         if (multicast)
4203                 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4204         else
4205                 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4206 
4207         if (hw->enabled)
4208                 hw_start_rx(hw);
4209 }
4210 
4211 /**
4212  * hw_set_promiscuous - enable or disable promiscuous receiving
4213  * @hw:         The hardware instance.
4214  * @prom:       To turn on or off the promiscuous feature.
4215  *
4216  * This routine enables/disables the hardware to accept all packets.
4217  */
4218 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4219 {
4220         /* Stop receiving for reconfiguration. */
4221         hw_stop_rx(hw);
4222 
4223         if (prom)
4224                 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4225         else
4226                 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4227 
4228         if (hw->enabled)
4229                 hw_start_rx(hw);
4230 }
4231 
4232 /**
4233  * sw_enable - enable the switch
4234  * @hw:         The hardware instance.
4235  * @enable:     The flag to enable or disable the switch
4236  *
4237  * This routine is used to enable/disable the switch in KSZ8842.
4238  */
4239 static void sw_enable(struct ksz_hw *hw, int enable)
4240 {
4241         int port;
4242 
4243         for (port = 0; port < SWITCH_PORT_NUM; port++) {
4244                 if (hw->dev_count > 1) {
4245                         /* Set port-base vlan membership with host port. */
4246                         sw_cfg_port_base_vlan(hw, port,
4247                                 HOST_MASK | (1 << port));
4248                         port_set_stp_state(hw, port, STP_STATE_DISABLED);
4249                 } else {
4250                         sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4251                         port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4252                 }
4253         }
4254         if (hw->dev_count > 1)
4255                 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4256         else
4257                 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4258 
4259         if (enable)
4260                 enable = KS8842_START;
4261         writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4262 }
4263 
4264 /**
4265  * sw_setup - setup the switch
4266  * @hw:         The hardware instance.
4267  *
4268  * This routine setup the hardware switch engine for default operation.
4269  */
4270 static void sw_setup(struct ksz_hw *hw)
4271 {
4272         int port;
4273 
4274         sw_set_global_ctrl(hw);
4275 
4276         /* Enable switch broadcast storm protection at 10% percent rate. */
4277         sw_init_broad_storm(hw);
4278         hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4279         for (port = 0; port < SWITCH_PORT_NUM; port++)
4280                 sw_ena_broad_storm(hw, port);
4281 
4282         sw_init_prio(hw);
4283 
4284         sw_init_mirror(hw);
4285 
4286         sw_init_prio_rate(hw);
4287 
4288         sw_init_vlan(hw);
4289 
4290         if (hw->features & STP_SUPPORT)
4291                 sw_init_stp(hw);
4292         if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4293                         SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4294                 hw->overrides |= PAUSE_FLOW_CTRL;
4295         sw_enable(hw, 1);
4296 }
4297 
4298 /**
4299  * ksz_start_timer - start kernel timer
4300  * @info:       Kernel timer information.
4301  * @time:       The time tick.
4302  *
4303  * This routine starts the kernel timer after the specified time tick.
4304  */
4305 static void ksz_start_timer(struct ksz_timer_info *info, int time)
4306 {
4307         info->cnt = 0;
4308         info->timer.expires = jiffies + time;
4309         add_timer(&info->timer);
4310 
4311         /* infinity */
4312         info->max = -1;
4313 }
4314 
4315 /**
4316  * ksz_stop_timer - stop kernel timer
4317  * @info:       Kernel timer information.
4318  *
4319  * This routine stops the kernel timer.
4320  */
4321 static void ksz_stop_timer(struct ksz_timer_info *info)
4322 {
4323         if (info->max) {
4324                 info->max = 0;
4325                 del_timer_sync(&info->timer);
4326         }
4327 }
4328 
4329 static void ksz_init_timer(struct ksz_timer_info *info, int period,
4330         void (*function)(struct timer_list *))
4331 {
4332         info->max = 0;
4333         info->period = period;
4334         timer_setup(&info->timer, function, 0);
4335 }
4336 
4337 static void ksz_update_timer(struct ksz_timer_info *info)
4338 {
4339         ++info->cnt;
4340         if (info->max > 0) {
4341                 if (info->cnt < info->max) {
4342                         info->timer.expires = jiffies + info->period;
4343                         add_timer(&info->timer);
4344                 } else
4345                         info->max = 0;
4346         } else if (info->max < 0) {
4347                 info->timer.expires = jiffies + info->period;
4348                 add_timer(&info->timer);
4349         }
4350 }
4351 
4352 /**
4353  * ksz_alloc_soft_desc - allocate software descriptors
4354  * @desc_info:  Descriptor information structure.
4355  * @transmit:   Indication that descriptors are for transmit.
4356  *
4357  * This local function allocates software descriptors for manipulation in
4358  * memory.
4359  *
4360  * Return 0 if successful.
4361  */
4362 static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4363 {
4364         desc_info->ring = kcalloc(desc_info->alloc, sizeof(struct ksz_desc),
4365                                   GFP_KERNEL);
4366         if (!desc_info->ring)
4367                 return 1;
4368         hw_init_desc(desc_info, transmit);
4369         return 0;
4370 }
4371 
4372 /**
4373  * ksz_alloc_desc - allocate hardware descriptors
4374  * @adapter:    Adapter information structure.
4375  *
4376  * This local function allocates hardware descriptors for receiving and
4377  * transmitting.
4378  *
4379  * Return 0 if successful.
4380  */
4381 static int ksz_alloc_desc(struct dev_info *adapter)
4382 {
4383         struct ksz_hw *hw = &adapter->hw;
4384         int offset;
4385 
4386         /* Allocate memory for RX & TX descriptors. */
4387         adapter->desc_pool.alloc_size =
4388                 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4389                 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4390                 DESC_ALIGNMENT;
4391 
4392         adapter->desc_pool.alloc_virt =
4393                 pci_zalloc_consistent(adapter->pdev,
4394                                       adapter->desc_pool.alloc_size,
4395                                       &adapter->desc_pool.dma_addr);
4396         if (adapter->desc_pool.alloc_virt == NULL) {
4397                 adapter->desc_pool.alloc_size = 0;
4398                 return 1;
4399         }
4400 
4401         /* Align to the next cache line boundary. */
4402         offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4403                 (DESC_ALIGNMENT -
4404                 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4405         adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4406         adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4407 
4408         /* Allocate receive/transmit descriptors. */
4409         hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4410                 adapter->desc_pool.virt;
4411         hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4412         offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4413         hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4414                 (adapter->desc_pool.virt + offset);
4415         hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4416 
4417         if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4418                 return 1;
4419         if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4420                 return 1;
4421 
4422         return 0;
4423 }
4424 
4425 /**
4426  * free_dma_buf - release DMA buffer resources
4427  * @adapter:    Adapter information structure.
4428  *
4429  * This routine is just a helper function to release the DMA buffer resources.
4430  */
4431 static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4432         int direction)
4433 {
4434         pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4435         dev_kfree_skb(dma_buf->skb);
4436         dma_buf->skb = NULL;
4437         dma_buf->dma = 0;
4438 }
4439 
4440 /**
4441  * ksz_init_rx_buffers - initialize receive descriptors
4442  * @adapter:    Adapter information structure.
4443  *
4444  * This routine initializes DMA buffers for receiving.
4445  */
4446 static void ksz_init_rx_buffers(struct dev_info *adapter)
4447 {
4448         int i;
4449         struct ksz_desc *desc;
4450         struct ksz_dma_buf *dma_buf;
4451         struct ksz_hw *hw = &adapter->hw;
4452         struct ksz_desc_info *info = &hw->rx_desc_info;
4453 
4454         for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4455                 get_rx_pkt(info, &desc);
4456 
4457                 dma_buf = DMA_BUFFER(desc);
4458                 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4459                         free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4460                 dma_buf->len = adapter->mtu;
4461                 if (!dma_buf->skb)
4462                         dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4463                 if (dma_buf->skb && !dma_buf->dma)
4464                         dma_buf->dma = pci_map_single(
4465                                 adapter->pdev,
4466                                 skb_tail_pointer(dma_buf->skb),
4467                                 dma_buf->len,
4468                                 PCI_DMA_FROMDEVICE);
4469 
4470                 /* Set descriptor. */
4471                 set_rx_buf(desc, dma_buf->dma);
4472                 set_rx_len(desc, dma_buf->len);
4473                 release_desc(desc);
4474         }
4475 }
4476 
4477 /**
4478  * ksz_alloc_mem - allocate memory for hardware descriptors
4479  * @adapter:    Adapter information structure.
4480  *
4481  * This function allocates memory for use by hardware descriptors for receiving
4482  * and transmitting.
4483  *
4484  * Return 0 if successful.
4485  */
4486 static int ksz_alloc_mem(struct dev_info *adapter)
4487 {
4488         struct ksz_hw *hw = &adapter->hw;
4489 
4490         /* Determine the number of receive and transmit descriptors. */
4491         hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4492         hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4493 
4494         /* Determine how many descriptors to skip transmit interrupt. */
4495         hw->tx_int_cnt = 0;
4496         hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4497         if (hw->tx_int_mask > 8)
4498                 hw->tx_int_mask = 8;
4499         while (hw->tx_int_mask) {
4500                 hw->tx_int_cnt++;
4501                 hw->tx_int_mask >>= 1;
4502         }
4503         if (hw->tx_int_cnt) {
4504                 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4505                 hw->tx_int_cnt = 0;
4506         }
4507 
4508         /* Determine the descriptor size. */
4509         hw->rx_desc_info.size =
4510                 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4511                 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4512         hw->tx_desc_info.size =
4513                 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4514                 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4515         if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4516                 pr_alert("Hardware descriptor size not right!\n");
4517         ksz_check_desc_num(&hw->rx_desc_info);
4518         ksz_check_desc_num(&hw->tx_desc_info);
4519 
4520         /* Allocate descriptors. */
4521         if (ksz_alloc_desc(adapter))
4522                 return 1;
4523 
4524         return 0;
4525 }
4526 
4527 /**
4528  * ksz_free_desc - free software and hardware descriptors
4529  * @adapter:    Adapter information structure.
4530  *
4531  * This local routine frees the software and hardware descriptors allocated by
4532  * ksz_alloc_desc().
4533  */
4534 static void ksz_free_desc(struct dev_info *adapter)
4535 {
4536         struct ksz_hw *hw = &adapter->hw;
4537 
4538         /* Reset descriptor. */
4539         hw->rx_desc_info.ring_virt = NULL;
4540         hw->tx_desc_info.ring_virt = NULL;
4541         hw->rx_desc_info.ring_phys = 0;
4542         hw->tx_desc_info.ring_phys = 0;
4543 
4544         /* Free memory. */
4545         if (adapter->desc_pool.alloc_virt)
4546                 pci_free_consistent(
4547                         adapter->pdev,
4548                         adapter->desc_pool.alloc_size,
4549                         adapter->desc_pool.alloc_virt,
4550                         adapter->desc_pool.dma_addr);
4551 
4552         /* Reset resource pool. */
4553         adapter->desc_pool.alloc_size = 0;
4554         adapter->desc_pool.alloc_virt = NULL;
4555 
4556         kfree(hw->rx_desc_info.ring);
4557         hw->rx_desc_info.ring = NULL;
4558         kfree(hw->tx_desc_info.ring);
4559         hw->tx_desc_info.ring = NULL;
4560 }
4561 
4562 /**
4563  * ksz_free_buffers - free buffers used in the descriptors
4564  * @adapter:    Adapter information structure.
4565  * @desc_info:  Descriptor information structure.
4566  *
4567  * This local routine frees buffers used in the DMA buffers.
4568  */
4569 static void ksz_free_buffers(struct dev_info *adapter,
4570         struct ksz_desc_info *desc_info, int direction)
4571 {
4572         int i;
4573         struct ksz_dma_buf *dma_buf;
4574         struct ksz_desc *desc = desc_info->ring;
4575 
4576         for (i = 0; i < desc_info->alloc; i++) {
4577                 dma_buf = DMA_BUFFER(desc);
4578                 if (dma_buf->skb)
4579                         free_dma_buf(adapter, dma_buf, direction);
4580                 desc++;
4581         }
4582 }
4583 
4584 /**
4585  * ksz_free_mem - free all resources used by descriptors
4586  * @adapter:    Adapter information structure.
4587  *
4588  * This local routine frees all the resources allocated by ksz_alloc_mem().
4589  */
4590 static void ksz_free_mem(struct dev_info *adapter)
4591 {
4592         /* Free transmit buffers. */
4593         ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4594                 PCI_DMA_TODEVICE);
4595 
4596         /* Free receive buffers. */
4597         ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4598                 PCI_DMA_FROMDEVICE);
4599 
4600         /* Free descriptors. */
4601         ksz_free_desc(adapter);
4602 }
4603 
4604 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4605         u64 *counter)
4606 {
4607         int i;
4608         int mib;
4609         int port;
4610         struct ksz_port_mib *port_mib;
4611 
4612         memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4613         for (i = 0, port = first; i < cnt; i++, port++) {
4614                 port_mib = &hw->port_mib[port];
4615                 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4616                         counter[mib] += port_mib->counter[mib];
4617         }
4618 }
4619 
4620 /**
4621  * send_packet - send packet
4622  * @skb:        Socket buffer.
4623  * @dev:        Network device.
4624  *
4625  * This routine is used to send a packet out to the network.
4626  */
4627 static void send_packet(struct sk_buff *skb, struct net_device *dev)
4628 {
4629         struct ksz_desc *desc;
4630         struct ksz_desc *first;
4631         struct dev_priv *priv = netdev_priv(dev);
4632         struct dev_info *hw_priv = priv->adapter;
4633         struct ksz_hw *hw = &hw_priv->hw;
4634         struct ksz_desc_info *info = &hw->tx_desc_info;
4635         struct ksz_dma_buf *dma_buf;
4636         int len;
4637         int last_frag = skb_shinfo(skb)->nr_frags;
4638 
4639         /*
4640          * KSZ8842 with multiple device interfaces needs to be told which port
4641          * to send.
4642          */
4643         if (hw->dev_count > 1)
4644                 hw->dst_ports = 1 << priv->port.first_port;
4645 
4646         /* Hardware will pad the length to 60. */
4647         len = skb->len;
4648 
4649         /* Remember the very first descriptor. */
4650         first = info->cur;
4651         desc = first;
4652 
4653         dma_buf = DMA_BUFFER(desc);
4654         if (last_frag) {
4655                 int frag;
4656                 skb_frag_t *this_frag;
4657 
4658                 dma_buf->len = skb_headlen(skb);
4659 
4660                 dma_buf->dma = pci_map_single(
4661                         hw_priv->pdev, skb->data, dma_buf->len,
4662                         PCI_DMA_TODEVICE);
4663                 set_tx_buf(desc, dma_buf->dma);
4664                 set_tx_len(desc, dma_buf->len);
4665 
4666                 frag = 0;
4667                 do {
4668                         this_frag = &skb_shinfo(skb)->frags[frag];
4669 
4670                         /* Get a new descriptor. */
4671                         get_tx_pkt(info, &desc);
4672 
4673                         /* Keep track of descriptors used so far. */
4674                         ++hw->tx_int_cnt;
4675 
4676                         dma_buf = DMA_BUFFER(desc);
4677                         dma_buf->len = skb_frag_size(this_frag);
4678 
4679                         dma_buf->dma = pci_map_single(
4680                                 hw_priv->pdev,
4681                                 skb_frag_address(this_frag),
4682                                 dma_buf->len,
4683                                 PCI_DMA_TODEVICE);
4684                         set_tx_buf(desc, dma_buf->dma);
4685                         set_tx_len(desc, dma_buf->len);
4686 
4687                         frag++;
4688                         if (frag == last_frag)
4689                                 break;
4690 
4691                         /* Do not release the last descriptor here. */
4692                         release_desc(desc);
4693                 } while (1);
4694 
4695                 /* current points to the last descriptor. */
4696                 info->cur = desc;
4697 
4698                 /* Release the first descriptor. */
4699                 release_desc(first);
4700         } else {
4701                 dma_buf->len = len;
4702 
4703                 dma_buf->dma = pci_map_single(
4704                         hw_priv->pdev, skb->data, dma_buf->len,
4705                         PCI_DMA_TODEVICE);
4706                 set_tx_buf(desc, dma_buf->dma);
4707                 set_tx_len(desc, dma_buf->len);
4708         }
4709 
4710         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4711                 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4712                 (desc)->sw.buf.tx.csum_gen_udp = 1;
4713         }
4714 
4715         /*
4716          * The last descriptor holds the packet so that it can be returned to
4717          * network subsystem after all descriptors are transmitted.
4718          */
4719         dma_buf->skb = skb;
4720 
4721         hw_send_pkt(hw);
4722 
4723         /* Update transmit statistics. */
4724         dev->stats.tx_packets++;
4725         dev->stats.tx_bytes += len;
4726 }
4727 
4728 /**
4729  * transmit_cleanup - clean up transmit descriptors
4730  * @dev:        Network device.
4731  *
4732  * This routine is called to clean up the transmitted buffers.
4733  */
4734 static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4735 {
4736         int last;
4737         union desc_stat status;
4738         struct ksz_hw *hw = &hw_priv->hw;
4739         struct ksz_desc_info *info = &hw->tx_desc_info;
4740         struct ksz_desc *desc;
4741         struct ksz_dma_buf *dma_buf;
4742         struct net_device *dev = NULL;
4743 
4744         spin_lock_irq(&hw_priv->hwlock);
4745         last = info->last;
4746 
4747         while (info->avail < info->alloc) {
4748                 /* Get next descriptor which is not hardware owned. */
4749                 desc = &info->ring[last];
4750                 status.data = le32_to_cpu(desc->phw->ctrl.data);
4751                 if (status.tx.hw_owned) {
4752                         if (normal)
4753                                 break;
4754                         else
4755                                 reset_desc(desc, status);
4756                 }
4757 
4758                 dma_buf = DMA_BUFFER(desc);
4759                 pci_unmap_single(
4760                         hw_priv->pdev, dma_buf->dma, dma_buf->len,
4761                         PCI_DMA_TODEVICE);
4762 
4763                 /* This descriptor contains the last buffer in the packet. */
4764                 if (dma_buf->skb) {
4765                         dev = dma_buf->skb->dev;
4766 
4767                         /* Release the packet back to network subsystem. */
4768                         dev_kfree_skb_irq(dma_buf->skb);
4769                         dma_buf->skb = NULL;
4770                 }
4771 
4772                 /* Free the transmitted descriptor. */
4773                 last++;
4774                 last &= info->mask;
4775                 info->avail++;
4776         }
4777         info->last = last;
4778         spin_unlock_irq(&hw_priv->hwlock);
4779 
4780         /* Notify the network subsystem that the packet has been sent. */
4781         if (dev)
4782                 netif_trans_update(dev);
4783 }
4784 
4785 /**
4786  * transmit_done - transmit done processing
4787  * @dev:        Network device.
4788  *
4789  * This routine is called when the transmit interrupt is triggered, indicating
4790  * either a packet is sent successfully or there are transmit errors.
4791  */
4792 static void tx_done(struct dev_info *hw_priv)
4793 {
4794         struct ksz_hw *hw = &hw_priv->hw;
4795         int port;
4796 
4797         transmit_cleanup(hw_priv, 1);
4798 
4799         for (port = 0; port < hw->dev_count; port++) {
4800                 struct net_device *dev = hw->port_info[port].pdev;
4801 
4802                 if (netif_running(dev) && netif_queue_stopped(dev))
4803                         netif_wake_queue(dev);
4804         }
4805 }
4806 
4807 static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4808 {
4809         skb->dev = old->dev;
4810         skb->protocol = old->protocol;
4811         skb->ip_summed = old->ip_summed;
4812         skb->csum = old->csum;
4813         skb_set_network_header(skb, ETH_HLEN);
4814 
4815         dev_consume_skb_any(old);
4816 }
4817 
4818 /**
4819  * netdev_tx - send out packet
4820  * @skb:        Socket buffer.
4821  * @dev:        Network device.
4822  *
4823  * This function is used by the upper network layer to send out a packet.
4824  *
4825  * Return 0 if successful; otherwise an error code indicating failure.
4826  */
4827 static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4828 {
4829         struct dev_priv *priv = netdev_priv(dev);
4830         struct dev_info *hw_priv = priv->adapter;
4831         struct ksz_hw *hw = &hw_priv->hw;
4832         int left;
4833         int num = 1;
4834         int rc = 0;
4835 
4836         if (hw->features & SMALL_PACKET_TX_BUG) {
4837                 struct sk_buff *org_skb = skb;
4838 
4839                 if (skb->len <= 48) {
4840                         if (skb_end_pointer(skb) - skb->data >= 50) {
4841                                 memset(&skb->data[skb->len], 0, 50 - skb->len);
4842                                 skb->len = 50;
4843                         } else {
4844                                 skb = netdev_alloc_skb(dev, 50);
4845                                 if (!skb)
4846                                         return NETDEV_TX_BUSY;
4847                                 memcpy(skb->data, org_skb->data, org_skb->len);
4848                                 memset(&skb->data[org_skb->len], 0,
4849                                         50 - org_skb->len);
4850                                 skb->len = 50;
4851                                 copy_old_skb(org_skb, skb);
4852                         }
4853                 }
4854         }
4855 
4856         spin_lock_irq(&hw_priv->hwlock);
4857 
4858         num = skb_shinfo(skb)->nr_frags + 1;
4859         left = hw_alloc_pkt(hw, skb->len, num);
4860         if (left) {
4861                 if (left < num ||
4862                     (CHECKSUM_PARTIAL == skb->ip_summed &&
4863                      skb->protocol == htons(ETH_P_IPV6))) {
4864                         struct sk_buff *org_skb = skb;
4865 
4866                         skb = netdev_alloc_skb(dev, org_skb->len);
4867                         if (!skb) {
4868                                 rc = NETDEV_TX_BUSY;
4869                                 goto unlock;
4870                         }
4871                         skb_copy_and_csum_dev(org_skb, skb->data);
4872                         org_skb->ip_summed = CHECKSUM_NONE;
4873                         skb->len = org_skb->len;
4874                         copy_old_skb(org_skb, skb);
4875                 }
4876                 send_packet(skb, dev);
4877                 if (left <= num)
4878                         netif_stop_queue(dev);
4879         } else {
4880                 /* Stop the transmit queue until packet is allocated. */
4881                 netif_stop_queue(dev);
4882                 rc = NETDEV_TX_BUSY;
4883         }
4884 unlock:
4885         spin_unlock_irq(&hw_priv->hwlock);
4886 
4887         return rc;
4888 }
4889 
4890 /**
4891  * netdev_tx_timeout - transmit timeout processing
4892  * @dev:        Network device.
4893  *
4894  * This routine is called when the transmit timer expires.  That indicates the
4895  * hardware is not running correctly because transmit interrupts are not
4896  * triggered to free up resources so that the transmit routine can continue
4897  * sending out packets.  The hardware is reset to correct the problem.
4898  */
4899 static void netdev_tx_timeout(struct net_device *dev)
4900 {
4901         static unsigned long last_reset;
4902 
4903         struct dev_priv *priv = netdev_priv(dev);
4904         struct dev_info *hw_priv = priv->adapter;
4905         struct ksz_hw *hw = &hw_priv->hw;
4906         int port;
4907 
4908         if (hw->dev_count > 1) {
4909                 /*
4910                  * Only reset the hardware if time between calls is long
4911                  * enough.
4912                  */
4913                 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4914                         hw_priv = NULL;
4915         }
4916 
4917         last_reset = jiffies;
4918         if (hw_priv) {
4919                 hw_dis_intr(hw);
4920                 hw_disable(hw);
4921 
4922                 transmit_cleanup(hw_priv, 0);
4923                 hw_reset_pkts(&hw->rx_desc_info);
4924                 hw_reset_pkts(&hw->tx_desc_info);
4925                 ksz_init_rx_buffers(hw_priv);
4926 
4927                 hw_reset(hw);
4928 
4929                 hw_set_desc_base(hw,
4930                         hw->tx_desc_info.ring_phys,
4931                         hw->rx_desc_info.ring_phys);
4932                 hw_set_addr(hw);
4933                 if (hw->all_multi)
4934                         hw_set_multicast(hw, hw->all_multi);
4935                 else if (hw->multi_list_size)
4936                         hw_set_grp_addr(hw);
4937 
4938                 if (hw->dev_count > 1) {
4939                         hw_set_add_addr(hw);
4940                         for (port = 0; port < SWITCH_PORT_NUM; port++) {
4941                                 struct net_device *port_dev;
4942 
4943                                 port_set_stp_state(hw, port,
4944                                         STP_STATE_DISABLED);
4945 
4946                                 port_dev = hw->port_info[port].pdev;
4947                                 if (netif_running(port_dev))
4948                                         port_set_stp_state(hw, port,
4949                                                 STP_STATE_SIMPLE);
4950                         }
4951                 }
4952 
4953                 hw_enable(hw);
4954                 hw_ena_intr(hw);
4955         }
4956 
4957         netif_trans_update(dev);
4958         netif_wake_queue(dev);
4959 }
4960 
4961 static inline void csum_verified(struct sk_buff *skb)
4962 {
4963         unsigned short protocol;
4964         struct iphdr *iph;
4965 
4966         protocol = skb->protocol;
4967         skb_reset_network_header(skb);
4968         iph = (struct iphdr *) skb_network_header(skb);
4969         if (protocol == htons(ETH_P_8021Q)) {
4970                 protocol = iph->tot_len;
4971                 skb_set_network_header(skb, VLAN_HLEN);
4972                 iph = (struct iphdr *) skb_network_header(skb);
4973         }
4974         if (protocol == htons(ETH_P_IP)) {
4975                 if (iph->protocol == IPPROTO_TCP)
4976                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4977         }
4978 }
4979 
4980 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4981         struct ksz_desc *desc, union desc_stat status)
4982 {
4983         int packet_len;
4984         struct dev_priv *priv = netdev_priv(dev);
4985         struct dev_info *hw_priv = priv->adapter;
4986         struct ksz_dma_buf *dma_buf;
4987         struct sk_buff *skb;
4988         int rx_status;
4989 
4990         /* Received length includes 4-byte CRC. */
4991         packet_len = status.rx.frame_len - 4;
4992 
4993         dma_buf = DMA_BUFFER(desc);
4994         pci_dma_sync_single_for_cpu(
4995                 hw_priv->pdev, dma_buf->dma, packet_len + 4,
4996                 PCI_DMA_FROMDEVICE);
4997 
4998         do {
4999                 /* skb->data != skb->head */
5000                 skb = netdev_alloc_skb(dev, packet_len + 2);
5001                 if (!skb) {
5002                         dev->stats.rx_dropped++;
5003                         return -ENOMEM;
5004                 }
5005 
5006                 /*
5007                  * Align socket buffer in 4-byte boundary for better
5008                  * performance.
5009                  */
5010                 skb_reserve(skb, 2);
5011 
5012                 skb_put_data(skb, dma_buf->skb->data, packet_len);
5013         } while (0);
5014 
5015         skb->protocol = eth_type_trans(skb, dev);
5016 
5017         if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5018                 csum_verified(skb);
5019 
5020         /* Update receive statistics. */
5021         dev->stats.rx_packets++;
5022         dev->stats.rx_bytes += packet_len;
5023 
5024         /* Notify upper layer for received packet. */
5025         rx_status = netif_rx(skb);
5026 
5027         return 0;
5028 }
5029 
5030 static int dev_rcv_packets(struct dev_info *hw_priv)
5031 {
5032         int next;
5033         union desc_stat status;
5034         struct ksz_hw *hw = &hw_priv->hw;
5035         struct net_device *dev = hw->port_info[0].pdev;
5036         struct ksz_desc_info *info = &hw->rx_desc_info;
5037         int left = info->alloc;
5038         struct ksz_desc *desc;
5039         int received = 0;
5040 
5041         next = info->next;
5042         while (left--) {
5043                 /* Get next descriptor which is not hardware owned. */
5044                 desc = &info->ring[next];
5045                 status.data = le32_to_cpu(desc->phw->ctrl.data);
5046                 if (status.rx.hw_owned)
5047                         break;
5048 
5049                 /* Status valid only when last descriptor bit is set. */
5050                 if (status.rx.last_desc && status.rx.first_desc) {
5051                         if (rx_proc(dev, hw, desc, status))
5052                                 goto release_packet;
5053                         received++;
5054                 }
5055 
5056 release_packet:
5057                 release_desc(desc);
5058                 next++;
5059                 next &= info->mask;
5060         }
5061         info->next = next;
5062 
5063         return received;
5064 }
5065 
5066 static int port_rcv_packets(struct dev_info *hw_priv)
5067 {
5068         int next;
5069         union desc_stat status;
5070         struct ksz_hw *hw = &hw_priv->hw;
5071         struct net_device *dev = hw->port_info[0].pdev;
5072         struct ksz_desc_info *info = &hw->rx_desc_info;
5073         int left = info->alloc;
5074         struct ksz_desc *desc;
5075         int received = 0;
5076 
5077         next = info->next;
5078         while (left--) {
5079                 /* Get next descriptor which is not hardware owned. */
5080                 desc = &info->ring[next];
5081                 status.data = le32_to_cpu(desc->phw->ctrl.data);
5082                 if (status.rx.hw_owned)
5083                         break;
5084 
5085                 if (hw->dev_count > 1) {
5086                         /* Get received port number. */
5087                         int p = HW_TO_DEV_PORT(status.rx.src_port);
5088 
5089                         dev = hw->port_info[p].pdev;
5090                         if (!netif_running(dev))
5091                                 goto release_packet;
5092                 }
5093 
5094                 /* Status valid only when last descriptor bit is set. */
5095                 if (status.rx.last_desc && status.rx.first_desc) {
5096                         if (rx_proc(dev, hw, desc, status))
5097                                 goto release_packet;
5098                         received++;
5099                 }
5100 
5101 release_packet:
5102                 release_desc(desc);
5103                 next++;
5104                 next &= info->mask;
5105         }
5106         info->next = next;
5107 
5108         return received;
5109 }
5110 
5111 static int dev_rcv_special(struct dev_info *hw_priv)
5112 {
5113         int next;
5114         union desc_stat status;
5115         struct ksz_hw *hw = &hw_priv->hw;
5116         struct net_device *dev = hw->port_info[0].pdev;
5117         struct ksz_desc_info *info = &hw->rx_desc_info;
5118         int left = info->alloc;
5119         struct ksz_desc *desc;
5120         int received = 0;
5121 
5122         next = info->next;
5123         while (left--) {
5124                 /* Get next descriptor which is not hardware owned. */
5125                 desc = &info->ring[next];
5126                 status.data = le32_to_cpu(desc->phw->ctrl.data);
5127                 if (status.rx.hw_owned)
5128                         break;
5129 
5130                 if (hw->dev_count > 1) {
5131                         /* Get received port number. */
5132                         int p = HW_TO_DEV_PORT(status.rx.src_port);
5133 
5134                         dev = hw->port_info[p].pdev;
5135                         if (!netif_running(dev))
5136                                 goto release_packet;
5137                 }
5138 
5139                 /* Status valid only when last descriptor bit is set. */
5140                 if (status.rx.last_desc && status.rx.first_desc) {
5141                         /*
5142                          * Receive without error.  With receive errors
5143                          * disabled, packets with receive errors will be
5144                          * dropped, so no need to check the error bit.
5145                          */
5146                         if (!status.rx.error || (status.data &
5147                                         KS_DESC_RX_ERROR_COND) ==
5148                                         KS_DESC_RX_ERROR_TOO_LONG) {
5149                                 if (rx_proc(dev, hw, desc, status))
5150                                         goto release_packet;
5151                                 received++;
5152                         } else {
5153                                 struct dev_priv *priv = netdev_priv(dev);
5154 
5155                                 /* Update receive error statistics. */
5156                                 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5157                         }
5158                 }
5159 
5160 release_packet:
5161                 release_desc(desc);
5162                 next++;
5163                 next &= info->mask;
5164         }
5165         info->next = next;
5166 
5167         return received;
5168 }
5169 
5170 static void rx_proc_task(unsigned long data)
5171 {
5172         struct dev_info *hw_priv = (struct dev_info *) data;
5173         struct ksz_hw *hw = &hw_priv->hw;
5174 
5175         if (!hw->enabled)
5176                 return;
5177         if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5178 
5179                 /* In case receive process is suspended because of overrun. */
5180                 hw_resume_rx(hw);
5181 
5182                 /* tasklets are interruptible. */
5183                 spin_lock_irq(&hw_priv->hwlock);
5184                 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5185                 spin_unlock_irq(&hw_priv->hwlock);
5186         } else {
5187                 hw_ack_intr(hw, KS884X_INT_RX);
5188                 tasklet_schedule(&hw_priv->rx_tasklet);
5189         }
5190 }
5191 
5192 static void tx_proc_task(unsigned long data)
5193 {
5194         struct dev_info *hw_priv = (struct dev_info *) data;
5195         struct ksz_hw *hw = &hw_priv->hw;
5196 
5197         hw_ack_intr(hw, KS884X_INT_TX_MASK);
5198 
5199         tx_done(hw_priv);
5200 
5201         /* tasklets are interruptible. */
5202         spin_lock_irq(&hw_priv->hwlock);
5203         hw_turn_on_intr(hw, KS884X_INT_TX);
5204         spin_unlock_irq(&hw_priv->hwlock);
5205 }
5206 
5207 static inline void handle_rx_stop(struct ksz_hw *hw)
5208 {
5209         /* Receive just has been stopped. */
5210         if (0 == hw->rx_stop)
5211                 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5212         else if (hw->rx_stop > 1) {
5213                 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5214                         hw_start_rx(hw);
5215                 } else {
5216                         hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5217                         hw->rx_stop = 0;
5218                 }
5219         } else
5220                 /* Receive just has been started. */
5221                 hw->rx_stop++;
5222 }
5223 
5224 /**
5225  * netdev_intr - interrupt handling
5226  * @irq:        Interrupt number.
5227  * @dev_id:     Network device.
5228  *
5229  * This function is called by upper network layer to signal interrupt.
5230  *
5231  * Return IRQ_HANDLED if interrupt is handled.
5232  */
5233 static irqreturn_t netdev_intr(int irq, void *dev_id)
5234 {
5235         uint int_enable = 0;
5236         struct net_device *dev = (struct net_device *) dev_id;
5237         struct dev_priv *priv = netdev_priv(dev);
5238         struct dev_info *hw_priv = priv->adapter;
5239         struct ksz_hw *hw = &hw_priv->hw;
5240 
5241         spin_lock(&hw_priv->hwlock);
5242 
5243         hw_read_intr(hw, &int_enable);
5244 
5245         /* Not our interrupt! */
5246         if (!int_enable) {
5247                 spin_unlock(&hw_priv->hwlock);
5248                 return IRQ_NONE;
5249         }
5250 
5251         do {
5252                 hw_ack_intr(hw, int_enable);
5253                 int_enable &= hw->intr_mask;
5254 
5255                 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5256                         hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5257                         tasklet_schedule(&hw_priv->tx_tasklet);
5258                 }
5259 
5260                 if (likely(int_enable & KS884X_INT_RX)) {
5261                         hw_dis_intr_bit(hw, KS884X_INT_RX);
5262                         tasklet_schedule(&hw_priv->rx_tasklet);
5263                 }
5264 
5265                 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5266                         dev->stats.rx_fifo_errors++;
5267                         hw_resume_rx(hw);
5268                 }
5269 
5270                 if (unlikely(int_enable & KS884X_INT_PHY)) {
5271                         struct ksz_port *port = &priv->port;
5272 
5273                         hw->features |= LINK_INT_WORKING;
5274                         port_get_link_speed(port);
5275                 }
5276 
5277                 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5278                         handle_rx_stop(hw);
5279                         break;
5280                 }
5281 
5282                 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5283                         u32 data;
5284 
5285                         hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5286                         pr_info("Tx stopped\n");
5287                         data = readl(hw->io + KS_DMA_TX_CTRL);
5288                         if (!(data & DMA_TX_ENABLE))
5289                                 pr_info("Tx disabled\n");
5290                         break;
5291                 }
5292         } while (0);
5293 
5294         hw_ena_intr(hw);
5295 
5296         spin_unlock(&hw_priv->hwlock);
5297 
5298         return IRQ_HANDLED;
5299 }
5300 
5301 /*
5302  * Linux network device functions
5303  */
5304 
5305 static unsigned long next_jiffies;
5306 
5307 #ifdef CONFIG_NET_POLL_CONTROLLER
5308 static void netdev_netpoll(struct net_device *dev)
5309 {
5310         struct dev_priv *priv = netdev_priv(dev);
5311         struct dev_info *hw_priv = priv->adapter;
5312 
5313         hw_dis_intr(&hw_priv->hw);
5314         netdev_intr(dev->irq, dev);
5315 }
5316 #endif
5317 
5318 static void bridge_change(struct ksz_hw *hw)
5319 {
5320         int port;
5321         u8  member;
5322         struct ksz_switch *sw = hw->ksz_switch;
5323 
5324         /* No ports in forwarding state. */
5325         if (!sw->member) {
5326                 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5327                 sw_block_addr(hw);
5328         }
5329         for (port = 0; port < SWITCH_PORT_NUM; port++) {
5330                 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5331                         member = HOST_MASK | sw->member;
5332                 else
5333                         member = HOST_MASK | (1 << port);
5334                 if (member != sw->port_cfg[port].member)
5335                         sw_cfg_port_base_vlan(hw, port, member);
5336         }
5337 }
5338 
5339 /**
5340  * netdev_close - close network device
5341  * @dev:        Network device.
5342  *
5343  * This function process the close operation of network device.  This is caused
5344  * by the user command "ifconfig ethX down."
5345  *
5346  * Return 0 if successful; otherwise an error code indicating failure.
5347  */
5348 static int netdev_close(struct net_device *dev)
5349 {
5350         struct dev_priv *priv = netdev_priv(dev);
5351         struct dev_info *hw_priv = priv->adapter;
5352         struct ksz_port *port = &priv->port;
5353         struct ksz_hw *hw = &hw_priv->hw;
5354         int pi;
5355 
5356         netif_stop_queue(dev);
5357 
5358         ksz_stop_timer(&priv->monitor_timer_info);
5359 
5360         /* Need to shut the port manually in multiple device interfaces mode. */
5361         if (hw->dev_count > 1) {
5362                 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5363 
5364                 /* Port is closed.  Need to change bridge setting. */
5365                 if (hw->features & STP_SUPPORT) {
5366                         pi = 1 << port->first_port;
5367                         if (hw->ksz_switch->member & pi) {
5368                                 hw->ksz_switch->member &= ~pi;
5369                                 bridge_change(hw);
5370                         }
5371                 }
5372         }
5373         if (port->first_port > 0)
5374                 hw_del_addr(hw, dev->dev_addr);
5375         if (!hw_priv->wol_enable)
5376                 port_set_power_saving(port, true);
5377 
5378         if (priv->multicast)
5379                 --hw->all_multi;
5380         if (priv->promiscuous)
5381                 --hw->promiscuous;
5382 
5383         hw_priv->opened--;
5384         if (!(hw_priv->opened)) {
5385                 ksz_stop_timer(&hw_priv->mib_timer_info);
5386                 flush_work(&hw_priv->mib_read);
5387 
5388                 hw_dis_intr(hw);
5389                 hw_disable(hw);
5390                 hw_clr_multicast(hw);
5391 
5392                 /* Delay for receive task to stop scheduling itself. */
5393                 msleep(2000 / HZ);
5394 
5395                 tasklet_kill(&hw_priv->rx_tasklet);
5396                 tasklet_kill(&hw_priv->tx_tasklet);
5397                 free_irq(dev->irq, hw_priv->dev);
5398 
5399                 transmit_cleanup(hw_priv, 0);
5400                 hw_reset_pkts(&hw->rx_desc_info);
5401                 hw_reset_pkts(&hw->tx_desc_info);
5402 
5403                 /* Clean out static MAC table when the switch is shutdown. */
5404                 if (hw->features & STP_SUPPORT)
5405                         sw_clr_sta_mac_table(hw);
5406         }
5407 
5408         return 0;
5409 }
5410 
5411 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5412 {
5413         if (hw->ksz_switch) {
5414                 u32 data;
5415 
5416                 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5417                 if (hw->features & RX_HUGE_FRAME)
5418                         data |= SWITCH_HUGE_PACKET;
5419                 else
5420                         data &= ~SWITCH_HUGE_PACKET;
5421                 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5422         }
5423         if (hw->features & RX_HUGE_FRAME) {
5424                 hw->rx_cfg |= DMA_RX_ERROR;
5425                 hw_priv->dev_rcv = dev_rcv_special;
5426         } else {
5427                 hw->rx_cfg &= ~DMA_RX_ERROR;
5428                 if (hw->dev_count > 1)
5429                         hw_priv->dev_rcv = port_rcv_packets;
5430                 else
5431                         hw_priv->dev_rcv = dev_rcv_packets;
5432         }
5433 }
5434 
5435 static int prepare_hardware(struct net_device *dev)
5436 {
5437         struct dev_priv *priv = netdev_priv(dev);
5438         struct dev_info *hw_priv = priv->adapter;
5439         struct ksz_hw *hw = &hw_priv->hw;
5440         int rc = 0;
5441 
5442         /* Remember the network device that requests interrupts. */
5443         hw_priv->dev = dev;
5444         rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5445         if (rc)
5446                 return rc;
5447         tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
5448                      (unsigned long) hw_priv);
5449         tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
5450                      (unsigned long) hw_priv);
5451 
5452         hw->promiscuous = 0;
5453         hw->all_multi = 0;
5454         hw->multi_list_size = 0;
5455 
5456         hw_reset(hw);
5457 
5458         hw_set_desc_base(hw,
5459                 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5460         hw_set_addr(hw);
5461         hw_cfg_huge_frame(hw_priv, hw);
5462         ksz_init_rx_buffers(hw_priv);
5463         return 0;
5464 }
5465 
5466 static void set_media_state(struct net_device *dev, int media_state)
5467 {
5468         struct dev_priv *priv = netdev_priv(dev);
5469 
5470         if (media_state == priv->media_state)
5471                 netif_carrier_on(dev);
5472         else
5473                 netif_carrier_off(dev);
5474         netif_info(priv, link, dev, "link %s\n",
5475                    media_state == priv->media_state ? "on" : "off");
5476 }
5477 
5478 /**
5479  * netdev_open - open network device
5480  * @dev:        Network device.
5481  *
5482  * This function process the open operation of network device.  This is caused
5483  * by the user command "ifconfig ethX up."
5484  *
5485  * Return 0 if successful; otherwise an error code indicating failure.
5486  */
5487 static int netdev_open(struct net_device *dev)
5488 {
5489         struct dev_priv *priv = netdev_priv(dev);
5490         struct dev_info *hw_priv = priv->adapter;
5491         struct ksz_hw *hw = &hw_priv->hw;
5492         struct ksz_port *port = &priv->port;
5493         int i;
5494         int p;
5495         int rc = 0;
5496 
5497         priv->multicast = 0;
5498         priv->promiscuous = 0;
5499 
5500         /* Reset device statistics. */
5501         memset(&dev->stats, 0, sizeof(struct net_device_stats));
5502         memset((void *) port->counter, 0,
5503                 (sizeof(u64) * OID_COUNTER_LAST));
5504 
5505         if (!(hw_priv->opened)) {
5506                 rc = prepare_hardware(dev);
5507                 if (rc)
5508                         return rc;
5509                 for (i = 0; i < hw->mib_port_cnt; i++) {
5510                         if (next_jiffies < jiffies)
5511                                 next_jiffies = jiffies + HZ * 2;
5512                         else
5513                                 next_jiffies += HZ * 1;
5514                         hw_priv->counter[i].time = next_jiffies;
5515                         hw->port_mib[i].state = media_disconnected;
5516                         port_init_cnt(hw, i);
5517                 }
5518                 if (hw->ksz_switch)
5519                         hw->port_mib[HOST_PORT].state = media_connected;
5520                 else {
5521                         hw_add_wol_bcast(hw);
5522                         hw_cfg_wol_pme(hw, 0);
5523                         hw_clr_wol_pme_status(&hw_priv->hw);
5524                 }
5525         }
5526         port_set_power_saving(port, false);
5527 
5528         for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5529                 /*
5530                  * Initialize to invalid value so that link detection
5531                  * is done.
5532                  */
5533                 hw->port_info[p].partner = 0xFF;
5534                 hw->port_info[p].state = media_disconnected;
5535         }
5536 
5537         /* Need to open the port in multiple device interfaces mode. */
5538         if (hw->dev_count > 1) {
5539                 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5540                 if (port->first_port > 0)
5541                         hw_add_addr(hw, dev->dev_addr);
5542         }
5543 
5544         port_get_link_speed(port);
5545         if (port->force_link)
5546                 port_force_link_speed(port);
5547         else
5548                 port_set_link_speed(port);
5549 
5550         if (!(hw_priv->opened)) {
5551                 hw_setup_intr(hw);
5552                 hw_enable(hw);
5553                 hw_ena_intr(hw);
5554 
5555                 if (hw->mib_port_cnt)
5556                         ksz_start_timer(&hw_priv->mib_timer_info,
5557                                 hw_priv->mib_timer_info.period);
5558         }
5559 
5560         hw_priv->opened++;
5561 
5562         ksz_start_timer(&priv->monitor_timer_info,
5563                 priv->monitor_timer_info.period);
5564 
5565         priv->media_state = port->linked->state;
5566 
5567         set_media_state(dev, media_connected);
5568         netif_start_queue(dev);
5569 
5570         return 0;
5571 }
5572 
5573 /* RX errors = rx_errors */
5574 /* RX dropped = rx_dropped */
5575 /* RX overruns = rx_fifo_errors */
5576 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5577 /* TX errors = tx_errors */
5578 /* TX dropped = tx_dropped */
5579 /* TX overruns = tx_fifo_errors */
5580 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5581 /* collisions = collisions */
5582 
5583 /**
5584  * netdev_query_statistics - query network device statistics
5585  * @dev:        Network device.
5586  *
5587  * This function returns the statistics of the network device.  The device
5588  * needs not be opened.
5589  *
5590  * Return network device statistics.
5591  */
5592 static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5593 {
5594         struct dev_priv *priv = netdev_priv(dev);
5595         struct ksz_port *port = &priv->port;
5596         struct ksz_hw *hw = &priv->adapter->hw;
5597         struct ksz_port_mib *mib;
5598         int i;
5599         int p;
5600 
5601         dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5602         dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5603 
5604         /* Reset to zero to add count later. */
5605         dev->stats.multicast = 0;
5606         dev->stats.collisions = 0;
5607         dev->stats.rx_length_errors = 0;
5608         dev->stats.rx_crc_errors = 0;
5609         dev->stats.rx_frame_errors = 0;
5610         dev->stats.tx_window_errors = 0;
5611 
5612         for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5613                 mib = &hw->port_mib[p];
5614 
5615                 dev->stats.multicast += (unsigned long)
5616                         mib->counter[MIB_COUNTER_RX_MULTICAST];
5617 
5618                 dev->stats.collisions += (unsigned long)
5619                         mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5620 
5621                 dev->stats.rx_length_errors += (unsigned long)(
5622                         mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5623                         mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5624                         mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5625                         mib->counter[MIB_COUNTER_RX_JABBER]);
5626                 dev->stats.rx_crc_errors += (unsigned long)
5627                         mib->counter[MIB_COUNTER_RX_CRC_ERR];
5628                 dev->stats.rx_frame_errors += (unsigned long)(
5629                         mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5630                         mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5631 
5632                 dev->stats.tx_window_errors += (unsigned long)
5633                         mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5634         }
5635 
5636         return &dev->stats;
5637 }
5638 
5639 /**
5640  * netdev_set_mac_address - set network device MAC address
5641  * @dev:        Network device.
5642  * @addr:       Buffer of MAC address.
5643  *
5644  * This function is used to set the MAC address of the network device.
5645  *
5646  * Return 0 to indicate success.
5647  */
5648 static int netdev_set_mac_address(struct net_device *dev, void *addr)
5649 {
5650         struct dev_priv *priv = netdev_priv(dev);
5651         struct dev_info *hw_priv = priv->adapter;
5652         struct ksz_hw *hw = &hw_priv->hw;
5653         struct sockaddr *mac = addr;
5654         uint interrupt;
5655 
5656         if (priv->port.first_port > 0)
5657                 hw_del_addr(hw, dev->dev_addr);
5658         else {
5659                 hw->mac_override = 1;
5660                 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5661         }
5662 
5663         memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN);
5664 
5665         interrupt = hw_block_intr(hw);
5666 
5667         if (priv->port.first_port > 0)
5668                 hw_add_addr(hw, dev->dev_addr);
5669         else
5670                 hw_set_addr(hw);
5671         hw_restore_intr(hw, interrupt);
5672 
5673         return 0;
5674 }
5675 
5676 static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5677         struct ksz_hw *hw, int promiscuous)
5678 {
5679         if (promiscuous != priv->promiscuous) {
5680                 u8 prev_state = hw->promiscuous;
5681 
5682                 if (promiscuous)
5683                         ++hw->promiscuous;
5684                 else
5685                         --hw->promiscuous;
5686                 priv->promiscuous = promiscuous;
5687 
5688                 /* Turn on/off promiscuous mode. */
5689                 if (hw->promiscuous <= 1 && prev_state <= 1)
5690                         hw_set_promiscuous(hw, hw->promiscuous);
5691 
5692                 /*
5693                  * Port is not in promiscuous mode, meaning it is released
5694                  * from the bridge.
5695                  */
5696                 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5697                     (dev->priv_flags & IFF_BRIDGE_PORT)) {
5698                         struct ksz_switch *sw = hw->ksz_switch;
5699                         int port = priv->port.first_port;
5700 
5701                         port_set_stp_state(hw, port, STP_STATE_DISABLED);
5702                         port = 1 << port;
5703                         if (sw->member & port) {
5704                                 sw->member &= ~port;
5705                                 bridge_change(hw);
5706                         }
5707                 }
5708         }
5709 }
5710 
5711 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5712         int multicast)
5713 {
5714         if (multicast != priv->multicast) {
5715                 u8 all_multi = hw->all_multi;
5716 
5717                 if (multicast)
5718                         ++hw->all_multi;
5719                 else
5720                         --hw->all_multi;
5721                 priv->multicast = multicast;
5722 
5723                 /* Turn on/off all multicast mode. */
5724                 if (hw->all_multi <= 1 && all_multi <= 1)
5725                         hw_set_multicast(hw, hw->all_multi);
5726         }
5727 }
5728 
5729 /**
5730  * netdev_set_rx_mode
5731  * @dev:        Network device.
5732  *
5733  * This routine is used to set multicast addresses or put the network device
5734  * into promiscuous mode.
5735  */
5736 static void netdev_set_rx_mode(struct net_device *dev)
5737 {
5738         struct dev_priv *priv = netdev_priv(dev);
5739         struct dev_info *hw_priv = priv->adapter;
5740         struct ksz_hw *hw = &hw_priv->hw;
5741         struct netdev_hw_addr *ha;
5742         int multicast = (dev->flags & IFF_ALLMULTI);
5743 
5744         dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5745 
5746         if (hw_priv->hw.dev_count > 1)
5747                 multicast |= (dev->flags & IFF_MULTICAST);
5748         dev_set_multicast(priv, hw, multicast);
5749 
5750         /* Cannot use different hashes in multiple device interfaces mode. */
5751         if (hw_priv->hw.dev_count > 1)
5752                 return;
5753 
5754         if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5755                 int i = 0;
5756 
5757                 /* List too big to support so turn on all multicast mode. */
5758                 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5759                         if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5760                                 hw->multi_list_size = MAX_MULTICAST_LIST;
5761                                 ++hw->all_multi;
5762                                 hw_set_multicast(hw, hw->all_multi);
5763                         }
5764                         return;
5765                 }
5766 
5767                 netdev_for_each_mc_addr(ha, dev) {
5768                         if (i >= MAX_MULTICAST_LIST)
5769                                 break;
5770                         memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5771                 }
5772                 hw->multi_list_size = (u8) i;
5773                 hw_set_grp_addr(hw);
5774         } else {
5775                 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5776                         --hw->all_multi;
5777                         hw_set_multicast(hw, hw->all_multi);
5778                 }
5779                 hw->multi_list_size = 0;
5780                 hw_clr_multicast(hw);
5781         }
5782 }
5783 
5784 static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5785 {
5786         struct dev_priv *priv = netdev_priv(dev);
5787         struct dev_info *hw_priv = priv->adapter;
5788         struct ksz_hw *hw = &hw_priv->hw;
5789         int hw_mtu;
5790 
5791         if (netif_running(dev))
5792                 return -EBUSY;
5793 
5794         /* Cannot use different MTU in multiple device interfaces mode. */
5795         if (hw->dev_count > 1)
5796                 if (dev != hw_priv->dev)
5797                         return 0;
5798 
5799         hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5800         if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5801                 hw->features |= RX_HUGE_FRAME;
5802                 hw_mtu = MAX_RX_BUF_SIZE;
5803         } else {
5804                 hw->features &= ~RX_HUGE_FRAME;
5805                 hw_mtu = REGULAR_RX_BUF_SIZE;
5806         }
5807         hw_mtu = (hw_mtu + 3) & ~3;
5808         hw_priv->mtu = hw_mtu;
5809         dev->mtu = new_mtu;
5810 
5811         return 0;
5812 }
5813 
5814 /**
5815  * netdev_ioctl - I/O control processing
5816  * @dev:        Network device.
5817  * @ifr:        Interface request structure.
5818  * @cmd:        I/O control code.
5819  *
5820  * This function is used to process I/O control calls.
5821  *
5822  * Return 0 to indicate success.
5823  */
5824 static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5825 {
5826         struct dev_priv *priv = netdev_priv(dev);
5827         struct dev_info *hw_priv = priv->adapter;
5828         struct ksz_hw *hw = &hw_priv->hw;
5829         struct ksz_port *port = &priv->port;
5830         int result = 0;
5831         struct mii_ioctl_data *data = if_mii(ifr);
5832 
5833         if (down_interruptible(&priv->proc_sem))
5834                 return -ERESTARTSYS;
5835 
5836         switch (cmd) {
5837         /* Get address of MII PHY in use. */
5838         case SIOCGMIIPHY:
5839                 data->phy_id = priv->id;
5840 
5841                 /* Fallthrough... */
5842 
5843         /* Read MII PHY register. */
5844         case SIOCGMIIREG:
5845                 if (data->phy_id != priv->id || data->reg_num >= 6)
5846                         result = -EIO;
5847                 else
5848                         hw_r_phy(hw, port->linked->port_id, data->reg_num,
5849                                 &data->val_out);
5850                 break;
5851 
5852         /* Write MII PHY register. */
5853         case SIOCSMIIREG:
5854                 if (!capable(CAP_NET_ADMIN))
5855                         result = -EPERM;
5856                 else if (data->phy_id != priv->id || data->reg_num >= 6)
5857                         result = -EIO;
5858                 else
5859                         hw_w_phy(hw, port->linked->port_id, data->reg_num,
5860                                 data->val_in);
5861                 break;
5862 
5863         default:
5864                 result = -EOPNOTSUPP;
5865         }
5866 
5867         up(&priv->proc_sem);
5868 
5869         return result;
5870 }
5871 
5872 /*
5873  * MII support
5874  */
5875 
5876 /**
5877  * mdio_read - read PHY register
5878  * @dev:        Network device.
5879  * @phy_id:     The PHY id.
5880  * @reg_num:    The register number.
5881  *
5882  * This function returns the PHY register value.
5883  *
5884  * Return the register value.
5885  */
5886 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5887 {
5888         struct dev_priv *priv = netdev_priv(dev);
5889         struct ksz_port *port = &priv->port;
5890         struct ksz_hw *hw = port->hw;
5891         u16 val_out;
5892 
5893         hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5894         return val_out;
5895 }
5896 
5897 /**
5898  * mdio_write - set PHY register
5899  * @dev:        Network device.
5900  * @phy_id:     The PHY id.
5901  * @reg_num:    The register number.
5902  * @val:        The register value.
5903  *
5904  * This procedure sets the PHY register value.
5905  */
5906 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5907 {
5908         struct dev_priv *priv = netdev_priv(dev);
5909         struct ksz_port *port = &priv->port;
5910         struct ksz_hw *hw = port->hw;
5911         int i;
5912         int pi;
5913 
5914         for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5915                 hw_w_phy(hw, pi, reg_num << 1, val);
5916 }
5917 
5918 /*
5919  * ethtool support
5920  */
5921 
5922 #define EEPROM_SIZE                     0x40
5923 
5924 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5925 
5926 #define ADVERTISED_ALL                  \
5927         (ADVERTISED_10baseT_Half |      \
5928         ADVERTISED_10baseT_Full |       \
5929         ADVERTISED_100baseT_Half |      \
5930         ADVERTISED_100baseT_Full)
5931 
5932 /* These functions use the MII functions in mii.c. */
5933 
5934 /**
5935  * netdev_get_link_ksettings - get network device settings
5936  * @dev:        Network device.
5937  * @cmd:        Ethtool command.
5938  *
5939  * This function queries the PHY and returns its state in the ethtool command.
5940  *
5941  * Return 0 if successful; otherwise an error code.
5942  */
5943 static int netdev_get_link_ksettings(struct net_device *dev,
5944                                      struct ethtool_link_ksettings *cmd)
5945 {
5946         struct dev_priv *priv = netdev_priv(dev);
5947         struct dev_info *hw_priv = priv->adapter;
5948 
5949         mutex_lock(&hw_priv->lock);
5950         mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5951         ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5952         mutex_unlock(&hw_priv->lock);
5953 
5954         /* Save advertised settings for workaround in next function. */
5955         ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5956                                                 cmd->link_modes.advertising);
5957 
5958         return 0;
5959 }
5960 
5961 /**
5962  * netdev_set_link_ksettings - set network device settings
5963  * @dev:        Network device.
5964  * @cmd:        Ethtool command.
5965  *
5966  * This function sets the PHY according to the ethtool command.
5967  *
5968  * Return 0 if successful; otherwise an error code.
5969  */
5970 static int netdev_set_link_ksettings(struct net_device *dev,
5971                                      const struct ethtool_link_ksettings *cmd)
5972 {
5973         struct dev_priv *priv = netdev_priv(dev);
5974         struct dev_info *hw_priv = priv->adapter;
5975         struct ksz_port *port = &priv->port;
5976         struct ethtool_link_ksettings copy_cmd;
5977         u32 speed = cmd->base.speed;
5978         u32 advertising;
5979         int rc;
5980 
5981         ethtool_convert_link_mode_to_legacy_u32(&advertising,
5982                                                 cmd->link_modes.advertising);
5983 
5984         /*
5985          * ethtool utility does not change advertised setting if auto
5986          * negotiation is not specified explicitly.
5987          */
5988         if (cmd->base.autoneg && priv->advertising == advertising) {
5989                 advertising |= ADVERTISED_ALL;
5990                 if (10 == speed)
5991                         advertising &=
5992                                 ~(ADVERTISED_100baseT_Full |
5993                                 ADVERTISED_100baseT_Half);
5994                 else if (100 == speed)
5995                         advertising &=
5996                                 ~(ADVERTISED_10baseT_Full |
5997                                 ADVERTISED_10baseT_Half);
5998                 if (0 == cmd->base.duplex)
5999                         advertising &=
6000                                 ~(ADVERTISED_100baseT_Full |
6001                                 ADVERTISED_10baseT_Full);
6002                 else if (1 == cmd->base.duplex)
6003                         advertising &=
6004                                 ~(ADVERTISED_100baseT_Half |
6005                                 ADVERTISED_10baseT_Half);
6006         }
6007         mutex_lock(&hw_priv->lock);
6008         if (cmd->base.autoneg &&
6009             (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
6010                 port->duplex = 0;
6011                 port->speed = 0;
6012                 port->force_link = 0;
6013         } else {
6014                 port->duplex = cmd->base.duplex + 1;
6015                 if (1000 != speed)
6016                         port->speed = speed;
6017                 if (cmd->base.autoneg)
6018                         port->force_link = 0;
6019                 else
6020                         port->force_link = 1;
6021         }
6022 
6023         memcpy(&copy_cmd, cmd, sizeof(copy_cmd));
6024         ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
6025                                                 advertising);
6026         rc = mii_ethtool_set_link_ksettings(
6027                 &priv->mii_if,
6028                 (const struct ethtool_link_ksettings *)&copy_cmd);
6029         mutex_unlock(&hw_priv->lock);
6030         return rc;
6031 }
6032 
6033 /**
6034  * netdev_nway_reset - restart auto-negotiation
6035  * @dev:        Network device.
6036  *
6037  * This function restarts the PHY for auto-negotiation.
6038  *
6039  * Return 0 if successful; otherwise an error code.
6040  */
6041 static int netdev_nway_reset(struct net_device *dev)
6042 {
6043         struct dev_priv *priv = netdev_priv(dev);
6044         struct dev_info *hw_priv = priv->adapter;
6045         int rc;
6046 
6047         mutex_lock(&hw_priv->lock);
6048         rc = mii_nway_restart(&priv->mii_if);
6049         mutex_unlock(&hw_priv->lock);
6050         return rc;
6051 }
6052 
6053 /**
6054  * netdev_get_link - get network device link status
6055  * @dev:        Network device.
6056  *
6057  * This function gets the link status from the PHY.
6058  *
6059  * Return true if PHY is linked and false otherwise.
6060  */
6061 static u32 netdev_get_link(struct net_device *dev)
6062 {
6063         struct dev_priv *priv = netdev_priv(dev);
6064         int rc;
6065 
6066         rc = mii_link_ok(&priv->mii_if);
6067         return rc;
6068 }
6069 
6070 /**
6071  * netdev_get_drvinfo - get network driver information
6072  * @dev:        Network device.
6073  * @info:       Ethtool driver info data structure.
6074  *
6075  * This procedure returns the driver information.
6076  */
6077 static void netdev_get_drvinfo(struct net_device *dev,
6078         struct ethtool_drvinfo *info)
6079 {
6080         struct dev_priv *priv = netdev_priv(dev);
6081         struct dev_info *hw_priv = priv->adapter;
6082 
6083         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
6084         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
6085         strlcpy(info->bus_info, pci_name(hw_priv->pdev),
6086                 sizeof(info->bus_info));
6087 }
6088 
6089 /**
6090  * netdev_get_regs_len - get length of register dump
6091  * @dev:        Network device.
6092  *
6093  * This function returns the length of the register dump.
6094  *
6095  * Return length of the register dump.
6096  */
6097 static struct hw_regs {
6098         int start;
6099         int end;
6100 } hw_regs_range[] = {
6101         { KS_DMA_TX_CTRL,       KS884X_INTERRUPTS_STATUS },
6102         { KS_ADD_ADDR_0_LO,     KS_ADD_ADDR_F_HI },
6103         { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6104         { KS884X_SIDER_P,       KS8842_SGCR7_P },
6105         { KS8842_MACAR1_P,      KS8842_TOSR8_P },
6106         { KS884X_P1MBCR_P,      KS8842_P3ERCR_P },
6107         { 0, 0 }
6108 };
6109 
6110 static int netdev_get_regs_len(struct net_device *dev)
6111 {
6112         struct hw_regs *range = hw_regs_range;
6113         int regs_len = 0x10 * sizeof(u32);
6114 
6115         while (range->end > range->start) {
6116                 regs_len += (range->end - range->start + 3) / 4 * 4;
6117                 range++;
6118         }
6119         return regs_len;
6120 }
6121 
6122 /**
6123  * netdev_get_regs - get register dump
6124  * @dev:        Network device.
6125  * @regs:       Ethtool registers data structure.
6126  * @ptr:        Buffer to store the register values.
6127  *
6128  * This procedure dumps the register values in the provided buffer.
6129  */
6130 static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6131         void *ptr)
6132 {
6133         struct dev_priv *priv = netdev_priv(dev);
6134         struct dev_info *hw_priv = priv->adapter;
6135         struct ksz_hw *hw = &hw_priv->hw;
6136         int *buf = (int *) ptr;
6137         struct hw_regs *range = hw_regs_range;
6138         int len;
6139 
6140         mutex_lock(&hw_priv->lock);
6141         regs->version = 0;
6142         for (len = 0; len < 0x40; len += 4) {
6143                 pci_read_config_dword(hw_priv->pdev, len, buf);
6144                 buf++;
6145         }
6146         while (range->end > range->start) {
6147                 for (len = range->start; len < range->end; len += 4) {
6148                         *buf = readl(hw->io + len);
6149                         buf++;
6150                 }
6151                 range++;
6152         }
6153         mutex_unlock(&hw_priv->lock);
6154 }
6155 
6156 #define WOL_SUPPORT                     \
6157         (WAKE_PHY | WAKE_MAGIC |        \
6158         WAKE_UCAST | WAKE_MCAST |       \
6159         WAKE_BCAST | WAKE_ARP)
6160 
6161 /**
6162  * netdev_get_wol - get Wake-on-LAN support
6163  * @dev:        Network device.
6164  * @wol:        Ethtool Wake-on-LAN data structure.
6165  *
6166  * This procedure returns Wake-on-LAN support.
6167  */
6168 static void netdev_get_wol(struct net_device *dev,
6169         struct ethtool_wolinfo *wol)
6170 {
6171         struct dev_priv *priv = netdev_priv(dev);
6172         struct dev_info *hw_priv = priv->adapter;
6173 
6174         wol->supported = hw_priv->wol_support;
6175         wol->wolopts = hw_priv->wol_enable;
6176         memset(&wol->sopass, 0, sizeof(wol->sopass));
6177 }
6178 
6179 /**
6180  * netdev_set_wol - set Wake-on-LAN support
6181  * @dev:        Network device.
6182  * @wol:        Ethtool Wake-on-LAN data structure.
6183  *
6184  * This function sets Wake-on-LAN support.
6185  *
6186  * Return 0 if successful; otherwise an error code.
6187  */
6188 static int netdev_set_wol(struct net_device *dev,
6189         struct ethtool_wolinfo *wol)
6190 {
6191         struct dev_priv *priv = netdev_priv(dev);
6192         struct dev_info *hw_priv = priv->adapter;
6193 
6194         /* Need to find a way to retrieve the device IP address. */
6195         static const u8 net_addr[] = { 192, 168, 1, 1 };
6196 
6197         if (wol->wolopts & ~hw_priv->wol_support)
6198                 return -EINVAL;
6199 
6200         hw_priv->wol_enable = wol->wolopts;
6201 
6202         /* Link wakeup cannot really be disabled. */
6203         if (wol->wolopts)
6204                 hw_priv->wol_enable |= WAKE_PHY;
6205         hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6206         return 0;
6207 }
6208 
6209 /**
6210  * netdev_get_msglevel - get debug message level
6211  * @dev:        Network device.
6212  *
6213  * This function returns current debug message level.
6214  *
6215  * Return current debug message flags.
6216  */
6217 static u32 netdev_get_msglevel(struct net_device *dev)
6218 {
6219         struct dev_priv *priv = netdev_priv(dev);
6220 
6221         return priv->msg_enable;
6222 }
6223 
6224 /**
6225  * netdev_set_msglevel - set debug message level
6226  * @dev:        Network device.
6227  * @value:      Debug message flags.
6228  *
6229  * This procedure sets debug message level.
6230  */
6231 static void netdev_set_msglevel(struct net_device *dev, u32 value)
6232 {
6233         struct dev_priv *priv = netdev_priv(dev);
6234 
6235         priv->msg_enable = value;
6236 }
6237 
6238 /**
6239  * netdev_get_eeprom_len - get EEPROM length
6240  * @dev:        Network device.
6241  *
6242  * This function returns the length of the EEPROM.
6243  *
6244  * Return length of the EEPROM.
6245  */
6246 static int netdev_get_eeprom_len(struct net_device *dev)
6247 {
6248         return EEPROM_SIZE * 2;
6249 }
6250 
6251 /**
6252  * netdev_get_eeprom - get EEPROM data
6253  * @dev:        Network device.
6254  * @eeprom:     Ethtool EEPROM data structure.
6255  * @data:       Buffer to store the EEPROM data.
6256  *
6257  * This function dumps the EEPROM data in the provided buffer.
6258  *
6259  * Return 0 if successful; otherwise an error code.
6260  */
6261 #define EEPROM_MAGIC                    0x10A18842
6262 
6263 static int netdev_get_eeprom(struct net_device *dev,
6264         struct ethtool_eeprom *eeprom, u8 *data)
6265 {
6266         struct dev_priv *priv = netdev_priv(dev);
6267         struct dev_info *hw_priv = priv->adapter;
6268         u8 *eeprom_byte = (u8 *) eeprom_data;
6269         int i;
6270         int len;
6271 
6272         len = (eeprom->offset + eeprom->len + 1) / 2;
6273         for (i = eeprom->offset / 2; i < len; i++)
6274                 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6275         eeprom->magic = EEPROM_MAGIC;
6276         memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6277 
6278         return 0;
6279 }
6280 
6281 /**
6282  * netdev_set_eeprom - write EEPROM data
6283  * @dev:        Network device.
6284  * @eeprom:     Ethtool EEPROM data structure.
6285  * @data:       Data buffer.
6286  *
6287  * This function modifies the EEPROM data one byte at a time.
6288  *
6289  * Return 0 if successful; otherwise an error code.
6290  */
6291 static int netdev_set_eeprom(struct net_device *dev,
6292         struct ethtool_eeprom *eeprom, u8 *data)
6293 {
6294         struct dev_priv *priv = netdev_priv(dev);
6295         struct dev_info *hw_priv = priv->adapter;
6296         u16 eeprom_word[EEPROM_SIZE];
6297         u8 *eeprom_byte = (u8 *) eeprom_word;
6298         int i;
6299         int len;
6300 
6301         if (eeprom->magic != EEPROM_MAGIC)
6302                 return -EINVAL;
6303 
6304         len = (eeprom->offset + eeprom->len + 1) / 2;
6305         for (i = eeprom->offset / 2; i < len; i++)
6306                 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6307         memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6308         memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6309         for (i = 0; i < EEPROM_SIZE; i++)
6310                 if (eeprom_word[i] != eeprom_data[i]) {
6311                         eeprom_data[i] = eeprom_word[i];
6312                         eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6313         }
6314 
6315         return 0;
6316 }
6317 
6318 /**
6319  * netdev_get_pauseparam - get flow control parameters
6320  * @dev:        Network device.
6321  * @pause:      Ethtool PAUSE settings data structure.
6322  *
6323  * This procedure returns the PAUSE control flow settings.
6324  */
6325 static void netdev_get_pauseparam(struct net_device *dev,
6326         struct ethtool_pauseparam *pause)
6327 {
6328         struct dev_priv *priv = netdev_priv(dev);
6329         struct dev_info *hw_priv = priv->adapter;
6330         struct ksz_hw *hw = &hw_priv->hw;
6331 
6332         pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6333         if (!hw->ksz_switch) {
6334                 pause->rx_pause =
6335                         (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6336                 pause->tx_pause =
6337                         (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6338         } else {
6339                 pause->rx_pause =
6340                         (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6341                                 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6342                 pause->tx_pause =
6343                         (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6344                                 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6345         }
6346 }
6347 
6348 /**
6349  * netdev_set_pauseparam - set flow control parameters
6350  * @dev:        Network device.
6351  * @pause:      Ethtool PAUSE settings data structure.
6352  *
6353  * This function sets the PAUSE control flow settings.
6354  * Not implemented yet.
6355  *
6356  * Return 0 if successful; otherwise an error code.
6357  */
6358 static int netdev_set_pauseparam(struct net_device *dev,
6359         struct ethtool_pauseparam *pause)
6360 {
6361         struct dev_priv *priv = netdev_priv(dev);
6362         struct dev_info *hw_priv = priv->adapter;
6363         struct ksz_hw *hw = &hw_priv->hw;
6364         struct ksz_port *port = &priv->port;
6365 
6366         mutex_lock(&hw_priv->lock);
6367         if (pause->autoneg) {
6368                 if (!pause->rx_pause && !pause->tx_pause)
6369                         port->flow_ctrl = PHY_NO_FLOW_CTRL;
6370                 else
6371                         port->flow_ctrl = PHY_FLOW_CTRL;
6372                 hw->overrides &= ~PAUSE_FLOW_CTRL;
6373                 port->force_link = 0;
6374                 if (hw->ksz_switch) {
6375                         sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6376                                 SWITCH_RX_FLOW_CTRL, 1);
6377                         sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6378                                 SWITCH_TX_FLOW_CTRL, 1);
6379                 }
6380                 port_set_link_speed(port);
6381         } else {
6382                 hw->overrides |= PAUSE_FLOW_CTRL;
6383                 if (hw->ksz_switch) {
6384                         sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6385                                 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6386                         sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6387                                 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6388                 } else
6389                         set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6390         }
6391         mutex_unlock(&hw_priv->lock);
6392 
6393         return 0;
6394 }
6395 
6396 /**
6397  * netdev_get_ringparam - get tx/rx ring parameters
6398  * @dev:        Network device.
6399  * @pause:      Ethtool RING settings data structure.
6400  *
6401  * This procedure returns the TX/RX ring settings.
6402  */
6403 static void netdev_get_ringparam(struct net_device *dev,
6404         struct ethtool_ringparam *ring)
6405 {
6406         struct dev_priv *priv = netdev_priv(dev);
6407         struct dev_info *hw_priv = priv->adapter;
6408         struct ksz_hw *hw = &hw_priv->hw;
6409 
6410         ring->tx_max_pending = (1 << 9);
6411         ring->tx_pending = hw->tx_desc_info.alloc;
6412         ring->rx_max_pending = (1 << 9);
6413         ring->rx_pending = hw->rx_desc_info.alloc;
6414 }
6415 
6416 #define STATS_LEN                       (TOTAL_PORT_COUNTER_NUM)
6417 
6418 static struct {
6419         char string[ETH_GSTRING_LEN];
6420 } ethtool_stats_keys[STATS_LEN] = {
6421         { "rx_lo_priority_octets" },
6422         { "rx_hi_priority_octets" },
6423         { "rx_undersize_packets" },
6424         { "rx_fragments" },
6425         { "rx_oversize_packets" },
6426         { "rx_jabbers" },
6427         { "rx_symbol_errors" },
6428         { "rx_crc_errors" },
6429         { "rx_align_errors" },
6430         { "rx_mac_ctrl_packets" },
6431         { "rx_pause_packets" },
6432         { "rx_bcast_packets" },
6433         { "rx_mcast_packets" },
6434         { "rx_ucast_packets" },
6435         { "rx_64_or_less_octet_packets" },
6436         { "rx_65_to_127_octet_packets" },
6437         { "rx_128_to_255_octet_packets" },
6438         { "rx_256_to_511_octet_packets" },
6439         { "rx_512_to_1023_octet_packets" },
6440         { "rx_1024_to_1522_octet_packets" },
6441 
6442         { "tx_lo_priority_octets" },
6443         { "tx_hi_priority_octets" },
6444         { "tx_late_collisions" },
6445         { "tx_pause_packets" },
6446         { "tx_bcast_packets" },
6447         { "tx_mcast_packets" },
6448         { "tx_ucast_packets" },
6449         { "tx_deferred" },
6450         { "tx_total_collisions" },
6451         { "tx_excessive_collisions" },
6452         { "tx_single_collisions" },
6453         { "tx_mult_collisions" },
6454 
6455         { "rx_discards" },
6456         { "tx_discards" },
6457 };
6458 
6459 /**
6460  * netdev_get_strings - get statistics identity strings
6461  * @dev:        Network device.
6462  * @stringset:  String set identifier.
6463  * @buf:        Buffer to store the strings.
6464  *
6465  * This procedure returns the strings used to identify the statistics.
6466  */
6467 static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6468 {
6469         struct dev_priv *priv = netdev_priv(dev);
6470         struct dev_info *hw_priv = priv->adapter;
6471         struct ksz_hw *hw = &hw_priv->hw;
6472 
6473         if (ETH_SS_STATS == stringset)
6474                 memcpy(buf, &ethtool_stats_keys,
6475                         ETH_GSTRING_LEN * hw->mib_cnt);
6476 }
6477 
6478 /**
6479  * netdev_get_sset_count - get statistics size
6480  * @dev:        Network device.
6481  * @sset:       The statistics set number.
6482  *
6483  * This function returns the size of the statistics to be reported.
6484  *
6485  * Return size of the statistics to be reported.
6486  */
6487 static int netdev_get_sset_count(struct net_device *dev, int sset)
6488 {
6489         struct dev_priv *priv = netdev_priv(dev);
6490         struct dev_info *hw_priv = priv->adapter;
6491         struct ksz_hw *hw = &hw_priv->hw;
6492 
6493         switch (sset) {
6494         case ETH_SS_STATS:
6495                 return hw->mib_cnt;
6496         default:
6497                 return -EOPNOTSUPP;
6498         }
6499 }
6500 
6501 /**
6502  * netdev_get_ethtool_stats - get network device statistics
6503  * @dev:        Network device.
6504  * @stats:      Ethtool statistics data structure.
6505  * @data:       Buffer to store the statistics.
6506  *
6507  * This procedure returns the statistics.
6508  */
6509 static void netdev_get_ethtool_stats(struct net_device *dev,
6510         struct ethtool_stats *stats, u64 *data)
6511 {
6512         struct dev_priv *priv = netdev_priv(dev);
6513         struct dev_info *hw_priv = priv->adapter;
6514         struct ksz_hw *hw = &hw_priv->hw;
6515         struct ksz_port *port = &priv->port;
6516         int n_stats = stats->n_stats;
6517         int i;
6518         int n;
6519         int p;
6520         int rc;
6521         u64 counter[TOTAL_PORT_COUNTER_NUM];
6522 
6523         mutex_lock(&hw_priv->lock);
6524         n = SWITCH_PORT_NUM;
6525         for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6526                 if (media_connected == hw->port_mib[p].state) {
6527                         hw_priv->counter[p].read = 1;
6528 
6529                         /* Remember first port that requests read. */
6530                         if (n == SWITCH_PORT_NUM)
6531                                 n = p;
6532                 }
6533         }
6534         mutex_unlock(&hw_priv->lock);
6535 
6536         if (n < SWITCH_PORT_NUM)
6537                 schedule_work(&hw_priv->mib_read);
6538 
6539         if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6540                 p = n;
6541                 rc = wait_event_interruptible_timeout(
6542                         hw_priv->counter[p].counter,
6543                         2 == hw_priv->counter[p].read,
6544                         HZ * 1);
6545         } else
6546                 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6547                         if (0 == i) {
6548                                 rc = wait_event_interruptible_timeout(
6549                                         hw_priv->counter[p].counter,
6550                                         2 == hw_priv->counter[p].read,
6551                                         HZ * 2);
6552                         } else if (hw->port_mib[p].cnt_ptr) {
6553                                 rc = wait_event_interruptible_timeout(
6554                                         hw_priv->counter[p].counter,
6555                                         2 == hw_priv->counter[p].read,
6556                                         HZ * 1);
6557                         }
6558                 }
6559 
6560         get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6561         n = hw->mib_cnt;
6562         if (n > n_stats)
6563                 n = n_stats;
6564         n_stats -= n;
6565         for (i = 0; i < n; i++)
6566                 *data++ = counter[i];
6567 }
6568 
6569 /**
6570  * netdev_set_features - set receive checksum support
6571  * @dev:        Network device.
6572  * @features:   New device features (offloads).
6573  *
6574  * This function sets receive checksum support setting.
6575  *
6576  * Return 0 if successful; otherwise an error code.
6577  */
6578 static int netdev_set_features(struct net_device *dev,
6579         netdev_features_t features)
6580 {
6581         struct dev_priv *priv = netdev_priv(dev);
6582         struct dev_info *hw_priv = priv->adapter;
6583         struct ksz_hw *hw = &hw_priv->hw;
6584 
6585         mutex_lock(&hw_priv->lock);
6586 
6587         /* see note in hw_setup() */
6588         if (features & NETIF_F_RXCSUM)
6589                 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6590         else
6591                 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6592 
6593         if (hw->enabled)
6594                 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6595 
6596         mutex_unlock(&hw_priv->lock);
6597 
6598         return 0;
6599 }
6600 
6601 static const struct ethtool_ops netdev_ethtool_ops = {
6602         .nway_reset             = netdev_nway_reset,
6603         .get_link               = netdev_get_link,
6604         .get_drvinfo            = netdev_get_drvinfo,
6605         .get_regs_len           = netdev_get_regs_len,
6606         .get_regs               = netdev_get_regs,
6607         .get_wol                = netdev_get_wol,
6608         .set_wol                = netdev_set_wol,
6609         .get_msglevel           = netdev_get_msglevel,
6610         .set_msglevel           = netdev_set_msglevel,
6611         .get_eeprom_len         = netdev_get_eeprom_len,
6612         .get_eeprom             = netdev_get_eeprom,
6613         .set_eeprom             = netdev_set_eeprom,
6614         .get_pauseparam         = netdev_get_pauseparam,
6615         .set_pauseparam         = netdev_set_pauseparam,
6616         .get_ringparam          = netdev_get_ringparam,
6617         .get_strings            = netdev_get_strings,
6618         .get_sset_count         = netdev_get_sset_count,
6619         .get_ethtool_stats      = netdev_get_ethtool_stats,
6620         .get_link_ksettings     = netdev_get_link_ksettings,
6621         .set_link_ksettings     = netdev_set_link_ksettings,
6622 };
6623 
6624 /*
6625  * Hardware monitoring
6626  */
6627 
6628 static void update_link(struct net_device *dev, struct dev_priv *priv,
6629         struct ksz_port *port)
6630 {
6631         if (priv->media_state != port->linked->state) {
6632                 priv->media_state = port->linked->state;
6633                 if (netif_running(dev))
6634                         set_media_state(dev, media_connected);
6635         }
6636 }
6637 
6638 static void mib_read_work(struct work_struct *work)
6639 {
6640         struct dev_info *hw_priv =
6641                 container_of(work, struct dev_info, mib_read);
6642         struct ksz_hw *hw = &hw_priv->hw;
6643         struct ksz_port_mib *mib;
6644         int i;
6645 
6646         next_jiffies = jiffies;
6647         for (i = 0; i < hw->mib_port_cnt; i++) {
6648                 mib = &hw->port_mib[i];
6649 
6650                 /* Reading MIB counters or requested to read. */
6651                 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6652 
6653                         /* Need to process receive interrupt. */
6654                         if (port_r_cnt(hw, i))
6655                                 break;
6656                         hw_priv->counter[i].read = 0;
6657 
6658                         /* Finish reading counters. */
6659                         if (0 == mib->cnt_ptr) {
6660                                 hw_priv->counter[i].read = 2;
6661                                 wake_up_interruptible(
6662                                         &hw_priv->counter[i].counter);
6663                         }
6664                 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6665                         /* Only read MIB counters when the port is connected. */
6666                         if (media_connected == mib->state)
6667                                 hw_priv->counter[i].read = 1;
6668                         next_jiffies += HZ * 1 * hw->mib_port_cnt;
6669                         hw_priv->counter[i].time = next_jiffies;
6670 
6671                 /* Port is just disconnected. */
6672                 } else if (mib->link_down) {
6673                         mib->link_down = 0;
6674 
6675                         /* Read counters one last time after link is lost. */
6676                         hw_priv->counter[i].read = 1;
6677                 }
6678         }
6679 }
6680 
6681 static void mib_monitor(struct timer_list *t)
6682 {
6683         struct dev_info *hw_priv = from_timer(hw_priv, t, mib_timer_info.timer);
6684 
6685         mib_read_work(&hw_priv->mib_read);
6686 
6687         /* This is used to verify Wake-on-LAN is working. */
6688         if (hw_priv->pme_wait) {
6689                 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6690                         hw_clr_wol_pme_status(&hw_priv->hw);
6691                         hw_priv->pme_wait = 0;
6692                 }
6693         } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6694 
6695                 /* PME is asserted.  Wait 2 seconds to clear it. */
6696                 hw_priv->pme_wait = jiffies + HZ * 2;
6697         }
6698 
6699         ksz_update_timer(&hw_priv->mib_timer_info);
6700 }
6701 
6702 /**
6703  * dev_monitor - periodic monitoring
6704  * @ptr:        Network device pointer.
6705  *
6706  * This routine is run in a kernel timer to monitor the network device.
6707  */
6708 static void dev_monitor(struct timer_list *t)
6709 {
6710         struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer);
6711         struct net_device *dev = priv->mii_if.dev;
6712         struct dev_info *hw_priv = priv->adapter;
6713         struct ksz_hw *hw = &hw_priv->hw;
6714         struct ksz_port *port = &priv->port;
6715 
6716         if (!(hw->features & LINK_INT_WORKING))
6717                 port_get_link_speed(port);
6718         update_link(dev, priv, port);
6719 
6720         ksz_update_timer(&priv->monitor_timer_info);
6721 }
6722 
6723 /*
6724  * Linux network device interface functions
6725  */
6726 
6727 /* Driver exported variables */
6728 
6729 static int msg_enable;
6730 
6731 static char *macaddr = ":";
6732 static char *mac1addr = ":";
6733 
6734 /*
6735  * This enables multiple network device mode for KSZ8842, which contains a
6736  * switch with two physical ports.  Some users like to take control of the
6737  * ports for running Spanning Tree Protocol.  The driver will create an
6738  * additional eth? device for the other port.
6739  *
6740  * Some limitations are the network devices cannot have different MTU and
6741  * multicast hash tables.
6742  */
6743 static int multi_dev;
6744 
6745 /*
6746  * As most users select multiple network device mode to use Spanning Tree
6747  * Protocol, this enables a feature in which most unicast and multicast packets
6748  * are forwarded inside the switch and not passed to the host.  Only packets
6749  * that need the host's attention are passed to it.  This prevents the host
6750  * wasting CPU time to examine each and every incoming packets and do the
6751  * forwarding itself.
6752  *
6753  * As the hack requires the private bridge header, the driver cannot compile
6754  * with just the kernel headers.
6755  *
6756  * Enabling STP support also turns on multiple network device mode.
6757  */
6758 static int stp;
6759 
6760 /*
6761  * This enables fast aging in the KSZ8842 switch.  Not sure what situation
6762  * needs that.  However, fast aging is used to flush the dynamic MAC table when
6763  * STP support is enabled.
6764  */
6765 static int fast_aging;
6766 
6767 /**
6768  * netdev_init - initialize network device.
6769  * @dev:        Network device.
6770  *
6771  * This function initializes the network device.
6772  *
6773  * Return 0 if successful; otherwise an error code indicating failure.
6774  */
6775 static int __init netdev_init(struct net_device *dev)
6776 {
6777         struct dev_priv *priv = netdev_priv(dev);
6778 
6779         /* 500 ms timeout */
6780         ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6781                 dev_monitor);
6782 
6783         /* 500 ms timeout */
6784         dev->watchdog_timeo = HZ / 2;
6785 
6786         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6787 
6788         /*
6789          * Hardware does not really support IPv6 checksum generation, but
6790          * driver actually runs faster with this on.
6791          */
6792         dev->hw_features |= NETIF_F_IPV6_CSUM;
6793 
6794         dev->features |= dev->hw_features;
6795 
6796         sema_init(&priv->proc_sem, 1);
6797 
6798         priv->mii_if.phy_id_mask = 0x1;
6799         priv->mii_if.reg_num_mask = 0x7;
6800         priv->mii_if.dev = dev;
6801         priv->mii_if.mdio_read = mdio_read;
6802         priv->mii_if.mdio_write = mdio_write;
6803         priv->mii_if.phy_id = priv->port.first_port + 1;
6804 
6805         priv->msg_enable = netif_msg_init(msg_enable,
6806                 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6807 
6808         return 0;
6809 }
6810 
6811 static const struct net_device_ops netdev_ops = {
6812         .ndo_init               = netdev_init,
6813         .ndo_open               = netdev_open,
6814         .ndo_stop               = netdev_close,
6815         .ndo_get_stats          = netdev_query_statistics,
6816         .ndo_start_xmit         = netdev_tx,
6817         .ndo_tx_timeout         = netdev_tx_timeout,
6818         .ndo_change_mtu         = netdev_change_mtu,
6819         .ndo_set_features       = netdev_set_features,
6820         .ndo_set_mac_address    = netdev_set_mac_address,
6821         .ndo_validate_addr      = eth_validate_addr,
6822         .ndo_do_ioctl           = netdev_ioctl,
6823         .ndo_set_rx_mode        = netdev_set_rx_mode,
6824 #ifdef CONFIG_NET_POLL_CONTROLLER
6825         .ndo_poll_controller    = netdev_netpoll,
6826 #endif
6827 };
6828 
6829 static void netdev_free(struct net_device *dev)
6830 {
6831         if (dev->watchdog_timeo)
6832                 unregister_netdev(dev);
6833 
6834         free_netdev(dev);
6835 }
6836 
6837 struct platform_info {
6838         struct dev_info dev_info;
6839         struct net_device *netdev[SWITCH_PORT_NUM];
6840 };
6841 
6842 static int net_device_present;
6843 
6844 static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6845 {
6846         int i;
6847         int j;
6848         int got_num;
6849         int num;
6850 
6851         i = j = num = got_num = 0;
6852         while (j < ETH_ALEN) {
6853                 if (macaddr[i]) {
6854                         int digit;
6855 
6856                         got_num = 1;
6857                         digit = hex_to_bin(macaddr[i]);
6858                         if (digit >= 0)
6859                                 num = num * 16 + digit;
6860                         else if (':' == macaddr[i])
6861                                 got_num = 2;
6862                         else
6863                                 break;
6864                 } else if (got_num)
6865                         got_num = 2;
6866                 else
6867                         break;
6868                 if (2 == got_num) {
6869                         if (MAIN_PORT == port) {
6870                                 hw_priv->hw.override_addr[j++] = (u8) num;
6871                                 hw_priv->hw.override_addr[5] +=
6872                                         hw_priv->hw.id;
6873                         } else {
6874                                 hw_priv->hw.ksz_switch->other_addr[j++] =
6875                                         (u8) num;
6876                                 hw_priv->hw.ksz_switch->other_addr[5] +=
6877                                         hw_priv->hw.id;
6878                         }
6879                         num = got_num = 0;
6880                 }
6881                 i++;
6882         }
6883         if (ETH_ALEN == j) {
6884                 if (MAIN_PORT == port)
6885                         hw_priv->hw.mac_override = 1;
6886         }
6887 }
6888 
6889 #define KS884X_DMA_MASK                 (~0x0UL)
6890 
6891 static void read_other_addr(struct ksz_hw *hw)
6892 {
6893         int i;
6894         u16 data[3];
6895         struct ksz_switch *sw = hw->ksz_switch;
6896 
6897         for (i = 0; i < 3; i++)
6898                 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6899         if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6900                 sw->other_addr[5] = (u8) data[0];
6901                 sw->other_addr[4] = (u8)(data[0] >> 8);
6902                 sw->other_addr[3] = (u8) data[1];
6903                 sw->other_addr[2] = (u8)(data[1] >> 8);
6904                 sw->other_addr[1] = (u8) data[2];
6905                 sw->other_addr[0] = (u8)(data[2] >> 8);
6906         }
6907 }
6908 
6909 #ifndef PCI_VENDOR_ID_MICREL_KS
6910 #define PCI_VENDOR_ID_MICREL_KS         0x16c6
6911 #endif
6912 
6913 static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6914 {
6915         struct net_device *dev;
6916         struct dev_priv *priv;
6917         struct dev_info *hw_priv;
6918         struct ksz_hw *hw;
6919         struct platform_info *info;
6920         struct ksz_port *port;
6921         unsigned long reg_base;
6922         unsigned long reg_len;
6923         int cnt;
6924         int i;
6925         int mib_port_count;
6926         int pi;
6927         int port_count;
6928         int result;
6929         char banner[sizeof(version)];
6930         struct ksz_switch *sw = NULL;
6931 
6932         result = pci_enable_device(pdev);
6933         if (result)
6934                 return result;
6935 
6936         result = -ENODEV;
6937 
6938         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6939                         pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6940                 return result;
6941 
6942         reg_base = pci_resource_start(pdev, 0);
6943         reg_len = pci_resource_len(pdev, 0);
6944         if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6945                 return result;
6946 
6947         if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6948                 return result;
6949         pci_set_master(pdev);
6950 
6951         result = -ENOMEM;
6952 
6953         info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6954         if (!info)
6955                 goto pcidev_init_dev_err;
6956 
6957         hw_priv = &info->dev_info;
6958         hw_priv->pdev = pdev;
6959 
6960         hw = &hw_priv->hw;
6961 
6962         hw->io = ioremap(reg_base, reg_len);
6963         if (!hw->io)
6964                 goto pcidev_init_io_err;
6965 
6966         cnt = hw_init(hw);
6967         if (!cnt) {
6968                 if (msg_enable & NETIF_MSG_PROBE)
6969                         pr_alert("chip not detected\n");
6970                 result = -ENODEV;
6971                 goto pcidev_init_alloc_err;
6972         }
6973 
6974         snprintf(banner, sizeof(banner), "%s", version);
6975         banner[13] = cnt + '0';         /* Replace x in "Micrel KSZ884x" */
6976         dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6977         dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6978 
6979         /* Assume device is KSZ8841. */
6980         hw->dev_count = 1;
6981         port_count = 1;
6982         mib_port_count = 1;
6983         hw->addr_list_size = 0;
6984         hw->mib_cnt = PORT_COUNTER_NUM;
6985         hw->mib_port_cnt = 1;
6986 
6987         /* KSZ8842 has a switch with multiple ports. */
6988         if (2 == cnt) {
6989                 if (fast_aging)
6990                         hw->overrides |= FAST_AGING;
6991 
6992                 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
6993 
6994                 /* Multiple network device interfaces are required. */
6995                 if (multi_dev) {
6996                         hw->dev_count = SWITCH_PORT_NUM;
6997                         hw->addr_list_size = SWITCH_PORT_NUM - 1;
6998                 }
6999 
7000                 /* Single network device has multiple ports. */
7001                 if (1 == hw->dev_count) {
7002                         port_count = SWITCH_PORT_NUM;
7003                         mib_port_count = SWITCH_PORT_NUM;
7004                 }
7005                 hw->mib_port_cnt = TOTAL_PORT_NUM;
7006                 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7007                 if (!hw->ksz_switch)
7008                         goto pcidev_init_alloc_err;
7009 
7010                 sw = hw->ksz_switch;
7011         }
7012         for (i = 0; i < hw->mib_port_cnt; i++)
7013                 hw->port_mib[i].mib_start = 0;
7014 
7015         hw->parent = hw_priv;
7016 
7017         /* Default MTU is 1500. */
7018         hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7019 
7020         if (ksz_alloc_mem(hw_priv))
7021                 goto pcidev_init_mem_err;
7022 
7023         hw_priv->hw.id = net_device_present;
7024 
7025         spin_lock_init(&hw_priv->hwlock);
7026         mutex_init(&hw_priv->lock);
7027 
7028         for (i = 0; i < TOTAL_PORT_NUM; i++)
7029                 init_waitqueue_head(&hw_priv->counter[i].counter);
7030 
7031         if (macaddr[0] != ':')
7032                 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7033 
7034         /* Read MAC address and initialize override address if not overridden. */
7035         hw_read_addr(hw);
7036 
7037         /* Multiple device interfaces mode requires a second MAC address. */
7038         if (hw->dev_count > 1) {
7039                 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
7040                 read_other_addr(hw);
7041                 if (mac1addr[0] != ':')
7042                         get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7043         }
7044 
7045         hw_setup(hw);
7046         if (hw->ksz_switch)
7047                 sw_setup(hw);
7048         else {
7049                 hw_priv->wol_support = WOL_SUPPORT;
7050                 hw_priv->wol_enable = 0;
7051         }
7052 
7053         INIT_WORK(&hw_priv->mib_read, mib_read_work);
7054 
7055         /* 500 ms timeout */
7056         ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7057                 mib_monitor);
7058 
7059         for (i = 0; i < hw->dev_count; i++) {
7060                 dev = alloc_etherdev(sizeof(struct dev_priv));
7061                 if (!dev)
7062                         goto pcidev_init_reg_err;
7063                 SET_NETDEV_DEV(dev, &pdev->dev);
7064                 info->netdev[i] = dev;
7065 
7066                 priv = netdev_priv(dev);
7067                 priv->adapter = hw_priv;
7068                 priv->id = net_device_present++;
7069 
7070                 port = &priv->port;
7071                 port->port_cnt = port_count;
7072                 port->mib_port_cnt = mib_port_count;
7073                 port->first_port = i;
7074                 port->flow_ctrl = PHY_FLOW_CTRL;
7075 
7076                 port->hw = hw;
7077                 port->linked = &hw->port_info[port->first_port];
7078 
7079                 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7080                         hw->port_info[pi].port_id = pi;
7081                         hw->port_info[pi].pdev = dev;
7082                         hw->port_info[pi].state = media_disconnected;
7083                 }
7084 
7085                 dev->mem_start = (unsigned long) hw->io;
7086                 dev->mem_end = dev->mem_start + reg_len - 1;
7087                 dev->irq = pdev->irq;
7088                 if (MAIN_PORT == i)
7089                         memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7090                                ETH_ALEN);
7091                 else {
7092                         memcpy(dev->dev_addr, sw->other_addr, ETH_ALEN);
7093                         if (ether_addr_equal(sw->other_addr, hw->override_addr))
7094                                 dev->dev_addr[5] += port->first_port;
7095                 }
7096 
7097                 dev->netdev_ops = &netdev_ops;
7098                 dev->ethtool_ops = &netdev_ethtool_ops;
7099 
7100                 /* MTU range: 60 - 1894 */
7101                 dev->min_mtu = ETH_ZLEN;
7102                 dev->max_mtu = MAX_RX_BUF_SIZE -
7103                                (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7104 
7105                 if (register_netdev(dev))
7106                         goto pcidev_init_reg_err;
7107                 port_set_power_saving(port, true);
7108         }
7109 
7110         pci_dev_get(hw_priv->pdev);
7111         pci_set_drvdata(pdev, info);
7112         return 0;
7113 
7114 pcidev_init_reg_err:
7115         for (i = 0; i < hw->dev_count; i++) {
7116                 if (info->netdev[i]) {
7117                         netdev_free(info->netdev[i]);
7118                         info->netdev[i] = NULL;
7119                 }
7120         }
7121 
7122 pcidev_init_mem_err:
7123         ksz_free_mem(hw_priv);
7124         kfree(hw->ksz_switch);
7125 
7126 pcidev_init_alloc_err:
7127         iounmap(hw->io);
7128 
7129 pcidev_init_io_err:
7130         kfree(info);
7131 
7132 pcidev_init_dev_err:
7133         release_mem_region(reg_base, reg_len);
7134 
7135         return result;
7136 }
7137 
7138 static void pcidev_exit(struct pci_dev *pdev)
7139 {
7140         int i;
7141         struct platform_info *info = pci_get_drvdata(pdev);
7142         struct dev_info *hw_priv = &info->dev_info;
7143 
7144         release_mem_region(pci_resource_start(pdev, 0),
7145                 pci_resource_len(pdev, 0));
7146         for (i = 0; i < hw_priv->hw.dev_count; i++) {
7147                 if (info->netdev[i])
7148                         netdev_free(info->netdev[i]);
7149         }
7150         if (hw_priv->hw.io)
7151                 iounmap(hw_priv->hw.io);
7152         ksz_free_mem(hw_priv);
7153         kfree(hw_priv->hw.ksz_switch);
7154         pci_dev_put(hw_priv->pdev);
7155         kfree(info);
7156 }
7157 
7158 #ifdef CONFIG_PM
7159 static int pcidev_resume(struct pci_dev *pdev)
7160 {
7161         int i;
7162         struct platform_info *info = pci_get_drvdata(pdev);
7163         struct dev_info *hw_priv = &info->dev_info;
7164         struct ksz_hw *hw = &hw_priv->hw;
7165 
7166         pci_set_power_state(pdev, PCI_D0);
7167         pci_restore_state(pdev);
7168         pci_enable_wake(pdev, PCI_D0, 0);
7169 
7170         if (hw_priv->wol_enable)
7171                 hw_cfg_wol_pme(hw, 0);
7172         for (i = 0; i < hw->dev_count; i++) {
7173                 if (info->netdev[i]) {
7174                         struct net_device *dev = info->netdev[i];
7175 
7176                         if (netif_running(dev)) {
7177                                 netdev_open(dev);
7178                                 netif_device_attach(dev);
7179                         }
7180                 }
7181         }
7182         return 0;
7183 }
7184 
7185 static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7186 {
7187         int i;
7188         struct platform_info *info = pci_get_drvdata(pdev);
7189         struct dev_info *hw_priv = &info->dev_info;
7190         struct ksz_hw *hw = &hw_priv->hw;
7191 
7192         /* Need to find a way to retrieve the device IP address. */
7193         static const u8 net_addr[] = { 192, 168, 1, 1 };
7194 
7195         for (i = 0; i < hw->dev_count; i++) {
7196                 if (info->netdev[i]) {
7197                         struct net_device *dev = info->netdev[i];
7198 
7199                         if (netif_running(dev)) {
7200                                 netif_device_detach(dev);
7201                                 netdev_close(dev);
7202                         }
7203                 }
7204         }
7205         if (hw_priv->wol_enable) {
7206                 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7207                 hw_cfg_wol_pme(hw, 1);
7208         }
7209 
7210         pci_save_state(pdev);
7211         pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7212         pci_set_power_state(pdev, pci_choose_state(pdev, state));
7213         return 0;
7214 }
7215 #endif
7216 
7217 static char pcidev_name[] = "ksz884xp";
7218 
7219 static const struct pci_device_id pcidev_table[] = {
7220         { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7222         { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7223                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7224         { 0 }
7225 };
7226 
7227 MODULE_DEVICE_TABLE(pci, pcidev_table);
7228 
7229 static struct pci_driver pci_device_driver = {
7230 #ifdef CONFIG_PM
7231         .suspend        = pcidev_suspend,
7232         .resume         = pcidev_resume,
7233 #endif
7234         .name           = pcidev_name,
7235         .id_table       = pcidev_table,
7236         .probe          = pcidev_init,
7237         .remove         = pcidev_exit
7238 };
7239 
7240 module_pci_driver(pci_device_driver);
7241 
7242 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7243 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7244 MODULE_LICENSE("GPL");
7245 
7246 module_param_named(message, msg_enable, int, 0);
7247 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7248 
7249 module_param(macaddr, charp, 0);
7250 module_param(mac1addr, charp, 0);
7251 module_param(fast_aging, int, 0);
7252 module_param(multi_dev, int, 0);
7253 module_param(stp, int, 0);
7254 MODULE_PARM_DESC(macaddr, "MAC address");
7255 MODULE_PARM_DESC(mac1addr, "Second MAC address");
7256 MODULE_PARM_DESC(fast_aging, "Fast aging");
7257 MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7258 MODULE_PARM_DESC(stp, "STP support");

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