This source file includes following definitions.
- hw_atl_reg_glb_cpu_sem_set
- hw_atl_reg_glb_cpu_sem_get
- hw_atl_glb_glb_reg_res_dis_set
- hw_atl_glb_soft_res_set
- hw_atl_glb_soft_res_get
- hw_atl_reg_glb_mif_id_get
- hw_atl_rpb_rx_dma_drop_pkt_cnt_get
- hw_atl_stats_rx_dma_good_octet_counter_get
- hw_atl_stats_rx_dma_good_pkt_counter_get
- hw_atl_stats_tx_dma_good_octet_counter_get
- hw_atl_stats_tx_dma_good_pkt_counter_get
- hw_atl_itr_irq_auto_masklsw_set
- hw_atl_itr_irq_map_en_rx_set
- hw_atl_itr_irq_map_en_tx_set
- hw_atl_itr_irq_map_rx_set
- hw_atl_itr_irq_map_tx_set
- hw_atl_itr_irq_msk_clearlsw_set
- hw_atl_itr_irq_msk_setlsw_set
- hw_atl_itr_irq_reg_res_dis_set
- hw_atl_itr_irq_status_clearlsw_set
- hw_atl_itr_irq_statuslsw_get
- hw_atl_itr_res_irq_get
- hw_atl_itr_res_irq_set
- hw_atl_itr_rsc_en_set
- hw_atl_itr_rsc_delay_set
- hw_atl_rdm_cpu_id_set
- hw_atl_rdm_rx_dca_en_set
- hw_atl_rdm_rx_dca_mode_set
- hw_atl_rdm_rx_desc_data_buff_size_set
- hw_atl_rdm_rx_desc_dca_en_set
- hw_atl_rdm_rx_desc_en_set
- hw_atl_rdm_rx_desc_head_buff_size_set
- hw_atl_rdm_rx_desc_head_splitting_set
- hw_atl_rdm_rx_desc_head_ptr_get
- hw_atl_rdm_rx_desc_len_set
- hw_atl_rdm_rx_desc_res_set
- hw_atl_rdm_rx_desc_wr_wb_irq_en_set
- hw_atl_rdm_rx_head_dca_en_set
- hw_atl_rdm_rx_pld_dca_en_set
- hw_atl_rdm_rdm_intr_moder_en_set
- hw_atl_reg_gen_irq_map_set
- hw_atl_reg_gen_irq_status_get
- hw_atl_reg_irq_glb_ctl_set
- hw_atl_reg_irq_thr_set
- hw_atl_reg_rx_dma_desc_base_addresslswset
- hw_atl_reg_rx_dma_desc_base_addressmswset
- hw_atl_reg_rx_dma_desc_status_get
- hw_atl_reg_rx_dma_desc_tail_ptr_set
- hw_atl_reg_rx_flr_mcst_flr_msk_set
- hw_atl_reg_rx_flr_mcst_flr_set
- hw_atl_reg_rx_flr_rss_control1set
- hw_atl_reg_rx_flr_control2_set
- hw_atl_reg_rx_intr_moder_ctrl_set
- hw_atl_reg_tx_dma_debug_ctl_set
- hw_atl_reg_tx_dma_desc_base_addresslswset
- hw_atl_reg_tx_dma_desc_base_addressmswset
- hw_atl_reg_tx_dma_desc_tail_ptr_set
- hw_atl_reg_tx_intr_moder_ctrl_set
- hw_atl_rpb_dma_sys_lbk_set
- hw_atl_rpb_rpf_rx_traf_class_mode_set
- hw_atl_rpb_rx_buff_en_set
- hw_atl_rpb_rx_buff_hi_threshold_per_tc_set
- hw_atl_rpb_rx_buff_lo_threshold_per_tc_set
- hw_atl_rpb_rx_flow_ctl_mode_set
- hw_atl_rdm_rx_dma_desc_cache_init_tgl
- hw_atl_rdm_rx_dma_desc_cache_init_done_get
- hw_atl_rpb_rx_pkt_buff_size_per_tc_set
- hw_atl_rpb_rx_xoff_en_per_tc_set
- hw_atl_rpfl2broadcast_count_threshold_set
- hw_atl_rpfl2broadcast_en_set
- hw_atl_rpfl2broadcast_flr_act_set
- hw_atl_rpfl2multicast_flr_en_set
- hw_atl_rpfl2promiscuous_mode_en_set
- hw_atl_rpfl2unicast_flr_act_set
- hw_atl_rpfl2_uc_flr_en_set
- hw_atl_rpfl2unicast_dest_addresslsw_set
- hw_atl_rpfl2unicast_dest_addressmsw_set
- hw_atl_rpfl2_accept_all_mc_packets_set
- hw_atl_rpf_rpb_user_priority_tc_map_set
- hw_atl_rpf_rss_key_addr_set
- hw_atl_rpf_rss_key_wr_data_set
- hw_atl_rpf_rss_key_wr_en_get
- hw_atl_rpf_rss_key_wr_en_set
- hw_atl_rpf_rss_redir_tbl_addr_set
- hw_atl_rpf_rss_redir_tbl_wr_data_set
- hw_atl_rpf_rss_redir_wr_en_get
- hw_atl_rpf_rss_redir_wr_en_set
- hw_atl_rpf_tpo_to_rpf_sys_lbk_set
- hw_atl_rpf_vlan_inner_etht_set
- hw_atl_rpf_vlan_outer_etht_set
- hw_atl_rpf_vlan_prom_mode_en_set
- hw_atl_rpf_vlan_accept_untagged_packets_set
- hw_atl_rpf_vlan_untagged_act_set
- hw_atl_rpf_vlan_flr_en_set
- hw_atl_rpf_vlan_flr_act_set
- hw_atl_rpf_vlan_id_flr_set
- hw_atl_rpf_vlan_rxq_en_flr_set
- hw_atl_rpf_vlan_rxq_flr_set
- hw_atl_rpf_etht_flr_en_set
- hw_atl_rpf_etht_user_priority_en_set
- hw_atl_rpf_etht_rx_queue_en_set
- hw_atl_rpf_etht_user_priority_set
- hw_atl_rpf_etht_rx_queue_set
- hw_atl_rpf_etht_mgt_queue_set
- hw_atl_rpf_etht_flr_act_set
- hw_atl_rpf_etht_flr_set
- hw_atl_rpf_l4_spd_set
- hw_atl_rpf_l4_dpd_set
- hw_atl_rpo_ipv4header_crc_offload_en_set
- hw_atl_rpo_rx_desc_vlan_stripping_set
- hw_atl_rpo_outer_vlan_tag_mode_set
- hw_atl_rpo_outer_vlan_tag_mode_get
- hw_atl_rpo_tcp_udp_crc_offload_en_set
- hw_atl_rpo_lro_en_set
- hw_atl_rpo_lro_patch_optimization_en_set
- hw_atl_rpo_lro_qsessions_lim_set
- hw_atl_rpo_lro_total_desc_lim_set
- hw_atl_rpo_lro_min_pay_of_first_pkt_set
- hw_atl_rpo_lro_pkt_lim_set
- hw_atl_rpo_lro_max_num_of_descriptors_set
- hw_atl_rpo_lro_time_base_divider_set
- hw_atl_rpo_lro_inactive_interval_set
- hw_atl_rpo_lro_max_coalescing_interval_set
- hw_atl_rx_rx_reg_res_dis_set
- hw_atl_tdm_cpu_id_set
- hw_atl_tdm_large_send_offload_en_set
- hw_atl_tdm_tx_dca_en_set
- hw_atl_tdm_tx_dca_mode_set
- hw_atl_tdm_tx_desc_dca_en_set
- hw_atl_tdm_tx_desc_en_set
- hw_atl_tdm_tx_desc_head_ptr_get
- hw_atl_tdm_tx_desc_len_set
- hw_atl_tdm_tx_desc_wr_wb_irq_en_set
- hw_atl_tdm_tx_desc_wr_wb_threshold_set
- hw_atl_tdm_tdm_intr_moder_en_set
- hw_atl_thm_lso_tcp_flag_of_first_pkt_set
- hw_atl_thm_lso_tcp_flag_of_last_pkt_set
- hw_atl_thm_lso_tcp_flag_of_middle_pkt_set
- hw_atl_tpb_tx_buff_en_set
- hw_atl_rpb_tps_tx_tc_mode_set
- hw_atl_tpb_tx_buff_hi_threshold_per_tc_set
- hw_atl_tpb_tx_buff_lo_threshold_per_tc_set
- hw_atl_tpb_tx_dma_sys_lbk_en_set
- hw_atl_tpb_tx_pkt_buff_size_per_tc_set
- hw_atl_tpb_tx_path_scp_ins_en_set
- hw_atl_tpo_ipv4header_crc_offload_en_set
- hw_atl_tpo_tcp_udp_crc_offload_en_set
- hw_atl_tpo_tx_pkt_sys_lbk_en_set
- hw_atl_tps_tx_pkt_shed_data_arb_mode_set
- hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set
- hw_atl_tps_tx_pkt_shed_desc_rate_lim_set
- hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set
- hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set
- hw_atl_tps_tx_pkt_shed_desc_tc_weight_set
- hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set
- hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set
- hw_atl_tps_tx_pkt_shed_tc_data_weight_set
- hw_atl_tx_tx_reg_res_dis_set
- hw_atl_msm_reg_access_status_get
- hw_atl_msm_reg_addr_for_indirect_addr_set
- hw_atl_msm_reg_rd_strobe_set
- hw_atl_msm_reg_rd_data_get
- hw_atl_msm_reg_wr_data_set
- hw_atl_msm_reg_wr_strobe_set
- hw_atl_pci_pci_reg_res_dis_set
- hw_atl_reg_glb_cpu_scratch_scp_set
- hw_atl_mcp_up_force_intr_set
- hw_atl_rpfl3l4_ipv4_dest_addr_clear
- hw_atl_rpfl3l4_ipv4_src_addr_clear
- hw_atl_rpfl3l4_cmd_clear
- hw_atl_rpfl3l4_ipv6_dest_addr_clear
- hw_atl_rpfl3l4_ipv6_src_addr_clear
- hw_atl_rpfl3l4_ipv4_dest_addr_set
- hw_atl_rpfl3l4_ipv4_src_addr_set
- hw_atl_rpfl3l4_cmd_set
- hw_atl_rpfl3l4_ipv6_src_addr_set
- hw_atl_rpfl3l4_ipv6_dest_addr_set
- hw_atl_sem_ram_get
- hw_atl_scrpad_get
- hw_atl_scrpad12_get
- hw_atl_scrpad25_get
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11 #include "hw_atl_llh.h"
12 #include "hw_atl_llh_internal.h"
13 #include "../aq_hw_utils.h"
14
15
16 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
17 u32 semaphore)
18 {
19 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
20 }
21
22 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
23 {
24 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
25 }
26
27 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
28 {
29 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
30 HW_ATL_GLB_REG_RES_DIS_MSK,
31 HW_ATL_GLB_REG_RES_DIS_SHIFT,
32 glb_reg_res_dis);
33 }
34
35 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
36 {
37 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
38 HW_ATL_GLB_SOFT_RES_MSK,
39 HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
40 }
41
42 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
43 {
44 return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
45 HW_ATL_GLB_SOFT_RES_MSK,
46 HW_ATL_GLB_SOFT_RES_SHIFT);
47 }
48
49 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
50 {
51 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
52 }
53
54
55 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
56 {
57 return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
58 }
59
60 u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
61 {
62 return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
63 }
64
65 u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
66 {
67 return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
68 }
69
70 u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
71 {
72 return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
73 }
74
75 u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
76 {
77 return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
78 }
79
80
81 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
82 u32 irq_auto_masklsw)
83 {
84 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
85 }
86
87 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
88 u32 rx)
89 {
90
91 static u32 itr_imr_rxren_adr[32] = {
92 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
93 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
94 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
95 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
96 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
97 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
98 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
99 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
100 };
101
102
103 static u32 itr_imr_rxren_msk[32] = {
104 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
105 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
106 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
107 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
108 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
109 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
110 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
111 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
112 };
113
114
115 static u32 itr_imr_rxren_shift[32] = {
116 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
117 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
118 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
119 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
120 };
121
122 aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
123 itr_imr_rxren_msk[rx],
124 itr_imr_rxren_shift[rx],
125 irq_map_en_rx);
126 }
127
128 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
129 u32 tx)
130 {
131
132 static u32 itr_imr_txten_adr[32] = {
133 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
134 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
135 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
136 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
137 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
138 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
139 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
140 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
141 };
142
143
144 static u32 itr_imr_txten_msk[32] = {
145 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
146 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
147 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
148 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
149 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
150 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
151 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
152 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
153 };
154
155
156 static u32 itr_imr_txten_shift[32] = {
157 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
158 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
159 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
160 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
161 };
162
163 aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
164 itr_imr_txten_msk[tx],
165 itr_imr_txten_shift[tx],
166 irq_map_en_tx);
167 }
168
169 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
170 {
171
172 static u32 itr_imr_rxr_adr[32] = {
173 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
174 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
175 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
176 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
177 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
178 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
179 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
180 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
181 };
182
183
184 static u32 itr_imr_rxr_msk[32] = {
185 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
186 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
187 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
188 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
189 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
190 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
191 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
192 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
193 };
194
195
196 static u32 itr_imr_rxr_shift[32] = {
197 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
198 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
199 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
200 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
201 };
202
203 aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
204 itr_imr_rxr_msk[rx],
205 itr_imr_rxr_shift[rx],
206 irq_map_rx);
207 }
208
209 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
210 {
211
212 static u32 itr_imr_txt_adr[32] = {
213 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
214 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
215 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
216 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
217 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
218 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
219 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
220 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
221 };
222
223
224 static u32 itr_imr_txt_msk[32] = {
225 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
226 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
227 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
228 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
229 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
230 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
231 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
232 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
233 };
234
235
236 static u32 itr_imr_txt_shift[32] = {
237 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
238 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
239 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
240 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
241 };
242
243 aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
244 itr_imr_txt_msk[tx],
245 itr_imr_txt_shift[tx],
246 irq_map_tx);
247 }
248
249 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
250 u32 irq_msk_clearlsw)
251 {
252 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
253 }
254
255 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
256 {
257 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
258 }
259
260 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
261 {
262 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
263 HW_ATL_ITR_REG_RES_DSBL_MSK,
264 HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
265 }
266
267 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
268 u32 irq_status_clearlsw)
269 {
270 aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
271 }
272
273 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
274 {
275 return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
276 }
277
278 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
279 {
280 return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
281 HW_ATL_ITR_RES_SHIFT);
282 }
283
284 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
285 {
286 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
287 HW_ATL_ITR_RES_SHIFT, res_irq);
288 }
289
290
291 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable)
292 {
293 aq_hw_write_reg(aq_hw, HW_ATL_ITR_RSC_EN_ADR, enable);
294 }
295
296
297 void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay)
298 {
299 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR,
300 HW_ATL_ITR_RSC_DELAY_MSK,
301 HW_ATL_ITR_RSC_DELAY_SHIFT,
302 delay);
303 }
304
305
306 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
307 {
308 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
309 HW_ATL_RDM_DCADCPUID_MSK,
310 HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
311 }
312
313 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
314 {
315 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
316 HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
317 }
318
319 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
320 {
321 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
322 HW_ATL_RDM_DCA_MODE_MSK,
323 HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
324 }
325
326 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
327 u32 rx_desc_data_buff_size,
328 u32 descriptor)
329 {
330 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
331 HW_ATL_RDM_DESCDDATA_SIZE_MSK,
332 HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
333 rx_desc_data_buff_size);
334 }
335
336 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
337 u32 dca)
338 {
339 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
340 HW_ATL_RDM_DCADDESC_EN_MSK,
341 HW_ATL_RDM_DCADDESC_EN_SHIFT,
342 rx_desc_dca_en);
343 }
344
345 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
346 u32 descriptor)
347 {
348 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
349 HW_ATL_RDM_DESCDEN_MSK,
350 HW_ATL_RDM_DESCDEN_SHIFT,
351 rx_desc_en);
352 }
353
354 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
355 u32 rx_desc_head_buff_size,
356 u32 descriptor)
357 {
358 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
359 HW_ATL_RDM_DESCDHDR_SIZE_MSK,
360 HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
361 rx_desc_head_buff_size);
362 }
363
364 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
365 u32 rx_desc_head_splitting,
366 u32 descriptor)
367 {
368 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
369 HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
370 HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
371 rx_desc_head_splitting);
372 }
373
374 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
375 {
376 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
377 HW_ATL_RDM_DESCDHD_MSK,
378 HW_ATL_RDM_DESCDHD_SHIFT);
379 }
380
381 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
382 u32 descriptor)
383 {
384 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
385 HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
386 rx_desc_len);
387 }
388
389 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
390 u32 descriptor)
391 {
392 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
393 HW_ATL_RDM_DESCDRESET_MSK,
394 HW_ATL_RDM_DESCDRESET_SHIFT,
395 rx_desc_res);
396 }
397
398 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
399 u32 rx_desc_wr_wb_irq_en)
400 {
401 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
402 HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
403 HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
404 rx_desc_wr_wb_irq_en);
405 }
406
407 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
408 u32 dca)
409 {
410 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
411 HW_ATL_RDM_DCADHDR_EN_MSK,
412 HW_ATL_RDM_DCADHDR_EN_SHIFT,
413 rx_head_dca_en);
414 }
415
416 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
417 u32 dca)
418 {
419 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
420 HW_ATL_RDM_DCADPAY_EN_MSK,
421 HW_ATL_RDM_DCADPAY_EN_SHIFT,
422 rx_pld_dca_en);
423 }
424
425 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
426 u32 rdm_intr_moder_en)
427 {
428 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
429 HW_ATL_RDM_INT_RIM_EN_MSK,
430 HW_ATL_RDM_INT_RIM_EN_SHIFT,
431 rdm_intr_moder_en);
432 }
433
434
435 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
436 u32 regidx)
437 {
438 aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
439 }
440
441 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
442 {
443 return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
444 }
445
446 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
447 {
448 aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
449 }
450
451 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
452 {
453 aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
454 }
455
456 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
457 u32 rx_dma_desc_base_addrlsw,
458 u32 descriptor)
459 {
460 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
461 rx_dma_desc_base_addrlsw);
462 }
463
464 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
465 u32 rx_dma_desc_base_addrmsw,
466 u32 descriptor)
467 {
468 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
469 rx_dma_desc_base_addrmsw);
470 }
471
472 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
473 {
474 return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
475 }
476
477 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
478 u32 rx_dma_desc_tail_ptr,
479 u32 descriptor)
480 {
481 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
482 rx_dma_desc_tail_ptr);
483 }
484
485 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
486 u32 rx_flr_mcst_flr_msk)
487 {
488 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
489 rx_flr_mcst_flr_msk);
490 }
491
492 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
493 u32 filter)
494 {
495 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
496 rx_flr_mcst_flr);
497 }
498
499 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
500 u32 rx_flr_rss_control1)
501 {
502 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
503 rx_flr_rss_control1);
504 }
505
506 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
507 u32 rx_filter_control2)
508 {
509 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
510 }
511
512 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
513 u32 rx_intr_moderation_ctl,
514 u32 queue)
515 {
516 aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
517 rx_intr_moderation_ctl);
518 }
519
520 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
521 u32 tx_dma_debug_ctl)
522 {
523 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
524 }
525
526 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
527 u32 tx_dma_desc_base_addrlsw,
528 u32 descriptor)
529 {
530 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
531 tx_dma_desc_base_addrlsw);
532 }
533
534 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
535 u32 tx_dma_desc_base_addrmsw,
536 u32 descriptor)
537 {
538 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
539 tx_dma_desc_base_addrmsw);
540 }
541
542 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
543 u32 tx_dma_desc_tail_ptr,
544 u32 descriptor)
545 {
546 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
547 tx_dma_desc_tail_ptr);
548 }
549
550 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
551 u32 tx_intr_moderation_ctl,
552 u32 queue)
553 {
554 aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
555 tx_intr_moderation_ctl);
556 }
557
558
559 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
560 {
561 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
562 HW_ATL_RPB_DMA_SYS_LBK_MSK,
563 HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
564 }
565
566 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
567 u32 rx_traf_class_mode)
568 {
569 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
570 HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
571 HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
572 rx_traf_class_mode);
573 }
574
575 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
576 {
577 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
578 HW_ATL_RPB_RX_BUF_EN_MSK,
579 HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
580 }
581
582 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
583 u32 rx_buff_hi_threshold_per_tc,
584 u32 buffer)
585 {
586 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
587 HW_ATL_RPB_RXBHI_THRESH_MSK,
588 HW_ATL_RPB_RXBHI_THRESH_SHIFT,
589 rx_buff_hi_threshold_per_tc);
590 }
591
592 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
593 u32 rx_buff_lo_threshold_per_tc,
594 u32 buffer)
595 {
596 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
597 HW_ATL_RPB_RXBLO_THRESH_MSK,
598 HW_ATL_RPB_RXBLO_THRESH_SHIFT,
599 rx_buff_lo_threshold_per_tc);
600 }
601
602 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
603 {
604 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
605 HW_ATL_RPB_RX_FC_MODE_MSK,
606 HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
607 }
608
609 void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
610 {
611 u32 val;
612
613 val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
614 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
615 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
616
617 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
618 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
619 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
620 val ^ 1);
621 }
622
623 u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
624 {
625 return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
626 RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
627 RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
628 }
629
630 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
631 u32 rx_pkt_buff_size_per_tc, u32 buffer)
632 {
633 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
634 HW_ATL_RPB_RXBBUF_SIZE_MSK,
635 HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
636 rx_pkt_buff_size_per_tc);
637 }
638
639 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
640 u32 buffer)
641 {
642 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
643 HW_ATL_RPB_RXBXOFF_EN_MSK,
644 HW_ATL_RPB_RXBXOFF_EN_SHIFT,
645 rx_xoff_en_per_tc);
646 }
647
648
649
650 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
651 u32 l2broadcast_count_threshold)
652 {
653 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
654 HW_ATL_RPFL2BC_THRESH_MSK,
655 HW_ATL_RPFL2BC_THRESH_SHIFT,
656 l2broadcast_count_threshold);
657 }
658
659 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
660 {
661 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
662 HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
663 }
664
665 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
666 u32 l2broadcast_flr_act)
667 {
668 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
669 HW_ATL_RPFL2BC_ACT_MSK,
670 HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
671 }
672
673 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
674 u32 l2multicast_flr_en,
675 u32 filter)
676 {
677 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
678 HW_ATL_RPFL2MC_ENF_MSK,
679 HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
680 }
681
682 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
683 u32 l2promiscuous_mode_en)
684 {
685 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
686 HW_ATL_RPFL2PROMIS_MODE_MSK,
687 HW_ATL_RPFL2PROMIS_MODE_SHIFT,
688 l2promiscuous_mode_en);
689 }
690
691 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
692 u32 l2unicast_flr_act,
693 u32 filter)
694 {
695 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
696 HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
697 l2unicast_flr_act);
698 }
699
700 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
701 u32 filter)
702 {
703 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
704 HW_ATL_RPFL2UC_ENF_MSK,
705 HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
706 }
707
708 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
709 u32 l2unicast_dest_addresslsw,
710 u32 filter)
711 {
712 aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
713 l2unicast_dest_addresslsw);
714 }
715
716 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
717 u32 l2unicast_dest_addressmsw,
718 u32 filter)
719 {
720 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
721 HW_ATL_RPFL2UC_DAFMSW_MSK,
722 HW_ATL_RPFL2UC_DAFMSW_SHIFT,
723 l2unicast_dest_addressmsw);
724 }
725
726 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
727 u32 l2_accept_all_mc_packets)
728 {
729 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
730 HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
731 HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
732 l2_accept_all_mc_packets);
733 }
734
735 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
736 u32 user_priority_tc_map, u32 tc)
737 {
738
739 static u32 rpf_rpb_rx_tc_upt_adr[8] = {
740 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
741 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
742 };
743
744
745 static u32 rpf_rpb_rx_tc_upt_msk[8] = {
746 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
747 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
748 };
749
750
751 static u32 rpf_rpb_rx_tc_upt_shft[8] = {
752 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
753 };
754
755 aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
756 rpf_rpb_rx_tc_upt_msk[tc],
757 rpf_rpb_rx_tc_upt_shft[tc],
758 user_priority_tc_map);
759 }
760
761 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
762 {
763 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
764 HW_ATL_RPF_RSS_KEY_ADDR_MSK,
765 HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
766 rss_key_addr);
767 }
768
769 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
770 {
771 aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
772 rss_key_wr_data);
773 }
774
775 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
776 {
777 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
778 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
779 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
780 }
781
782 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
783 {
784 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
785 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
786 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
787 rss_key_wr_en);
788 }
789
790 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
791 u32 rss_redir_tbl_addr)
792 {
793 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
794 HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
795 HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
796 rss_redir_tbl_addr);
797 }
798
799 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
800 u32 rss_redir_tbl_wr_data)
801 {
802 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
803 HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
804 HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
805 rss_redir_tbl_wr_data);
806 }
807
808 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
809 {
810 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
811 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
812 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
813 }
814
815 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
816 {
817 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
818 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
819 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
820 }
821
822 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
823 u32 tpo_to_rpf_sys_lbk)
824 {
825 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
826 HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
827 HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
828 tpo_to_rpf_sys_lbk);
829 }
830
831 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
832 {
833 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
834 HW_ATL_RPF_VL_INNER_TPID_MSK,
835 HW_ATL_RPF_VL_INNER_TPID_SHIFT,
836 vlan_inner_etht);
837 }
838
839 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
840 {
841 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
842 HW_ATL_RPF_VL_OUTER_TPID_MSK,
843 HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
844 vlan_outer_etht);
845 }
846
847 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
848 u32 vlan_prom_mode_en)
849 {
850 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
851 HW_ATL_RPF_VL_PROMIS_MODE_MSK,
852 HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
853 vlan_prom_mode_en);
854 }
855
856 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
857 u32 vlan_acc_untagged_packets)
858 {
859 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
860 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
861 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
862 vlan_acc_untagged_packets);
863 }
864
865 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
866 u32 vlan_untagged_act)
867 {
868 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
869 HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
870 HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
871 vlan_untagged_act);
872 }
873
874 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
875 u32 filter)
876 {
877 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
878 HW_ATL_RPF_VL_EN_F_MSK,
879 HW_ATL_RPF_VL_EN_F_SHIFT,
880 vlan_flr_en);
881 }
882
883 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
884 u32 filter)
885 {
886 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
887 HW_ATL_RPF_VL_ACT_F_MSK,
888 HW_ATL_RPF_VL_ACT_F_SHIFT,
889 vlan_flr_act);
890 }
891
892 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
893 u32 filter)
894 {
895 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
896 HW_ATL_RPF_VL_ID_F_MSK,
897 HW_ATL_RPF_VL_ID_F_SHIFT,
898 vlan_id_flr);
899 }
900
901 void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
902 u32 filter)
903 {
904 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
905 HW_ATL_RPF_VL_RXQ_EN_F_MSK,
906 HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
907 vlan_rxq_en);
908 }
909
910 void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
911 u32 filter)
912 {
913 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
914 HW_ATL_RPF_VL_RXQ_F_MSK,
915 HW_ATL_RPF_VL_RXQ_F_SHIFT,
916 vlan_rxq);
917 };
918
919 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
920 u32 filter)
921 {
922 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
923 HW_ATL_RPF_ET_ENF_MSK,
924 HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
925 }
926
927 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
928 u32 etht_user_priority_en, u32 filter)
929 {
930 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
931 HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
932 etht_user_priority_en);
933 }
934
935 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
936 u32 etht_rx_queue_en,
937 u32 filter)
938 {
939 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
940 HW_ATL_RPF_ET_RXQFEN_MSK,
941 HW_ATL_RPF_ET_RXQFEN_SHIFT,
942 etht_rx_queue_en);
943 }
944
945 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
946 u32 etht_user_priority,
947 u32 filter)
948 {
949 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
950 HW_ATL_RPF_ET_UPF_MSK,
951 HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
952 }
953
954 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
955 u32 filter)
956 {
957 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
958 HW_ATL_RPF_ET_RXQF_MSK,
959 HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
960 }
961
962 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
963 u32 filter)
964 {
965 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
966 HW_ATL_RPF_ET_MNG_RXQF_MSK,
967 HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
968 etht_mgt_queue);
969 }
970
971 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
972 u32 filter)
973 {
974 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
975 HW_ATL_RPF_ET_ACTF_MSK,
976 HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
977 }
978
979 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
980 {
981 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
982 HW_ATL_RPF_ET_VALF_MSK,
983 HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
984 }
985
986 void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
987 {
988 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
989 HW_ATL_RPF_L4_SPD_MSK,
990 HW_ATL_RPF_L4_SPD_SHIFT, val);
991 }
992
993 void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
994 {
995 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
996 HW_ATL_RPF_L4_DPD_MSK,
997 HW_ATL_RPF_L4_DPD_SHIFT, val);
998 }
999
1000
1001 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1002 u32 ipv4header_crc_offload_en)
1003 {
1004 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
1005 HW_ATL_RPO_IPV4CHK_EN_MSK,
1006 HW_ATL_RPO_IPV4CHK_EN_SHIFT,
1007 ipv4header_crc_offload_en);
1008 }
1009
1010 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
1011 u32 rx_desc_vlan_stripping,
1012 u32 descriptor)
1013 {
1014 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
1015 HW_ATL_RPO_DESCDVL_STRIP_MSK,
1016 HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
1017 rx_desc_vlan_stripping);
1018 }
1019
1020 void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
1021 u32 outervlantagmode)
1022 {
1023 aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1024 HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1025 HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
1026 outervlantagmode);
1027 }
1028
1029 u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
1030 {
1031 return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1032 HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1033 HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
1034 }
1035
1036 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1037 u32 tcp_udp_crc_offload_en)
1038 {
1039 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
1040 HW_ATL_RPOL4CHK_EN_MSK,
1041 HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
1042 }
1043
1044 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
1045 {
1046 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
1047 }
1048
1049 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1050 u32 lro_patch_optimization_en)
1051 {
1052 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1053 HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1054 HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1055 lro_patch_optimization_en);
1056 }
1057
1058 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1059 u32 lro_qsessions_lim)
1060 {
1061 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1062 HW_ATL_RPO_LRO_QSES_LMT_MSK,
1063 HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1064 lro_qsessions_lim);
1065 }
1066
1067 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1068 u32 lro_total_desc_lim)
1069 {
1070 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1071 HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1072 HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1073 lro_total_desc_lim);
1074 }
1075
1076 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1077 u32 lro_min_pld_of_first_pkt)
1078 {
1079 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1080 HW_ATL_RPO_LRO_PKT_MIN_MSK,
1081 HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1082 lro_min_pld_of_first_pkt);
1083 }
1084
1085 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1086 {
1087 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1088 }
1089
1090 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1091 u32 lro_max_number_of_descriptors,
1092 u32 lro)
1093 {
1094
1095 static u32 rpo_lro_ldes_max_adr[32] = {
1096 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1097 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1098 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1099 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1100 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1101 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1102 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1103 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1104 };
1105
1106
1107 static u32 rpo_lro_ldes_max_msk[32] = {
1108 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1109 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1110 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1111 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1112 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1113 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1114 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1115 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1116 };
1117
1118
1119 static u32 rpo_lro_ldes_max_shift[32] = {
1120 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1121 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1122 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1123 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1124 };
1125
1126 aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1127 rpo_lro_ldes_max_msk[lro],
1128 rpo_lro_ldes_max_shift[lro],
1129 lro_max_number_of_descriptors);
1130 }
1131
1132 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1133 u32 lro_time_base_divider)
1134 {
1135 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1136 HW_ATL_RPO_LRO_TB_DIV_MSK,
1137 HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1138 lro_time_base_divider);
1139 }
1140
1141 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1142 u32 lro_inactive_interval)
1143 {
1144 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1145 HW_ATL_RPO_LRO_INA_IVAL_MSK,
1146 HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1147 lro_inactive_interval);
1148 }
1149
1150 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1151 u32 lro_max_coal_interval)
1152 {
1153 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1154 HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1155 HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1156 lro_max_coal_interval);
1157 }
1158
1159
1160 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1161 {
1162 aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1163 HW_ATL_RX_REG_RES_DSBL_MSK,
1164 HW_ATL_RX_REG_RES_DSBL_SHIFT,
1165 rx_reg_res_dis);
1166 }
1167
1168
1169 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1170 {
1171 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1172 HW_ATL_TDM_DCADCPUID_MSK,
1173 HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1174 }
1175
1176 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1177 u32 large_send_offload_en)
1178 {
1179 aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1180 }
1181
1182 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1183 {
1184 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1185 HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1186 }
1187
1188 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1189 {
1190 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1191 HW_ATL_TDM_DCA_MODE_MSK,
1192 HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1193 }
1194
1195 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1196 u32 dca)
1197 {
1198 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1199 HW_ATL_TDM_DCADDESC_EN_MSK,
1200 HW_ATL_TDM_DCADDESC_EN_SHIFT,
1201 tx_desc_dca_en);
1202 }
1203
1204 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1205 u32 descriptor)
1206 {
1207 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1208 HW_ATL_TDM_DESCDEN_MSK,
1209 HW_ATL_TDM_DESCDEN_SHIFT,
1210 tx_desc_en);
1211 }
1212
1213 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1214 {
1215 return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1216 HW_ATL_TDM_DESCDHD_MSK,
1217 HW_ATL_TDM_DESCDHD_SHIFT);
1218 }
1219
1220 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1221 u32 descriptor)
1222 {
1223 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1224 HW_ATL_TDM_DESCDLEN_MSK,
1225 HW_ATL_TDM_DESCDLEN_SHIFT,
1226 tx_desc_len);
1227 }
1228
1229 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1230 u32 tx_desc_wr_wb_irq_en)
1231 {
1232 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1233 HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1234 HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1235 tx_desc_wr_wb_irq_en);
1236 }
1237
1238 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1239 u32 tx_desc_wr_wb_threshold,
1240 u32 descriptor)
1241 {
1242 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1243 HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1244 HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1245 tx_desc_wr_wb_threshold);
1246 }
1247
1248 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1249 u32 tdm_irq_moderation_en)
1250 {
1251 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1252 HW_ATL_TDM_INT_MOD_EN_MSK,
1253 HW_ATL_TDM_INT_MOD_EN_SHIFT,
1254 tdm_irq_moderation_en);
1255 }
1256
1257
1258 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1259 u32 lso_tcp_flag_of_first_pkt)
1260 {
1261 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1262 HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1263 HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1264 lso_tcp_flag_of_first_pkt);
1265 }
1266
1267 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1268 u32 lso_tcp_flag_of_last_pkt)
1269 {
1270 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1271 HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1272 HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1273 lso_tcp_flag_of_last_pkt);
1274 }
1275
1276 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1277 u32 lso_tcp_flag_of_middle_pkt)
1278 {
1279 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1280 HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1281 HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1282 lso_tcp_flag_of_middle_pkt);
1283 }
1284
1285
1286 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1287 {
1288 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1289 HW_ATL_TPB_TX_BUF_EN_MSK,
1290 HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1291 }
1292
1293 void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1294 u32 tx_traf_class_mode)
1295 {
1296 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1297 HW_ATL_TPB_TX_TC_MODE_MSK,
1298 HW_ATL_TPB_TX_TC_MODE_SHIFT,
1299 tx_traf_class_mode);
1300 }
1301
1302 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1303 u32 tx_buff_hi_threshold_per_tc,
1304 u32 buffer)
1305 {
1306 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1307 HW_ATL_TPB_TXBHI_THRESH_MSK,
1308 HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1309 tx_buff_hi_threshold_per_tc);
1310 }
1311
1312 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1313 u32 tx_buff_lo_threshold_per_tc,
1314 u32 buffer)
1315 {
1316 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1317 HW_ATL_TPB_TXBLO_THRESH_MSK,
1318 HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1319 tx_buff_lo_threshold_per_tc);
1320 }
1321
1322 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1323 {
1324 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1325 HW_ATL_TPB_DMA_SYS_LBK_MSK,
1326 HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1327 tx_dma_sys_lbk_en);
1328 }
1329
1330 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1331 u32 tx_pkt_buff_size_per_tc, u32 buffer)
1332 {
1333 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1334 HW_ATL_TPB_TXBBUF_SIZE_MSK,
1335 HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1336 tx_pkt_buff_size_per_tc);
1337 }
1338
1339 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1340 {
1341 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1342 HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1343 HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1344 tx_path_scp_ins_en);
1345 }
1346
1347
1348 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1349 u32 ipv4header_crc_offload_en)
1350 {
1351 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1352 HW_ATL_TPO_IPV4CHK_EN_MSK,
1353 HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1354 ipv4header_crc_offload_en);
1355 }
1356
1357 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1358 u32 tcp_udp_crc_offload_en)
1359 {
1360 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1361 HW_ATL_TPOL4CHK_EN_MSK,
1362 HW_ATL_TPOL4CHK_EN_SHIFT,
1363 tcp_udp_crc_offload_en);
1364 }
1365
1366 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1367 u32 tx_pkt_sys_lbk_en)
1368 {
1369 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1370 HW_ATL_TPO_PKT_SYS_LBK_MSK,
1371 HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1372 tx_pkt_sys_lbk_en);
1373 }
1374
1375
1376 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1377 u32 tx_pkt_shed_data_arb_mode)
1378 {
1379 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1380 HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1381 HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1382 tx_pkt_shed_data_arb_mode);
1383 }
1384
1385 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1386 u32 curr_time_res)
1387 {
1388 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1389 HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1390 HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1391 curr_time_res);
1392 }
1393
1394 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1395 u32 tx_pkt_shed_desc_rate_lim)
1396 {
1397 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1398 HW_ATL_TPS_DESC_RATE_LIM_MSK,
1399 HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1400 tx_pkt_shed_desc_rate_lim);
1401 }
1402
1403 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1404 u32 arb_mode)
1405 {
1406 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1407 HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1408 HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1409 arb_mode);
1410 }
1411
1412 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1413 u32 max_credit,
1414 u32 tc)
1415 {
1416 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1417 HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1418 HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1419 max_credit);
1420 }
1421
1422 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1423 u32 tx_pkt_shed_desc_tc_weight,
1424 u32 tc)
1425 {
1426 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1427 HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1428 HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1429 tx_pkt_shed_desc_tc_weight);
1430 }
1431
1432 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1433 u32 arb_mode)
1434 {
1435 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1436 HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1437 HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1438 arb_mode);
1439 }
1440
1441 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1442 u32 max_credit,
1443 u32 tc)
1444 {
1445 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1446 HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1447 HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1448 max_credit);
1449 }
1450
1451 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1452 u32 tx_pkt_shed_tc_data_weight,
1453 u32 tc)
1454 {
1455 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1456 HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1457 HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1458 tx_pkt_shed_tc_data_weight);
1459 }
1460
1461
1462 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1463 {
1464 aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1465 HW_ATL_TX_REG_RES_DSBL_MSK,
1466 HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1467 }
1468
1469
1470 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1471 {
1472 return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1473 HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1474 HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1475 }
1476
1477 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1478 u32 reg_addr_for_indirect_addr)
1479 {
1480 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1481 HW_ATL_MSM_REG_ADDR_MSK,
1482 HW_ATL_MSM_REG_ADDR_SHIFT,
1483 reg_addr_for_indirect_addr);
1484 }
1485
1486 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1487 {
1488 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1489 HW_ATL_MSM_REG_RD_STROBE_MSK,
1490 HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1491 reg_rd_strobe);
1492 }
1493
1494 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1495 {
1496 return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1497 }
1498
1499 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1500 {
1501 aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1502 }
1503
1504 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1505 {
1506 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1507 HW_ATL_MSM_REG_WR_STROBE_MSK,
1508 HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1509 reg_wr_strobe);
1510 }
1511
1512
1513 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1514 {
1515 aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1516 HW_ATL_PCI_REG_RES_DSBL_MSK,
1517 HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1518 pci_reg_res_dis);
1519 }
1520
1521 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1522 u32 glb_cpu_scratch_scp,
1523 u32 scratch_scp)
1524 {
1525 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1526 glb_cpu_scratch_scp);
1527 }
1528
1529 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1530 {
1531 aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1532 HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1533 HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1534 up_force_intr);
1535 }
1536
1537 void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1538 {
1539 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1540 }
1541
1542 void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1543 {
1544 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1545 }
1546
1547 void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1548 {
1549 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1550 }
1551
1552 void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1553 {
1554 int i;
1555
1556 for (i = 0; i < 4; ++i)
1557 aq_hw_write_reg(aq_hw,
1558 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1559 0U);
1560 }
1561
1562 void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1563 {
1564 int i;
1565
1566 for (i = 0; i < 4; ++i)
1567 aq_hw_write_reg(aq_hw,
1568 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1569 0U);
1570 }
1571
1572 void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1573 u32 ipv4_dest)
1574 {
1575 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1576 ipv4_dest);
1577 }
1578
1579 void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1580 u32 ipv4_src)
1581 {
1582 aq_hw_write_reg(aq_hw,
1583 HW_ATL_RPF_L3_SRCA_ADR(location),
1584 ipv4_src);
1585 }
1586
1587 void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1588 {
1589 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1590 }
1591
1592 void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1593 u32 *ipv6_src)
1594 {
1595 int i;
1596
1597 for (i = 0; i < 4; ++i)
1598 aq_hw_write_reg(aq_hw,
1599 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1600 ipv6_src[i]);
1601 }
1602
1603 void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1604 u32 *ipv6_dest)
1605 {
1606 int i;
1607
1608 for (i = 0; i < 4; ++i)
1609 aq_hw_write_reg(aq_hw,
1610 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1611 ipv6_dest[i]);
1612 }
1613
1614 u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
1615 {
1616 return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
1617 }
1618
1619 u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
1620 {
1621 return aq_hw_read_reg(aq_hw,
1622 HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
1623 }
1624
1625 u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
1626 {
1627 return hw_atl_scrpad_get(self, 0xB);
1628 }
1629
1630 u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
1631 {
1632 return hw_atl_scrpad_get(self, 0x18);
1633 }