This source file includes following definitions.
- aq_fw2x_init
- aq_fw2x_deinit
- link_speed_mask_2fw2x_ratemask
- fw2x_to_eee_mask
- eee_mask_to_fw2x
- aq_fw2x_set_link_speed
- aq_fw2x_set_mpi_flow_control
- aq_fw2x_upd_eee_rate_bits
- aq_fw2x_set_state
- aq_fw2x_update_link_status
- aq_fw2x_get_mac_permanent
- aq_fw2x_update_stats
- aq_fw2x_get_phy_temp
- aq_fw2x_set_sleep_proxy
- aq_fw2x_set_wol_params
- aq_fw2x_set_power
- aq_fw2x_set_eee_rate
- aq_fw2x_get_eee_rate
- aq_fw2x_renegotiate
- aq_fw2x_set_flow_control
- aq_fw2x_get_flow_control
- aq_fw2x_mbox_get
- aq_fw2x_rpc_get
- aq_fw2x_state2_get
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11 #include "../aq_hw.h"
12 #include "../aq_hw_utils.h"
13 #include "../aq_pci_func.h"
14 #include "../aq_ring.h"
15 #include "../aq_vec.h"
16 #include "../aq_nic.h"
17 #include "hw_atl_utils.h"
18 #include "hw_atl_llh.h"
19
20 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
21
22 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
23 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
24 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
25 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
26 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
27 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
28
29 #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE)
30 #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE)
31 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
32 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
33
34 #define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY)
35 #define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL)
36 #define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP)
37 #define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)
38 #define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE)
39 #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
40 #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)
41
42 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
43 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
44 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
45 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
46
47 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
48 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
49
50 struct __packed fw2x_msg_wol_pattern {
51 u8 mask[16];
52 u32 crc;
53 };
54
55 struct __packed fw2x_msg_wol {
56 u32 msg_id;
57 u8 hw_addr[ETH_ALEN];
58 u8 magic_packet_enabled;
59 u8 filter_count;
60 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
61 u8 link_up_enabled;
62 u8 link_down_enabled;
63 u16 reserved;
64 u32 link_up_timeout;
65 u32 link_down_timeout;
66 };
67
68 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
69 static int aq_fw2x_set_state(struct aq_hw_s *self,
70 enum hal_atl_utils_fw_state_e state);
71
72 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
73 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
74 static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
75
76 static int aq_fw2x_init(struct aq_hw_s *self)
77 {
78 int err = 0;
79
80
81 err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
82 self, self->mbox_addr,
83 self->mbox_addr != 0U,
84 1000U, 10000U);
85
86 err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
87 self, self->rpc_addr,
88 self->rpc_addr != 0U,
89 1000U, 100000U);
90
91 return err;
92 }
93
94 static int aq_fw2x_deinit(struct aq_hw_s *self)
95 {
96 int err = aq_fw2x_set_link_speed(self, 0);
97
98 if (!err)
99 err = aq_fw2x_set_state(self, MPI_DEINIT);
100
101 return err;
102 }
103
104 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
105 {
106 enum hw_atl_fw2x_rate rate = 0;
107
108 if (speed & AQ_NIC_RATE_10G)
109 rate |= FW2X_RATE_10G;
110
111 if (speed & AQ_NIC_RATE_5G)
112 rate |= FW2X_RATE_5G;
113
114 if (speed & AQ_NIC_RATE_5GSR)
115 rate |= FW2X_RATE_5G;
116
117 if (speed & AQ_NIC_RATE_2GS)
118 rate |= FW2X_RATE_2G5;
119
120 if (speed & AQ_NIC_RATE_1G)
121 rate |= FW2X_RATE_1G;
122
123 if (speed & AQ_NIC_RATE_100M)
124 rate |= FW2X_RATE_100M;
125
126 return rate;
127 }
128
129 static u32 fw2x_to_eee_mask(u32 speed)
130 {
131 u32 rate = 0;
132
133 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
134 rate |= AQ_NIC_RATE_EEE_10G;
135 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
136 rate |= AQ_NIC_RATE_EEE_5G;
137 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
138 rate |= AQ_NIC_RATE_EEE_2GS;
139 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
140 rate |= AQ_NIC_RATE_EEE_1G;
141
142 return rate;
143 }
144
145 static u32 eee_mask_to_fw2x(u32 speed)
146 {
147 u32 rate = 0;
148
149 if (speed & AQ_NIC_RATE_EEE_10G)
150 rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
151 if (speed & AQ_NIC_RATE_EEE_5G)
152 rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
153 if (speed & AQ_NIC_RATE_EEE_2GS)
154 rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
155 if (speed & AQ_NIC_RATE_EEE_1G)
156 rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
157
158 return rate;
159 }
160
161 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
162 {
163 u32 val = link_speed_mask_2fw2x_ratemask(speed);
164
165 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
166
167 return 0;
168 }
169
170 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
171 {
172 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
173 *mpi_state |= BIT(CAPS_HI_PAUSE);
174 else
175 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
176
177 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
178 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
179 else
180 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
181 }
182
183 static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,
184 u32 eee_speeds)
185 {
186 *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
187 HW_ATL_FW2X_CAP_EEE_2G5_MASK |
188 HW_ATL_FW2X_CAP_EEE_5G_MASK |
189 HW_ATL_FW2X_CAP_EEE_10G_MASK);
190
191 *mpi_opts |= eee_mask_to_fw2x(eee_speeds);
192 }
193
194 static int aq_fw2x_set_state(struct aq_hw_s *self,
195 enum hal_atl_utils_fw_state_e state)
196 {
197 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
198 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
199
200 switch (state) {
201 case MPI_INIT:
202 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
203 aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);
204 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
205 break;
206 case MPI_DEINIT:
207 mpi_state |= BIT(CAPS_HI_LINK_DROP);
208 break;
209 case MPI_RESET:
210 case MPI_POWER:
211
212 break;
213 }
214 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
215 return 0;
216 }
217
218 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
219 {
220 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
221 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
222 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
223 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
224
225 if (speed) {
226 if (speed & FW2X_RATE_10G)
227 link_status->mbps = 10000;
228 else if (speed & FW2X_RATE_5G)
229 link_status->mbps = 5000;
230 else if (speed & FW2X_RATE_2G5)
231 link_status->mbps = 2500;
232 else if (speed & FW2X_RATE_1G)
233 link_status->mbps = 1000;
234 else if (speed & FW2X_RATE_100M)
235 link_status->mbps = 100;
236 else
237 link_status->mbps = 10000;
238 } else {
239 link_status->mbps = 0;
240 }
241
242 return 0;
243 }
244
245 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
246 {
247 int err = 0;
248 u32 h = 0U;
249 u32 l = 0U;
250 u32 mac_addr[2] = { 0 };
251 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
252
253 if (efuse_addr != 0) {
254 err = hw_atl_utils_fw_downld_dwords(self,
255 efuse_addr + (40U * 4U),
256 mac_addr,
257 ARRAY_SIZE(mac_addr));
258 if (err)
259 return err;
260 mac_addr[0] = __swab32(mac_addr[0]);
261 mac_addr[1] = __swab32(mac_addr[1]);
262 }
263
264 ether_addr_copy(mac, (u8 *)mac_addr);
265
266 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
267 unsigned int rnd = 0;
268
269 get_random_bytes(&rnd, sizeof(unsigned int));
270
271 l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16);
272 h = 0x8001300EU;
273
274 mac[5] = (u8)(0xFFU & l);
275 l >>= 8;
276 mac[4] = (u8)(0xFFU & l);
277 l >>= 8;
278 mac[3] = (u8)(0xFFU & l);
279 l >>= 8;
280 mac[2] = (u8)(0xFFU & l);
281 mac[1] = (u8)(0xFFU & h);
282 h >>= 8;
283 mac[0] = (u8)(0xFFU & h);
284 }
285 return err;
286 }
287
288 static int aq_fw2x_update_stats(struct aq_hw_s *self)
289 {
290 int err = 0;
291 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
292 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
293 u32 stats_val;
294
295
296 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
297 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
298
299
300 err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
301 self, stats_val,
302 orig_stats_val != (stats_val &
303 BIT(CAPS_HI_STATISTICS)),
304 1U, 10000U);
305 if (err)
306 return err;
307
308 return hw_atl_utils_update_stats(self);
309 }
310
311 static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
312 {
313 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
314 u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;
315 u32 phy_temp_offset;
316 u32 temp_res;
317 int err = 0;
318 u32 val;
319
320 phy_temp_offset = self->mbox_addr +
321 offsetof(struct hw_atl_utils_mbox, info) +
322 offsetof(struct hw_aq_info, phy_temperature);
323
324 mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;
325 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
326
327 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
328 temp_val !=
329 (val & HW_ATL_FW2X_CTRL_TEMPERATURE),
330 1U, 10000U);
331 err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,
332 &temp_res, 1);
333
334 if (err)
335 return err;
336
337
338
339
340 *temp = (temp_res & 0xFFFF) * 1000 / 256;
341
342 return 0;
343 }
344
345 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
346 {
347 struct hw_atl_utils_fw_rpc *rpc = NULL;
348 struct offload_info *cfg = NULL;
349 unsigned int rpc_size = 0U;
350 u32 mpi_opts;
351 int err = 0;
352 u32 val;
353
354 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
355
356 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
357 if (err < 0)
358 goto err_exit;
359
360 memset(rpc, 0, rpc_size);
361 cfg = (struct offload_info *)(&rpc->msg_id + 1);
362
363 memcpy(cfg->mac_addr, mac, ETH_ALEN);
364 cfg->len = sizeof(*cfg);
365
366
367 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
368 mpi_opts &= ~HW_ATL_FW2X_CTRL_SLEEP_PROXY;
369 mpi_opts &= ~HW_ATL_FW2X_CTRL_LINK_DROP;
370
371 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
372
373 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
374 if (err < 0)
375 goto err_exit;
376
377
378 mpi_opts |= HW_ATL_FW2X_CTRL_SLEEP_PROXY;
379 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
380
381 err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
382 self, val,
383 val & HW_ATL_FW2X_CTRL_SLEEP_PROXY,
384 1U, 100000U);
385
386 err_exit:
387 return err;
388 }
389
390 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
391 {
392 struct hw_atl_utils_fw_rpc *rpc = NULL;
393 struct fw2x_msg_wol *msg = NULL;
394 u32 mpi_opts;
395 int err = 0;
396 u32 val;
397
398 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
399 if (err < 0)
400 goto err_exit;
401
402 msg = (struct fw2x_msg_wol *)rpc;
403
404 memset(msg, 0, sizeof(*msg));
405
406 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
407 msg->magic_packet_enabled = true;
408 memcpy(msg->hw_addr, mac, ETH_ALEN);
409
410 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
411 mpi_opts &= ~(HW_ATL_FW2X_CTRL_SLEEP_PROXY | HW_ATL_FW2X_CTRL_WOL);
412
413 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
414
415 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
416 if (err < 0)
417 goto err_exit;
418
419
420 mpi_opts |= HW_ATL_FW2X_CTRL_WOL;
421 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
422
423 err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
424 self, val, val & HW_ATL_FW2X_CTRL_WOL,
425 1U, 10000U);
426
427 err_exit:
428 return err;
429 }
430
431 static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,
432 u8 *mac)
433 {
434 int err = 0;
435
436 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
437 err = aq_fw2x_set_sleep_proxy(self, mac);
438 if (err < 0)
439 goto err_exit;
440 err = aq_fw2x_set_wol_params(self, mac);
441 }
442
443 err_exit:
444 return err;
445 }
446
447 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
448 {
449 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
450
451 aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);
452
453 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
454
455 return 0;
456 }
457
458 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
459 u32 *supported_rates)
460 {
461 u32 mpi_state;
462 u32 caps_hi;
463 int err = 0;
464 u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) +
465 offsetof(struct hw_aq_info, caps_hi);
466
467 err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi,
468 sizeof(caps_hi) / sizeof(u32));
469
470 if (err)
471 return err;
472
473 *supported_rates = fw2x_to_eee_mask(caps_hi);
474
475 mpi_state = aq_fw2x_state2_get(self);
476 *rate = fw2x_to_eee_mask(mpi_state);
477
478 return err;
479 }
480
481 static int aq_fw2x_renegotiate(struct aq_hw_s *self)
482 {
483 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
484
485 mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
486
487 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
488
489 return 0;
490 }
491
492 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
493 {
494 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
495
496 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
497
498 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
499
500 return 0;
501 }
502
503 static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
504 {
505 u32 mpi_state = aq_fw2x_state2_get(self);
506
507 if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)
508 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
509 *fcmode = AQ_NIC_FC_RX;
510 else
511 *fcmode = AQ_NIC_FC_RX | AQ_NIC_FC_TX;
512 else
513 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
514 *fcmode = AQ_NIC_FC_TX;
515 else
516 *fcmode = 0;
517
518 return 0;
519 }
520
521 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
522 {
523 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
524 }
525
526 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
527 {
528 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
529 }
530
531 static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
532 {
533 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
534 }
535
536 const struct aq_fw_ops aq_fw_2x_ops = {
537 .init = aq_fw2x_init,
538 .deinit = aq_fw2x_deinit,
539 .reset = NULL,
540 .renegotiate = aq_fw2x_renegotiate,
541 .get_mac_permanent = aq_fw2x_get_mac_permanent,
542 .set_link_speed = aq_fw2x_set_link_speed,
543 .set_state = aq_fw2x_set_state,
544 .update_link_status = aq_fw2x_update_link_status,
545 .update_stats = aq_fw2x_update_stats,
546 .get_phy_temp = aq_fw2x_get_phy_temp,
547 .set_power = aq_fw2x_set_power,
548 .set_eee_rate = aq_fw2x_set_eee_rate,
549 .get_eee_rate = aq_fw2x_get_eee_rate,
550 .set_flow_control = aq_fw2x_set_flow_control,
551 .get_flow_control = aq_fw2x_get_flow_control
552 };