This source file includes following definitions.
- dwmac_dma_reset
- dwmac_enable_dma_transmission
- dwmac_enable_dma_irq
- dwmac_disable_dma_irq
- dwmac_dma_start_tx
- dwmac_dma_stop_tx
- dwmac_dma_start_rx
- dwmac_dma_stop_rx
- show_tx_process_state
- show_rx_process_state
- dwmac_dma_interrupt
- dwmac_dma_flush_tx_fifo
- stmmac_set_mac_addr
- stmmac_set_mac
- stmmac_get_mac_addr
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8
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include "common.h"
12 #include "dwmac_dma.h"
13
14 #define GMAC_HI_REG_AE 0x80000000
15
16 int dwmac_dma_reset(void __iomem *ioaddr)
17 {
18 u32 value = readl(ioaddr + DMA_BUS_MODE);
19 int err;
20
21
22 value |= DMA_BUS_MODE_SFT_RESET;
23 writel(value, ioaddr + DMA_BUS_MODE);
24
25 err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
26 !(value & DMA_BUS_MODE_SFT_RESET),
27 10000, 100000);
28 if (err)
29 return -EBUSY;
30
31 return 0;
32 }
33
34
35 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
36 {
37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
38 }
39
40 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
41 {
42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
43 }
44
45 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
46 {
47 writel(0, ioaddr + DMA_INTR_ENA);
48 }
49
50 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
51 {
52 u32 value = readl(ioaddr + DMA_CONTROL);
53 value |= DMA_CONTROL_ST;
54 writel(value, ioaddr + DMA_CONTROL);
55 }
56
57 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
58 {
59 u32 value = readl(ioaddr + DMA_CONTROL);
60 value &= ~DMA_CONTROL_ST;
61 writel(value, ioaddr + DMA_CONTROL);
62 }
63
64 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
65 {
66 u32 value = readl(ioaddr + DMA_CONTROL);
67 value |= DMA_CONTROL_SR;
68 writel(value, ioaddr + DMA_CONTROL);
69 }
70
71 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
72 {
73 u32 value = readl(ioaddr + DMA_CONTROL);
74 value &= ~DMA_CONTROL_SR;
75 writel(value, ioaddr + DMA_CONTROL);
76 }
77
78 #ifdef DWMAC_DMA_DEBUG
79 static void show_tx_process_state(unsigned int status)
80 {
81 unsigned int state;
82 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
83
84 switch (state) {
85 case 0:
86 pr_debug("- TX (Stopped): Reset or Stop command\n");
87 break;
88 case 1:
89 pr_debug("- TX (Running): Fetching the Tx desc\n");
90 break;
91 case 2:
92 pr_debug("- TX (Running): Waiting for end of tx\n");
93 break;
94 case 3:
95 pr_debug("- TX (Running): Reading the data "
96 "and queuing the data into the Tx buf\n");
97 break;
98 case 6:
99 pr_debug("- TX (Suspended): Tx Buff Underflow "
100 "or an unavailable Transmit descriptor\n");
101 break;
102 case 7:
103 pr_debug("- TX (Running): Closing Tx descriptor\n");
104 break;
105 default:
106 break;
107 }
108 }
109
110 static void show_rx_process_state(unsigned int status)
111 {
112 unsigned int state;
113 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
114
115 switch (state) {
116 case 0:
117 pr_debug("- RX (Stopped): Reset or Stop command\n");
118 break;
119 case 1:
120 pr_debug("- RX (Running): Fetching the Rx desc\n");
121 break;
122 case 2:
123 pr_debug("- RX (Running): Checking for end of pkt\n");
124 break;
125 case 3:
126 pr_debug("- RX (Running): Waiting for Rx pkt\n");
127 break;
128 case 4:
129 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
130 break;
131 case 5:
132 pr_debug("- RX (Running): Closing Rx descriptor\n");
133 break;
134 case 6:
135 pr_debug("- RX(Running): Flushing the current frame"
136 " from the Rx buf\n");
137 break;
138 case 7:
139 pr_debug("- RX (Running): Queuing the Rx frame"
140 " from the Rx buf into memory\n");
141 break;
142 default:
143 break;
144 }
145 }
146 #endif
147
148 int dwmac_dma_interrupt(void __iomem *ioaddr,
149 struct stmmac_extra_stats *x, u32 chan)
150 {
151 int ret = 0;
152
153 u32 intr_status = readl(ioaddr + DMA_STATUS);
154
155 #ifdef DWMAC_DMA_DEBUG
156
157 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
158 show_tx_process_state(intr_status);
159 show_rx_process_state(intr_status);
160 #endif
161
162 if (unlikely(intr_status & DMA_STATUS_AIS)) {
163 if (unlikely(intr_status & DMA_STATUS_UNF)) {
164 ret = tx_hard_error_bump_tc;
165 x->tx_undeflow_irq++;
166 }
167 if (unlikely(intr_status & DMA_STATUS_TJT))
168 x->tx_jabber_irq++;
169
170 if (unlikely(intr_status & DMA_STATUS_OVF))
171 x->rx_overflow_irq++;
172
173 if (unlikely(intr_status & DMA_STATUS_RU))
174 x->rx_buf_unav_irq++;
175 if (unlikely(intr_status & DMA_STATUS_RPS))
176 x->rx_process_stopped_irq++;
177 if (unlikely(intr_status & DMA_STATUS_RWT))
178 x->rx_watchdog_irq++;
179 if (unlikely(intr_status & DMA_STATUS_ETI))
180 x->tx_early_irq++;
181 if (unlikely(intr_status & DMA_STATUS_TPS)) {
182 x->tx_process_stopped_irq++;
183 ret = tx_hard_error;
184 }
185 if (unlikely(intr_status & DMA_STATUS_FBI)) {
186 x->fatal_bus_error_irq++;
187 ret = tx_hard_error;
188 }
189 }
190
191 if (likely(intr_status & DMA_STATUS_NIS)) {
192 x->normal_irq_n++;
193 if (likely(intr_status & DMA_STATUS_RI)) {
194 u32 value = readl(ioaddr + DMA_INTR_ENA);
195
196 if (likely(value & DMA_INTR_ENA_RIE)) {
197 x->rx_normal_irq_n++;
198 ret |= handle_rx;
199 }
200 }
201 if (likely(intr_status & DMA_STATUS_TI)) {
202 x->tx_normal_irq_n++;
203 ret |= handle_tx;
204 }
205 if (unlikely(intr_status & DMA_STATUS_ERI))
206 x->rx_early_irq++;
207 }
208
209 if (unlikely(intr_status &
210 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
211 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
212
213
214 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
215
216 return ret;
217 }
218
219 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
220 {
221 u32 csr6 = readl(ioaddr + DMA_CONTROL);
222 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
223
224 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
225 }
226
227 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
228 unsigned int high, unsigned int low)
229 {
230 unsigned long data;
231
232 data = (addr[5] << 8) | addr[4];
233
234
235
236
237 writel(data | GMAC_HI_REG_AE, ioaddr + high);
238 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
239 writel(data, ioaddr + low);
240 }
241 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
242
243
244 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
245 {
246 u32 value = readl(ioaddr + MAC_CTRL_REG);
247
248 if (enable)
249 value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
250 else
251 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
252
253 writel(value, ioaddr + MAC_CTRL_REG);
254 }
255
256 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
257 unsigned int high, unsigned int low)
258 {
259 unsigned int hi_addr, lo_addr;
260
261
262 hi_addr = readl(ioaddr + high);
263 lo_addr = readl(ioaddr + low);
264
265
266 addr[0] = lo_addr & 0xff;
267 addr[1] = (lo_addr >> 8) & 0xff;
268 addr[2] = (lo_addr >> 16) & 0xff;
269 addr[3] = (lo_addr >> 24) & 0xff;
270 addr[4] = hi_addr & 0xff;
271 addr[5] = (hi_addr >> 8) & 0xff;
272 }
273 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);