This source file includes following definitions.
- meson8b_dwmac_mask_bits
- meson8b_dwmac_register_clk
- meson8b_init_rgmii_tx_clk
- meson8b_set_phy_mode
- meson_axg_set_phy_mode
- meson8b_init_prg_eth
- meson8b_dwmac_probe
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8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/device.h>
11 #include <linux/ethtool.h>
12 #include <linux/io.h>
13 #include <linux/ioport.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/of_net.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/platform_device.h>
19 #include <linux/stmmac.h>
20
21 #include "stmmac_platform.h"
22
23 #define PRG_ETH0 0x0
24
25 #define PRG_ETH0_RGMII_MODE BIT(0)
26
27 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
28 #define PRG_ETH0_EXT_RGMII_MODE 1
29 #define PRG_ETH0_EXT_RMII_MODE 4
30
31
32 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
34
35 #define PRG_ETH0_TXDLY_SHIFT 5
36 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
37
38
39 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7
40 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
41
42 #define PRG_ETH0_RGMII_TX_CLK_EN 10
43
44 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
45 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
46
47 #define MUX_CLK_NUM_PARENTS 2
48
49 struct meson8b_dwmac;
50
51 struct meson8b_dwmac_data {
52 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
53 };
54
55 struct meson8b_dwmac {
56 struct device *dev;
57 void __iomem *regs;
58
59 const struct meson8b_dwmac_data *data;
60 phy_interface_t phy_mode;
61 struct clk *rgmii_tx_clk;
62 u32 tx_delay_ns;
63 };
64
65 struct meson8b_dwmac_clk_configs {
66 struct clk_mux m250_mux;
67 struct clk_divider m250_div;
68 struct clk_fixed_factor fixed_div2;
69 struct clk_gate rgmii_tx_en;
70 };
71
72 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
73 u32 mask, u32 value)
74 {
75 u32 data;
76
77 data = readl(dwmac->regs + reg);
78 data &= ~mask;
79 data |= (value & mask);
80
81 writel(data, dwmac->regs + reg);
82 }
83
84 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
85 const char *name_suffix,
86 const char **parent_names,
87 int num_parents,
88 const struct clk_ops *ops,
89 struct clk_hw *hw)
90 {
91 struct clk_init_data init;
92 char clk_name[32];
93
94 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
95 name_suffix);
96
97 init.name = clk_name;
98 init.ops = ops;
99 init.flags = CLK_SET_RATE_PARENT;
100 init.parent_names = parent_names;
101 init.num_parents = num_parents;
102
103 hw->init = &init;
104
105 return devm_clk_register(dwmac->dev, hw);
106 }
107
108 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
109 {
110 int i, ret;
111 struct clk *clk;
112 struct device *dev = dwmac->dev;
113 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS];
114 struct meson8b_dwmac_clk_configs *clk_configs;
115 static const struct clk_div_table div_table[] = {
116 { .div = 2, .val = 2, },
117 { .div = 3, .val = 3, },
118 { .div = 4, .val = 4, },
119 { .div = 5, .val = 5, },
120 { .div = 6, .val = 6, },
121 { .div = 7, .val = 7, },
122 { }
123 };
124
125 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
126 if (!clk_configs)
127 return -ENOMEM;
128
129
130 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
131 char name[16];
132
133 snprintf(name, sizeof(name), "clkin%d", i);
134 clk = devm_clk_get(dev, name);
135 if (IS_ERR(clk)) {
136 ret = PTR_ERR(clk);
137 if (ret != -EPROBE_DEFER)
138 dev_err(dev, "Missing clock %s\n", name);
139 return ret;
140 }
141
142 mux_parent_names[i] = __clk_get_name(clk);
143 }
144
145 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
146 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
147 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
148 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names,
149 MUX_CLK_NUM_PARENTS, &clk_mux_ops,
150 &clk_configs->m250_mux.hw);
151 if (WARN_ON(IS_ERR(clk)))
152 return PTR_ERR(clk);
153
154 parent_name = __clk_get_name(clk);
155 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
156 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
157 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
158 clk_configs->m250_div.table = div_table;
159 clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO |
160 CLK_DIVIDER_ROUND_CLOSEST;
161 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1,
162 &clk_divider_ops,
163 &clk_configs->m250_div.hw);
164 if (WARN_ON(IS_ERR(clk)))
165 return PTR_ERR(clk);
166
167 parent_name = __clk_get_name(clk);
168 clk_configs->fixed_div2.mult = 1;
169 clk_configs->fixed_div2.div = 2;
170 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1,
171 &clk_fixed_factor_ops,
172 &clk_configs->fixed_div2.hw);
173 if (WARN_ON(IS_ERR(clk)))
174 return PTR_ERR(clk);
175
176 parent_name = __clk_get_name(clk);
177 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
178 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
179 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1,
180 &clk_gate_ops,
181 &clk_configs->rgmii_tx_en.hw);
182 if (WARN_ON(IS_ERR(clk)))
183 return PTR_ERR(clk);
184
185 dwmac->rgmii_tx_clk = clk;
186
187 return 0;
188 }
189
190 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
191 {
192 switch (dwmac->phy_mode) {
193 case PHY_INTERFACE_MODE_RGMII:
194 case PHY_INTERFACE_MODE_RGMII_RXID:
195 case PHY_INTERFACE_MODE_RGMII_ID:
196 case PHY_INTERFACE_MODE_RGMII_TXID:
197
198 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
199 PRG_ETH0_RGMII_MODE,
200 PRG_ETH0_RGMII_MODE);
201 break;
202 case PHY_INTERFACE_MODE_RMII:
203
204 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
205 PRG_ETH0_RGMII_MODE, 0);
206 break;
207 default:
208 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
209 phy_modes(dwmac->phy_mode));
210 return -EINVAL;
211 }
212
213 return 0;
214 }
215
216 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
217 {
218 switch (dwmac->phy_mode) {
219 case PHY_INTERFACE_MODE_RGMII:
220 case PHY_INTERFACE_MODE_RGMII_RXID:
221 case PHY_INTERFACE_MODE_RGMII_ID:
222 case PHY_INTERFACE_MODE_RGMII_TXID:
223
224 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
225 PRG_ETH0_EXT_PHY_MODE_MASK,
226 PRG_ETH0_EXT_RGMII_MODE);
227 break;
228 case PHY_INTERFACE_MODE_RMII:
229
230 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
231 PRG_ETH0_EXT_PHY_MODE_MASK,
232 PRG_ETH0_EXT_RMII_MODE);
233 break;
234 default:
235 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
236 phy_modes(dwmac->phy_mode));
237 return -EINVAL;
238 }
239
240 return 0;
241 }
242
243 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
244 {
245 int ret;
246 u8 tx_dly_val = 0;
247
248 switch (dwmac->phy_mode) {
249 case PHY_INTERFACE_MODE_RGMII:
250 case PHY_INTERFACE_MODE_RGMII_RXID:
251
252
253
254
255 tx_dly_val = dwmac->tx_delay_ns >> 1;
256
257
258 case PHY_INTERFACE_MODE_RGMII_ID:
259 case PHY_INTERFACE_MODE_RGMII_TXID:
260
261 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
262 PRG_ETH0_INVERTED_RMII_CLK, 0);
263
264 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
265 tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
266
267
268
269
270
271
272 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
273 if (ret) {
274 dev_err(dwmac->dev,
275 "failed to set RGMII TX clock\n");
276 return ret;
277 }
278
279 ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
280 if (ret) {
281 dev_err(dwmac->dev,
282 "failed to enable the RGMII TX clock\n");
283 return ret;
284 }
285
286 devm_add_action_or_reset(dwmac->dev,
287 (void(*)(void *))clk_disable_unprepare,
288 dwmac->rgmii_tx_clk);
289 break;
290
291 case PHY_INTERFACE_MODE_RMII:
292
293 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
294 PRG_ETH0_INVERTED_RMII_CLK,
295 PRG_ETH0_INVERTED_RMII_CLK);
296
297
298 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
299 0);
300
301 break;
302
303 default:
304 dev_err(dwmac->dev, "unsupported phy-mode %s\n",
305 phy_modes(dwmac->phy_mode));
306 return -EINVAL;
307 }
308
309
310 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
311 PRG_ETH0_TX_AND_PHY_REF_CLK);
312
313 return 0;
314 }
315
316 static int meson8b_dwmac_probe(struct platform_device *pdev)
317 {
318 struct plat_stmmacenet_data *plat_dat;
319 struct stmmac_resources stmmac_res;
320 struct meson8b_dwmac *dwmac;
321 int ret;
322
323 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
324 if (ret)
325 return ret;
326
327 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
328 if (IS_ERR(plat_dat))
329 return PTR_ERR(plat_dat);
330
331 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
332 if (!dwmac) {
333 ret = -ENOMEM;
334 goto err_remove_config_dt;
335 }
336
337 dwmac->data = (const struct meson8b_dwmac_data *)
338 of_device_get_match_data(&pdev->dev);
339 if (!dwmac->data) {
340 ret = -EINVAL;
341 goto err_remove_config_dt;
342 }
343 dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
344 if (IS_ERR(dwmac->regs)) {
345 ret = PTR_ERR(dwmac->regs);
346 goto err_remove_config_dt;
347 }
348
349 dwmac->dev = &pdev->dev;
350 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
351 if ((int)dwmac->phy_mode < 0) {
352 dev_err(&pdev->dev, "missing phy-mode property\n");
353 ret = -EINVAL;
354 goto err_remove_config_dt;
355 }
356
357
358 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
359 &dwmac->tx_delay_ns))
360 dwmac->tx_delay_ns = 2;
361
362 ret = meson8b_init_rgmii_tx_clk(dwmac);
363 if (ret)
364 goto err_remove_config_dt;
365
366 ret = dwmac->data->set_phy_mode(dwmac);
367 if (ret)
368 goto err_remove_config_dt;
369
370 ret = meson8b_init_prg_eth(dwmac);
371 if (ret)
372 goto err_remove_config_dt;
373
374 plat_dat->bsp_priv = dwmac;
375
376 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
377 if (ret)
378 goto err_remove_config_dt;
379
380 return 0;
381
382 err_remove_config_dt:
383 stmmac_remove_config_dt(pdev, plat_dat);
384
385 return ret;
386 }
387
388 static const struct meson8b_dwmac_data meson8b_dwmac_data = {
389 .set_phy_mode = meson8b_set_phy_mode,
390 };
391
392 static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
393 .set_phy_mode = meson_axg_set_phy_mode,
394 };
395
396 static const struct of_device_id meson8b_dwmac_match[] = {
397 {
398 .compatible = "amlogic,meson8b-dwmac",
399 .data = &meson8b_dwmac_data,
400 },
401 {
402 .compatible = "amlogic,meson8m2-dwmac",
403 .data = &meson8b_dwmac_data,
404 },
405 {
406 .compatible = "amlogic,meson-gxbb-dwmac",
407 .data = &meson8b_dwmac_data,
408 },
409 {
410 .compatible = "amlogic,meson-axg-dwmac",
411 .data = &meson_axg_dwmac_data,
412 },
413 { }
414 };
415 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
416
417 static struct platform_driver meson8b_dwmac_driver = {
418 .probe = meson8b_dwmac_probe,
419 .remove = stmmac_pltfr_remove,
420 .driver = {
421 .name = "meson8b-dwmac",
422 .pm = &stmmac_pltfr_pm_ops,
423 .of_match_table = meson8b_dwmac_match,
424 },
425 };
426 module_platform_driver(meson8b_dwmac_driver);
427
428 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
429 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");
430 MODULE_LICENSE("GPL v2");