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11 #ifndef __COMMON_H__
12 #define __COMMON_H__
13
14 #include <linux/etherdevice.h>
15 #include <linux/netdevice.h>
16 #include <linux/stmmac.h>
17 #include <linux/phy.h>
18 #include <linux/module.h>
19 #if IS_ENABLED(CONFIG_VLAN_8021Q)
20 #define STMMAC_VLAN_TAG_USED
21 #include <linux/if_vlan.h>
22 #endif
23
24 #include "descs.h"
25 #include "hwif.h"
26 #include "mmc.h"
27
28
29 #define DWMAC_CORE_3_40 0x34
30 #define DWMAC_CORE_3_50 0x35
31 #define DWMAC_CORE_4_00 0x40
32 #define DWMAC_CORE_4_10 0x41
33 #define DWMAC_CORE_5_00 0x50
34 #define DWMAC_CORE_5_10 0x51
35 #define DWXGMAC_CORE_2_10 0x21
36
37 #define STMMAC_CHAN0 0
38
39
40 #define DMA_TX_SIZE 512
41 #define DMA_RX_SIZE 512
42 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
43
44 #undef FRAME_FILTER_DEBUG
45
46
47
48 struct stmmac_extra_stats {
49
50 unsigned long tx_underflow ____cacheline_aligned;
51 unsigned long tx_carrier;
52 unsigned long tx_losscarrier;
53 unsigned long vlan_tag;
54 unsigned long tx_deferred;
55 unsigned long tx_vlan;
56 unsigned long tx_jabber;
57 unsigned long tx_frame_flushed;
58 unsigned long tx_payload_error;
59 unsigned long tx_ip_header_error;
60
61 unsigned long rx_desc;
62 unsigned long sa_filter_fail;
63 unsigned long overflow_error;
64 unsigned long ipc_csum_error;
65 unsigned long rx_collision;
66 unsigned long rx_crc_errors;
67 unsigned long dribbling_bit;
68 unsigned long rx_length;
69 unsigned long rx_mii;
70 unsigned long rx_multicast;
71 unsigned long rx_gmac_overflow;
72 unsigned long rx_watchdog;
73 unsigned long da_rx_filter_fail;
74 unsigned long sa_rx_filter_fail;
75 unsigned long rx_missed_cntr;
76 unsigned long rx_overflow_cntr;
77 unsigned long rx_vlan;
78 unsigned long rx_split_hdr_pkt_n;
79
80 unsigned long tx_undeflow_irq;
81 unsigned long tx_process_stopped_irq;
82 unsigned long tx_jabber_irq;
83 unsigned long rx_overflow_irq;
84 unsigned long rx_buf_unav_irq;
85 unsigned long rx_process_stopped_irq;
86 unsigned long rx_watchdog_irq;
87 unsigned long tx_early_irq;
88 unsigned long fatal_bus_error_irq;
89
90 unsigned long rx_early_irq;
91 unsigned long threshold;
92 unsigned long tx_pkt_n;
93 unsigned long rx_pkt_n;
94 unsigned long normal_irq_n;
95 unsigned long rx_normal_irq_n;
96 unsigned long napi_poll;
97 unsigned long tx_normal_irq_n;
98 unsigned long tx_clean;
99 unsigned long tx_set_ic_bit;
100 unsigned long irq_receive_pmt_irq_n;
101
102 unsigned long mmc_tx_irq_n;
103 unsigned long mmc_rx_irq_n;
104 unsigned long mmc_rx_csum_offload_irq_n;
105
106 unsigned long irq_tx_path_in_lpi_mode_n;
107 unsigned long irq_tx_path_exit_lpi_mode_n;
108 unsigned long irq_rx_path_in_lpi_mode_n;
109 unsigned long irq_rx_path_exit_lpi_mode_n;
110 unsigned long phy_eee_wakeup_error_n;
111
112 unsigned long ip_hdr_err;
113 unsigned long ip_payload_err;
114 unsigned long ip_csum_bypassed;
115 unsigned long ipv4_pkt_rcvd;
116 unsigned long ipv6_pkt_rcvd;
117 unsigned long no_ptp_rx_msg_type_ext;
118 unsigned long ptp_rx_msg_type_sync;
119 unsigned long ptp_rx_msg_type_follow_up;
120 unsigned long ptp_rx_msg_type_delay_req;
121 unsigned long ptp_rx_msg_type_delay_resp;
122 unsigned long ptp_rx_msg_type_pdelay_req;
123 unsigned long ptp_rx_msg_type_pdelay_resp;
124 unsigned long ptp_rx_msg_type_pdelay_follow_up;
125 unsigned long ptp_rx_msg_type_announce;
126 unsigned long ptp_rx_msg_type_management;
127 unsigned long ptp_rx_msg_pkt_reserved_type;
128 unsigned long ptp_frame_type;
129 unsigned long ptp_ver;
130 unsigned long timestamp_dropped;
131 unsigned long av_pkt_rcvd;
132 unsigned long av_tagged_pkt_rcvd;
133 unsigned long vlan_tag_priority_val;
134 unsigned long l3_filter_match;
135 unsigned long l4_filter_match;
136 unsigned long l3_l4_filter_no_match;
137
138 unsigned long irq_pcs_ane_n;
139 unsigned long irq_pcs_link_n;
140 unsigned long irq_rgmii_n;
141 unsigned long pcs_link;
142 unsigned long pcs_duplex;
143 unsigned long pcs_speed;
144
145 unsigned long mtl_tx_status_fifo_full;
146 unsigned long mtl_tx_fifo_not_empty;
147 unsigned long mmtl_fifo_ctrl;
148 unsigned long mtl_tx_fifo_read_ctrl_write;
149 unsigned long mtl_tx_fifo_read_ctrl_wait;
150 unsigned long mtl_tx_fifo_read_ctrl_read;
151 unsigned long mtl_tx_fifo_read_ctrl_idle;
152 unsigned long mac_tx_in_pause;
153 unsigned long mac_tx_frame_ctrl_xfer;
154 unsigned long mac_tx_frame_ctrl_idle;
155 unsigned long mac_tx_frame_ctrl_wait;
156 unsigned long mac_tx_frame_ctrl_pause;
157 unsigned long mac_gmii_tx_proto_engine;
158 unsigned long mtl_rx_fifo_fill_level_full;
159 unsigned long mtl_rx_fifo_fill_above_thresh;
160 unsigned long mtl_rx_fifo_fill_below_thresh;
161 unsigned long mtl_rx_fifo_fill_level_empty;
162 unsigned long mtl_rx_fifo_read_ctrl_flush;
163 unsigned long mtl_rx_fifo_read_ctrl_read_data;
164 unsigned long mtl_rx_fifo_read_ctrl_status;
165 unsigned long mtl_rx_fifo_read_ctrl_idle;
166 unsigned long mtl_rx_fifo_ctrl_active;
167 unsigned long mac_rx_frame_ctrl_fifo;
168 unsigned long mac_gmii_rx_proto_engine;
169
170 unsigned long tx_tso_frames;
171 unsigned long tx_tso_nfrags;
172 };
173
174
175 struct stmmac_safety_stats {
176 unsigned long mac_errors[32];
177 unsigned long mtl_errors[32];
178 unsigned long dma_errors[32];
179 };
180
181
182 #define STMMAC_SAFETY_FEAT_SIZE \
183 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
184
185
186 #define CSR_F_35M 35000000
187 #define CSR_F_60M 60000000
188 #define CSR_F_100M 100000000
189 #define CSR_F_150M 150000000
190 #define CSR_F_250M 250000000
191 #define CSR_F_300M 300000000
192
193 #define MAC_CSR_H_FRQ_MASK 0x20
194
195 #define HASH_TABLE_SIZE 64
196 #define PAUSE_TIME 0xffff
197
198
199 #define FLOW_OFF 0
200 #define FLOW_RX 1
201 #define FLOW_TX 2
202 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
203
204
205 #define STMMAC_PCS_RGMII (1 << 0)
206 #define STMMAC_PCS_SGMII (1 << 1)
207 #define STMMAC_PCS_TBI (1 << 2)
208 #define STMMAC_PCS_RTBI (1 << 3)
209
210 #define SF_DMA_MODE 1
211
212
213 #define DMA_HW_FEAT_MIISEL 0x00000001
214 #define DMA_HW_FEAT_GMIISEL 0x00000002
215 #define DMA_HW_FEAT_HDSEL 0x00000004
216 #define DMA_HW_FEAT_EXTHASHEN 0x00000008
217 #define DMA_HW_FEAT_HASHSEL 0x00000010
218 #define DMA_HW_FEAT_ADDMAC 0x00000020
219 #define DMA_HW_FEAT_PCSSEL 0x00000040
220 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080
221 #define DMA_HW_FEAT_SMASEL 0x00000100
222 #define DMA_HW_FEAT_RWKSEL 0x00000200
223 #define DMA_HW_FEAT_MGKSEL 0x00000400
224 #define DMA_HW_FEAT_MMCSEL 0x00000800
225 #define DMA_HW_FEAT_TSVER1SEL 0x00001000
226 #define DMA_HW_FEAT_TSVER2SEL 0x00002000
227 #define DMA_HW_FEAT_EEESEL 0x00004000
228 #define DMA_HW_FEAT_AVSEL 0x00008000
229 #define DMA_HW_FEAT_TXCOESEL 0x00010000
230 #define DMA_HW_FEAT_RXTYP1COE 0x00020000
231 #define DMA_HW_FEAT_RXTYP2COE 0x00040000
232 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000
233 #define DMA_HW_FEAT_RXCHCNT 0x00300000
234 #define DMA_HW_FEAT_TXCHCNT 0x00c00000
235 #define DMA_HW_FEAT_ENHDESSEL 0x01000000
236
237 #define DMA_HW_FEAT_INTTSEN 0x02000000
238 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000
239 #define DMA_HW_FEAT_SAVLANINS 0x08000000
240 #define DMA_HW_FEAT_ACTPHYIF 0x70000000
241 #define DEFAULT_DMA_PBL 8
242
243
244 #define PCS_ANE_IRQ BIT(2)
245 #define PCS_LINK_IRQ BIT(1)
246 #define PCS_RGSMIIIS_IRQ BIT(0)
247
248
249 #define MAX_DMA_RIWT 0xff
250 #define MIN_DMA_RIWT 0x10
251
252 #define STMMAC_COAL_TX_TIMER 1000
253 #define STMMAC_MAX_COAL_TX_TICK 100000
254 #define STMMAC_TX_MAX_FRAMES 256
255 #define STMMAC_TX_FRAMES 1
256 #define STMMAC_RX_FRAMES 25
257
258
259 enum packets_types {
260 PACKET_AVCPQ = 0x1,
261 PACKET_PTPQ = 0x2,
262 PACKET_DCBCPQ = 0x3,
263 PACKET_UPQ = 0x4,
264 PACKET_MCBCQ = 0x5,
265 };
266
267
268 enum rx_frame_status {
269 good_frame = 0x0,
270 discard_frame = 0x1,
271 csum_none = 0x2,
272 llc_snap = 0x4,
273 dma_own = 0x8,
274 rx_not_ls = 0x10,
275 };
276
277
278 enum tx_frame_status {
279 tx_done = 0x0,
280 tx_not_ls = 0x1,
281 tx_err = 0x2,
282 tx_dma_own = 0x4,
283 };
284
285 enum dma_irq_status {
286 tx_hard_error = 0x1,
287 tx_hard_error_bump_tc = 0x2,
288 handle_rx = 0x4,
289 handle_tx = 0x8,
290 };
291
292
293 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
294 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
295 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
296 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
297
298 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
299
300
301 struct rgmii_adv {
302 unsigned int pause;
303 unsigned int duplex;
304 unsigned int lp_pause;
305 unsigned int lp_duplex;
306 };
307
308 #define STMMAC_PCS_PAUSE 1
309 #define STMMAC_PCS_ASYM_PAUSE 2
310
311
312 struct dma_features {
313 unsigned int mbps_10_100;
314 unsigned int mbps_1000;
315 unsigned int half_duplex;
316 unsigned int hash_filter;
317 unsigned int multi_addr;
318 unsigned int pcs;
319 unsigned int sma_mdio;
320 unsigned int pmt_remote_wake_up;
321 unsigned int pmt_magic_frame;
322 unsigned int rmon;
323
324 unsigned int time_stamp;
325
326 unsigned int atime_stamp;
327
328 unsigned int eee;
329 unsigned int av;
330 unsigned int hash_tb_sz;
331 unsigned int tsoen;
332
333 unsigned int tx_coe;
334 unsigned int rx_coe;
335 unsigned int rx_coe_type1;
336 unsigned int rx_coe_type2;
337 unsigned int rxfifo_over_2048;
338
339 unsigned int number_rx_channel;
340 unsigned int number_tx_channel;
341
342 unsigned int number_rx_queues;
343 unsigned int number_tx_queues;
344
345 unsigned int pps_out_num;
346
347 unsigned int enh_desc;
348
349 unsigned int tx_fifo_size;
350 unsigned int rx_fifo_size;
351
352 unsigned int asp;
353
354 unsigned int frpsel;
355 unsigned int frpbs;
356 unsigned int frpes;
357 unsigned int addr64;
358 unsigned int rssen;
359 unsigned int vlhash;
360 unsigned int sphen;
361 unsigned int vlins;
362 unsigned int dvlan;
363 unsigned int l3l4fnum;
364 unsigned int arpoffsel;
365 };
366
367
368 #define BUF_SIZE_16KiB 16368
369 #define BUF_SIZE_8KiB 8188
370 #define BUF_SIZE_4KiB 4096
371 #define BUF_SIZE_2KiB 2048
372
373
374 #define PMT_NOT_SUPPORTED 0
375 #define PMT_SUPPORTED 1
376
377
378 #define MAC_CTRL_REG 0x00000000
379 #define MAC_ENABLE_TX 0x00000008
380 #define MAC_ENABLE_RX 0x00000004
381
382
383 #define STMMAC_DEFAULT_LIT_LS 0x3E8
384 #define STMMAC_DEFAULT_TWT_LS 0x1E
385
386 #define STMMAC_CHAIN_MODE 0x1
387 #define STMMAC_RING_MODE 0x2
388
389 #define JUMBO_LEN 9000
390
391
392 #define STMMAC_RSS_HASH_KEY_SIZE 40
393 #define STMMAC_RSS_MAX_TABLE_SIZE 256
394
395
396 #define STMMAC_VLAN_NONE 0x0
397 #define STMMAC_VLAN_REMOVE 0x1
398 #define STMMAC_VLAN_INSERT 0x2
399 #define STMMAC_VLAN_REPLACE 0x3
400
401 extern const struct stmmac_desc_ops enh_desc_ops;
402 extern const struct stmmac_desc_ops ndesc_ops;
403
404 struct mac_device_info;
405
406 extern const struct stmmac_hwtimestamp stmmac_ptp;
407 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
408
409 struct mac_link {
410 u32 speed_mask;
411 u32 speed10;
412 u32 speed100;
413 u32 speed1000;
414 u32 speed2500;
415 u32 duplex;
416 struct {
417 u32 speed2500;
418 u32 speed5000;
419 u32 speed10000;
420 } xgmii;
421 };
422
423 struct mii_regs {
424 unsigned int addr;
425 unsigned int data;
426 unsigned int addr_shift;
427 unsigned int reg_shift;
428 unsigned int addr_mask;
429 unsigned int reg_mask;
430 unsigned int clk_csr_shift;
431 unsigned int clk_csr_mask;
432 };
433
434 struct mac_device_info {
435 const struct stmmac_ops *mac;
436 const struct stmmac_desc_ops *desc;
437 const struct stmmac_dma_ops *dma;
438 const struct stmmac_mode_ops *mode;
439 const struct stmmac_hwtimestamp *ptp;
440 const struct stmmac_tc_ops *tc;
441 const struct stmmac_mmc_ops *mmc;
442 struct mii_regs mii;
443 struct mac_link link;
444 void __iomem *pcsr;
445 unsigned int multicast_filter_bins;
446 unsigned int unicast_filter_entries;
447 unsigned int mcast_bits_log2;
448 unsigned int rx_csum;
449 unsigned int pcs;
450 unsigned int pmt;
451 unsigned int ps;
452 };
453
454 struct stmmac_rx_routing {
455 u32 reg_mask;
456 u32 reg_shift;
457 };
458
459 int dwmac100_setup(struct stmmac_priv *priv);
460 int dwmac1000_setup(struct stmmac_priv *priv);
461 int dwmac4_setup(struct stmmac_priv *priv);
462 int dwxgmac2_setup(struct stmmac_priv *priv);
463
464 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
465 unsigned int high, unsigned int low);
466 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
467 unsigned int high, unsigned int low);
468 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
469
470 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
471 unsigned int high, unsigned int low);
472 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
473 unsigned int high, unsigned int low);
474 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
475
476 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
477
478 extern const struct stmmac_mode_ops ring_mode_ops;
479 extern const struct stmmac_mode_ops chain_mode_ops;
480 extern const struct stmmac_desc_ops dwmac4_desc_ops;
481
482 #endif