1
2
3
4
5
6
7
8
9
10 #ifndef __DWMAC4_H__
11 #define __DWMAC4_H__
12
13 #include "common.h"
14
15
16 #define GMAC_CONFIG 0x00000000
17 #define GMAC_PACKET_FILTER 0x00000008
18 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
19 #define GMAC_VLAN_TAG 0x00000050
20 #define GMAC_VLAN_HASH_TABLE 0x00000058
21 #define GMAC_RX_FLOW_CTRL 0x00000090
22 #define GMAC_VLAN_INCL 0x00000060
23 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
24 #define GMAC_TXQ_PRTY_MAP0 0x98
25 #define GMAC_TXQ_PRTY_MAP1 0x9C
26 #define GMAC_RXQ_CTRL0 0x000000a0
27 #define GMAC_RXQ_CTRL1 0x000000a4
28 #define GMAC_RXQ_CTRL2 0x000000a8
29 #define GMAC_RXQ_CTRL3 0x000000ac
30 #define GMAC_INT_STATUS 0x000000b0
31 #define GMAC_INT_EN 0x000000b4
32 #define GMAC_1US_TIC_COUNTER 0x000000dc
33 #define GMAC_PCS_BASE 0x000000e0
34 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
35 #define GMAC_PMT 0x000000c0
36 #define GMAC_DEBUG 0x00000114
37 #define GMAC_HW_FEATURE0 0x0000011c
38 #define GMAC_HW_FEATURE1 0x00000120
39 #define GMAC_HW_FEATURE2 0x00000124
40 #define GMAC_HW_FEATURE3 0x00000128
41 #define GMAC_MDIO_ADDR 0x00000200
42 #define GMAC_MDIO_DATA 0x00000204
43 #define GMAC_ARP_ADDR 0x00000210
44 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
45 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
46
47
48 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
49 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0
50 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
51 #define GMAC_RXQCTRL_PTPQ_SHIFT 4
52 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
53 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
54 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
55 #define GMAC_RXQCTRL_UPQ_SHIFT 12
56 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
57 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16
58 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
59 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
60 #define GMAC_RXQCTRL_TACPQE BIT(21)
61 #define GMAC_RXQCTRL_TACPQE_SHIFT 21
62
63
64 #define GMAC_PACKET_FILTER_PR BIT(0)
65 #define GMAC_PACKET_FILTER_HMC BIT(2)
66 #define GMAC_PACKET_FILTER_PM BIT(4)
67 #define GMAC_PACKET_FILTER_PCF BIT(7)
68 #define GMAC_PACKET_FILTER_HPF BIT(10)
69 #define GMAC_PACKET_FILTER_VTFE BIT(16)
70
71 #define GMAC_MAX_PERFECT_ADDRESSES 128
72
73
74 #define GMAC_VLAN_EDVLP BIT(26)
75 #define GMAC_VLAN_VTHM BIT(25)
76 #define GMAC_VLAN_DOVLTC BIT(20)
77 #define GMAC_VLAN_ESVL BIT(18)
78 #define GMAC_VLAN_ETV BIT(16)
79 #define GMAC_VLAN_VID GENMASK(15, 0)
80 #define GMAC_VLAN_VLTI BIT(20)
81 #define GMAC_VLAN_CSVL BIT(19)
82 #define GMAC_VLAN_VLC GENMASK(17, 16)
83 #define GMAC_VLAN_VLC_SHIFT 16
84
85
86 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
87 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
88 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
89
90
91 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
92
93
94 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
95 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
96
97
98 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
99 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
100
101
102 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
103 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
104
105
106 #define GMAC_INT_RGSMIIS BIT(0)
107 #define GMAC_INT_PCS_LINK BIT(1)
108 #define GMAC_INT_PCS_ANE BIT(2)
109 #define GMAC_INT_PCS_PHYIS BIT(3)
110 #define GMAC_INT_PMT_EN BIT(4)
111 #define GMAC_INT_LPI_EN BIT(5)
112
113 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
114 GMAC_INT_PCS_ANE)
115
116 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
117
118 enum dwmac4_irq_status {
119 time_stamp_irq = 0x00001000,
120 mmc_rx_csum_offload_irq = 0x00000800,
121 mmc_tx_irq = 0x00000400,
122 mmc_rx_irq = 0x00000200,
123 mmc_irq = 0x00000100,
124 lpi_irq = 0x00000020,
125 pmt_irq = 0x00000010,
126 };
127
128
129 enum power_event {
130 pointer_reset = 0x80000000,
131 global_unicast = 0x00000200,
132 wake_up_rx_frame = 0x00000040,
133 magic_frame = 0x00000020,
134 wake_up_frame_en = 0x00000004,
135 magic_pkt_en = 0x00000002,
136 power_down = 0x00000001,
137 };
138
139
140
141
142
143 #define GMAC4_LPI_CTRL_STATUS 0xd0
144 #define GMAC4_LPI_TIMER_CTRL 0xd4
145
146
147 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21)
148 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19)
149 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17)
150 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16)
151 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3)
152 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2)
153 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1)
154 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0)
155
156
157 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
158 #define GMAC_DEBUG_TFCSTS_SHIFT 17
159 #define GMAC_DEBUG_TFCSTS_IDLE 0
160 #define GMAC_DEBUG_TFCSTS_WAIT 1
161 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
162 #define GMAC_DEBUG_TFCSTS_XFER 3
163 #define GMAC_DEBUG_TPESTS BIT(16)
164 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
165 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1
166 #define GMAC_DEBUG_RPESTS BIT(0)
167
168
169 #define GMAC_CONFIG_ARPEN BIT(31)
170 #define GMAC_CONFIG_SARC GENMASK(30, 28)
171 #define GMAC_CONFIG_SARC_SHIFT 28
172 #define GMAC_CONFIG_IPC BIT(27)
173 #define GMAC_CONFIG_2K BIT(22)
174 #define GMAC_CONFIG_ACS BIT(20)
175 #define GMAC_CONFIG_BE BIT(18)
176 #define GMAC_CONFIG_JD BIT(17)
177 #define GMAC_CONFIG_JE BIT(16)
178 #define GMAC_CONFIG_PS BIT(15)
179 #define GMAC_CONFIG_FES BIT(14)
180 #define GMAC_CONFIG_DM BIT(13)
181 #define GMAC_CONFIG_LM BIT(12)
182 #define GMAC_CONFIG_DCRS BIT(9)
183 #define GMAC_CONFIG_TE BIT(1)
184 #define GMAC_CONFIG_RE BIT(0)
185
186
187 #define GMAC_HW_FEAT_SAVLANINS BIT(27)
188 #define GMAC_HW_FEAT_ADDMAC BIT(18)
189 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
190 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
191 #define GMAC_HW_FEAT_EEESEL BIT(13)
192 #define GMAC_HW_FEAT_TSSEL BIT(12)
193 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
194 #define GMAC_HW_FEAT_MMCSEL BIT(8)
195 #define GMAC_HW_FEAT_MGKSEL BIT(7)
196 #define GMAC_HW_FEAT_RWKSEL BIT(6)
197 #define GMAC_HW_FEAT_SMASEL BIT(5)
198 #define GMAC_HW_FEAT_VLHASH BIT(4)
199 #define GMAC_HW_FEAT_PCSSEL BIT(3)
200 #define GMAC_HW_FEAT_HDSEL BIT(2)
201 #define GMAC_HW_FEAT_GMIISEL BIT(1)
202 #define GMAC_HW_FEAT_MIISEL BIT(0)
203
204
205 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
206 #define GMAC_HW_FEAT_AVSEL BIT(20)
207 #define GMAC_HW_TSOEN BIT(18)
208 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
209 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
210
211
212 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)
213 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
214 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
215 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
216 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
217
218
219 #define GMAC_HW_FEAT_ASP GENMASK(29, 28)
220 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
221 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
222 #define GMAC_HW_FEAT_FRPSEL BIT(10)
223 #define GMAC_HW_FEAT_DVLAN BIT(5)
224
225
226 #define GMAC_HI_DCS GENMASK(18, 16)
227 #define GMAC_HI_DCS_SHIFT 16
228 #define GMAC_HI_REG_AE BIT(31)
229
230
231 #define MTL_OPERATION_MODE 0x00000c00
232 #define MTL_FRPE BIT(15)
233 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
234 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
235 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
236 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
237 #define MTL_OPERATION_SCHALG_SP (0x3 << 5)
238 #define MTL_OPERATION_RAA BIT(2)
239 #define MTL_OPERATION_RAA_SP (0x0 << 2)
240 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
241
242 #define MTL_INT_STATUS 0x00000c20
243 #define MTL_INT_QX(x) BIT(x)
244
245 #define MTL_RXQ_DMA_MAP0 0x00000c30
246 #define MTL_RXQ_DMA_MAP1 0x00000c34
247 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
248 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
249 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
250 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
251
252 #define MTL_CHAN_BASE_ADDR 0x00000d00
253 #define MTL_CHAN_BASE_OFFSET 0x40
254 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
255 (x * MTL_CHAN_BASE_OFFSET))
256
257 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
258 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
259 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
260 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
261 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
262
263 #define MTL_OP_MODE_RSF BIT(5)
264 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
265 #define MTL_OP_MODE_TXQEN_AV BIT(2)
266 #define MTL_OP_MODE_TXQEN BIT(3)
267 #define MTL_OP_MODE_TSF BIT(1)
268
269 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
270 #define MTL_OP_MODE_TQS_SHIFT 16
271
272 #define MTL_OP_MODE_TTC_MASK 0x70
273 #define MTL_OP_MODE_TTC_SHIFT 4
274
275 #define MTL_OP_MODE_TTC_32 0
276 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
277 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
278 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
279 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
280 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
281 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
282 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
283
284 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
285 #define MTL_OP_MODE_RQS_SHIFT 20
286
287 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
288 #define MTL_OP_MODE_RFD_SHIFT 14
289
290 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
291 #define MTL_OP_MODE_RFA_SHIFT 8
292
293 #define MTL_OP_MODE_EHFC BIT(7)
294
295 #define MTL_OP_MODE_RTC_MASK 0x18
296 #define MTL_OP_MODE_RTC_SHIFT 3
297
298 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
299 #define MTL_OP_MODE_RTC_64 0
300 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
301 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
302
303
304 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
305 #define MTL_ETS_CTRL_BASE_OFFSET 0x40
306 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \
307 ((x) * MTL_ETS_CTRL_BASE_OFFSET))
308
309 #define MTL_ETS_CTRL_CC BIT(3)
310 #define MTL_ETS_CTRL_AVALG BIT(2)
311
312
313 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
314 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
315 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \
316 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
317 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
318
319
320 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
321 #define MTL_SEND_SLP_CRED_OFFSET 0x40
322 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \
323 ((x) * MTL_SEND_SLP_CRED_OFFSET))
324
325 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
326
327
328 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
329 #define MTL_HIGH_CRED_OFFSET 0x40
330 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \
331 ((x) * MTL_HIGH_CRED_OFFSET))
332
333 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
334
335
336 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24
337 #define MTL_LOW_CRED_OFFSET 0x40
338 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \
339 ((x) * MTL_LOW_CRED_OFFSET))
340
341 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
342
343
344 #define MTL_DEBUG_TXSTSFSTS BIT(5)
345 #define MTL_DEBUG_TXFSTS BIT(4)
346 #define MTL_DEBUG_TWCSTS BIT(3)
347
348
349 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
350 #define MTL_DEBUG_TRCSTS_SHIFT 1
351 #define MTL_DEBUG_TRCSTS_IDLE 0
352 #define MTL_DEBUG_TRCSTS_READ 1
353 #define MTL_DEBUG_TRCSTS_TXW 2
354 #define MTL_DEBUG_TRCSTS_WRITE 3
355 #define MTL_DEBUG_TXPAUSED BIT(0)
356
357
358 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
359 #define MTL_DEBUG_RXFSTS_SHIFT 4
360 #define MTL_DEBUG_RXFSTS_EMPTY 0
361 #define MTL_DEBUG_RXFSTS_BT 1
362 #define MTL_DEBUG_RXFSTS_AT 2
363 #define MTL_DEBUG_RXFSTS_FULL 3
364 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
365 #define MTL_DEBUG_RRCSTS_SHIFT 1
366 #define MTL_DEBUG_RRCSTS_IDLE 0
367 #define MTL_DEBUG_RRCSTS_RDATA 1
368 #define MTL_DEBUG_RRCSTS_RSTAT 2
369 #define MTL_DEBUG_RRCSTS_FLUSH 3
370 #define MTL_DEBUG_RWCSTS BIT(0)
371
372
373 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
374 #define MTL_RX_OVERFLOW_INT BIT(16)
375
376
377 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
378 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
379 GMAC_CONFIG_JE)
380
381
382 #define GMAC_REG_NUM 132
383
384
385 #define MTL_DEBUG_TXSTSFSTS BIT(5)
386 #define MTL_DEBUG_TXFSTS BIT(4)
387 #define MTL_DEBUG_TWCSTS BIT(3)
388
389
390 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
391 #define MTL_DEBUG_TRCSTS_SHIFT 1
392 #define MTL_DEBUG_TRCSTS_IDLE 0
393 #define MTL_DEBUG_TRCSTS_READ 1
394 #define MTL_DEBUG_TRCSTS_TXW 2
395 #define MTL_DEBUG_TRCSTS_WRITE 3
396 #define MTL_DEBUG_TXPAUSED BIT(0)
397
398
399 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
400 #define MTL_DEBUG_RXFSTS_SHIFT 4
401 #define MTL_DEBUG_RXFSTS_EMPTY 0
402 #define MTL_DEBUG_RXFSTS_BT 1
403 #define MTL_DEBUG_RXFSTS_AT 2
404 #define MTL_DEBUG_RXFSTS_FULL 3
405 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
406 #define MTL_DEBUG_RRCSTS_SHIFT 1
407 #define MTL_DEBUG_RRCSTS_IDLE 0
408 #define MTL_DEBUG_RRCSTS_RDATA 1
409 #define MTL_DEBUG_RRCSTS_RSTAT 2
410 #define MTL_DEBUG_RRCSTS_FLUSH 3
411 #define MTL_DEBUG_RWCSTS BIT(0)
412
413
414 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
415 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
416 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
417 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
418 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
419 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
420 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
421 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
422 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
423
424 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
425
426 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
427 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
428 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
429
430 extern const struct stmmac_dma_ops dwmac4_dma_ops;
431 extern const struct stmmac_dma_ops dwmac410_dma_ops;
432 #endif