This source file includes following definitions.
- dwmac100_core_init
- dwmac100_dump_mac_regs
- dwmac100_rx_ipc_enable
- dwmac100_irq_status
- dwmac100_set_umac_addr
- dwmac100_get_umac_addr
- dwmac100_set_filter
- dwmac100_flow_ctrl
- dwmac100_pmt
- dwmac100_set_mac_loopback
- dwmac100_setup
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17 #include <linux/crc32.h>
18 #include <net/dsa.h>
19 #include <asm/io.h>
20 #include "stmmac.h"
21 #include "dwmac100.h"
22
23 static void dwmac100_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
25 {
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + MAC_CONTROL);
28
29 value |= MAC_CORE_INIT;
30
31
32
33
34
35 if (netdev_uses_dsa(dev))
36 value &= ~MAC_CONTROL_ASTP;
37
38 writel(value, ioaddr + MAC_CONTROL);
39
40 #ifdef STMMAC_VLAN_TAG_USED
41 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
42 #endif
43 }
44
45 static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
46 {
47 void __iomem *ioaddr = hw->pcsr;
48
49 reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
50 reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
51 reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
52 reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
53 reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
54 reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
55 reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
56 reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
57 }
58
59 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
60 {
61 return 0;
62 }
63
64 static int dwmac100_irq_status(struct mac_device_info *hw,
65 struct stmmac_extra_stats *x)
66 {
67 return 0;
68 }
69
70 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
71 unsigned char *addr,
72 unsigned int reg_n)
73 {
74 void __iomem *ioaddr = hw->pcsr;
75 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
76 }
77
78 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
79 unsigned char *addr,
80 unsigned int reg_n)
81 {
82 void __iomem *ioaddr = hw->pcsr;
83 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
84 }
85
86 static void dwmac100_set_filter(struct mac_device_info *hw,
87 struct net_device *dev)
88 {
89 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
90 u32 value = readl(ioaddr + MAC_CONTROL);
91
92 if (dev->flags & IFF_PROMISC) {
93 value |= MAC_CONTROL_PR;
94 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
95 MAC_CONTROL_HP);
96 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
97 || (dev->flags & IFF_ALLMULTI)) {
98 value |= MAC_CONTROL_PM;
99 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
100 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
101 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
102 } else if (netdev_mc_empty(dev)) {
103 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
104 MAC_CONTROL_HO | MAC_CONTROL_HP);
105 } else {
106 u32 mc_filter[2];
107 struct netdev_hw_addr *ha;
108
109
110
111
112 value |= MAC_CONTROL_HP;
113 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
114 MAC_CONTROL_IF | MAC_CONTROL_HO);
115
116 memset(mc_filter, 0, sizeof(mc_filter));
117 netdev_for_each_mc_addr(ha, dev) {
118
119
120
121 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
122
123
124
125
126 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
127 }
128 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
129 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
130 }
131
132 writel(value, ioaddr + MAC_CONTROL);
133 }
134
135 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
136 unsigned int fc, unsigned int pause_time,
137 u32 tx_cnt)
138 {
139 void __iomem *ioaddr = hw->pcsr;
140 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
141
142 if (duplex)
143 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
144 writel(flow, ioaddr + MAC_FLOW_CTRL);
145 }
146
147
148 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
149 {
150 return;
151 }
152
153 static void dwmac100_set_mac_loopback(void __iomem *ioaddr, bool enable)
154 {
155 u32 value = readl(ioaddr + MAC_CONTROL);
156
157 if (enable)
158 value |= MAC_CONTROL_OM;
159 else
160 value &= ~MAC_CONTROL_OM;
161
162 writel(value, ioaddr + MAC_CONTROL);
163 }
164
165 const struct stmmac_ops dwmac100_ops = {
166 .core_init = dwmac100_core_init,
167 .set_mac = stmmac_set_mac,
168 .rx_ipc = dwmac100_rx_ipc_enable,
169 .dump_regs = dwmac100_dump_mac_regs,
170 .host_irq_status = dwmac100_irq_status,
171 .set_filter = dwmac100_set_filter,
172 .flow_ctrl = dwmac100_flow_ctrl,
173 .pmt = dwmac100_pmt,
174 .set_umac_addr = dwmac100_set_umac_addr,
175 .get_umac_addr = dwmac100_get_umac_addr,
176 .set_mac_loopback = dwmac100_set_mac_loopback,
177 };
178
179 int dwmac100_setup(struct stmmac_priv *priv)
180 {
181 struct mac_device_info *mac = priv->hw;
182
183 dev_info(priv->device, "\tDWMAC100\n");
184
185 mac->pcsr = priv->ioaddr;
186 mac->link.duplex = MAC_CONTROL_F;
187 mac->link.speed10 = 0;
188 mac->link.speed100 = 0;
189 mac->link.speed1000 = 0;
190 mac->link.speed_mask = MAC_CONTROL_PS;
191 mac->mii.addr = MAC_MII_ADDR;
192 mac->mii.data = MAC_MII_DATA;
193 mac->mii.addr_shift = 11;
194 mac->mii.addr_mask = 0x0000F800;
195 mac->mii.reg_shift = 6;
196 mac->mii.reg_mask = 0x000007C0;
197 mac->mii.clk_csr_shift = 2;
198 mac->mii.clk_csr_mask = GENMASK(5, 2);
199
200 return 0;
201 }