drivers/net/ethernet/stmicro/stmmac/dwmac4

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   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * DWMAC4 DMA Header file.
   4  *
   5  * Copyright (C) 2007-2015  STMicroelectronics Ltd
   6  *
   7  * Author: Alexandre Torgue <alexandre.torgue@st.com>
   8  */
   9 
  10 #ifndef __DWMAC4_DMA_H__
  11 #define __DWMAC4_DMA_H__
  12 
  13 /* Define the max channel number used for tx (also rx).
  14  * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
  15  */
  16 #define DMA_CHANNEL_NB_MAX              1
  17 
  18 #define DMA_BUS_MODE                    0x00001000
  19 #define DMA_SYS_BUS_MODE                0x00001004
  20 #define DMA_STATUS                      0x00001008
  21 #define DMA_DEBUG_STATUS_0              0x0000100c
  22 #define DMA_DEBUG_STATUS_1              0x00001010
  23 #define DMA_DEBUG_STATUS_2              0x00001014
  24 #define DMA_AXI_BUS_MODE                0x00001028
  25 
  26 /* DMA Bus Mode bitmap */
  27 #define DMA_BUS_MODE_SFT_RESET          BIT(0)
  28 
  29 /* DMA SYS Bus Mode bitmap */
  30 #define DMA_BUS_MODE_SPH                BIT(24)
  31 #define DMA_BUS_MODE_PBL                BIT(16)
  32 #define DMA_BUS_MODE_PBL_SHIFT          16
  33 #define DMA_BUS_MODE_RPBL_SHIFT         16
  34 #define DMA_BUS_MODE_MB                 BIT(14)
  35 #define DMA_BUS_MODE_FB                 BIT(0)
  36 
  37 /* DMA Interrupt top status */
  38 #define DMA_STATUS_MAC                  BIT(17)
  39 #define DMA_STATUS_MTL                  BIT(16)
  40 #define DMA_STATUS_CHAN7                BIT(7)
  41 #define DMA_STATUS_CHAN6                BIT(6)
  42 #define DMA_STATUS_CHAN5                BIT(5)
  43 #define DMA_STATUS_CHAN4                BIT(4)
  44 #define DMA_STATUS_CHAN3                BIT(3)
  45 #define DMA_STATUS_CHAN2                BIT(2)
  46 #define DMA_STATUS_CHAN1                BIT(1)
  47 #define DMA_STATUS_CHAN0                BIT(0)
  48 
  49 /* DMA debug status bitmap */
  50 #define DMA_DEBUG_STATUS_TS_MASK        0xf
  51 #define DMA_DEBUG_STATUS_RS_MASK        0xf
  52 
  53 /* DMA AXI bitmap */
  54 #define DMA_AXI_EN_LPI                  BIT(31)
  55 #define DMA_AXI_LPI_XIT_FRM             BIT(30)
  56 #define DMA_AXI_WR_OSR_LMT              GENMASK(27, 24)
  57 #define DMA_AXI_WR_OSR_LMT_SHIFT        24
  58 #define DMA_AXI_RD_OSR_LMT              GENMASK(19, 16)
  59 #define DMA_AXI_RD_OSR_LMT_SHIFT        16
  60 
  61 #define DMA_AXI_OSR_MAX                 0xf
  62 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
  63                                 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
  64 
  65 #define DMA_SYS_BUS_MB                  BIT(14)
  66 #define DMA_AXI_1KBBE                   BIT(13)
  67 #define DMA_SYS_BUS_AAL                 BIT(12)
  68 #define DMA_AXI_BLEN256                 BIT(7)
  69 #define DMA_AXI_BLEN128                 BIT(6)
  70 #define DMA_AXI_BLEN64                  BIT(5)
  71 #define DMA_AXI_BLEN32                  BIT(4)
  72 #define DMA_AXI_BLEN16                  BIT(3)
  73 #define DMA_AXI_BLEN8                   BIT(2)
  74 #define DMA_AXI_BLEN4                   BIT(1)
  75 #define DMA_SYS_BUS_FB                  BIT(0)
  76 
  77 #define DMA_BURST_LEN_DEFAULT           (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
  78                                         DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
  79                                         DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
  80                                         DMA_AXI_BLEN4)
  81 
  82 #define DMA_AXI_BURST_LEN_MASK          0x000000FE
  83 
  84 /* Following DMA defines are chanels oriented */
  85 #define DMA_CHAN_BASE_ADDR              0x00001100
  86 #define DMA_CHAN_BASE_OFFSET            0x80
  87 #define DMA_CHANX_BASE_ADDR(x)          (DMA_CHAN_BASE_ADDR + \
  88                                         (x * DMA_CHAN_BASE_OFFSET))
  89 #define DMA_CHAN_REG_NUMBER             17
  90 
  91 #define DMA_CHAN_CONTROL(x)             DMA_CHANX_BASE_ADDR(x)
  92 #define DMA_CHAN_TX_CONTROL(x)          (DMA_CHANX_BASE_ADDR(x) + 0x4)
  93 #define DMA_CHAN_RX_CONTROL(x)          (DMA_CHANX_BASE_ADDR(x) + 0x8)
  94 #define DMA_CHAN_TX_BASE_ADDR(x)        (DMA_CHANX_BASE_ADDR(x) + 0x14)
  95 #define DMA_CHAN_RX_BASE_ADDR(x)        (DMA_CHANX_BASE_ADDR(x) + 0x1c)
  96 #define DMA_CHAN_TX_END_ADDR(x)         (DMA_CHANX_BASE_ADDR(x) + 0x20)
  97 #define DMA_CHAN_RX_END_ADDR(x)         (DMA_CHANX_BASE_ADDR(x) + 0x28)
  98 #define DMA_CHAN_TX_RING_LEN(x)         (DMA_CHANX_BASE_ADDR(x) + 0x2c)
  99 #define DMA_CHAN_RX_RING_LEN(x)         (DMA_CHANX_BASE_ADDR(x) + 0x30)
 100 #define DMA_CHAN_INTR_ENA(x)            (DMA_CHANX_BASE_ADDR(x) + 0x34)
 101 #define DMA_CHAN_RX_WATCHDOG(x)         (DMA_CHANX_BASE_ADDR(x) + 0x38)
 102 #define DMA_CHAN_SLOT_CTRL_STATUS(x)    (DMA_CHANX_BASE_ADDR(x) + 0x3c)
 103 #define DMA_CHAN_CUR_TX_DESC(x)         (DMA_CHANX_BASE_ADDR(x) + 0x44)
 104 #define DMA_CHAN_CUR_RX_DESC(x)         (DMA_CHANX_BASE_ADDR(x) + 0x4c)
 105 #define DMA_CHAN_CUR_TX_BUF_ADDR(x)     (DMA_CHANX_BASE_ADDR(x) + 0x54)
 106 #define DMA_CHAN_CUR_RX_BUF_ADDR(x)     (DMA_CHANX_BASE_ADDR(x) + 0x5c)
 107 #define DMA_CHAN_STATUS(x)              (DMA_CHANX_BASE_ADDR(x) + 0x60)
 108 
 109 /* DMA Control X */
 110 #define DMA_CONTROL_MSS_MASK            GENMASK(13, 0)
 111 
 112 /* DMA Tx Channel X Control register defines */
 113 #define DMA_CONTROL_TSE                 BIT(12)
 114 #define DMA_CONTROL_OSP                 BIT(4)
 115 #define DMA_CONTROL_ST                  BIT(0)
 116 
 117 /* DMA Rx Channel X Control register defines */
 118 #define DMA_CONTROL_SR                  BIT(0)
 119 #define DMA_RBSZ_MASK                   GENMASK(14, 1)
 120 #define DMA_RBSZ_SHIFT                  1
 121 
 122 /* Interrupt status per channel */
 123 #define DMA_CHAN_STATUS_REB             GENMASK(21, 19)
 124 #define DMA_CHAN_STATUS_REB_SHIFT       19
 125 #define DMA_CHAN_STATUS_TEB             GENMASK(18, 16)
 126 #define DMA_CHAN_STATUS_TEB_SHIFT       16
 127 #define DMA_CHAN_STATUS_NIS             BIT(15)
 128 #define DMA_CHAN_STATUS_AIS             BIT(14)
 129 #define DMA_CHAN_STATUS_CDE             BIT(13)
 130 #define DMA_CHAN_STATUS_FBE             BIT(12)
 131 #define DMA_CHAN_STATUS_ERI             BIT(11)
 132 #define DMA_CHAN_STATUS_ETI             BIT(10)
 133 #define DMA_CHAN_STATUS_RWT             BIT(9)
 134 #define DMA_CHAN_STATUS_RPS             BIT(8)
 135 #define DMA_CHAN_STATUS_RBU             BIT(7)
 136 #define DMA_CHAN_STATUS_RI              BIT(6)
 137 #define DMA_CHAN_STATUS_TBU             BIT(2)
 138 #define DMA_CHAN_STATUS_TPS             BIT(1)
 139 #define DMA_CHAN_STATUS_TI              BIT(0)
 140 
 141 /* Interrupt enable bits per channel */
 142 #define DMA_CHAN_INTR_ENA_NIE           BIT(16)
 143 #define DMA_CHAN_INTR_ENA_AIE           BIT(15)
 144 #define DMA_CHAN_INTR_ENA_NIE_4_10      BIT(15)
 145 #define DMA_CHAN_INTR_ENA_AIE_4_10      BIT(14)
 146 #define DMA_CHAN_INTR_ENA_CDE           BIT(13)
 147 #define DMA_CHAN_INTR_ENA_FBE           BIT(12)
 148 #define DMA_CHAN_INTR_ENA_ERE           BIT(11)
 149 #define DMA_CHAN_INTR_ENA_ETE           BIT(10)
 150 #define DMA_CHAN_INTR_ENA_RWE           BIT(9)
 151 #define DMA_CHAN_INTR_ENA_RSE           BIT(8)
 152 #define DMA_CHAN_INTR_ENA_RBUE          BIT(7)
 153 #define DMA_CHAN_INTR_ENA_RIE           BIT(6)
 154 #define DMA_CHAN_INTR_ENA_TBUE          BIT(2)
 155 #define DMA_CHAN_INTR_ENA_TSE           BIT(1)
 156 #define DMA_CHAN_INTR_ENA_TIE           BIT(0)
 157 
 158 #define DMA_CHAN_INTR_NORMAL            (DMA_CHAN_INTR_ENA_NIE | \
 159                                          DMA_CHAN_INTR_ENA_RIE | \
 160                                          DMA_CHAN_INTR_ENA_TIE)
 161 
 162 #define DMA_CHAN_INTR_ABNORMAL          (DMA_CHAN_INTR_ENA_AIE | \
 163                                          DMA_CHAN_INTR_ENA_FBE)
 164 /* DMA default interrupt mask for 4.00 */
 165 #define DMA_CHAN_INTR_DEFAULT_MASK      (DMA_CHAN_INTR_NORMAL | \
 166                                          DMA_CHAN_INTR_ABNORMAL)
 167 
 168 #define DMA_CHAN_INTR_NORMAL_4_10       (DMA_CHAN_INTR_ENA_NIE_4_10 | \
 169                                          DMA_CHAN_INTR_ENA_RIE | \
 170                                          DMA_CHAN_INTR_ENA_TIE)
 171 
 172 #define DMA_CHAN_INTR_ABNORMAL_4_10     (DMA_CHAN_INTR_ENA_AIE_4_10 | \
 173                                          DMA_CHAN_INTR_ENA_FBE)
 174 /* DMA default interrupt mask for 4.10a */
 175 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
 176                                          DMA_CHAN_INTR_ABNORMAL_4_10)
 177 
 178 /* channel 0 specific fields */
 179 #define DMA_CHAN0_DBG_STAT_TPS          GENMASK(15, 12)
 180 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT    12
 181 #define DMA_CHAN0_DBG_STAT_RPS          GENMASK(11, 8)
 182 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT    8
 183 
 184 int dwmac4_dma_reset(void __iomem *ioaddr);
 185 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan);
 186 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan);
 187 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan);
 188 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);
 189 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);
 190 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);
 191 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan);
 192 int dwmac4_dma_interrupt(void __iomem *ioaddr,
 193                          struct stmmac_extra_stats *x, u32 chan);
 194 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
 195 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
 196 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 197 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 198 
 199 #endif /* __DWMAC4_DMA_H__ */
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root/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

INCLUDED FROM
