This source file includes following definitions.
- dwmac4_dma_reset
- dwmac4_set_rx_tail_ptr
- dwmac4_set_tx_tail_ptr
- dwmac4_dma_start_tx
- dwmac4_dma_stop_tx
- dwmac4_dma_start_rx
- dwmac4_dma_stop_rx
- dwmac4_set_tx_ring_len
- dwmac4_set_rx_ring_len
- dwmac4_enable_dma_irq
- dwmac410_enable_dma_irq
- dwmac4_disable_dma_irq
- dwmac4_dma_interrupt
- stmmac_dwmac4_set_mac_addr
- stmmac_dwmac4_set_mac
- stmmac_dwmac4_get_mac_addr
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8 #include <linux/io.h>
9 #include <linux/delay.h>
10 #include "common.h"
11 #include "dwmac4_dma.h"
12 #include "dwmac4.h"
13
14 int dwmac4_dma_reset(void __iomem *ioaddr)
15 {
16 u32 value = readl(ioaddr + DMA_BUS_MODE);
17 int limit;
18
19
20 value |= DMA_BUS_MODE_SFT_RESET;
21 writel(value, ioaddr + DMA_BUS_MODE);
22 limit = 10;
23 while (limit--) {
24 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
25 break;
26 mdelay(10);
27 }
28
29 if (limit < 0)
30 return -EBUSY;
31
32 return 0;
33 }
34
35 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
36 {
37 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(chan));
38 }
39
40 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
41 {
42 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(chan));
43 }
44
45 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan)
46 {
47 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
48
49 value |= DMA_CONTROL_ST;
50 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
51
52 value = readl(ioaddr + GMAC_CONFIG);
53 value |= GMAC_CONFIG_TE;
54 writel(value, ioaddr + GMAC_CONFIG);
55 }
56
57 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan)
58 {
59 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
60
61 value &= ~DMA_CONTROL_ST;
62 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
63
64 value = readl(ioaddr + GMAC_CONFIG);
65 value &= ~GMAC_CONFIG_TE;
66 writel(value, ioaddr + GMAC_CONFIG);
67 }
68
69 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan)
70 {
71 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
72
73 value |= DMA_CONTROL_SR;
74
75 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
76
77 value = readl(ioaddr + GMAC_CONFIG);
78 value |= GMAC_CONFIG_RE;
79 writel(value, ioaddr + GMAC_CONFIG);
80 }
81
82 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan)
83 {
84 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
85
86 value &= ~DMA_CONTROL_SR;
87 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
88 }
89
90 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
91 {
92 writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(chan));
93 }
94
95 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
96 {
97 writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(chan));
98 }
99
100 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan)
101 {
102 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr +
103 DMA_CHAN_INTR_ENA(chan));
104 }
105
106 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan)
107 {
108 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
109 ioaddr + DMA_CHAN_INTR_ENA(chan));
110 }
111
112 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan)
113 {
114 writel(0, ioaddr + DMA_CHAN_INTR_ENA(chan));
115 }
116
117 int dwmac4_dma_interrupt(void __iomem *ioaddr,
118 struct stmmac_extra_stats *x, u32 chan)
119 {
120 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
121 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
122 int ret = 0;
123
124
125 if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
126 if (unlikely(intr_status & DMA_CHAN_STATUS_RBU))
127 x->rx_buf_unav_irq++;
128 if (unlikely(intr_status & DMA_CHAN_STATUS_RPS))
129 x->rx_process_stopped_irq++;
130 if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))
131 x->rx_watchdog_irq++;
132 if (unlikely(intr_status & DMA_CHAN_STATUS_ETI))
133 x->tx_early_irq++;
134 if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) {
135 x->tx_process_stopped_irq++;
136 ret = tx_hard_error;
137 }
138 if (unlikely(intr_status & DMA_CHAN_STATUS_FBE)) {
139 x->fatal_bus_error_irq++;
140 ret = tx_hard_error;
141 }
142 }
143
144 if (likely(intr_status & DMA_CHAN_STATUS_NIS)) {
145 x->normal_irq_n++;
146 if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
147 x->rx_normal_irq_n++;
148 ret |= handle_rx;
149 }
150 if (likely(intr_status & (DMA_CHAN_STATUS_TI |
151 DMA_CHAN_STATUS_TBU))) {
152 x->tx_normal_irq_n++;
153 ret |= handle_tx;
154 }
155 if (unlikely(intr_status & DMA_CHAN_STATUS_ERI))
156 x->rx_early_irq++;
157 }
158
159 writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan));
160 return ret;
161 }
162
163 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
164 unsigned int high, unsigned int low)
165 {
166 unsigned long data;
167
168 data = (addr[5] << 8) | addr[4];
169
170
171
172
173 data |= (STMMAC_CHAN0 << GMAC_HI_DCS_SHIFT);
174 writel(data | GMAC_HI_REG_AE, ioaddr + high);
175 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
176 writel(data, ioaddr + low);
177 }
178
179
180 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable)
181 {
182 u32 value = readl(ioaddr + GMAC_CONFIG);
183
184 if (enable)
185 value |= GMAC_CONFIG_RE | GMAC_CONFIG_TE;
186 else
187 value &= ~(GMAC_CONFIG_TE | GMAC_CONFIG_RE);
188
189 writel(value, ioaddr + GMAC_CONFIG);
190 }
191
192 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
193 unsigned int high, unsigned int low)
194 {
195 unsigned int hi_addr, lo_addr;
196
197
198 hi_addr = readl(ioaddr + high);
199 lo_addr = readl(ioaddr + low);
200
201
202 addr[0] = lo_addr & 0xff;
203 addr[1] = (lo_addr >> 8) & 0xff;
204 addr[2] = (lo_addr >> 16) & 0xff;
205 addr[3] = (lo_addr >> 24) & 0xff;
206 addr[4] = hi_addr & 0xff;
207 addr[5] = (hi_addr >> 8) & 0xff;
208 }