drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

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This source file includes following definitions.
sun8i_dwmac_dma_reset
sun8i_dwmac_dma_init
sun8i_dwmac_dma_init_rx
sun8i_dwmac_dma_init_tx
sun8i_dwmac_dump_regs
sun8i_dwmac_dump_mac_regs
sun8i_dwmac_enable_dma_irq
sun8i_dwmac_disable_dma_irq
sun8i_dwmac_dma_start_tx
sun8i_dwmac_enable_dma_transmission
sun8i_dwmac_dma_stop_tx
sun8i_dwmac_dma_start_rx
sun8i_dwmac_dma_stop_rx
sun8i_dwmac_dma_interrupt
sun8i_dwmac_dma_operation_mode_rx
sun8i_dwmac_dma_operation_mode_tx
sun8i_dwmac_init
sun8i_dwmac_core_init
sun8i_dwmac_set_mac
sun8i_dwmac_set_umac_addr
sun8i_dwmac_get_umac_addr
sun8i_dwmac_rx_ipc_enable
sun8i_dwmac_set_filter
sun8i_dwmac_flow_ctrl
sun8i_dwmac_reset
get_ephy_nodes
sun8i_dwmac_power_internal_phy
sun8i_dwmac_unpower_internal_phy
mdio_mux_syscon_switch_fn
sun8i_dwmac_register_mdio_mux
sun8i_dwmac_set_syscon
sun8i_dwmac_unset_syscon
sun8i_dwmac_exit
sun8i_dwmac_set_mac_loopback
sun8i_dwmac_setup
sun8i_dwmac_get_syscon_from_dev
sun8i_dwmac_probe
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
   4  *
   5  * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
   6  */
   7 
   8 #include <linux/clk.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/mdio-mux.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_mdio.h>
  16 #include <linux/of_net.h>
  17 #include <linux/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/regmap.h>
  21 #include <linux/stmmac.h>
  22 
  23 #include "stmmac.h"
  24 #include "stmmac_platform.h"
  25 
  26 /* General notes on dwmac-sun8i:
  27  * Locking: no locking is necessary in this file because all necessary locking
  28  *              is done in the "stmmac files"
  29  */
  30 
  31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
  32  * @default_syscon_value:       The default value of the EMAC register in syscon
  33  *                              This value is used for disabling properly EMAC
  34  *                              and used as a good starting value in case of the
  35  *                              boot process(uboot) leave some stuff.
  36  * @syscon_field                reg_field for the syscon's gmac register
  37  * @soc_has_internal_phy:       Does the MAC embed an internal PHY
  38  * @support_mii:                Does the MAC handle MII
  39  * @support_rmii:               Does the MAC handle RMII
  40  * @support_rgmii:              Does the MAC handle RGMII
  41  *
  42  * @rx_delay_max:               Maximum raw value for RX delay chain
  43  * @tx_delay_max:               Maximum raw value for TX delay chain
  44  *                              These two also indicate the bitmask for
  45  *                              the RX and TX delay chain registers. A
  46  *                              value of zero indicates this is not supported.
  47  */
  48 struct emac_variant {
  49         u32 default_syscon_value;
  50         const struct reg_field *syscon_field;
  51         bool soc_has_internal_phy;
  52         bool support_mii;
  53         bool support_rmii;
  54         bool support_rgmii;
  55         u8 rx_delay_max;
  56         u8 tx_delay_max;
  57 };
  58 
  59 /* struct sunxi_priv_data - hold all sunxi private data
  60  * @tx_clk:     reference to MAC TX clock
  61  * @ephy_clk:   reference to the optional EPHY clock for the internal PHY
  62  * @regulator:  reference to the optional regulator
  63  * @rst_ephy:   reference to the optional EPHY reset for the internal PHY
  64  * @variant:    reference to the current board variant
  65  * @regmap:     regmap for using the syscon
  66  * @internal_phy_powered: Does the internal PHY is enabled
  67  * @mux_handle: Internal pointer used by mdio-mux lib
  68  */
  69 struct sunxi_priv_data {
  70         struct clk *tx_clk;
  71         struct clk *ephy_clk;
  72         struct regulator *regulator;
  73         struct reset_control *rst_ephy;
  74         const struct emac_variant *variant;
  75         struct regmap_field *regmap_field;
  76         bool internal_phy_powered;
  77         void *mux_handle;
  78 };
  79 
  80 /* EMAC clock register @ 0x30 in the "system control" address range */
  81 static const struct reg_field sun8i_syscon_reg_field = {
  82         .reg = 0x30,
  83         .lsb = 0,
  84         .msb = 31,
  85 };
  86 
  87 /* EMAC clock register @ 0x164 in the CCU address range */
  88 static const struct reg_field sun8i_ccu_reg_field = {
  89         .reg = 0x164,
  90         .lsb = 0,
  91         .msb = 31,
  92 };
  93 
  94 static const struct emac_variant emac_variant_h3 = {
  95         .default_syscon_value = 0x58000,
  96         .syscon_field = &sun8i_syscon_reg_field,
  97         .soc_has_internal_phy = true,
  98         .support_mii = true,
  99         .support_rmii = true,
 100         .support_rgmii = true,
 101         .rx_delay_max = 31,
 102         .tx_delay_max = 7,
 103 };
 104 
 105 static const struct emac_variant emac_variant_v3s = {
 106         .default_syscon_value = 0x38000,
 107         .syscon_field = &sun8i_syscon_reg_field,
 108         .soc_has_internal_phy = true,
 109         .support_mii = true
 110 };
 111 
 112 static const struct emac_variant emac_variant_a83t = {
 113         .default_syscon_value = 0,
 114         .syscon_field = &sun8i_syscon_reg_field,
 115         .soc_has_internal_phy = false,
 116         .support_mii = true,
 117         .support_rgmii = true,
 118         .rx_delay_max = 31,
 119         .tx_delay_max = 7,
 120 };
 121 
 122 static const struct emac_variant emac_variant_r40 = {
 123         .default_syscon_value = 0,
 124         .syscon_field = &sun8i_ccu_reg_field,
 125         .support_mii = true,
 126         .support_rgmii = true,
 127         .rx_delay_max = 7,
 128 };
 129 
 130 static const struct emac_variant emac_variant_a64 = {
 131         .default_syscon_value = 0,
 132         .syscon_field = &sun8i_syscon_reg_field,
 133         .soc_has_internal_phy = false,
 134         .support_mii = true,
 135         .support_rmii = true,
 136         .support_rgmii = true,
 137         .rx_delay_max = 31,
 138         .tx_delay_max = 7,
 139 };
 140 
 141 static const struct emac_variant emac_variant_h6 = {
 142         .default_syscon_value = 0x50000,
 143         .syscon_field = &sun8i_syscon_reg_field,
 144         /* The "Internal PHY" of H6 is not on the die. It's on the
 145          * co-packaged AC200 chip instead.
 146          */
 147         .soc_has_internal_phy = false,
 148         .support_mii = true,
 149         .support_rmii = true,
 150         .support_rgmii = true,
 151         .rx_delay_max = 31,
 152         .tx_delay_max = 7,
 153 };
 154 
 155 #define EMAC_BASIC_CTL0 0x00
 156 #define EMAC_BASIC_CTL1 0x04
 157 #define EMAC_INT_STA    0x08
 158 #define EMAC_INT_EN     0x0C
 159 #define EMAC_TX_CTL0    0x10
 160 #define EMAC_TX_CTL1    0x14
 161 #define EMAC_TX_FLOW_CTL        0x1C
 162 #define EMAC_TX_DESC_LIST 0x20
 163 #define EMAC_RX_CTL0    0x24
 164 #define EMAC_RX_CTL1    0x28
 165 #define EMAC_RX_DESC_LIST 0x34
 166 #define EMAC_RX_FRM_FLT 0x38
 167 #define EMAC_MDIO_CMD   0x48
 168 #define EMAC_MDIO_DATA  0x4C
 169 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
 170 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
 171 #define EMAC_TX_DMA_STA 0xB0
 172 #define EMAC_TX_CUR_DESC        0xB4
 173 #define EMAC_TX_CUR_BUF 0xB8
 174 #define EMAC_RX_DMA_STA 0xC0
 175 #define EMAC_RX_CUR_DESC        0xC4
 176 #define EMAC_RX_CUR_BUF 0xC8
 177 
 178 /* Use in EMAC_BASIC_CTL0 */
 179 #define EMAC_DUPLEX_FULL        BIT(0)
 180 #define EMAC_LOOPBACK           BIT(1)
 181 #define EMAC_SPEED_1000 0
 182 #define EMAC_SPEED_100 (0x03 << 2)
 183 #define EMAC_SPEED_10 (0x02 << 2)
 184 
 185 /* Use in EMAC_BASIC_CTL1 */
 186 #define EMAC_BURSTLEN_SHIFT             24
 187 
 188 /* Used in EMAC_RX_FRM_FLT */
 189 #define EMAC_FRM_FLT_RXALL              BIT(0)
 190 #define EMAC_FRM_FLT_CTL                BIT(13)
 191 #define EMAC_FRM_FLT_MULTICAST          BIT(16)
 192 
 193 /* Used in RX_CTL1*/
 194 #define EMAC_RX_MD              BIT(1)
 195 #define EMAC_RX_TH_MASK         GENMASK(5, 4)
 196 #define EMAC_RX_TH_32           0
 197 #define EMAC_RX_TH_64           (0x1 << 4)
 198 #define EMAC_RX_TH_96           (0x2 << 4)
 199 #define EMAC_RX_TH_128          (0x3 << 4)
 200 #define EMAC_RX_DMA_EN  BIT(30)
 201 #define EMAC_RX_DMA_START       BIT(31)
 202 
 203 /* Used in TX_CTL1*/
 204 #define EMAC_TX_MD              BIT(1)
 205 #define EMAC_TX_NEXT_FRM        BIT(2)
 206 #define EMAC_TX_TH_MASK         GENMASK(10, 8)
 207 #define EMAC_TX_TH_64           0
 208 #define EMAC_TX_TH_128          (0x1 << 8)
 209 #define EMAC_TX_TH_192          (0x2 << 8)
 210 #define EMAC_TX_TH_256          (0x3 << 8)
 211 #define EMAC_TX_DMA_EN  BIT(30)
 212 #define EMAC_TX_DMA_START       BIT(31)
 213 
 214 /* Used in RX_CTL0 */
 215 #define EMAC_RX_RECEIVER_EN             BIT(31)
 216 #define EMAC_RX_DO_CRC BIT(27)
 217 #define EMAC_RX_FLOW_CTL_EN             BIT(16)
 218 
 219 /* Used in TX_CTL0 */
 220 #define EMAC_TX_TRANSMITTER_EN  BIT(31)
 221 
 222 /* Used in EMAC_TX_FLOW_CTL */
 223 #define EMAC_TX_FLOW_CTL_EN             BIT(0)
 224 
 225 /* Used in EMAC_INT_STA */
 226 #define EMAC_TX_INT             BIT(0)
 227 #define EMAC_TX_DMA_STOP_INT    BIT(1)
 228 #define EMAC_TX_BUF_UA_INT      BIT(2)
 229 #define EMAC_TX_TIMEOUT_INT     BIT(3)
 230 #define EMAC_TX_UNDERFLOW_INT   BIT(4)
 231 #define EMAC_TX_EARLY_INT       BIT(5)
 232 #define EMAC_RX_INT             BIT(8)
 233 #define EMAC_RX_BUF_UA_INT      BIT(9)
 234 #define EMAC_RX_DMA_STOP_INT    BIT(10)
 235 #define EMAC_RX_TIMEOUT_INT     BIT(11)
 236 #define EMAC_RX_OVERFLOW_INT    BIT(12)
 237 #define EMAC_RX_EARLY_INT       BIT(13)
 238 #define EMAC_RGMII_STA_INT      BIT(16)
 239 
 240 #define MAC_ADDR_TYPE_DST BIT(31)
 241 
 242 /* H3 specific bits for EPHY */
 243 #define H3_EPHY_ADDR_SHIFT      20
 244 #define H3_EPHY_CLK_SEL         BIT(18) /* 1: 24MHz, 0: 25MHz */
 245 #define H3_EPHY_LED_POL         BIT(17) /* 1: active low, 0: active high */
 246 #define H3_EPHY_SHUTDOWN        BIT(16) /* 1: shutdown, 0: power up */
 247 #define H3_EPHY_SELECT          BIT(15) /* 1: internal PHY, 0: external PHY */
 248 #define H3_EPHY_MUX_MASK        (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
 249 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID        1
 250 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID        2
 251 
 252 /* H3/A64 specific bits */
 253 #define SYSCON_RMII_EN          BIT(13) /* 1: enable RMII (overrides EPIT) */
 254 
 255 /* Generic system control EMAC_CLK bits */
 256 #define SYSCON_ETXDC_SHIFT              10
 257 #define SYSCON_ERXDC_SHIFT              5
 258 /* EMAC PHY Interface Type */
 259 #define SYSCON_EPIT                     BIT(2) /* 1: RGMII, 0: MII */
 260 #define SYSCON_ETCS_MASK                GENMASK(1, 0)
 261 #define SYSCON_ETCS_MII         0x0
 262 #define SYSCON_ETCS_EXT_GMII    0x1
 263 #define SYSCON_ETCS_INT_GMII    0x2
 264 
 265 /* sun8i_dwmac_dma_reset() - reset the EMAC
 266  * Called from stmmac via stmmac_dma_ops->reset
 267  */
 268 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
 269 {
 270         writel(0, ioaddr + EMAC_RX_CTL1);
 271         writel(0, ioaddr + EMAC_TX_CTL1);
 272         writel(0, ioaddr + EMAC_RX_FRM_FLT);
 273         writel(0, ioaddr + EMAC_RX_DESC_LIST);
 274         writel(0, ioaddr + EMAC_TX_DESC_LIST);
 275         writel(0, ioaddr + EMAC_INT_EN);
 276         writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 277         return 0;
 278 }
 279 
 280 /* sun8i_dwmac_dma_init() - initialize the EMAC
 281  * Called from stmmac via stmmac_dma_ops->init
 282  */
 283 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
 284                                  struct stmmac_dma_cfg *dma_cfg, int atds)
 285 {
 286         writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
 287         writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 288 }
 289 
 290 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,
 291                                     struct stmmac_dma_cfg *dma_cfg,
 292                                     dma_addr_t dma_rx_phy, u32 chan)
 293 {
 294         /* Write RX descriptors address */
 295         writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
 296 }
 297 
 298 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,
 299                                     struct stmmac_dma_cfg *dma_cfg,
 300                                     dma_addr_t dma_tx_phy, u32 chan)
 301 {
 302         /* Write TX descriptors address */
 303         writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
 304 }
 305 
 306 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
 307  * Called from stmmac_dma_ops->dump_regs
 308  * Used for ethtool
 309  */
 310 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
 311 {
 312         int i;
 313 
 314         for (i = 0; i < 0xC8; i += 4) {
 315                 if (i == 0x32 || i == 0x3C)
 316                         continue;
 317                 reg_space[i / 4] = readl(ioaddr + i);
 318         }
 319 }
 320 
 321 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
 322  * Called from stmmac_ops->dump_regs
 323  * Used for ethtool
 324  */
 325 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
 326                                       u32 *reg_space)
 327 {
 328         int i;
 329         void __iomem *ioaddr = hw->pcsr;
 330 
 331         for (i = 0; i < 0xC8; i += 4) {
 332                 if (i == 0x32 || i == 0x3C)
 333                         continue;
 334                 reg_space[i / 4] = readl(ioaddr + i);
 335         }
 336 }
 337 
 338 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
 339 {
 340         writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
 341 }
 342 
 343 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
 344 {
 345         writel(0, ioaddr + EMAC_INT_EN);
 346 }
 347 
 348 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
 349 {
 350         u32 v;
 351 
 352         v = readl(ioaddr + EMAC_TX_CTL1);
 353         v |= EMAC_TX_DMA_START;
 354         v |= EMAC_TX_DMA_EN;
 355         writel(v, ioaddr + EMAC_TX_CTL1);
 356 }
 357 
 358 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
 359 {
 360         u32 v;
 361 
 362         v = readl(ioaddr + EMAC_TX_CTL1);
 363         v |= EMAC_TX_DMA_START;
 364         v |= EMAC_TX_DMA_EN;
 365         writel(v, ioaddr + EMAC_TX_CTL1);
 366 }
 367 
 368 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
 369 {
 370         u32 v;
 371 
 372         v = readl(ioaddr + EMAC_TX_CTL1);
 373         v &= ~EMAC_TX_DMA_EN;
 374         writel(v, ioaddr + EMAC_TX_CTL1);
 375 }
 376 
 377 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
 378 {
 379         u32 v;
 380 
 381         v = readl(ioaddr + EMAC_RX_CTL1);
 382         v |= EMAC_RX_DMA_START;
 383         v |= EMAC_RX_DMA_EN;
 384         writel(v, ioaddr + EMAC_RX_CTL1);
 385 }
 386 
 387 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
 388 {
 389         u32 v;
 390 
 391         v = readl(ioaddr + EMAC_RX_CTL1);
 392         v &= ~EMAC_RX_DMA_EN;
 393         writel(v, ioaddr + EMAC_RX_CTL1);
 394 }
 395 
 396 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
 397                                      struct stmmac_extra_stats *x, u32 chan)
 398 {
 399         u32 v;
 400         int ret = 0;
 401 
 402         v = readl(ioaddr + EMAC_INT_STA);
 403 
 404         if (v & EMAC_TX_INT) {
 405                 ret |= handle_tx;
 406                 x->tx_normal_irq_n++;
 407         }
 408 
 409         if (v & EMAC_TX_DMA_STOP_INT)
 410                 x->tx_process_stopped_irq++;
 411 
 412         if (v & EMAC_TX_BUF_UA_INT)
 413                 x->tx_process_stopped_irq++;
 414 
 415         if (v & EMAC_TX_TIMEOUT_INT)
 416                 ret |= tx_hard_error;
 417 
 418         if (v & EMAC_TX_UNDERFLOW_INT) {
 419                 ret |= tx_hard_error;
 420                 x->tx_undeflow_irq++;
 421         }
 422 
 423         if (v & EMAC_TX_EARLY_INT)
 424                 x->tx_early_irq++;
 425 
 426         if (v & EMAC_RX_INT) {
 427                 ret |= handle_rx;
 428                 x->rx_normal_irq_n++;
 429         }
 430 
 431         if (v & EMAC_RX_BUF_UA_INT)
 432                 x->rx_buf_unav_irq++;
 433 
 434         if (v & EMAC_RX_DMA_STOP_INT)
 435                 x->rx_process_stopped_irq++;
 436 
 437         if (v & EMAC_RX_TIMEOUT_INT)
 438                 ret |= tx_hard_error;
 439 
 440         if (v & EMAC_RX_OVERFLOW_INT) {
 441                 ret |= tx_hard_error;
 442                 x->rx_overflow_irq++;
 443         }
 444 
 445         if (v & EMAC_RX_EARLY_INT)
 446                 x->rx_early_irq++;
 447 
 448         if (v & EMAC_RGMII_STA_INT)
 449                 x->irq_rgmii_n++;
 450 
 451         writel(v, ioaddr + EMAC_INT_STA);
 452 
 453         return ret;
 454 }
 455 
 456 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
 457                                               u32 channel, int fifosz, u8 qmode)
 458 {
 459         u32 v;
 460 
 461         v = readl(ioaddr + EMAC_RX_CTL1);
 462         if (mode == SF_DMA_MODE) {
 463                 v |= EMAC_RX_MD;
 464         } else {
 465                 v &= ~EMAC_RX_MD;
 466                 v &= ~EMAC_RX_TH_MASK;
 467                 if (mode < 32)
 468                         v |= EMAC_RX_TH_32;
 469                 else if (mode < 64)
 470                         v |= EMAC_RX_TH_64;
 471                 else if (mode < 96)
 472                         v |= EMAC_RX_TH_96;
 473                 else if (mode < 128)
 474                         v |= EMAC_RX_TH_128;
 475         }
 476         writel(v, ioaddr + EMAC_RX_CTL1);
 477 }
 478 
 479 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
 480                                               u32 channel, int fifosz, u8 qmode)
 481 {
 482         u32 v;
 483 
 484         v = readl(ioaddr + EMAC_TX_CTL1);
 485         if (mode == SF_DMA_MODE) {
 486                 v |= EMAC_TX_MD;
 487                 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
 488                  * comment is
 489                  * "Operating on second frame increase the performance
 490                  * especially when transmit store-and-forward is used."
 491                  */
 492                 v |= EMAC_TX_NEXT_FRM;
 493         } else {
 494                 v &= ~EMAC_TX_MD;
 495                 v &= ~EMAC_TX_TH_MASK;
 496                 if (mode < 64)
 497                         v |= EMAC_TX_TH_64;
 498                 else if (mode < 128)
 499                         v |= EMAC_TX_TH_128;
 500                 else if (mode < 192)
 501                         v |= EMAC_TX_TH_192;
 502                 else if (mode < 256)
 503                         v |= EMAC_TX_TH_256;
 504         }
 505         writel(v, ioaddr + EMAC_TX_CTL1);
 506 }
 507 
 508 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
 509         .reset = sun8i_dwmac_dma_reset,
 510         .init = sun8i_dwmac_dma_init,
 511         .init_rx_chan = sun8i_dwmac_dma_init_rx,
 512         .init_tx_chan = sun8i_dwmac_dma_init_tx,
 513         .dump_regs = sun8i_dwmac_dump_regs,
 514         .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
 515         .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
 516         .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
 517         .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
 518         .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
 519         .start_tx = sun8i_dwmac_dma_start_tx,
 520         .stop_tx = sun8i_dwmac_dma_stop_tx,
 521         .start_rx = sun8i_dwmac_dma_start_rx,
 522         .stop_rx = sun8i_dwmac_dma_stop_rx,
 523         .dma_interrupt = sun8i_dwmac_dma_interrupt,
 524 };
 525 
 526 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
 527 {
 528         struct sunxi_priv_data *gmac = priv;
 529         int ret;
 530 
 531         if (gmac->regulator) {
 532                 ret = regulator_enable(gmac->regulator);
 533                 if (ret) {
 534                         dev_err(&pdev->dev, "Fail to enable regulator\n");
 535                         return ret;
 536                 }
 537         }
 538 
 539         ret = clk_prepare_enable(gmac->tx_clk);
 540         if (ret) {
 541                 if (gmac->regulator)
 542                         regulator_disable(gmac->regulator);
 543                 dev_err(&pdev->dev, "Could not enable AHB clock\n");
 544                 return ret;
 545         }
 546 
 547         return 0;
 548 }
 549 
 550 static void sun8i_dwmac_core_init(struct mac_device_info *hw,
 551                                   struct net_device *dev)
 552 {
 553         void __iomem *ioaddr = hw->pcsr;
 554         u32 v;
 555 
 556         v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
 557         writel(v, ioaddr + EMAC_BASIC_CTL1);
 558 }
 559 
 560 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
 561 {
 562         u32 t, r;
 563 
 564         t = readl(ioaddr + EMAC_TX_CTL0);
 565         r = readl(ioaddr + EMAC_RX_CTL0);
 566         if (enable) {
 567                 t |= EMAC_TX_TRANSMITTER_EN;
 568                 r |= EMAC_RX_RECEIVER_EN;
 569         } else {
 570                 t &= ~EMAC_TX_TRANSMITTER_EN;
 571                 r &= ~EMAC_RX_RECEIVER_EN;
 572         }
 573         writel(t, ioaddr + EMAC_TX_CTL0);
 574         writel(r, ioaddr + EMAC_RX_CTL0);
 575 }
 576 
 577 /* Set MAC address at slot reg_n
 578  * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
 579  * If addr is NULL, clear the slot
 580  */
 581 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
 582                                       unsigned char *addr,
 583                                       unsigned int reg_n)
 584 {
 585         void __iomem *ioaddr = hw->pcsr;
 586         u32 v;
 587 
 588         if (!addr) {
 589                 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
 590                 return;
 591         }
 592 
 593         stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 594                             EMAC_MACADDR_LO(reg_n));
 595         if (reg_n > 0) {
 596                 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
 597                 v |= MAC_ADDR_TYPE_DST;
 598                 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
 599         }
 600 }
 601 
 602 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
 603                                       unsigned char *addr,
 604                                       unsigned int reg_n)
 605 {
 606         void __iomem *ioaddr = hw->pcsr;
 607 
 608         stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 609                             EMAC_MACADDR_LO(reg_n));
 610 }
 611 
 612 /* caution this function must return non 0 to work */
 613 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
 614 {
 615         void __iomem *ioaddr = hw->pcsr;
 616         u32 v;
 617 
 618         v = readl(ioaddr + EMAC_RX_CTL0);
 619         v |= EMAC_RX_DO_CRC;
 620         writel(v, ioaddr + EMAC_RX_CTL0);
 621 
 622         return 1;
 623 }
 624 
 625 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
 626                                    struct net_device *dev)
 627 {
 628         void __iomem *ioaddr = hw->pcsr;
 629         u32 v;
 630         int i = 1;
 631         struct netdev_hw_addr *ha;
 632         int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
 633 
 634         v = EMAC_FRM_FLT_CTL;
 635 
 636         if (dev->flags & IFF_PROMISC) {
 637                 v = EMAC_FRM_FLT_RXALL;
 638         } else if (dev->flags & IFF_ALLMULTI) {
 639                 v |= EMAC_FRM_FLT_MULTICAST;
 640         } else if (macaddrs <= hw->unicast_filter_entries) {
 641                 if (!netdev_mc_empty(dev)) {
 642                         netdev_for_each_mc_addr(ha, dev) {
 643                                 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 644                                 i++;
 645                         }
 646                 }
 647                 if (!netdev_uc_empty(dev)) {
 648                         netdev_for_each_uc_addr(ha, dev) {
 649                                 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 650                                 i++;
 651                         }
 652                 }
 653         } else {
 654                 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL))
 655                         netdev_info(dev, "Too many address, switching to promiscuous\n");
 656                 v = EMAC_FRM_FLT_RXALL;
 657         }
 658 
 659         /* Disable unused address filter slots */
 660         while (i < hw->unicast_filter_entries)
 661                 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
 662 
 663         writel(v, ioaddr + EMAC_RX_FRM_FLT);
 664 }
 665 
 666 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
 667                                   unsigned int duplex, unsigned int fc,
 668                                   unsigned int pause_time, u32 tx_cnt)
 669 {
 670         void __iomem *ioaddr = hw->pcsr;
 671         u32 v;
 672 
 673         v = readl(ioaddr + EMAC_RX_CTL0);
 674         if (fc == FLOW_AUTO)
 675                 v |= EMAC_RX_FLOW_CTL_EN;
 676         else
 677                 v &= ~EMAC_RX_FLOW_CTL_EN;
 678         writel(v, ioaddr + EMAC_RX_CTL0);
 679 
 680         v = readl(ioaddr + EMAC_TX_FLOW_CTL);
 681         if (fc == FLOW_AUTO)
 682                 v |= EMAC_TX_FLOW_CTL_EN;
 683         else
 684                 v &= ~EMAC_TX_FLOW_CTL_EN;
 685         writel(v, ioaddr + EMAC_TX_FLOW_CTL);
 686 }
 687 
 688 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
 689 {
 690         u32 v;
 691         int err;
 692 
 693         v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
 694         writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
 695 
 696         /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
 697          * need more if no cable plugged. 100ms seems OK
 698          */
 699         err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
 700                                  !(v & 0x01), 100, 100000);
 701 
 702         if (err) {
 703                 dev_err(priv->device, "EMAC reset timeout\n");
 704                 return -EFAULT;
 705         }
 706         return 0;
 707 }
 708 
 709 /* Search in mdio-mux node for internal PHY node and get its clk/reset */
 710 static int get_ephy_nodes(struct stmmac_priv *priv)
 711 {
 712         struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 713         struct device_node *mdio_mux, *iphynode;
 714         struct device_node *mdio_internal;
 715         int ret;
 716 
 717         mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
 718         if (!mdio_mux) {
 719                 dev_err(priv->device, "Cannot get mdio-mux node\n");
 720                 return -ENODEV;
 721         }
 722 
 723         mdio_internal = of_get_compatible_child(mdio_mux,
 724                                                 "allwinner,sun8i-h3-mdio-internal");
 725         of_node_put(mdio_mux);
 726         if (!mdio_internal) {
 727                 dev_err(priv->device, "Cannot get internal_mdio node\n");
 728                 return -ENODEV;
 729         }
 730 
 731         /* Seek for internal PHY */
 732         for_each_child_of_node(mdio_internal, iphynode) {
 733                 gmac->ephy_clk = of_clk_get(iphynode, 0);
 734                 if (IS_ERR(gmac->ephy_clk))
 735                         continue;
 736                 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
 737                 if (IS_ERR(gmac->rst_ephy)) {
 738                         ret = PTR_ERR(gmac->rst_ephy);
 739                         if (ret == -EPROBE_DEFER) {
 740                                 of_node_put(iphynode);
 741                                 of_node_put(mdio_internal);
 742                                 return ret;
 743                         }
 744                         continue;
 745                 }
 746                 dev_info(priv->device, "Found internal PHY node\n");
 747                 of_node_put(iphynode);
 748                 of_node_put(mdio_internal);
 749                 return 0;
 750         }
 751 
 752         of_node_put(mdio_internal);
 753         return -ENODEV;
 754 }
 755 
 756 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
 757 {
 758         struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 759         int ret;
 760 
 761         if (gmac->internal_phy_powered) {
 762                 dev_warn(priv->device, "Internal PHY already powered\n");
 763                 return 0;
 764         }
 765 
 766         dev_info(priv->device, "Powering internal PHY\n");
 767         ret = clk_prepare_enable(gmac->ephy_clk);
 768         if (ret) {
 769                 dev_err(priv->device, "Cannot enable internal PHY\n");
 770                 return ret;
 771         }
 772 
 773         /* Make sure the EPHY is properly reseted, as U-Boot may leave
 774          * it at deasserted state, and thus it may fail to reset EMAC.
 775          */
 776         reset_control_assert(gmac->rst_ephy);
 777 
 778         ret = reset_control_deassert(gmac->rst_ephy);
 779         if (ret) {
 780                 dev_err(priv->device, "Cannot deassert internal phy\n");
 781                 clk_disable_unprepare(gmac->ephy_clk);
 782                 return ret;
 783         }
 784 
 785         gmac->internal_phy_powered = true;
 786 
 787         return 0;
 788 }
 789 
 790 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
 791 {
 792         if (!gmac->internal_phy_powered)
 793                 return 0;
 794 
 795         clk_disable_unprepare(gmac->ephy_clk);
 796         reset_control_assert(gmac->rst_ephy);
 797         gmac->internal_phy_powered = false;
 798         return 0;
 799 }
 800 
 801 /* MDIO multiplexing switch function
 802  * This function is called by the mdio-mux layer when it thinks the mdio bus
 803  * multiplexer needs to switch.
 804  * 'current_child' is the current value of the mux register
 805  * 'desired_child' is the value of the 'reg' property of the target child MDIO
 806  * node.
 807  * The first time this function is called, current_child == -1.
 808  * If current_child == desired_child, then the mux is already set to the
 809  * correct bus.
 810  */
 811 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
 812                                      void *data)
 813 {
 814         struct stmmac_priv *priv = data;
 815         struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 816         u32 reg, val;
 817         int ret = 0;
 818         bool need_power_ephy = false;
 819 
 820         if (current_child ^ desired_child) {
 821                 regmap_field_read(gmac->regmap_field, &reg);
 822                 switch (desired_child) {
 823                 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
 824                         dev_info(priv->device, "Switch mux to internal PHY");
 825                         val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
 826 
 827                         need_power_ephy = true;
 828                         break;
 829                 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
 830                         dev_info(priv->device, "Switch mux to external PHY");
 831                         val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
 832                         need_power_ephy = false;
 833                         break;
 834                 default:
 835                         dev_err(priv->device, "Invalid child ID %x\n",
 836                                 desired_child);
 837                         return -EINVAL;
 838                 }
 839                 regmap_field_write(gmac->regmap_field, val);
 840                 if (need_power_ephy) {
 841                         ret = sun8i_dwmac_power_internal_phy(priv);
 842                         if (ret)
 843                                 return ret;
 844                 } else {
 845                         sun8i_dwmac_unpower_internal_phy(gmac);
 846                 }
 847                 /* After changing syscon value, the MAC need reset or it will
 848                  * use the last value (and so the last PHY set).
 849                  */
 850                 ret = sun8i_dwmac_reset(priv);
 851         }
 852         return ret;
 853 }
 854 
 855 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
 856 {
 857         int ret;
 858         struct device_node *mdio_mux;
 859         struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 860 
 861         mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
 862         if (!mdio_mux)
 863                 return -ENODEV;
 864 
 865         ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
 866                             &gmac->mux_handle, priv, priv->mii);
 867         return ret;
 868 }
 869 
 870 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
 871 {
 872         struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 873         struct device_node *node = priv->device->of_node;
 874         int ret;
 875         u32 reg, val;
 876 
 877         ret = regmap_field_read(gmac->regmap_field, &val);
 878         if (ret) {
 879                 dev_err(priv->device, "Fail to read from regmap field.\n");
 880                 return ret;
 881         }
 882 
 883         reg = gmac->variant->default_syscon_value;
 884         if (reg != val)
 885                 dev_warn(priv->device,
 886                          "Current syscon value is not the default %x (expect %x)\n",
 887                          val, reg);
 888 
 889         if (gmac->variant->soc_has_internal_phy) {
 890                 if (of_property_read_bool(node, "allwinner,leds-active-low"))
 891                         reg |= H3_EPHY_LED_POL;
 892                 else
 893                         reg &= ~H3_EPHY_LED_POL;
 894 
 895                 /* Force EPHY xtal frequency to 24MHz. */
 896                 reg |= H3_EPHY_CLK_SEL;
 897 
 898                 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
 899                 if (ret < 0) {
 900                         dev_err(priv->device, "Could not parse MDIO addr\n");
 901                         return ret;
 902                 }
 903                 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
 904                  * address. No need to mask it again.
 905                  */
 906                 reg |= 1 << H3_EPHY_ADDR_SHIFT;
 907         } else {
 908                 /* For SoCs without internal PHY the PHY selection bit should be
 909                  * set to 0 (external PHY).
 910                  */
 911                 reg &= ~H3_EPHY_SELECT;
 912         }
 913 
 914         if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
 915                 if (val % 100) {
 916                         dev_err(priv->device, "tx-delay must be a multiple of 100\n");
 917                         return -EINVAL;
 918                 }
 919                 val /= 100;
 920                 dev_dbg(priv->device, "set tx-delay to %x\n", val);
 921                 if (val <= gmac->variant->tx_delay_max) {
 922                         reg &= ~(gmac->variant->tx_delay_max <<
 923                                  SYSCON_ETXDC_SHIFT);
 924                         reg |= (val << SYSCON_ETXDC_SHIFT);
 925                 } else {
 926                         dev_err(priv->device, "Invalid TX clock delay: %d\n",
 927                                 val);
 928                         return -EINVAL;
 929                 }
 930         }
 931 
 932         if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
 933                 if (val % 100) {
 934                         dev_err(priv->device, "rx-delay must be a multiple of 100\n");
 935                         return -EINVAL;
 936                 }
 937                 val /= 100;
 938                 dev_dbg(priv->device, "set rx-delay to %x\n", val);
 939                 if (val <= gmac->variant->rx_delay_max) {
 940                         reg &= ~(gmac->variant->rx_delay_max <<
 941                                  SYSCON_ERXDC_SHIFT);
 942                         reg |= (val << SYSCON_ERXDC_SHIFT);
 943                 } else {
 944                         dev_err(priv->device, "Invalid RX clock delay: %d\n",
 945                                 val);
 946                         return -EINVAL;
 947                 }
 948         }
 949 
 950         /* Clear interface mode bits */
 951         reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
 952         if (gmac->variant->support_rmii)
 953                 reg &= ~SYSCON_RMII_EN;
 954 
 955         switch (priv->plat->interface) {
 956         case PHY_INTERFACE_MODE_MII:
 957                 /* default */
 958                 break;
 959         case PHY_INTERFACE_MODE_RGMII:
 960         case PHY_INTERFACE_MODE_RGMII_ID:
 961         case PHY_INTERFACE_MODE_RGMII_RXID:
 962         case PHY_INTERFACE_MODE_RGMII_TXID:
 963                 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
 964                 break;
 965         case PHY_INTERFACE_MODE_RMII:
 966                 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
 967                 break;
 968         default:
 969                 dev_err(priv->device, "Unsupported interface mode: %s",
 970                         phy_modes(priv->plat->interface));
 971                 return -EINVAL;
 972         }
 973 
 974         regmap_field_write(gmac->regmap_field, reg);
 975 
 976         return 0;
 977 }
 978 
 979 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
 980 {
 981         u32 reg = gmac->variant->default_syscon_value;
 982 
 983         regmap_field_write(gmac->regmap_field, reg);
 984 }
 985 
 986 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
 987 {
 988         struct sunxi_priv_data *gmac = priv;
 989 
 990         if (gmac->variant->soc_has_internal_phy) {
 991                 /* sun8i_dwmac_exit could be called with mdiomux uninit */
 992                 if (gmac->mux_handle)
 993                         mdio_mux_uninit(gmac->mux_handle);
 994                 if (gmac->internal_phy_powered)
 995                         sun8i_dwmac_unpower_internal_phy(gmac);
 996         }
 997 
 998         sun8i_dwmac_unset_syscon(gmac);
 999 
1000         reset_control_put(gmac->rst_ephy);
1001 
1002         clk_disable_unprepare(gmac->tx_clk);
1003 
1004         if (gmac->regulator)
1005                 regulator_disable(gmac->regulator);
1006 }
1007 
1008 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
1009 {
1010         u32 value = readl(ioaddr + EMAC_BASIC_CTL0);
1011 
1012         if (enable)
1013                 value |= EMAC_LOOPBACK;
1014         else
1015                 value &= ~EMAC_LOOPBACK;
1016 
1017         writel(value, ioaddr + EMAC_BASIC_CTL0);
1018 }
1019 
1020 static const struct stmmac_ops sun8i_dwmac_ops = {
1021         .core_init = sun8i_dwmac_core_init,
1022         .set_mac = sun8i_dwmac_set_mac,
1023         .dump_regs = sun8i_dwmac_dump_mac_regs,
1024         .rx_ipc = sun8i_dwmac_rx_ipc_enable,
1025         .set_filter = sun8i_dwmac_set_filter,
1026         .flow_ctrl = sun8i_dwmac_flow_ctrl,
1027         .set_umac_addr = sun8i_dwmac_set_umac_addr,
1028         .get_umac_addr = sun8i_dwmac_get_umac_addr,
1029         .set_mac_loopback = sun8i_dwmac_set_mac_loopback,
1030 };
1031 
1032 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
1033 {
1034         struct mac_device_info *mac;
1035         struct stmmac_priv *priv = ppriv;
1036         int ret;
1037 
1038         mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1039         if (!mac)
1040                 return NULL;
1041 
1042         ret = sun8i_dwmac_set_syscon(priv);
1043         if (ret)
1044                 return NULL;
1045 
1046         mac->pcsr = priv->ioaddr;
1047         mac->mac = &sun8i_dwmac_ops;
1048         mac->dma = &sun8i_dwmac_dma_ops;
1049 
1050         priv->dev->priv_flags |= IFF_UNICAST_FLT;
1051 
1052         /* The loopback bit seems to be re-set when link change
1053          * Simply mask it each time
1054          * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1055          */
1056         mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1057         mac->link.speed10 = EMAC_SPEED_10;
1058         mac->link.speed100 = EMAC_SPEED_100;
1059         mac->link.speed1000 = EMAC_SPEED_1000;
1060         mac->link.duplex = EMAC_DUPLEX_FULL;
1061         mac->mii.addr = EMAC_MDIO_CMD;
1062         mac->mii.data = EMAC_MDIO_DATA;
1063         mac->mii.reg_shift = 4;
1064         mac->mii.reg_mask = GENMASK(8, 4);
1065         mac->mii.addr_shift = 12;
1066         mac->mii.addr_mask = GENMASK(16, 12);
1067         mac->mii.clk_csr_shift = 20;
1068         mac->mii.clk_csr_mask = GENMASK(22, 20);
1069         mac->unicast_filter_entries = 8;
1070 
1071         /* Synopsys Id is not available */
1072         priv->synopsys_id = 0;
1073 
1074         return mac;
1075 }
1076 
1077 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1078 {
1079         struct device_node *syscon_node;
1080         struct platform_device *syscon_pdev;
1081         struct regmap *regmap = NULL;
1082 
1083         syscon_node = of_parse_phandle(node, "syscon", 0);
1084         if (!syscon_node)
1085                 return ERR_PTR(-ENODEV);
1086 
1087         syscon_pdev = of_find_device_by_node(syscon_node);
1088         if (!syscon_pdev) {
1089                 /* platform device might not be probed yet */
1090                 regmap = ERR_PTR(-EPROBE_DEFER);
1091                 goto out_put_node;
1092         }
1093 
1094         /* If no regmap is found then the other device driver is at fault */
1095         regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1096         if (!regmap)
1097                 regmap = ERR_PTR(-EINVAL);
1098 
1099         platform_device_put(syscon_pdev);
1100 out_put_node:
1101         of_node_put(syscon_node);
1102         return regmap;
1103 }
1104 
1105 static int sun8i_dwmac_probe(struct platform_device *pdev)
1106 {
1107         struct plat_stmmacenet_data *plat_dat;
1108         struct stmmac_resources stmmac_res;
1109         struct sunxi_priv_data *gmac;
1110         struct device *dev = &pdev->dev;
1111         int ret;
1112         struct stmmac_priv *priv;
1113         struct net_device *ndev;
1114         struct regmap *regmap;
1115 
1116         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1117         if (ret)
1118                 return ret;
1119 
1120         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1121         if (IS_ERR(plat_dat))
1122                 return PTR_ERR(plat_dat);
1123 
1124         gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1125         if (!gmac)
1126                 return -ENOMEM;
1127 
1128         gmac->variant = of_device_get_match_data(&pdev->dev);
1129         if (!gmac->variant) {
1130                 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1131                 return -EINVAL;
1132         }
1133 
1134         gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
1135         if (IS_ERR(gmac->tx_clk)) {
1136                 dev_err(dev, "Could not get TX clock\n");
1137                 return PTR_ERR(gmac->tx_clk);
1138         }
1139 
1140         /* Optional regulator for PHY */
1141         gmac->regulator = devm_regulator_get_optional(dev, "phy");
1142         if (IS_ERR(gmac->regulator)) {
1143                 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1144                         return -EPROBE_DEFER;
1145                 dev_info(dev, "No regulator found\n");
1146                 gmac->regulator = NULL;
1147         }
1148 
1149         /* The "GMAC clock control" register might be located in the
1150          * CCU address range (on the R40), or the system control address
1151          * range (on most other sun8i and later SoCs).
1152          *
1153          * The former controls most if not all clocks in the SoC. The
1154          * latter has an SoC identification register, and on some SoCs,
1155          * controls to map device specific SRAM to either the intended
1156          * peripheral, or the CPU address space.
1157          *
1158          * In either case, there should be a coordinated and restricted
1159          * method of accessing the register needed here. This is done by
1160          * having the device export a custom regmap, instead of a generic
1161          * syscon, which grants all access to all registers.
1162          *
1163          * To support old device trees, we fall back to using the syscon
1164          * interface if possible.
1165          */
1166         regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1167         if (IS_ERR(regmap))
1168                 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1169                                                          "syscon");
1170         if (IS_ERR(regmap)) {
1171                 ret = PTR_ERR(regmap);
1172                 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1173                 return ret;
1174         }
1175 
1176         gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1177                                                      *gmac->variant->syscon_field);
1178         if (IS_ERR(gmac->regmap_field)) {
1179                 ret = PTR_ERR(gmac->regmap_field);
1180                 dev_err(dev, "Unable to map syscon register: %d\n", ret);
1181                 return ret;
1182         }
1183 
1184         ret = of_get_phy_mode(dev->of_node);
1185         if (ret < 0)
1186                 return -EINVAL;
1187         plat_dat->interface = ret;
1188 
1189         /* platform data specifying hardware features and callbacks.
1190          * hardware features were copied from Allwinner drivers.
1191          */
1192         plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1193         plat_dat->tx_coe = 1;
1194         plat_dat->has_sun8i = true;
1195         plat_dat->bsp_priv = gmac;
1196         plat_dat->init = sun8i_dwmac_init;
1197         plat_dat->exit = sun8i_dwmac_exit;
1198         plat_dat->setup = sun8i_dwmac_setup;
1199 
1200         ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1201         if (ret)
1202                 return ret;
1203 
1204         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1205         if (ret)
1206                 goto dwmac_exit;
1207 
1208         ndev = dev_get_drvdata(&pdev->dev);
1209         priv = netdev_priv(ndev);
1210         /* The mux must be registered after parent MDIO
1211          * so after stmmac_dvr_probe()
1212          */
1213         if (gmac->variant->soc_has_internal_phy) {
1214                 ret = get_ephy_nodes(priv);
1215                 if (ret)
1216                         goto dwmac_exit;
1217                 ret = sun8i_dwmac_register_mdio_mux(priv);
1218                 if (ret) {
1219                         dev_err(&pdev->dev, "Failed to register mux\n");
1220                         goto dwmac_mux;
1221                 }
1222         } else {
1223                 ret = sun8i_dwmac_reset(priv);
1224                 if (ret)
1225                         goto dwmac_exit;
1226         }
1227 
1228         return ret;
1229 dwmac_mux:
1230         sun8i_dwmac_unset_syscon(gmac);
1231 dwmac_exit:
1232         stmmac_pltfr_remove(pdev);
1233 return ret;
1234 }
1235 
1236 static const struct of_device_id sun8i_dwmac_match[] = {
1237         { .compatible = "allwinner,sun8i-h3-emac",
1238                 .data = &emac_variant_h3 },
1239         { .compatible = "allwinner,sun8i-v3s-emac",
1240                 .data = &emac_variant_v3s },
1241         { .compatible = "allwinner,sun8i-a83t-emac",
1242                 .data = &emac_variant_a83t },
1243         { .compatible = "allwinner,sun8i-r40-gmac",
1244                 .data = &emac_variant_r40 },
1245         { .compatible = "allwinner,sun50i-a64-emac",
1246                 .data = &emac_variant_a64 },
1247         { .compatible = "allwinner,sun50i-h6-emac",
1248                 .data = &emac_variant_h6 },
1249         { }
1250 };
1251 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1252 
1253 static struct platform_driver sun8i_dwmac_driver = {
1254         .probe  = sun8i_dwmac_probe,
1255         .remove = stmmac_pltfr_remove,
1256         .driver = {
1257                 .name           = "dwmac-sun8i",
1258                 .pm             = &stmmac_pltfr_pm_ops,
1259                 .of_match_table = sun8i_dwmac_match,
1260         },
1261 };
1262 module_platform_driver(sun8i_dwmac_driver);
1263 
1264 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1265 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1266 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

DEFINITIONS
