1
2
3
4 #ifndef __HCLGE_ERR_H
5 #define __HCLGE_ERR_H
6
7 #include "hclge_main.h"
8 #include "hnae3.h"
9
10 #define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10
11 #define HCLGE_PF_RAS_INT_MIN_BD_NUM 4
12 #define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10
13 #define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4
14
15 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
16 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
17 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
18
19 #define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800
20 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
21
22 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
23 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
24 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
25 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
26 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
27 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
28 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
29 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
30 #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
31 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
32 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
33 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
34 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
35 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
36 #define HCLGE_IGU_ERR_INT_EN 0x0000066F
37 #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
38 #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
39 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
40 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
41 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
42 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
43 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
44 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003
45 #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
46 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
47 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
48 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
49 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
50 #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
51 #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
52 #define HCLGE_NCSI_ERR_INT_EN 0x3
53 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
54 #define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
55 #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
56 #define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
57 #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
58 #define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
59 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
60 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
61 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
62 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
63 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
64 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
65 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
66 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
67 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
68 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
69 #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
70 #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
71 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
72 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
73 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
74 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
75 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
76 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
77 #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
78 #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
79 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
80 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
81 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
82 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
83
84 #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
85 #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
86 #define HCLGE_IGU_INT_MASK GENMASK(3, 0)
87 #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
88 #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
89 #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
90 #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)
91 #define HCLGE_PPU_PF_INT_RAS_MASK 0x18
92 #define HCLGE_PPU_PF_INT_MSIX_MASK 0x26
93 #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01
94 #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
95 #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
96 #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
97
98 #define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
99 #define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
100 #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
101 #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
102 #define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
103 #define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
104 #define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)
105 #define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
106 #define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
107 #define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
108 #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
109
110 enum hclge_err_int_type {
111 HCLGE_ERR_INT_MSIX = 0,
112 HCLGE_ERR_INT_RAS_CE = 1,
113 HCLGE_ERR_INT_RAS_NFE = 2,
114 HCLGE_ERR_INT_RAS_FE = 3,
115 };
116
117 struct hclge_hw_blk {
118 u32 msk;
119 const char *name;
120 int (*config_err_int)(struct hclge_dev *hdev, bool en);
121 };
122
123 struct hclge_hw_error {
124 u32 int_msk;
125 const char *msg;
126 enum hnae3_reset_type reset_level;
127 };
128
129 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
130 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
131 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
132 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
133 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
134 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
135 unsigned long *reset_requests);
136 #endif