1
2
3
4 #ifndef __HCLGE_DEBUGFS_H
5 #define __HCLGE_DEBUGFS_H
6
7 #include <linux/etherdevice.h>
8 #include "hclge_cmd.h"
9
10 #define HCLGE_DBG_BUF_LEN 256
11 #define HCLGE_DBG_MNG_TBL_MAX 64
12
13 #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0)
14 #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1)
15 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2)
16 #define HCLGE_DBG_MNG_E_TYPE_B BIT(11)
17 #define HCLGE_DBG_MNG_DROP_B BIT(13)
18 #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF
19 #define HCLGE_DBG_MNG_PF_ID 0x0007
20 #define HCLGE_DBG_MNG_VF_ID 0x00FF
21
22
23 #define HCLGE_DBG_DFX_BIOS_OFFSET 1
24 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2
25 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3
26 #define HCLGE_DBG_DFX_IGU_OFFSET 4
27 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5
28
29 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6
30 #define HCLGE_DBG_DFX_NCSI_OFFSET 7
31 #define HCLGE_DBG_DFX_RTC_OFFSET 8
32 #define HCLGE_DBG_DFX_PPP_OFFSET 9
33 #define HCLGE_DBG_DFX_RCB_OFFSET 10
34 #define HCLGE_DBG_DFX_TQP_OFFSET 11
35
36 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12
37
38 #pragma pack(1)
39
40 struct hclge_qos_pri_map_cmd {
41 u8 pri0_tc : 4,
42 pri1_tc : 4;
43 u8 pri2_tc : 4,
44 pri3_tc : 4;
45 u8 pri4_tc : 4,
46 pri5_tc : 4;
47 u8 pri6_tc : 4,
48 pri7_tc : 4;
49 u8 vlan_pri : 4,
50 rev : 4;
51 };
52
53 struct hclge_dbg_bitmap_cmd {
54 union {
55 u8 bitmap;
56 struct {
57 u8 bit0 : 1,
58 bit1 : 1,
59 bit2 : 1,
60 bit3 : 1,
61 bit4 : 1,
62 bit5 : 1,
63 bit6 : 1,
64 bit7 : 1;
65 };
66 };
67 };
68
69 struct hclge_dbg_reg_common_msg {
70 int msg_num;
71 int offset;
72 enum hclge_opcode_type cmd;
73 };
74
75 #define HCLGE_DBG_MAX_DFX_MSG_LEN 60
76 struct hclge_dbg_dfx_message {
77 int flag;
78 char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
79 };
80
81 #define HCLGE_DBG_MAC_REG_TYPE_LEN 32
82 struct hclge_dbg_reg_type_info {
83 const char *reg_type;
84 struct hclge_dbg_dfx_message *dfx_msg;
85 struct hclge_dbg_reg_common_msg reg_msg;
86 };
87
88 #pragma pack()
89
90 static struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
91 {false, "Reserved"},
92 {true, "BP_CPU_STATE"},
93 {true, "DFX_MSIX_INFO_NIC_0"},
94 {true, "DFX_MSIX_INFO_NIC_1"},
95 {true, "DFX_MSIX_INFO_NIC_2"},
96 {true, "DFX_MSIX_INFO_NIC_3"},
97
98 {true, "DFX_MSIX_INFO_ROC_0"},
99 {true, "DFX_MSIX_INFO_ROC_1"},
100 {true, "DFX_MSIX_INFO_ROC_2"},
101 {true, "DFX_MSIX_INFO_ROC_3"},
102 {false, "Reserved"},
103 {false, "Reserved"},
104 };
105
106 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = {
107 {false, "Reserved"},
108 {true, "SSU_ETS_PORT_STATUS"},
109 {true, "SSU_ETS_TCG_STATUS"},
110 {false, "Reserved"},
111 {false, "Reserved"},
112 {true, "SSU_BP_STATUS_0"},
113
114 {true, "SSU_BP_STATUS_1"},
115 {true, "SSU_BP_STATUS_2"},
116 {true, "SSU_BP_STATUS_3"},
117 {true, "SSU_BP_STATUS_4"},
118 {true, "SSU_BP_STATUS_5"},
119 {true, "SSU_MAC_TX_PFC_IND"},
120
121 {true, "MAC_SSU_RX_PFC_IND"},
122 {true, "BTMP_AGEING_ST_B0"},
123 {true, "BTMP_AGEING_ST_B1"},
124 {true, "BTMP_AGEING_ST_B2"},
125 {false, "Reserved"},
126 {false, "Reserved"},
127
128 {true, "FULL_DROP_NUM"},
129 {true, "PART_DROP_NUM"},
130 {true, "PPP_KEY_DROP_NUM"},
131 {true, "PPP_RLT_DROP_NUM"},
132 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"},
133 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"},
134
135 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"},
136 {true, "NCSI_PACKET_CURR_BUFFER_CNT"},
137 {true, "BTMP_AGEING_RLS_CNT_BANK0"},
138 {true, "BTMP_AGEING_RLS_CNT_BANK1"},
139 {true, "BTMP_AGEING_RLS_CNT_BANK2"},
140 {true, "SSU_MB_RD_RLT_DROP_CNT"},
141
142 {true, "SSU_PPP_MAC_KEY_NUM_L"},
143 {true, "SSU_PPP_MAC_KEY_NUM_H"},
144 {true, "SSU_PPP_HOST_KEY_NUM_L"},
145 {true, "SSU_PPP_HOST_KEY_NUM_H"},
146 {true, "PPP_SSU_MAC_RLT_NUM_L"},
147 {true, "PPP_SSU_MAC_RLT_NUM_H"},
148
149 {true, "PPP_SSU_HOST_RLT_NUM_L"},
150 {true, "PPP_SSU_HOST_RLT_NUM_H"},
151 {true, "NCSI_RX_PACKET_IN_CNT_L"},
152 {true, "NCSI_RX_PACKET_IN_CNT_H"},
153 {true, "NCSI_TX_PACKET_OUT_CNT_L"},
154 {true, "NCSI_TX_PACKET_OUT_CNT_H"},
155
156 {true, "SSU_KEY_DROP_NUM"},
157 {true, "MB_UNCOPY_NUM"},
158 {true, "RX_OQ_DROP_PKT_CNT"},
159 {true, "TX_OQ_DROP_PKT_CNT"},
160 {true, "BANK_UNBALANCE_DROP_CNT"},
161 {true, "BANK_UNBALANCE_RX_DROP_CNT"},
162
163 {true, "NIC_L2_ERR_DROP_PKT_CNT"},
164 {true, "ROC_L2_ERR_DROP_PKT_CNT"},
165 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"},
166 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"},
167 {true, "RX_OQ_GLB_DROP_PKT_CNT"},
168 {false, "Reserved"},
169
170 {true, "LO_PRI_UNICAST_CUR_CNT"},
171 {true, "HI_PRI_MULTICAST_CUR_CNT"},
172 {true, "LO_PRI_MULTICAST_CUR_CNT"},
173 {false, "Reserved"},
174 {false, "Reserved"},
175 {false, "Reserved"},
176 };
177
178 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = {
179 {true, "prt_id"},
180 {true, "PACKET_TC_CURR_BUFFER_CNT_0"},
181 {true, "PACKET_TC_CURR_BUFFER_CNT_1"},
182 {true, "PACKET_TC_CURR_BUFFER_CNT_2"},
183 {true, "PACKET_TC_CURR_BUFFER_CNT_3"},
184 {true, "PACKET_TC_CURR_BUFFER_CNT_4"},
185
186 {true, "PACKET_TC_CURR_BUFFER_CNT_5"},
187 {true, "PACKET_TC_CURR_BUFFER_CNT_6"},
188 {true, "PACKET_TC_CURR_BUFFER_CNT_7"},
189 {true, "PACKET_CURR_BUFFER_CNT"},
190 {false, "Reserved"},
191 {false, "Reserved"},
192
193 {true, "RX_PACKET_IN_CNT_L"},
194 {true, "RX_PACKET_IN_CNT_H"},
195 {true, "RX_PACKET_OUT_CNT_L"},
196 {true, "RX_PACKET_OUT_CNT_H"},
197 {true, "TX_PACKET_IN_CNT_L"},
198 {true, "TX_PACKET_IN_CNT_H"},
199
200 {true, "TX_PACKET_OUT_CNT_L"},
201 {true, "TX_PACKET_OUT_CNT_H"},
202 {true, "ROC_RX_PACKET_IN_CNT_L"},
203 {true, "ROC_RX_PACKET_IN_CNT_H"},
204 {true, "ROC_TX_PACKET_OUT_CNT_L"},
205 {true, "ROC_TX_PACKET_OUT_CNT_H"},
206
207 {true, "RX_PACKET_TC_IN_CNT_0_L"},
208 {true, "RX_PACKET_TC_IN_CNT_0_H"},
209 {true, "RX_PACKET_TC_IN_CNT_1_L"},
210 {true, "RX_PACKET_TC_IN_CNT_1_H"},
211 {true, "RX_PACKET_TC_IN_CNT_2_L"},
212 {true, "RX_PACKET_TC_IN_CNT_2_H"},
213
214 {true, "RX_PACKET_TC_IN_CNT_3_L"},
215 {true, "RX_PACKET_TC_IN_CNT_3_H"},
216 {true, "RX_PACKET_TC_IN_CNT_4_L"},
217 {true, "RX_PACKET_TC_IN_CNT_4_H"},
218 {true, "RX_PACKET_TC_IN_CNT_5_L"},
219 {true, "RX_PACKET_TC_IN_CNT_5_H"},
220
221 {true, "RX_PACKET_TC_IN_CNT_6_L"},
222 {true, "RX_PACKET_TC_IN_CNT_6_H"},
223 {true, "RX_PACKET_TC_IN_CNT_7_L"},
224 {true, "RX_PACKET_TC_IN_CNT_7_H"},
225 {true, "RX_PACKET_TC_OUT_CNT_0_L"},
226 {true, "RX_PACKET_TC_OUT_CNT_0_H"},
227
228 {true, "RX_PACKET_TC_OUT_CNT_1_L"},
229 {true, "RX_PACKET_TC_OUT_CNT_1_H"},
230 {true, "RX_PACKET_TC_OUT_CNT_2_L"},
231 {true, "RX_PACKET_TC_OUT_CNT_2_H"},
232 {true, "RX_PACKET_TC_OUT_CNT_3_L"},
233 {true, "RX_PACKET_TC_OUT_CNT_3_H"},
234
235 {true, "RX_PACKET_TC_OUT_CNT_4_L"},
236 {true, "RX_PACKET_TC_OUT_CNT_4_H"},
237 {true, "RX_PACKET_TC_OUT_CNT_5_L"},
238 {true, "RX_PACKET_TC_OUT_CNT_5_H"},
239 {true, "RX_PACKET_TC_OUT_CNT_6_L"},
240 {true, "RX_PACKET_TC_OUT_CNT_6_H"},
241
242 {true, "RX_PACKET_TC_OUT_CNT_7_L"},
243 {true, "RX_PACKET_TC_OUT_CNT_7_H"},
244 {true, "TX_PACKET_TC_IN_CNT_0_L"},
245 {true, "TX_PACKET_TC_IN_CNT_0_H"},
246 {true, "TX_PACKET_TC_IN_CNT_1_L"},
247 {true, "TX_PACKET_TC_IN_CNT_1_H"},
248
249 {true, "TX_PACKET_TC_IN_CNT_2_L"},
250 {true, "TX_PACKET_TC_IN_CNT_2_H"},
251 {true, "TX_PACKET_TC_IN_CNT_3_L"},
252 {true, "TX_PACKET_TC_IN_CNT_3_H"},
253 {true, "TX_PACKET_TC_IN_CNT_4_L"},
254 {true, "TX_PACKET_TC_IN_CNT_4_H"},
255
256 {true, "TX_PACKET_TC_IN_CNT_5_L"},
257 {true, "TX_PACKET_TC_IN_CNT_5_H"},
258 {true, "TX_PACKET_TC_IN_CNT_6_L"},
259 {true, "TX_PACKET_TC_IN_CNT_6_H"},
260 {true, "TX_PACKET_TC_IN_CNT_7_L"},
261 {true, "TX_PACKET_TC_IN_CNT_7_H"},
262
263 {true, "TX_PACKET_TC_OUT_CNT_0_L"},
264 {true, "TX_PACKET_TC_OUT_CNT_0_H"},
265 {true, "TX_PACKET_TC_OUT_CNT_1_L"},
266 {true, "TX_PACKET_TC_OUT_CNT_1_H"},
267 {true, "TX_PACKET_TC_OUT_CNT_2_L"},
268 {true, "TX_PACKET_TC_OUT_CNT_2_H"},
269
270 {true, "TX_PACKET_TC_OUT_CNT_3_L"},
271 {true, "TX_PACKET_TC_OUT_CNT_3_H"},
272 {true, "TX_PACKET_TC_OUT_CNT_4_L"},
273 {true, "TX_PACKET_TC_OUT_CNT_4_H"},
274 {true, "TX_PACKET_TC_OUT_CNT_5_L"},
275 {true, "TX_PACKET_TC_OUT_CNT_5_H"},
276
277 {true, "TX_PACKET_TC_OUT_CNT_6_L"},
278 {true, "TX_PACKET_TC_OUT_CNT_6_H"},
279 {true, "TX_PACKET_TC_OUT_CNT_7_L"},
280 {true, "TX_PACKET_TC_OUT_CNT_7_H"},
281 {false, "Reserved"},
282 {false, "Reserved"},
283 };
284
285 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = {
286 {true, "OQ_INDEX"},
287 {true, "QUEUE_CNT"},
288 {false, "Reserved"},
289 {false, "Reserved"},
290 {false, "Reserved"},
291 {false, "Reserved"},
292 };
293
294 static struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {
295 {true, "prt_id"},
296 {true, "IGU_RX_ERR_PKT"},
297 {true, "IGU_RX_NO_SOF_PKT"},
298 {true, "EGU_TX_1588_SHORT_PKT"},
299 {true, "EGU_TX_1588_PKT"},
300 {true, "EGU_TX_ERR_PKT"},
301
302 {true, "IGU_RX_OUT_L2_PKT"},
303 {true, "IGU_RX_OUT_L3_PKT"},
304 {true, "IGU_RX_OUT_L4_PKT"},
305 {true, "IGU_RX_IN_L2_PKT"},
306 {true, "IGU_RX_IN_L3_PKT"},
307 {true, "IGU_RX_IN_L4_PKT"},
308
309 {true, "IGU_RX_EL3E_PKT"},
310 {true, "IGU_RX_EL4E_PKT"},
311 {true, "IGU_RX_L3E_PKT"},
312 {true, "IGU_RX_L4E_PKT"},
313 {true, "IGU_RX_ROCEE_PKT"},
314 {true, "IGU_RX_OUT_UDP0_PKT"},
315
316 {true, "IGU_RX_IN_UDP0_PKT"},
317 {false, "Reserved"},
318 {false, "Reserved"},
319 {false, "Reserved"},
320 {false, "Reserved"},
321 {false, "Reserved"},
322
323 {true, "IGU_RX_OVERSIZE_PKT_L"},
324 {true, "IGU_RX_OVERSIZE_PKT_H"},
325 {true, "IGU_RX_UNDERSIZE_PKT_L"},
326 {true, "IGU_RX_UNDERSIZE_PKT_H"},
327 {true, "IGU_RX_OUT_ALL_PKT_L"},
328 {true, "IGU_RX_OUT_ALL_PKT_H"},
329
330 {true, "IGU_TX_OUT_ALL_PKT_L"},
331 {true, "IGU_TX_OUT_ALL_PKT_H"},
332 {true, "IGU_RX_UNI_PKT_L"},
333 {true, "IGU_RX_UNI_PKT_H"},
334 {true, "IGU_RX_MULTI_PKT_L"},
335 {true, "IGU_RX_MULTI_PKT_H"},
336
337 {true, "IGU_RX_BROAD_PKT_L"},
338 {true, "IGU_RX_BROAD_PKT_H"},
339 {true, "EGU_TX_OUT_ALL_PKT_L"},
340 {true, "EGU_TX_OUT_ALL_PKT_H"},
341 {true, "EGU_TX_UNI_PKT_L"},
342 {true, "EGU_TX_UNI_PKT_H"},
343
344 {true, "EGU_TX_MULTI_PKT_L"},
345 {true, "EGU_TX_MULTI_PKT_H"},
346 {true, "EGU_TX_BROAD_PKT_L"},
347 {true, "EGU_TX_BROAD_PKT_H"},
348 {true, "IGU_TX_KEY_NUM_L"},
349 {true, "IGU_TX_KEY_NUM_H"},
350
351 {true, "IGU_RX_NON_TUN_PKT_L"},
352 {true, "IGU_RX_NON_TUN_PKT_H"},
353 {true, "IGU_RX_TUN_PKT_L"},
354 {true, "IGU_RX_TUN_PKT_H"},
355 {false, "Reserved"},
356 {false, "Reserved"},
357 };
358
359 static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = {
360 {true, "tc_queue_num"},
361 {true, "FSM_DFX_ST0"},
362 {true, "FSM_DFX_ST1"},
363 {true, "RPU_RX_PKT_DROP_CNT"},
364 {true, "BUF_WAIT_TIMEOUT"},
365 {true, "BUF_WAIT_TIMEOUT_QID"},
366 };
367
368 static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = {
369 {false, "Reserved"},
370 {true, "FIFO_DFX_ST0"},
371 {true, "FIFO_DFX_ST1"},
372 {true, "FIFO_DFX_ST2"},
373 {true, "FIFO_DFX_ST3"},
374 {true, "FIFO_DFX_ST4"},
375
376 {true, "FIFO_DFX_ST5"},
377 {false, "Reserved"},
378 {false, "Reserved"},
379 {false, "Reserved"},
380 {false, "Reserved"},
381 {false, "Reserved"},
382 };
383
384 static struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = {
385 {false, "Reserved"},
386 {true, "NCSI_EGU_TX_FIFO_STS"},
387 {true, "NCSI_PAUSE_STATUS"},
388 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"},
389 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"},
390 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"},
391
392 {true, "NCSI_RX_CTRL_PKT_CNT"},
393 {true, "NCSI_RX_PT_DMAC_ERR_CNT"},
394 {true, "NCSI_RX_PT_SMAC_ERR_CNT"},
395 {true, "NCSI_RX_PT_PKT_CNT"},
396 {true, "NCSI_RX_FCS_ERR_CNT"},
397 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"},
398
399 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"},
400 {true, "NCSI_TX_CTRL_PKT_CNT"},
401 {true, "NCSI_TX_PT_DMAC_ERR_CNT"},
402 {true, "NCSI_TX_PT_SMAC_ERR_CNT"},
403 {true, "NCSI_TX_PT_PKT_CNT"},
404 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"},
405
406 {true, "NCSI_TX_PT_PKT_ERR_CNT"},
407 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"},
408 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"},
409 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"},
410 {false, "Reserved"},
411 {false, "Reserved"},
412
413 {true, "NCSI_MAC_RX_OCTETS_OK"},
414 {true, "NCSI_MAC_RX_OCTETS_BAD"},
415 {true, "NCSI_MAC_RX_UC_PKTS"},
416 {true, "NCSI_MAC_RX_MC_PKTS"},
417 {true, "NCSI_MAC_RX_BC_PKTS"},
418 {true, "NCSI_MAC_RX_PKTS_64OCTETS"},
419
420 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"},
421 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"},
422 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"},
423 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"},
424 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"},
425 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"},
426
427 {true, "NCSI_MAC_RX_FCS_ERRORS"},
428 {true, "NCSI_MAC_RX_LONG_ERRORS"},
429 {true, "NCSI_MAC_RX_JABBER_ERRORS"},
430 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"},
431 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"},
432 {true, "NCSI_MAC_RX_FILT_PKT_CNT"},
433
434 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"},
435 {true, "NCSI_MAC_TX_OCTETS_OK"},
436 {true, "NCSI_MAC_TX_OCTETS_BAD"},
437 {true, "NCSI_MAC_TX_UC_PKTS"},
438 {true, "NCSI_MAC_TX_MC_PKTS"},
439 {true, "NCSI_MAC_TX_BC_PKTS"},
440
441 {true, "NCSI_MAC_TX_PKTS_64OCTETS"},
442 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"},
443 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"},
444 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"},
445 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"},
446 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"},
447
448 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"},
449 {true, "NCSI_MAC_TX_UNDERRUN"},
450 {true, "NCSI_MAC_TX_CRC_ERROR"},
451 {true, "NCSI_MAC_TX_PAUSE_FRAMES"},
452 {true, "NCSI_MAC_RX_PAD_PKTS"},
453 {true, "NCSI_MAC_RX_PAUSE_FRAMES"},
454 };
455
456 static struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = {
457 {false, "Reserved"},
458 {true, "LGE_IGU_AFIFO_DFX_0"},
459 {true, "LGE_IGU_AFIFO_DFX_1"},
460 {true, "LGE_IGU_AFIFO_DFX_2"},
461 {true, "LGE_IGU_AFIFO_DFX_3"},
462 {true, "LGE_IGU_AFIFO_DFX_4"},
463
464 {true, "LGE_IGU_AFIFO_DFX_5"},
465 {true, "LGE_IGU_AFIFO_DFX_6"},
466 {true, "LGE_IGU_AFIFO_DFX_7"},
467 {true, "LGE_EGU_AFIFO_DFX_0"},
468 {true, "LGE_EGU_AFIFO_DFX_1"},
469 {true, "LGE_EGU_AFIFO_DFX_2"},
470
471 {true, "LGE_EGU_AFIFO_DFX_3"},
472 {true, "LGE_EGU_AFIFO_DFX_4"},
473 {true, "LGE_EGU_AFIFO_DFX_5"},
474 {true, "LGE_EGU_AFIFO_DFX_6"},
475 {true, "LGE_EGU_AFIFO_DFX_7"},
476 {true, "CGE_IGU_AFIFO_DFX_0"},
477
478 {true, "CGE_IGU_AFIFO_DFX_1"},
479 {true, "CGE_EGU_AFIFO_DFX_0"},
480 {true, "CGE_EGU_AFIFO_DFX_1"},
481 {false, "Reserved"},
482 {false, "Reserved"},
483 {false, "Reserved"},
484 };
485
486 static struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = {
487 {false, "Reserved"},
488 {true, "DROP_FROM_PRT_PKT_CNT"},
489 {true, "DROP_FROM_HOST_PKT_CNT"},
490 {true, "DROP_TX_VLAN_PROC_CNT"},
491 {true, "DROP_MNG_CNT"},
492 {true, "DROP_FD_CNT"},
493
494 {true, "DROP_NO_DST_CNT"},
495 {true, "DROP_MC_MBID_FULL_CNT"},
496 {true, "DROP_SC_FILTERED"},
497 {true, "PPP_MC_DROP_PKT_CNT"},
498 {true, "DROP_PT_CNT"},
499 {true, "DROP_MAC_ANTI_SPOOF_CNT"},
500
501 {true, "DROP_IG_VFV_CNT"},
502 {true, "DROP_IG_PRTV_CNT"},
503 {true, "DROP_CNM_PFC_PAUSE_CNT"},
504 {true, "DROP_TORUS_TC_CNT"},
505 {true, "DROP_TORUS_LPBK_CNT"},
506 {true, "PPP_HFS_STS"},
507
508 {true, "PPP_MC_RSLT_STS"},
509 {true, "PPP_P3U_STS"},
510 {true, "PPP_RSLT_DESCR_STS"},
511 {true, "PPP_UMV_STS_0"},
512 {true, "PPP_UMV_STS_1"},
513 {true, "PPP_VFV_STS"},
514
515 {true, "PPP_GRO_KEY_CNT"},
516 {true, "PPP_GRO_INFO_CNT"},
517 {true, "PPP_GRO_DROP_CNT"},
518 {true, "PPP_GRO_OUT_CNT"},
519 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"},
520 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"},
521
522 {true, "PPP_GRO_INFO_MATCH_CNT"},
523 {true, "PPP_GRO_FREE_ENTRY_CNT"},
524 {true, "PPP_GRO_INNER_DFX_SIGNAL"},
525 {false, "Reserved"},
526 {false, "Reserved"},
527 {false, "Reserved"},
528
529 {true, "GET_RX_PKT_CNT_L"},
530 {true, "GET_RX_PKT_CNT_H"},
531 {true, "GET_TX_PKT_CNT_L"},
532 {true, "GET_TX_PKT_CNT_H"},
533 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"},
534 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"},
535
536 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"},
537 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"},
538 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"},
539 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"},
540 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"},
541 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"},
542
543 {true, "SEND_MC_FROM_PRT_CNT_L"},
544 {true, "SEND_MC_FROM_PRT_CNT_H"},
545 {true, "SEND_MC_FROM_HOST_CNT_L"},
546 {true, "SEND_MC_FROM_HOST_CNT_H"},
547 {true, "SSU_MC_RD_CNT_L"},
548 {true, "SSU_MC_RD_CNT_H"},
549
550 {true, "SSU_MC_DROP_CNT_L"},
551 {true, "SSU_MC_DROP_CNT_H"},
552 {true, "SSU_MC_RD_PKT_CNT_L"},
553 {true, "SSU_MC_RD_PKT_CNT_H"},
554 {true, "PPP_MC_2HOST_PKT_CNT_L"},
555 {true, "PPP_MC_2HOST_PKT_CNT_H"},
556
557 {true, "PPP_MC_2PRT_PKT_CNT_L"},
558 {true, "PPP_MC_2PRT_PKT_CNT_H"},
559 {true, "NTSNOS_PKT_CNT_L"},
560 {true, "NTSNOS_PKT_CNT_H"},
561 {true, "NTUP_PKT_CNT_L"},
562 {true, "NTUP_PKT_CNT_H"},
563
564 {true, "NTLCL_PKT_CNT_L"},
565 {true, "NTLCL_PKT_CNT_H"},
566 {true, "NTTGT_PKT_CNT_L"},
567 {true, "NTTGT_PKT_CNT_H"},
568 {true, "RTNS_PKT_CNT_L"},
569 {true, "RTNS_PKT_CNT_H"},
570
571 {true, "RTLPBK_PKT_CNT_L"},
572 {true, "RTLPBK_PKT_CNT_H"},
573 {true, "NR_PKT_CNT_L"},
574 {true, "NR_PKT_CNT_H"},
575 {true, "RR_PKT_CNT_L"},
576 {true, "RR_PKT_CNT_H"},
577
578 {true, "MNG_TBL_HIT_CNT_L"},
579 {true, "MNG_TBL_HIT_CNT_H"},
580 {true, "FD_TBL_HIT_CNT_L"},
581 {true, "FD_TBL_HIT_CNT_H"},
582 {true, "FD_LKUP_CNT_L"},
583 {true, "FD_LKUP_CNT_H"},
584
585 {true, "BC_HIT_CNT_L"},
586 {true, "BC_HIT_CNT_H"},
587 {true, "UM_TBL_UC_HIT_CNT_L"},
588 {true, "UM_TBL_UC_HIT_CNT_H"},
589 {true, "UM_TBL_MC_HIT_CNT_L"},
590 {true, "UM_TBL_MC_HIT_CNT_H"},
591
592 {true, "UM_TBL_VMDQ1_HIT_CNT_L"},
593 {true, "UM_TBL_VMDQ1_HIT_CNT_H"},
594 {true, "MTA_TBL_HIT_CNT_L"},
595 {true, "MTA_TBL_HIT_CNT_H"},
596 {true, "FWD_BONDING_HIT_CNT_L"},
597 {true, "FWD_BONDING_HIT_CNT_H"},
598
599 {true, "PROMIS_TBL_HIT_CNT_L"},
600 {true, "PROMIS_TBL_HIT_CNT_H"},
601 {true, "GET_TUNL_PKT_CNT_L"},
602 {true, "GET_TUNL_PKT_CNT_H"},
603 {true, "GET_BMC_PKT_CNT_L"},
604 {true, "GET_BMC_PKT_CNT_H"},
605
606 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"},
607 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"},
608 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"},
609 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"},
610 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"},
611 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"},
612
613 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"},
614 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"},
615 {true, "PPP_MC_2BMC_PKT_CNT_L"},
616 {true, "PPP_MC_2BMC_PKT_CNT_H"},
617 {true, "VLAN_MIRR_CNT_L"},
618 {true, "VLAN_MIRR_CNT_H"},
619
620 {true, "IG_MIRR_CNT_L"},
621 {true, "IG_MIRR_CNT_H"},
622 {true, "EG_MIRR_CNT_L"},
623 {true, "EG_MIRR_CNT_H"},
624 {true, "RX_DEFAULT_HOST_HIT_CNT_L"},
625 {true, "RX_DEFAULT_HOST_HIT_CNT_H"},
626
627 {true, "LAN_PAIR_CNT_L"},
628 {true, "LAN_PAIR_CNT_H"},
629 {true, "UM_TBL_MC_HIT_PKT_CNT_L"},
630 {true, "UM_TBL_MC_HIT_PKT_CNT_H"},
631 {true, "MTA_TBL_HIT_PKT_CNT_L"},
632 {true, "MTA_TBL_HIT_PKT_CNT_H"},
633
634 {true, "PROMIS_TBL_HIT_PKT_CNT_L"},
635 {true, "PROMIS_TBL_HIT_PKT_CNT_H"},
636 {false, "Reserved"},
637 {false, "Reserved"},
638 {false, "Reserved"},
639 {false, "Reserved"},
640 };
641
642 static struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = {
643 {false, "Reserved"},
644 {true, "FSM_DFX_ST0"},
645 {true, "FSM_DFX_ST1"},
646 {true, "FSM_DFX_ST2"},
647 {true, "FIFO_DFX_ST0"},
648 {true, "FIFO_DFX_ST1"},
649
650 {true, "FIFO_DFX_ST2"},
651 {true, "FIFO_DFX_ST3"},
652 {true, "FIFO_DFX_ST4"},
653 {true, "FIFO_DFX_ST5"},
654 {true, "FIFO_DFX_ST6"},
655 {true, "FIFO_DFX_ST7"},
656
657 {true, "FIFO_DFX_ST8"},
658 {true, "FIFO_DFX_ST9"},
659 {true, "FIFO_DFX_ST10"},
660 {true, "FIFO_DFX_ST11"},
661 {true, "Q_CREDIT_VLD_0"},
662 {true, "Q_CREDIT_VLD_1"},
663
664 {true, "Q_CREDIT_VLD_2"},
665 {true, "Q_CREDIT_VLD_3"},
666 {true, "Q_CREDIT_VLD_4"},
667 {true, "Q_CREDIT_VLD_5"},
668 {true, "Q_CREDIT_VLD_6"},
669 {true, "Q_CREDIT_VLD_7"},
670
671 {true, "Q_CREDIT_VLD_8"},
672 {true, "Q_CREDIT_VLD_9"},
673 {true, "Q_CREDIT_VLD_10"},
674 {true, "Q_CREDIT_VLD_11"},
675 {true, "Q_CREDIT_VLD_12"},
676 {true, "Q_CREDIT_VLD_13"},
677
678 {true, "Q_CREDIT_VLD_14"},
679 {true, "Q_CREDIT_VLD_15"},
680 {true, "Q_CREDIT_VLD_16"},
681 {true, "Q_CREDIT_VLD_17"},
682 {true, "Q_CREDIT_VLD_18"},
683 {true, "Q_CREDIT_VLD_19"},
684
685 {true, "Q_CREDIT_VLD_20"},
686 {true, "Q_CREDIT_VLD_21"},
687 {true, "Q_CREDIT_VLD_22"},
688 {true, "Q_CREDIT_VLD_23"},
689 {true, "Q_CREDIT_VLD_24"},
690 {true, "Q_CREDIT_VLD_25"},
691
692 {true, "Q_CREDIT_VLD_26"},
693 {true, "Q_CREDIT_VLD_27"},
694 {true, "Q_CREDIT_VLD_28"},
695 {true, "Q_CREDIT_VLD_29"},
696 {true, "Q_CREDIT_VLD_30"},
697 {true, "Q_CREDIT_VLD_31"},
698
699 {true, "GRO_BD_SERR_CNT"},
700 {true, "GRO_CONTEXT_SERR_CNT"},
701 {true, "RX_STASH_CFG_SERR_CNT"},
702 {true, "AXI_RD_FBD_SERR_CNT"},
703 {true, "GRO_BD_MERR_CNT"},
704 {true, "GRO_CONTEXT_MERR_CNT"},
705
706 {true, "RX_STASH_CFG_MERR_CNT"},
707 {true, "AXI_RD_FBD_MERR_CNT"},
708 {false, "Reserved"},
709 {false, "Reserved"},
710 {false, "Reserved"},
711 {false, "Reserved"},
712 };
713
714 static struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {
715 {true, "q_num"},
716 {true, "RCB_CFG_RX_RING_TAIL"},
717 {true, "RCB_CFG_RX_RING_HEAD"},
718 {true, "RCB_CFG_RX_RING_FBDNUM"},
719 {true, "RCB_CFG_RX_RING_OFFSET"},
720 {true, "RCB_CFG_RX_RING_FBDOFFSET"},
721
722 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"},
723 {true, "RCB_CFG_TX_RING_TAIL"},
724 {true, "RCB_CFG_TX_RING_HEAD"},
725 {true, "RCB_CFG_TX_RING_FBDNUM"},
726 {true, "RCB_CFG_TX_RING_OFFSET"},
727 {true, "RCB_CFG_TX_RING_EBDNUM"},
728 };
729
730 #endif