This source file includes following definitions.
- ring_space
- is_ring_empty
- hns3_read_reg
- hns3_write_reg
- hns3_dev_ongoing_func_reset
- hns3_nic_resetting
- hns3_page_order
- hns3_dcbnl_setup
1
2
3
4 #ifndef __HNS3_ENET_H
5 #define __HNS3_ENET_H
6
7 #include <linux/if_vlan.h>
8
9 #include "hnae3.h"
10
11 #define HNS3_MOD_VERSION "1.0"
12
13 extern const char hns3_driver_version[];
14
15 enum hns3_nic_state {
16 HNS3_NIC_STATE_TESTING,
17 HNS3_NIC_STATE_RESETTING,
18 HNS3_NIC_STATE_INITED,
19 HNS3_NIC_STATE_DOWN,
20 HNS3_NIC_STATE_DISABLED,
21 HNS3_NIC_STATE_REMOVING,
22 HNS3_NIC_STATE_SERVICE_INITED,
23 HNS3_NIC_STATE_SERVICE_SCHED,
24 HNS3_NIC_STATE2_RESET_REQUESTED,
25 HNS3_NIC_STATE_MAX
26 };
27
28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
36
37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
40 #define HNS3_RING_TX_RING_TC_REG 0x00050
41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
45 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
46 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
47 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
48 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
49 #define HNS3_RING_PREFETCH_EN_REG 0x0007C
50 #define HNS3_RING_CFG_VF_NUM_REG 0x00080
51 #define HNS3_RING_ASID_REG 0x0008C
52 #define HNS3_RING_EN_REG 0x00090
53 #define HNS3_RING_T0_BE_RST 0x00094
54 #define HNS3_RING_COULD_BE_RST 0x00098
55 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c
56
57 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0
58 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
59 #define HNS3_RX_RING_INT_STS_REG 0x000A8
60 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC
61 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
62 #define HNS3_TX_RING_INT_STS_REG 0x000B4
63 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
64 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
65 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
66 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
67
68 #define HNS3_RING_MB_CTRL_REG 0x00100
69 #define HNS3_RING_MB_DATA_BASE_REG 0x00200
70
71 #define HNS3_TX_REG_OFFSET 0x40
72
73 #define HNS3_RX_HEAD_SIZE 256
74
75 #define HNS3_TX_TIMEOUT (5 * HZ)
76 #define HNS3_RING_NAME_LEN 16
77 #define HNS3_BUFFER_SIZE_2048 2048
78 #define HNS3_RING_MAX_PENDING 32760
79 #define HNS3_RING_MIN_PENDING 24
80 #define HNS3_RING_BD_MULTIPLE 8
81
82 #define HNS3_MAC_MAX_FRAME 9728
83 #define HNS3_MAX_MTU \
84 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
85
86 #define HNS3_BD_SIZE_512_TYPE 0
87 #define HNS3_BD_SIZE_1024_TYPE 1
88 #define HNS3_BD_SIZE_2048_TYPE 2
89 #define HNS3_BD_SIZE_4096_TYPE 3
90
91 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
92 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
93 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
94 #define HNS3_RX_FLAG_L4ID_UDP 0x0
95 #define HNS3_RX_FLAG_L4ID_TCP 0x1
96
97 #define HNS3_RXD_DMAC_S 0
98 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
99 #define HNS3_RXD_VLAN_S 2
100 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
101 #define HNS3_RXD_L3ID_S 4
102 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
103 #define HNS3_RXD_L4ID_S 8
104 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
105 #define HNS3_RXD_FRAG_B 12
106 #define HNS3_RXD_STRP_TAGP_S 13
107 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
108
109 #define HNS3_RXD_L2E_B 16
110 #define HNS3_RXD_L3E_B 17
111 #define HNS3_RXD_L4E_B 18
112 #define HNS3_RXD_TRUNCAT_B 19
113 #define HNS3_RXD_HOI_B 20
114 #define HNS3_RXD_DOI_B 21
115 #define HNS3_RXD_OL3E_B 22
116 #define HNS3_RXD_OL4E_B 23
117 #define HNS3_RXD_GRO_COUNT_S 24
118 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
119 #define HNS3_RXD_GRO_FIXID_B 30
120 #define HNS3_RXD_GRO_ECN_B 31
121
122 #define HNS3_RXD_ODMAC_S 0
123 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
124 #define HNS3_RXD_OVLAN_S 2
125 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
126 #define HNS3_RXD_OL3ID_S 4
127 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
128 #define HNS3_RXD_OL4ID_S 8
129 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
130 #define HNS3_RXD_FBHI_S 12
131 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
132 #define HNS3_RXD_FBLI_S 14
133 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
134
135 #define HNS3_RXD_BDTYPE_S 0
136 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
137 #define HNS3_RXD_VLD_B 4
138 #define HNS3_RXD_UDP0_B 5
139 #define HNS3_RXD_EXTEND_B 7
140 #define HNS3_RXD_FE_B 8
141 #define HNS3_RXD_LUM_B 9
142 #define HNS3_RXD_CRCP_B 10
143 #define HNS3_RXD_L3L4P_B 11
144 #define HNS3_RXD_TSIND_S 12
145 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
146 #define HNS3_RXD_LKBK_B 15
147 #define HNS3_RXD_GRO_SIZE_S 16
148 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
149
150 #define HNS3_TXD_L3T_S 0
151 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
152 #define HNS3_TXD_L4T_S 2
153 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
154 #define HNS3_TXD_L3CS_B 4
155 #define HNS3_TXD_L4CS_B 5
156 #define HNS3_TXD_VLAN_B 6
157 #define HNS3_TXD_TSO_B 7
158
159 #define HNS3_TXD_L2LEN_S 8
160 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
161 #define HNS3_TXD_L3LEN_S 16
162 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
163 #define HNS3_TXD_L4LEN_S 24
164 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
165
166 #define HNS3_TXD_OL3T_S 0
167 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
168 #define HNS3_TXD_OVLAN_B 2
169 #define HNS3_TXD_MACSEC_B 3
170 #define HNS3_TXD_TUNTYPE_S 4
171 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
172
173 #define HNS3_TXD_BDTYPE_S 0
174 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
175 #define HNS3_TXD_FE_B 4
176 #define HNS3_TXD_SC_S 5
177 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
178 #define HNS3_TXD_EXTEND_B 7
179 #define HNS3_TXD_VLD_B 8
180 #define HNS3_TXD_RI_B 9
181 #define HNS3_TXD_RA_B 10
182 #define HNS3_TXD_TSYN_B 11
183 #define HNS3_TXD_DECTTL_S 12
184 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
185
186 #define HNS3_TXD_MSS_S 0
187 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
188
189 #define HNS3_TX_LAST_SIZE_M 0xffff
190
191 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
192 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
193
194 #define HNS3_VECTOR_NOT_INITED 0
195 #define HNS3_VECTOR_INITED 1
196
197 #define HNS3_MAX_BD_SIZE 65535
198 #define HNS3_MAX_BD_NUM_NORMAL 8
199 #define HNS3_MAX_BD_NUM_TSO 63
200 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
201
202 #define HNS3_VECTOR_GL0_OFFSET 0x100
203 #define HNS3_VECTOR_GL1_OFFSET 0x200
204 #define HNS3_VECTOR_GL2_OFFSET 0x300
205 #define HNS3_VECTOR_RL_OFFSET 0x900
206 #define HNS3_VECTOR_RL_EN_B 6
207
208 #define HNS3_RING_EN_B 0
209
210 enum hns3_pkt_l2t_type {
211 HNS3_L2_TYPE_UNICAST,
212 HNS3_L2_TYPE_MULTICAST,
213 HNS3_L2_TYPE_BROADCAST,
214 HNS3_L2_TYPE_INVALID,
215 };
216
217 enum hns3_pkt_l3t_type {
218 HNS3_L3T_NONE,
219 HNS3_L3T_IPV6,
220 HNS3_L3T_IPV4,
221 HNS3_L3T_RESERVED
222 };
223
224 enum hns3_pkt_l4t_type {
225 HNS3_L4T_UNKNOWN,
226 HNS3_L4T_TCP,
227 HNS3_L4T_UDP,
228 HNS3_L4T_SCTP
229 };
230
231 enum hns3_pkt_ol3t_type {
232 HNS3_OL3T_NONE,
233 HNS3_OL3T_IPV6,
234 HNS3_OL3T_IPV4_NO_CSUM,
235 HNS3_OL3T_IPV4_CSUM
236 };
237
238 enum hns3_pkt_tun_type {
239 HNS3_TUN_NONE,
240 HNS3_TUN_MAC_IN_UDP,
241 HNS3_TUN_NVGRE,
242 HNS3_TUN_OTHER
243 };
244
245
246 struct __packed hns3_desc {
247 __le64 addr;
248 union {
249 struct {
250 __le16 vlan_tag;
251 __le16 send_size;
252 union {
253 __le32 type_cs_vlan_tso_len;
254 struct {
255 __u8 type_cs_vlan_tso;
256 __u8 l2_len;
257 __u8 l3_len;
258 __u8 l4_len;
259 };
260 };
261 __le16 outer_vlan_tag;
262 __le16 tv;
263
264 union {
265 __le32 ol_type_vlan_len_msec;
266 struct {
267 __u8 ol_type_vlan_msec;
268 __u8 ol2_len;
269 __u8 ol3_len;
270 __u8 ol4_len;
271 };
272 };
273
274 __le32 paylen;
275 __le16 bdtp_fe_sc_vld_ra_ri;
276 __le16 mss;
277 } tx;
278
279 struct {
280 __le32 l234_info;
281 __le16 pkt_len;
282 __le16 size;
283
284 __le32 rss_hash;
285 __le16 fd_id;
286 __le16 vlan_tag;
287
288 union {
289 __le32 ol_info;
290 struct {
291 __le16 o_dm_vlan_id_fb;
292 __le16 ot_vlan_tag;
293 };
294 };
295
296 __le32 bd_base_info;
297 } rx;
298 };
299 };
300
301 struct hns3_desc_cb {
302 dma_addr_t dma;
303 void *buf;
304
305
306 void *priv;
307 u32 page_offset;
308 u32 length;
309
310 u16 reuse_flag;
311
312
313 u16 type;
314 };
315
316 enum hns3_pkt_l3type {
317 HNS3_L3_TYPE_IPV4,
318 HNS3_L3_TYPE_IPV6,
319 HNS3_L3_TYPE_ARP,
320 HNS3_L3_TYPE_RARP,
321 HNS3_L3_TYPE_IPV4_OPT,
322 HNS3_L3_TYPE_IPV6_EXT,
323 HNS3_L3_TYPE_LLDP,
324 HNS3_L3_TYPE_BPDU,
325 HNS3_L3_TYPE_MAC_PAUSE,
326 HNS3_L3_TYPE_PFC_PAUSE,
327
328
329
330 HNS3_L3_TYPE_CNM = 0xc,
331
332
333
334 HNS3_L3_TYPE_PARSE_FAIL = 0xf
335 };
336
337 enum hns3_pkt_l4type {
338 HNS3_L4_TYPE_UDP,
339 HNS3_L4_TYPE_TCP,
340 HNS3_L4_TYPE_GRE,
341 HNS3_L4_TYPE_SCTP,
342 HNS3_L4_TYPE_IGMP,
343 HNS3_L4_TYPE_ICMP,
344
345
346
347 HNS3_L4_TYPE_PARSE_FAIL = 0xf
348 };
349
350 enum hns3_pkt_ol3type {
351 HNS3_OL3_TYPE_IPV4 = 0,
352 HNS3_OL3_TYPE_IPV6,
353
354 HNS3_OL3_TYPE_IPV4_OPT = 4,
355 HNS3_OL3_TYPE_IPV6_EXT,
356
357
358
359 HNS3_OL3_TYPE_PARSE_FAIL = 0xf
360 };
361
362 enum hns3_pkt_ol4type {
363 HNS3_OL4_TYPE_NO_TUN,
364 HNS3_OL4_TYPE_MAC_IN_UDP,
365 HNS3_OL4_TYPE_NVGRE,
366 HNS3_OL4_TYPE_UNKNOWN
367 };
368
369 struct ring_stats {
370 u64 io_err_cnt;
371 u64 sw_err_cnt;
372 u64 seg_pkt_cnt;
373 union {
374 struct {
375 u64 tx_pkts;
376 u64 tx_bytes;
377 u64 tx_err_cnt;
378 u64 restart_queue;
379 u64 tx_busy;
380 u64 tx_copy;
381 u64 tx_vlan_err;
382 u64 tx_l4_proto_err;
383 u64 tx_l2l3l4_err;
384 u64 tx_tso_err;
385 };
386 struct {
387 u64 rx_pkts;
388 u64 rx_bytes;
389 u64 rx_err_cnt;
390 u64 reuse_pg_cnt;
391 u64 err_pkt_len;
392 u64 err_bd_num;
393 u64 l2_err;
394 u64 l3l4_csum_err;
395 u64 rx_multicast;
396 u64 non_reuse_pg;
397 };
398 };
399 };
400
401 struct hns3_enet_ring {
402 u8 __iomem *io_base;
403 struct hns3_desc *desc;
404 struct hns3_desc_cb *desc_cb;
405 struct hns3_enet_ring *next;
406 struct hns3_enet_tqp_vector *tqp_vector;
407 struct hnae3_queue *tqp;
408 struct device *dev;
409
410
411 struct ring_stats stats;
412 struct u64_stats_sync syncp;
413
414 dma_addr_t desc_dma_addr;
415 u32 buf_size;
416 u16 desc_num;
417 int next_to_use;
418
419
420
421
422 int next_to_clean;
423
424 u32 pull_len;
425 u32 frag_num;
426 unsigned char *va;
427
428 u32 flag;
429
430 int pending_buf;
431 struct sk_buff *skb;
432 struct sk_buff *tail_skb;
433 };
434
435 struct hns_queue;
436
437 struct hns3_nic_ring_data {
438 struct hns3_enet_ring *ring;
439 struct napi_struct napi;
440 int queue_index;
441 int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
442 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
443 void (*fini_process)(struct hns3_nic_ring_data *);
444 };
445
446 enum hns3_flow_level_range {
447 HNS3_FLOW_LOW = 0,
448 HNS3_FLOW_MID = 1,
449 HNS3_FLOW_HIGH = 2,
450 HNS3_FLOW_ULTRA = 3,
451 };
452
453 #define HNS3_INT_GL_MAX 0x1FE0
454 #define HNS3_INT_GL_50K 0x0014
455 #define HNS3_INT_GL_20K 0x0032
456 #define HNS3_INT_GL_18K 0x0036
457 #define HNS3_INT_GL_8K 0x007C
458
459 #define HNS3_INT_RL_MAX 0x00EC
460 #define HNS3_INT_RL_ENABLE_MASK 0x40
461
462 struct hns3_enet_coalesce {
463 u16 int_gl;
464 u8 gl_adapt_enable;
465 enum hns3_flow_level_range flow_level;
466 };
467
468 struct hns3_enet_ring_group {
469
470 struct hns3_enet_ring *ring;
471 u64 total_bytes;
472 u64 total_packets;
473 u16 count;
474 struct hns3_enet_coalesce coal;
475 };
476
477 struct hns3_enet_tqp_vector {
478 struct hnae3_handle *handle;
479 u8 __iomem *mask_addr;
480 int vector_irq;
481 int irq_init_flag;
482
483 u16 idx;
484
485 struct napi_struct napi;
486
487 struct hns3_enet_ring_group rx_group;
488 struct hns3_enet_ring_group tx_group;
489
490 cpumask_t affinity_mask;
491 u16 num_tqps;
492 struct irq_affinity_notify affinity_notify;
493
494 char name[HNAE3_INT_NAME_LEN];
495
496 unsigned long last_jiffies;
497 } ____cacheline_internodealigned_in_smp;
498
499 enum hns3_udp_tnl_type {
500 HNS3_UDP_TNL_VXLAN,
501 HNS3_UDP_TNL_GENEVE,
502 HNS3_UDP_TNL_MAX,
503 };
504
505 struct hns3_udp_tunnel {
506 u16 dst_port;
507 int used;
508 };
509
510 struct hns3_nic_priv {
511 struct hnae3_handle *ae_handle;
512 u32 enet_ver;
513 u32 port_id;
514 struct net_device *netdev;
515 struct device *dev;
516
517
518
519
520
521 struct hns3_nic_ring_data *ring_data;
522 struct hns3_enet_tqp_vector *tqp_vector;
523 u16 vector_num;
524
525
526 int link;
527 u64 tx_timeout_count;
528
529 unsigned long state;
530
531 struct timer_list service_timer;
532
533 struct work_struct service_task;
534
535 struct notifier_block notifier_block;
536
537 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
538 struct hns3_enet_coalesce tx_coal;
539 struct hns3_enet_coalesce rx_coal;
540 };
541
542 union l3_hdr_info {
543 struct iphdr *v4;
544 struct ipv6hdr *v6;
545 unsigned char *hdr;
546 };
547
548 union l4_hdr_info {
549 struct tcphdr *tcp;
550 struct udphdr *udp;
551 struct gre_base_hdr *gre;
552 unsigned char *hdr;
553 };
554
555 struct hns3_hw_error_info {
556 enum hnae3_hw_error_type type;
557 const char *msg;
558 };
559
560 static inline int ring_space(struct hns3_enet_ring *ring)
561 {
562
563
564
565 int begin = smp_load_acquire(&ring->next_to_clean);
566 int end = READ_ONCE(ring->next_to_use);
567
568 return ((end >= begin) ? (ring->desc_num - end + begin) :
569 (begin - end)) - 1;
570 }
571
572 static inline int is_ring_empty(struct hns3_enet_ring *ring)
573 {
574 return ring->next_to_use == ring->next_to_clean;
575 }
576
577 static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
578 {
579 return readl(base + reg);
580 }
581
582 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
583 {
584 u8 __iomem *reg_addr = READ_ONCE(base);
585
586 writel(value, reg_addr + reg);
587 }
588
589 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
590 {
591 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET ||
592 ae_dev->reset_type == HNAE3_FLR_RESET ||
593 ae_dev->reset_type == HNAE3_VF_FUNC_RESET ||
594 ae_dev->reset_type == HNAE3_VF_FULL_RESET ||
595 ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
596 }
597
598 #define hns3_read_dev(a, reg) \
599 hns3_read_reg((a)->io_base, (reg))
600
601 static inline bool hns3_nic_resetting(struct net_device *netdev)
602 {
603 struct hns3_nic_priv *priv = netdev_priv(netdev);
604
605 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
606 }
607
608 #define hns3_write_dev(a, reg, value) \
609 hns3_write_reg((a)->io_base, (reg), (value))
610
611 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
612 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
613
614 #define ring_to_dev(ring) ((ring)->dev)
615
616 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
617 DMA_TO_DEVICE : DMA_FROM_DEVICE)
618
619 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
620
621 #define hns3_buf_size(_ring) ((_ring)->buf_size)
622
623 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
624 {
625 #if (PAGE_SIZE < 8192)
626 if (ring->buf_size > (PAGE_SIZE / 2))
627 return 1;
628 #endif
629 return 0;
630 }
631
632 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
633
634
635 #define hns3_for_each_ring(pos, head) \
636 for (pos = (head).ring; pos; pos = pos->next)
637
638 #define hns3_get_handle(ndev) \
639 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
640
641 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
642 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
643
644 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
645 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
646
647 void hns3_ethtool_set_ops(struct net_device *netdev);
648 int hns3_set_channels(struct net_device *netdev,
649 struct ethtool_channels *ch);
650
651 void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
652 int hns3_init_all_ring(struct hns3_nic_priv *priv);
653 int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
654 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
655 void hns3_fini_ring(struct hns3_enet_ring *ring);
656 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
657 bool hns3_is_phys_func(struct pci_dev *pdev);
658 int hns3_clean_rx_ring(
659 struct hns3_enet_ring *ring, int budget,
660 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
661
662 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
663 u32 gl_value);
664 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
665 u32 gl_value);
666 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
667 u32 rl_value);
668
669 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
670 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
671
672 #ifdef CONFIG_HNS3_DCB
673 void hns3_dcbnl_setup(struct hnae3_handle *handle);
674 #else
675 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
676 #endif
677
678 void hns3_dbg_init(struct hnae3_handle *handle);
679 void hns3_dbg_uninit(struct hnae3_handle *handle);
680 void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
681 void hns3_dbg_unregister_debugfs(void);
682 #endif