root/drivers/net/ethernet/cadence/macb.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. gem_ptp_do_txstamp
  2. gem_ptp_do_rxstamp
  3. gem_ptp_init
  4. gem_ptp_remove
  5. gem_ptp_do_txstamp
  6. gem_ptp_do_rxstamp
  7. macb_is_gem
  8. gem_has_ptp
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Atmel MACB Ethernet Controller driver
   4  *
   5  * Copyright (C) 2004-2006 Atmel Corporation
   6  */
   7 #ifndef _MACB_H
   8 #define _MACB_H
   9 
  10 #include <linux/phy.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/net_tstamp.h>
  13 #include <linux/interrupt.h>
  14 
  15 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
  16 #define MACB_EXT_DESC
  17 #endif
  18 
  19 #define MACB_GREGS_NBR 16
  20 #define MACB_GREGS_VERSION 2
  21 #define MACB_MAX_QUEUES 8
  22 
  23 /* MACB register offsets */
  24 #define MACB_NCR                0x0000 /* Network Control */
  25 #define MACB_NCFGR              0x0004 /* Network Config */
  26 #define MACB_NSR                0x0008 /* Network Status */
  27 #define MACB_TAR                0x000c /* AT91RM9200 only */
  28 #define MACB_TCR                0x0010 /* AT91RM9200 only */
  29 #define MACB_TSR                0x0014 /* Transmit Status */
  30 #define MACB_RBQP               0x0018 /* RX Q Base Address */
  31 #define MACB_TBQP               0x001c /* TX Q Base Address */
  32 #define MACB_RSR                0x0020 /* Receive Status */
  33 #define MACB_ISR                0x0024 /* Interrupt Status */
  34 #define MACB_IER                0x0028 /* Interrupt Enable */
  35 #define MACB_IDR                0x002c /* Interrupt Disable */
  36 #define MACB_IMR                0x0030 /* Interrupt Mask */
  37 #define MACB_MAN                0x0034 /* PHY Maintenance */
  38 #define MACB_PTR                0x0038
  39 #define MACB_PFR                0x003c
  40 #define MACB_FTO                0x0040
  41 #define MACB_SCF                0x0044
  42 #define MACB_MCF                0x0048
  43 #define MACB_FRO                0x004c
  44 #define MACB_FCSE               0x0050
  45 #define MACB_ALE                0x0054
  46 #define MACB_DTF                0x0058
  47 #define MACB_LCOL               0x005c
  48 #define MACB_EXCOL              0x0060
  49 #define MACB_TUND               0x0064
  50 #define MACB_CSE                0x0068
  51 #define MACB_RRE                0x006c
  52 #define MACB_ROVR               0x0070
  53 #define MACB_RSE                0x0074
  54 #define MACB_ELE                0x0078
  55 #define MACB_RJA                0x007c
  56 #define MACB_USF                0x0080
  57 #define MACB_STE                0x0084
  58 #define MACB_RLE                0x0088
  59 #define MACB_TPF                0x008c
  60 #define MACB_HRB                0x0090
  61 #define MACB_HRT                0x0094
  62 #define MACB_SA1B               0x0098
  63 #define MACB_SA1T               0x009c
  64 #define MACB_SA2B               0x00a0
  65 #define MACB_SA2T               0x00a4
  66 #define MACB_SA3B               0x00a8
  67 #define MACB_SA3T               0x00ac
  68 #define MACB_SA4B               0x00b0
  69 #define MACB_SA4T               0x00b4
  70 #define MACB_TID                0x00b8
  71 #define MACB_TPQ                0x00bc
  72 #define MACB_USRIO              0x00c0
  73 #define MACB_WOL                0x00c4
  74 #define MACB_MID                0x00fc
  75 #define MACB_TBQPH              0x04C8
  76 #define MACB_RBQPH              0x04D4
  77 
  78 /* GEM register offsets. */
  79 #define GEM_NCFGR               0x0004 /* Network Config */
  80 #define GEM_USRIO               0x000c /* User IO */
  81 #define GEM_DMACFG              0x0010 /* DMA Configuration */
  82 #define GEM_JML                 0x0048 /* Jumbo Max Length */
  83 #define GEM_HRB                 0x0080 /* Hash Bottom */
  84 #define GEM_HRT                 0x0084 /* Hash Top */
  85 #define GEM_SA1B                0x0088 /* Specific1 Bottom */
  86 #define GEM_SA1T                0x008C /* Specific1 Top */
  87 #define GEM_SA2B                0x0090 /* Specific2 Bottom */
  88 #define GEM_SA2T                0x0094 /* Specific2 Top */
  89 #define GEM_SA3B                0x0098 /* Specific3 Bottom */
  90 #define GEM_SA3T                0x009C /* Specific3 Top */
  91 #define GEM_SA4B                0x00A0 /* Specific4 Bottom */
  92 #define GEM_SA4T                0x00A4 /* Specific4 Top */
  93 #define GEM_EFTSH               0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
  94 #define GEM_EFRSH               0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
  95 #define GEM_PEFTSH              0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
  96 #define GEM_PEFRSH              0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
  97 #define GEM_OTX                 0x0100 /* Octets transmitted */
  98 #define GEM_OCTTXL              0x0100 /* Octets transmitted [31:0] */
  99 #define GEM_OCTTXH              0x0104 /* Octets transmitted [47:32] */
 100 #define GEM_TXCNT               0x0108 /* Frames Transmitted counter */
 101 #define GEM_TXBCCNT             0x010c /* Broadcast Frames counter */
 102 #define GEM_TXMCCNT             0x0110 /* Multicast Frames counter */
 103 #define GEM_TXPAUSECNT          0x0114 /* Pause Frames Transmitted Counter */
 104 #define GEM_TX64CNT             0x0118 /* 64 byte Frames TX counter */
 105 #define GEM_TX65CNT             0x011c /* 65-127 byte Frames TX counter */
 106 #define GEM_TX128CNT            0x0120 /* 128-255 byte Frames TX counter */
 107 #define GEM_TX256CNT            0x0124 /* 256-511 byte Frames TX counter */
 108 #define GEM_TX512CNT            0x0128 /* 512-1023 byte Frames TX counter */
 109 #define GEM_TX1024CNT           0x012c /* 1024-1518 byte Frames TX counter */
 110 #define GEM_TX1519CNT           0x0130 /* 1519+ byte Frames TX counter */
 111 #define GEM_TXURUNCNT           0x0134 /* TX under run error counter */
 112 #define GEM_SNGLCOLLCNT         0x0138 /* Single Collision Frame Counter */
 113 #define GEM_MULTICOLLCNT        0x013c /* Multiple Collision Frame Counter */
 114 #define GEM_EXCESSCOLLCNT       0x0140 /* Excessive Collision Frame Counter */
 115 #define GEM_LATECOLLCNT         0x0144 /* Late Collision Frame Counter */
 116 #define GEM_TXDEFERCNT          0x0148 /* Deferred Transmission Frame Counter */
 117 #define GEM_TXCSENSECNT         0x014c /* Carrier Sense Error Counter */
 118 #define GEM_ORX                 0x0150 /* Octets received */
 119 #define GEM_OCTRXL              0x0150 /* Octets received [31:0] */
 120 #define GEM_OCTRXH              0x0154 /* Octets received [47:32] */
 121 #define GEM_RXCNT               0x0158 /* Frames Received Counter */
 122 #define GEM_RXBROADCNT          0x015c /* Broadcast Frames Received Counter */
 123 #define GEM_RXMULTICNT          0x0160 /* Multicast Frames Received Counter */
 124 #define GEM_RXPAUSECNT          0x0164 /* Pause Frames Received Counter */
 125 #define GEM_RX64CNT             0x0168 /* 64 byte Frames RX Counter */
 126 #define GEM_RX65CNT             0x016c /* 65-127 byte Frames RX Counter */
 127 #define GEM_RX128CNT            0x0170 /* 128-255 byte Frames RX Counter */
 128 #define GEM_RX256CNT            0x0174 /* 256-511 byte Frames RX Counter */
 129 #define GEM_RX512CNT            0x0178 /* 512-1023 byte Frames RX Counter */
 130 #define GEM_RX1024CNT           0x017c /* 1024-1518 byte Frames RX Counter */
 131 #define GEM_RX1519CNT           0x0180 /* 1519+ byte Frames RX Counter */
 132 #define GEM_RXUNDRCNT           0x0184 /* Undersize Frames Received Counter */
 133 #define GEM_RXOVRCNT            0x0188 /* Oversize Frames Received Counter */
 134 #define GEM_RXJABCNT            0x018c /* Jabbers Received Counter */
 135 #define GEM_RXFCSCNT            0x0190 /* Frame Check Sequence Error Counter */
 136 #define GEM_RXLENGTHCNT         0x0194 /* Length Field Error Counter */
 137 #define GEM_RXSYMBCNT           0x0198 /* Symbol Error Counter */
 138 #define GEM_RXALIGNCNT          0x019c /* Alignment Error Counter */
 139 #define GEM_RXRESERRCNT         0x01a0 /* Receive Resource Error Counter */
 140 #define GEM_RXORCNT             0x01a4 /* Receive Overrun Counter */
 141 #define GEM_RXIPCCNT            0x01a8 /* IP header Checksum Error Counter */
 142 #define GEM_RXTCPCCNT           0x01ac /* TCP Checksum Error Counter */
 143 #define GEM_RXUDPCCNT           0x01b0 /* UDP Checksum Error Counter */
 144 #define GEM_TISUBN              0x01bc /* 1588 Timer Increment Sub-ns */
 145 #define GEM_TSH                 0x01c0 /* 1588 Timer Seconds High */
 146 #define GEM_TSL                 0x01d0 /* 1588 Timer Seconds Low */
 147 #define GEM_TN                  0x01d4 /* 1588 Timer Nanoseconds */
 148 #define GEM_TA                  0x01d8 /* 1588 Timer Adjust */
 149 #define GEM_TI                  0x01dc /* 1588 Timer Increment */
 150 #define GEM_EFTSL               0x01e0 /* PTP Event Frame Tx Seconds Low */
 151 #define GEM_EFTN                0x01e4 /* PTP Event Frame Tx Nanoseconds */
 152 #define GEM_EFRSL               0x01e8 /* PTP Event Frame Rx Seconds Low */
 153 #define GEM_EFRN                0x01ec /* PTP Event Frame Rx Nanoseconds */
 154 #define GEM_PEFTSL              0x01f0 /* PTP Peer Event Frame Tx Secs Low */
 155 #define GEM_PEFTN               0x01f4 /* PTP Peer Event Frame Tx Ns */
 156 #define GEM_PEFRSL              0x01f8 /* PTP Peer Event Frame Rx Sec Low */
 157 #define GEM_PEFRN               0x01fc /* PTP Peer Event Frame Rx Ns */
 158 #define GEM_DCFG1               0x0280 /* Design Config 1 */
 159 #define GEM_DCFG2               0x0284 /* Design Config 2 */
 160 #define GEM_DCFG3               0x0288 /* Design Config 3 */
 161 #define GEM_DCFG4               0x028c /* Design Config 4 */
 162 #define GEM_DCFG5               0x0290 /* Design Config 5 */
 163 #define GEM_DCFG6               0x0294 /* Design Config 6 */
 164 #define GEM_DCFG7               0x0298 /* Design Config 7 */
 165 #define GEM_DCFG8               0x029C /* Design Config 8 */
 166 #define GEM_DCFG10              0x02A4 /* Design Config 10 */
 167 
 168 #define GEM_TXBDCTRL    0x04cc /* TX Buffer Descriptor control register */
 169 #define GEM_RXBDCTRL    0x04d0 /* RX Buffer Descriptor control register */
 170 
 171 /* Screener Type 2 match registers */
 172 #define GEM_SCRT2               0x540
 173 
 174 /* EtherType registers */
 175 #define GEM_ETHT                0x06E0
 176 
 177 /* Type 2 compare registers */
 178 #define GEM_T2CMPW0             0x0700
 179 #define GEM_T2CMPW1             0x0704
 180 #define T2CMP_OFST(t2idx)       (t2idx * 2)
 181 
 182 /* type 2 compare registers
 183  * each location requires 3 compare regs
 184  */
 185 #define GEM_IP4SRC_CMP(idx)             (idx * 3)
 186 #define GEM_IP4DST_CMP(idx)             (idx * 3 + 1)
 187 #define GEM_PORT_CMP(idx)               (idx * 3 + 2)
 188 
 189 /* Which screening type 2 EtherType register will be used (0 - 7) */
 190 #define SCRT2_ETHT              0
 191 
 192 #define GEM_ISR(hw_q)           (0x0400 + ((hw_q) << 2))
 193 #define GEM_TBQP(hw_q)          (0x0440 + ((hw_q) << 2))
 194 #define GEM_TBQPH(hw_q)         (0x04C8)
 195 #define GEM_RBQP(hw_q)          (0x0480 + ((hw_q) << 2))
 196 #define GEM_RBQS(hw_q)          (0x04A0 + ((hw_q) << 2))
 197 #define GEM_RBQPH(hw_q)         (0x04D4)
 198 #define GEM_IER(hw_q)           (0x0600 + ((hw_q) << 2))
 199 #define GEM_IDR(hw_q)           (0x0620 + ((hw_q) << 2))
 200 #define GEM_IMR(hw_q)           (0x0640 + ((hw_q) << 2))
 201 
 202 /* Bitfields in NCR */
 203 #define MACB_LB_OFFSET          0 /* reserved */
 204 #define MACB_LB_SIZE            1
 205 #define MACB_LLB_OFFSET         1 /* Loop back local */
 206 #define MACB_LLB_SIZE           1
 207 #define MACB_RE_OFFSET          2 /* Receive enable */
 208 #define MACB_RE_SIZE            1
 209 #define MACB_TE_OFFSET          3 /* Transmit enable */
 210 #define MACB_TE_SIZE            1
 211 #define MACB_MPE_OFFSET         4 /* Management port enable */
 212 #define MACB_MPE_SIZE           1
 213 #define MACB_CLRSTAT_OFFSET     5 /* Clear stats regs */
 214 #define MACB_CLRSTAT_SIZE       1
 215 #define MACB_INCSTAT_OFFSET     6 /* Incremental stats regs */
 216 #define MACB_INCSTAT_SIZE       1
 217 #define MACB_WESTAT_OFFSET      7 /* Write enable stats regs */
 218 #define MACB_WESTAT_SIZE        1
 219 #define MACB_BP_OFFSET          8 /* Back pressure */
 220 #define MACB_BP_SIZE            1
 221 #define MACB_TSTART_OFFSET      9 /* Start transmission */
 222 #define MACB_TSTART_SIZE        1
 223 #define MACB_THALT_OFFSET       10 /* Transmit halt */
 224 #define MACB_THALT_SIZE         1
 225 #define MACB_NCR_TPF_OFFSET     11 /* Transmit pause frame */
 226 #define MACB_NCR_TPF_SIZE       1
 227 #define MACB_TZQ_OFFSET         12 /* Transmit zero quantum pause frame */
 228 #define MACB_TZQ_SIZE           1
 229 #define MACB_SRTSM_OFFSET       15
 230 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
 231 #define MACB_OSSMODE_SIZE       1
 232 
 233 /* Bitfields in NCFGR */
 234 #define MACB_SPD_OFFSET         0 /* Speed */
 235 #define MACB_SPD_SIZE           1
 236 #define MACB_FD_OFFSET          1 /* Full duplex */
 237 #define MACB_FD_SIZE            1
 238 #define MACB_BIT_RATE_OFFSET    2 /* Discard non-VLAN frames */
 239 #define MACB_BIT_RATE_SIZE      1
 240 #define MACB_JFRAME_OFFSET      3 /* reserved */
 241 #define MACB_JFRAME_SIZE        1
 242 #define MACB_CAF_OFFSET         4 /* Copy all frames */
 243 #define MACB_CAF_SIZE           1
 244 #define MACB_NBC_OFFSET         5 /* No broadcast */
 245 #define MACB_NBC_SIZE           1
 246 #define MACB_NCFGR_MTI_OFFSET   6 /* Multicast hash enable */
 247 #define MACB_NCFGR_MTI_SIZE     1
 248 #define MACB_UNI_OFFSET         7 /* Unicast hash enable */
 249 #define MACB_UNI_SIZE           1
 250 #define MACB_BIG_OFFSET         8 /* Receive 1536 byte frames */
 251 #define MACB_BIG_SIZE           1
 252 #define MACB_EAE_OFFSET         9 /* External address match enable */
 253 #define MACB_EAE_SIZE           1
 254 #define MACB_CLK_OFFSET         10
 255 #define MACB_CLK_SIZE           2
 256 #define MACB_RTY_OFFSET         12 /* Retry test */
 257 #define MACB_RTY_SIZE           1
 258 #define MACB_PAE_OFFSET         13 /* Pause enable */
 259 #define MACB_PAE_SIZE           1
 260 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
 261 #define MACB_RM9200_RMII_SIZE   1  /* AT91RM9200 only */
 262 #define MACB_RBOF_OFFSET        14 /* Receive buffer offset */
 263 #define MACB_RBOF_SIZE          2
 264 #define MACB_RLCE_OFFSET        16 /* Length field error frame discard */
 265 #define MACB_RLCE_SIZE          1
 266 #define MACB_DRFCS_OFFSET       17 /* FCS remove */
 267 #define MACB_DRFCS_SIZE         1
 268 #define MACB_EFRHD_OFFSET       18
 269 #define MACB_EFRHD_SIZE         1
 270 #define MACB_IRXFCS_OFFSET      19
 271 #define MACB_IRXFCS_SIZE        1
 272 
 273 /* GEM specific NCFGR bitfields. */
 274 #define GEM_GBE_OFFSET          10 /* Gigabit mode enable */
 275 #define GEM_GBE_SIZE            1
 276 #define GEM_PCSSEL_OFFSET       11
 277 #define GEM_PCSSEL_SIZE         1
 278 #define GEM_CLK_OFFSET          18 /* MDC clock division */
 279 #define GEM_CLK_SIZE            3
 280 #define GEM_DBW_OFFSET          21 /* Data bus width */
 281 #define GEM_DBW_SIZE            2
 282 #define GEM_RXCOEN_OFFSET       24
 283 #define GEM_RXCOEN_SIZE         1
 284 #define GEM_SGMIIEN_OFFSET      27
 285 #define GEM_SGMIIEN_SIZE        1
 286 
 287 
 288 /* Constants for data bus width. */
 289 #define GEM_DBW32               0 /* 32 bit AMBA AHB data bus width */
 290 #define GEM_DBW64               1 /* 64 bit AMBA AHB data bus width */
 291 #define GEM_DBW128              2 /* 128 bit AMBA AHB data bus width */
 292 
 293 /* Bitfields in DMACFG. */
 294 #define GEM_FBLDO_OFFSET        0 /* fixed burst length for DMA */
 295 #define GEM_FBLDO_SIZE          5
 296 #define GEM_ENDIA_DESC_OFFSET   6 /* endian swap mode for management descriptor access */
 297 #define GEM_ENDIA_DESC_SIZE     1
 298 #define GEM_ENDIA_PKT_OFFSET    7 /* endian swap mode for packet data access */
 299 #define GEM_ENDIA_PKT_SIZE      1
 300 #define GEM_RXBMS_OFFSET        8 /* RX packet buffer memory size select */
 301 #define GEM_RXBMS_SIZE          2
 302 #define GEM_TXPBMS_OFFSET       10 /* TX packet buffer memory size select */
 303 #define GEM_TXPBMS_SIZE         1
 304 #define GEM_TXCOEN_OFFSET       11 /* TX IP/TCP/UDP checksum gen offload */
 305 #define GEM_TXCOEN_SIZE         1
 306 #define GEM_RXBS_OFFSET         16 /* DMA receive buffer size */
 307 #define GEM_RXBS_SIZE           8
 308 #define GEM_DDRP_OFFSET         24 /* disc_when_no_ahb */
 309 #define GEM_DDRP_SIZE           1
 310 #define GEM_RXEXT_OFFSET        28 /* RX extended Buffer Descriptor mode */
 311 #define GEM_RXEXT_SIZE          1
 312 #define GEM_TXEXT_OFFSET        29 /* TX extended Buffer Descriptor mode */
 313 #define GEM_TXEXT_SIZE          1
 314 #define GEM_ADDR64_OFFSET       30 /* Address bus width - 64b or 32b */
 315 #define GEM_ADDR64_SIZE         1
 316 
 317 
 318 /* Bitfields in NSR */
 319 #define MACB_NSR_LINK_OFFSET    0 /* pcs_link_state */
 320 #define MACB_NSR_LINK_SIZE      1
 321 #define MACB_MDIO_OFFSET        1 /* status of the mdio_in pin */
 322 #define MACB_MDIO_SIZE          1
 323 #define MACB_IDLE_OFFSET        2 /* The PHY management logic is idle */
 324 #define MACB_IDLE_SIZE          1
 325 
 326 /* Bitfields in TSR */
 327 #define MACB_UBR_OFFSET         0 /* Used bit read */
 328 #define MACB_UBR_SIZE           1
 329 #define MACB_COL_OFFSET         1 /* Collision occurred */
 330 #define MACB_COL_SIZE           1
 331 #define MACB_TSR_RLE_OFFSET     2 /* Retry limit exceeded */
 332 #define MACB_TSR_RLE_SIZE       1
 333 #define MACB_TGO_OFFSET         3 /* Transmit go */
 334 #define MACB_TGO_SIZE           1
 335 #define MACB_BEX_OFFSET         4 /* TX frame corruption due to AHB error */
 336 #define MACB_BEX_SIZE           1
 337 #define MACB_RM9200_BNQ_OFFSET  4 /* AT91RM9200 only */
 338 #define MACB_RM9200_BNQ_SIZE    1 /* AT91RM9200 only */
 339 #define MACB_COMP_OFFSET        5 /* Trnasmit complete */
 340 #define MACB_COMP_SIZE          1
 341 #define MACB_UND_OFFSET         6 /* Trnasmit under run */
 342 #define MACB_UND_SIZE           1
 343 
 344 /* Bitfields in RSR */
 345 #define MACB_BNA_OFFSET         0 /* Buffer not available */
 346 #define MACB_BNA_SIZE           1
 347 #define MACB_REC_OFFSET         1 /* Frame received */
 348 #define MACB_REC_SIZE           1
 349 #define MACB_OVR_OFFSET         2 /* Receive overrun */
 350 #define MACB_OVR_SIZE           1
 351 
 352 /* Bitfields in ISR/IER/IDR/IMR */
 353 #define MACB_MFD_OFFSET         0 /* Management frame sent */
 354 #define MACB_MFD_SIZE           1
 355 #define MACB_RCOMP_OFFSET       1 /* Receive complete */
 356 #define MACB_RCOMP_SIZE         1
 357 #define MACB_RXUBR_OFFSET       2 /* RX used bit read */
 358 #define MACB_RXUBR_SIZE         1
 359 #define MACB_TXUBR_OFFSET       3 /* TX used bit read */
 360 #define MACB_TXUBR_SIZE         1
 361 #define MACB_ISR_TUND_OFFSET    4 /* Enable TX buffer under run interrupt */
 362 #define MACB_ISR_TUND_SIZE      1
 363 #define MACB_ISR_RLE_OFFSET     5 /* EN retry exceeded/late coll interrupt */
 364 #define MACB_ISR_RLE_SIZE       1
 365 #define MACB_TXERR_OFFSET       6 /* EN TX frame corrupt from error interrupt */
 366 #define MACB_TXERR_SIZE         1
 367 #define MACB_TCOMP_OFFSET       7 /* Enable transmit complete interrupt */
 368 #define MACB_TCOMP_SIZE         1
 369 #define MACB_ISR_LINK_OFFSET    9 /* Enable link change interrupt */
 370 #define MACB_ISR_LINK_SIZE      1
 371 #define MACB_ISR_ROVR_OFFSET    10 /* Enable receive overrun interrupt */
 372 #define MACB_ISR_ROVR_SIZE      1
 373 #define MACB_HRESP_OFFSET       11 /* Enable hrsep not OK interrupt */
 374 #define MACB_HRESP_SIZE         1
 375 #define MACB_PFR_OFFSET         12 /* Enable pause frame w/ quantum interrupt */
 376 #define MACB_PFR_SIZE           1
 377 #define MACB_PTZ_OFFSET         13 /* Enable pause time zero interrupt */
 378 #define MACB_PTZ_SIZE           1
 379 #define MACB_WOL_OFFSET         14 /* Enable wake-on-lan interrupt */
 380 #define MACB_WOL_SIZE           1
 381 #define MACB_DRQFR_OFFSET       18 /* PTP Delay Request Frame Received */
 382 #define MACB_DRQFR_SIZE         1
 383 #define MACB_SFR_OFFSET         19 /* PTP Sync Frame Received */
 384 #define MACB_SFR_SIZE           1
 385 #define MACB_DRQFT_OFFSET       20 /* PTP Delay Request Frame Transmitted */
 386 #define MACB_DRQFT_SIZE         1
 387 #define MACB_SFT_OFFSET         21 /* PTP Sync Frame Transmitted */
 388 #define MACB_SFT_SIZE           1
 389 #define MACB_PDRQFR_OFFSET      22 /* PDelay Request Frame Received */
 390 #define MACB_PDRQFR_SIZE        1
 391 #define MACB_PDRSFR_OFFSET      23 /* PDelay Response Frame Received */
 392 #define MACB_PDRSFR_SIZE        1
 393 #define MACB_PDRQFT_OFFSET      24 /* PDelay Request Frame Transmitted */
 394 #define MACB_PDRQFT_SIZE        1
 395 #define MACB_PDRSFT_OFFSET      25 /* PDelay Response Frame Transmitted */
 396 #define MACB_PDRSFT_SIZE        1
 397 #define MACB_SRI_OFFSET         26 /* TSU Seconds Register Increment */
 398 #define MACB_SRI_SIZE           1
 399 
 400 /* Timer increment fields */
 401 #define MACB_TI_CNS_OFFSET      0
 402 #define MACB_TI_CNS_SIZE        8
 403 #define MACB_TI_ACNS_OFFSET     8
 404 #define MACB_TI_ACNS_SIZE       8
 405 #define MACB_TI_NIT_OFFSET      16
 406 #define MACB_TI_NIT_SIZE        8
 407 
 408 /* Bitfields in MAN */
 409 #define MACB_DATA_OFFSET        0 /* data */
 410 #define MACB_DATA_SIZE          16
 411 #define MACB_CODE_OFFSET        16 /* Must be written to 10 */
 412 #define MACB_CODE_SIZE          2
 413 #define MACB_REGA_OFFSET        18 /* Register address */
 414 #define MACB_REGA_SIZE          5
 415 #define MACB_PHYA_OFFSET        23 /* PHY address */
 416 #define MACB_PHYA_SIZE          5
 417 #define MACB_RW_OFFSET          28 /* Operation. 10 is read. 01 is write. */
 418 #define MACB_RW_SIZE            2
 419 #define MACB_SOF_OFFSET         30 /* Must be written to 1 for Clause 22 */
 420 #define MACB_SOF_SIZE           2
 421 
 422 /* Bitfields in USRIO (AVR32) */
 423 #define MACB_MII_OFFSET                         0
 424 #define MACB_MII_SIZE                           1
 425 #define MACB_EAM_OFFSET                         1
 426 #define MACB_EAM_SIZE                           1
 427 #define MACB_TX_PAUSE_OFFSET                    2
 428 #define MACB_TX_PAUSE_SIZE                      1
 429 #define MACB_TX_PAUSE_ZERO_OFFSET               3
 430 #define MACB_TX_PAUSE_ZERO_SIZE                 1
 431 
 432 /* Bitfields in USRIO (AT91) */
 433 #define MACB_RMII_OFFSET                        0
 434 #define MACB_RMII_SIZE                          1
 435 #define GEM_RGMII_OFFSET                        0 /* GEM gigabit mode */
 436 #define GEM_RGMII_SIZE                          1
 437 #define MACB_CLKEN_OFFSET                       1
 438 #define MACB_CLKEN_SIZE                         1
 439 
 440 /* Bitfields in WOL */
 441 #define MACB_IP_OFFSET                          0
 442 #define MACB_IP_SIZE                            16
 443 #define MACB_MAG_OFFSET                         16
 444 #define MACB_MAG_SIZE                           1
 445 #define MACB_ARP_OFFSET                         17
 446 #define MACB_ARP_SIZE                           1
 447 #define MACB_SA1_OFFSET                         18
 448 #define MACB_SA1_SIZE                           1
 449 #define MACB_WOL_MTI_OFFSET                     19
 450 #define MACB_WOL_MTI_SIZE                       1
 451 
 452 /* Bitfields in MID */
 453 #define MACB_IDNUM_OFFSET                       16
 454 #define MACB_IDNUM_SIZE                         12
 455 #define MACB_REV_OFFSET                         0
 456 #define MACB_REV_SIZE                           16
 457 
 458 /* Bitfields in DCFG1. */
 459 #define GEM_IRQCOR_OFFSET                       23
 460 #define GEM_IRQCOR_SIZE                         1
 461 #define GEM_DBWDEF_OFFSET                       25
 462 #define GEM_DBWDEF_SIZE                         3
 463 
 464 /* Bitfields in DCFG2. */
 465 #define GEM_RX_PKT_BUFF_OFFSET                  20
 466 #define GEM_RX_PKT_BUFF_SIZE                    1
 467 #define GEM_TX_PKT_BUFF_OFFSET                  21
 468 #define GEM_TX_PKT_BUFF_SIZE                    1
 469 
 470 
 471 /* Bitfields in DCFG5. */
 472 #define GEM_TSU_OFFSET                          8
 473 #define GEM_TSU_SIZE                            1
 474 
 475 /* Bitfields in DCFG6. */
 476 #define GEM_PBUF_LSO_OFFSET                     27
 477 #define GEM_PBUF_LSO_SIZE                       1
 478 #define GEM_DAW64_OFFSET                        23
 479 #define GEM_DAW64_SIZE                          1
 480 
 481 /* Bitfields in DCFG8. */
 482 #define GEM_T1SCR_OFFSET                        24
 483 #define GEM_T1SCR_SIZE                          8
 484 #define GEM_T2SCR_OFFSET                        16
 485 #define GEM_T2SCR_SIZE                          8
 486 #define GEM_SCR2ETH_OFFSET                      8
 487 #define GEM_SCR2ETH_SIZE                        8
 488 #define GEM_SCR2CMP_OFFSET                      0
 489 #define GEM_SCR2CMP_SIZE                        8
 490 
 491 /* Bitfields in DCFG10 */
 492 #define GEM_TXBD_RDBUFF_OFFSET                  12
 493 #define GEM_TXBD_RDBUFF_SIZE                    4
 494 #define GEM_RXBD_RDBUFF_OFFSET                  8
 495 #define GEM_RXBD_RDBUFF_SIZE                    4
 496 
 497 /* Bitfields in TISUBN */
 498 #define GEM_SUBNSINCR_OFFSET                    0
 499 #define GEM_SUBNSINCRL_OFFSET                   24
 500 #define GEM_SUBNSINCRL_SIZE                     8
 501 #define GEM_SUBNSINCRH_OFFSET                   0
 502 #define GEM_SUBNSINCRH_SIZE                     16
 503 #define GEM_SUBNSINCR_SIZE                      24
 504 
 505 /* Bitfields in TI */
 506 #define GEM_NSINCR_OFFSET                       0
 507 #define GEM_NSINCR_SIZE                         8
 508 
 509 /* Bitfields in TSH */
 510 #define GEM_TSH_OFFSET                          0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
 511 #define GEM_TSH_SIZE                            16
 512 
 513 /* Bitfields in TSL */
 514 #define GEM_TSL_OFFSET                          0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
 515 #define GEM_TSL_SIZE                            32
 516 
 517 /* Bitfields in TN */
 518 #define GEM_TN_OFFSET                           0 /* TSU timer value (ns) */
 519 #define GEM_TN_SIZE                                     30
 520 
 521 /* Bitfields in TXBDCTRL */
 522 #define GEM_TXTSMODE_OFFSET                     4 /* TX Descriptor Timestamp Insertion mode */
 523 #define GEM_TXTSMODE_SIZE                       2
 524 
 525 /* Bitfields in RXBDCTRL */
 526 #define GEM_RXTSMODE_OFFSET                     4 /* RX Descriptor Timestamp Insertion mode */
 527 #define GEM_RXTSMODE_SIZE                       2
 528 
 529 /* Bitfields in SCRT2 */
 530 #define GEM_QUEUE_OFFSET                        0 /* Queue Number */
 531 #define GEM_QUEUE_SIZE                          4
 532 #define GEM_VLANPR_OFFSET                       4 /* VLAN Priority */
 533 #define GEM_VLANPR_SIZE                         3
 534 #define GEM_VLANEN_OFFSET                       8 /* VLAN Enable */
 535 #define GEM_VLANEN_SIZE                         1
 536 #define GEM_ETHT2IDX_OFFSET                     9 /* Index to screener type 2 EtherType register */
 537 #define GEM_ETHT2IDX_SIZE                       3
 538 #define GEM_ETHTEN_OFFSET                       12 /* EtherType Enable */
 539 #define GEM_ETHTEN_SIZE                         1
 540 #define GEM_CMPA_OFFSET                         13 /* Compare A - Index to screener type 2 Compare register */
 541 #define GEM_CMPA_SIZE                           5
 542 #define GEM_CMPAEN_OFFSET                       18 /* Compare A Enable */
 543 #define GEM_CMPAEN_SIZE                         1
 544 #define GEM_CMPB_OFFSET                         19 /* Compare B - Index to screener type 2 Compare register */
 545 #define GEM_CMPB_SIZE                           5
 546 #define GEM_CMPBEN_OFFSET                       24 /* Compare B Enable */
 547 #define GEM_CMPBEN_SIZE                         1
 548 #define GEM_CMPC_OFFSET                         25 /* Compare C - Index to screener type 2 Compare register */
 549 #define GEM_CMPC_SIZE                           5
 550 #define GEM_CMPCEN_OFFSET                       30 /* Compare C Enable */
 551 #define GEM_CMPCEN_SIZE                         1
 552 
 553 /* Bitfields in ETHT */
 554 #define GEM_ETHTCMP_OFFSET                      0 /* EtherType compare value */
 555 #define GEM_ETHTCMP_SIZE                        16
 556 
 557 /* Bitfields in T2CMPW0 */
 558 #define GEM_T2CMP_OFFSET                        16 /* 0xFFFF0000 compare value */
 559 #define GEM_T2CMP_SIZE                          16
 560 #define GEM_T2MASK_OFFSET                       0 /* 0x0000FFFF compare value or mask */
 561 #define GEM_T2MASK_SIZE                         16
 562 
 563 /* Bitfields in T2CMPW1 */
 564 #define GEM_T2DISMSK_OFFSET                     9 /* disable mask */
 565 #define GEM_T2DISMSK_SIZE                       1
 566 #define GEM_T2CMPOFST_OFFSET                    7 /* compare offset */
 567 #define GEM_T2CMPOFST_SIZE                      2
 568 #define GEM_T2OFST_OFFSET                       0 /* offset value */
 569 #define GEM_T2OFST_SIZE                         7
 570 
 571 /* Offset for screener type 2 compare values (T2CMPOFST).
 572  * Note the offset is applied after the specified point,
 573  * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
 574  * of 12 bytes from this would be the source IP address in an IP header
 575  */
 576 #define GEM_T2COMPOFST_SOF              0
 577 #define GEM_T2COMPOFST_ETYPE    1
 578 #define GEM_T2COMPOFST_IPHDR    2
 579 #define GEM_T2COMPOFST_TCPUDP   3
 580 
 581 /* offset from EtherType to IP address */
 582 #define ETYPE_SRCIP_OFFSET                      12
 583 #define ETYPE_DSTIP_OFFSET                      16
 584 
 585 /* offset from IP header to port */
 586 #define IPHDR_SRCPORT_OFFSET            0
 587 #define IPHDR_DSTPORT_OFFSET            2
 588 
 589 /* Transmit DMA buffer descriptor Word 1 */
 590 #define GEM_DMA_TXVALID_OFFSET          23 /* timestamp has been captured in the Buffer Descriptor */
 591 #define GEM_DMA_TXVALID_SIZE            1
 592 
 593 /* Receive DMA buffer descriptor Word 0 */
 594 #define GEM_DMA_RXVALID_OFFSET          2 /* indicates a valid timestamp in the Buffer Descriptor */
 595 #define GEM_DMA_RXVALID_SIZE            1
 596 
 597 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
 598 #define GEM_DMA_SECL_OFFSET                     30 /* Timestamp seconds[1:0]  */
 599 #define GEM_DMA_SECL_SIZE                       2
 600 #define GEM_DMA_NSEC_OFFSET                     0 /* Timestamp nanosecs [29:0] */
 601 #define GEM_DMA_NSEC_SIZE                       30
 602 
 603 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
 604 
 605 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
 606  * Old hardware supports only 6 bit precision but it is enough for PTP.
 607  * Less accuracy is used always instead of checking hardware version.
 608  */
 609 #define GEM_DMA_SECH_OFFSET                     0 /* Timestamp seconds[5:2] */
 610 #define GEM_DMA_SECH_SIZE                       4
 611 #define GEM_DMA_SEC_WIDTH                       (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
 612 #define GEM_DMA_SEC_TOP                         (1 << GEM_DMA_SEC_WIDTH)
 613 #define GEM_DMA_SEC_MASK                        (GEM_DMA_SEC_TOP - 1)
 614 
 615 /* Bitfields in ADJ */
 616 #define GEM_ADDSUB_OFFSET                       31
 617 #define GEM_ADDSUB_SIZE                         1
 618 /* Constants for CLK */
 619 #define MACB_CLK_DIV8                           0
 620 #define MACB_CLK_DIV16                          1
 621 #define MACB_CLK_DIV32                          2
 622 #define MACB_CLK_DIV64                          3
 623 
 624 /* GEM specific constants for CLK. */
 625 #define GEM_CLK_DIV8                            0
 626 #define GEM_CLK_DIV16                           1
 627 #define GEM_CLK_DIV32                           2
 628 #define GEM_CLK_DIV48                           3
 629 #define GEM_CLK_DIV64                           4
 630 #define GEM_CLK_DIV96                           5
 631 
 632 /* Constants for MAN register */
 633 #define MACB_MAN_SOF                            1
 634 #define MACB_MAN_WRITE                          1
 635 #define MACB_MAN_READ                           2
 636 #define MACB_MAN_CODE                           2
 637 
 638 /* Capability mask bits */
 639 #define MACB_CAPS_ISR_CLEAR_ON_WRITE            0x00000001
 640 #define MACB_CAPS_USRIO_HAS_CLKEN               0x00000002
 641 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII     0x00000004
 642 #define MACB_CAPS_NO_GIGABIT_HALF               0x00000008
 643 #define MACB_CAPS_USRIO_DISABLED                0x00000010
 644 #define MACB_CAPS_JUMBO                         0x00000020
 645 #define MACB_CAPS_GEM_HAS_PTP                   0x00000040
 646 #define MACB_CAPS_BD_RD_PREFETCH                0x00000080
 647 #define MACB_CAPS_NEEDS_RSTONUBR                0x00000100
 648 #define MACB_CAPS_FIFO_MODE                     0x10000000
 649 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE        0x20000000
 650 #define MACB_CAPS_SG_DISABLED                   0x40000000
 651 #define MACB_CAPS_MACB_IS_GEM                   0x80000000
 652 
 653 /* LSO settings */
 654 #define MACB_LSO_UFO_ENABLE                     0x01
 655 #define MACB_LSO_TSO_ENABLE                     0x02
 656 
 657 /* Bit manipulation macros */
 658 #define MACB_BIT(name)                                  \
 659         (1 << MACB_##name##_OFFSET)
 660 #define MACB_BF(name,value)                             \
 661         (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
 662          << MACB_##name##_OFFSET)
 663 #define MACB_BFEXT(name,value)\
 664         (((value) >> MACB_##name##_OFFSET)              \
 665          & ((1 << MACB_##name##_SIZE) - 1))
 666 #define MACB_BFINS(name,value,old)                      \
 667         (((old) & ~(((1 << MACB_##name##_SIZE) - 1)     \
 668                     << MACB_##name##_OFFSET))           \
 669          | MACB_BF(name,value))
 670 
 671 #define GEM_BIT(name)                                   \
 672         (1 << GEM_##name##_OFFSET)
 673 #define GEM_BF(name, value)                             \
 674         (((value) & ((1 << GEM_##name##_SIZE) - 1))     \
 675          << GEM_##name##_OFFSET)
 676 #define GEM_BFEXT(name, value)\
 677         (((value) >> GEM_##name##_OFFSET)               \
 678          & ((1 << GEM_##name##_SIZE) - 1))
 679 #define GEM_BFINS(name, value, old)                     \
 680         (((old) & ~(((1 << GEM_##name##_SIZE) - 1)      \
 681                     << GEM_##name##_OFFSET))            \
 682          | GEM_BF(name, value))
 683 
 684 /* Register access macros */
 685 #define macb_readl(port, reg)           (port)->macb_reg_readl((port), MACB_##reg)
 686 #define macb_writel(port, reg, value)   (port)->macb_reg_writel((port), MACB_##reg, (value))
 687 #define gem_readl(port, reg)            (port)->macb_reg_readl((port), GEM_##reg)
 688 #define gem_writel(port, reg, value)    (port)->macb_reg_writel((port), GEM_##reg, (value))
 689 #define queue_readl(queue, reg)         (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
 690 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
 691 #define gem_readl_n(port, reg, idx)             (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
 692 #define gem_writel_n(port, reg, idx, value)     (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
 693 
 694 #define PTP_TS_BUFFER_SIZE              128 /* must be power of 2 */
 695 
 696 /* Conditional GEM/MACB macros.  These perform the operation to the correct
 697  * register dependent on whether the device is a GEM or a MACB.  For registers
 698  * and bitfields that are common across both devices, use macb_{read,write}l
 699  * to avoid the cost of the conditional.
 700  */
 701 #define macb_or_gem_writel(__bp, __reg, __value) \
 702         ({ \
 703                 if (macb_is_gem((__bp))) \
 704                         gem_writel((__bp), __reg, __value); \
 705                 else \
 706                         macb_writel((__bp), __reg, __value); \
 707         })
 708 
 709 #define macb_or_gem_readl(__bp, __reg) \
 710         ({ \
 711                 u32 __v; \
 712                 if (macb_is_gem((__bp))) \
 713                         __v = gem_readl((__bp), __reg); \
 714                 else \
 715                         __v = macb_readl((__bp), __reg); \
 716                 __v; \
 717         })
 718 
 719 #define MACB_READ_NSR(bp)       macb_readl(bp, NSR)
 720 
 721 /* struct macb_dma_desc - Hardware DMA descriptor
 722  * @addr: DMA address of data buffer
 723  * @ctrl: Control and status bits
 724  */
 725 struct macb_dma_desc {
 726         u32     addr;
 727         u32     ctrl;
 728 };
 729 
 730 #ifdef MACB_EXT_DESC
 731 #define HW_DMA_CAP_32B          0
 732 #define HW_DMA_CAP_64B          (1 << 0)
 733 #define HW_DMA_CAP_PTP          (1 << 1)
 734 #define HW_DMA_CAP_64B_PTP      (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
 735 
 736 struct macb_dma_desc_64 {
 737         u32 addrh;
 738         u32 resvd;
 739 };
 740 
 741 struct macb_dma_desc_ptp {
 742         u32     ts_1;
 743         u32     ts_2;
 744 };
 745 
 746 struct gem_tx_ts {
 747         struct sk_buff *skb;
 748         struct macb_dma_desc_ptp desc_ptp;
 749 };
 750 #endif
 751 
 752 /* DMA descriptor bitfields */
 753 #define MACB_RX_USED_OFFSET                     0
 754 #define MACB_RX_USED_SIZE                       1
 755 #define MACB_RX_WRAP_OFFSET                     1
 756 #define MACB_RX_WRAP_SIZE                       1
 757 #define MACB_RX_WADDR_OFFSET                    2
 758 #define MACB_RX_WADDR_SIZE                      30
 759 
 760 #define MACB_RX_FRMLEN_OFFSET                   0
 761 #define MACB_RX_FRMLEN_SIZE                     12
 762 #define MACB_RX_OFFSET_OFFSET                   12
 763 #define MACB_RX_OFFSET_SIZE                     2
 764 #define MACB_RX_SOF_OFFSET                      14
 765 #define MACB_RX_SOF_SIZE                        1
 766 #define MACB_RX_EOF_OFFSET                      15
 767 #define MACB_RX_EOF_SIZE                        1
 768 #define MACB_RX_CFI_OFFSET                      16
 769 #define MACB_RX_CFI_SIZE                        1
 770 #define MACB_RX_VLAN_PRI_OFFSET                 17
 771 #define MACB_RX_VLAN_PRI_SIZE                   3
 772 #define MACB_RX_PRI_TAG_OFFSET                  20
 773 #define MACB_RX_PRI_TAG_SIZE                    1
 774 #define MACB_RX_VLAN_TAG_OFFSET                 21
 775 #define MACB_RX_VLAN_TAG_SIZE                   1
 776 #define MACB_RX_TYPEID_MATCH_OFFSET             22
 777 #define MACB_RX_TYPEID_MATCH_SIZE               1
 778 #define MACB_RX_SA4_MATCH_OFFSET                23
 779 #define MACB_RX_SA4_MATCH_SIZE                  1
 780 #define MACB_RX_SA3_MATCH_OFFSET                24
 781 #define MACB_RX_SA3_MATCH_SIZE                  1
 782 #define MACB_RX_SA2_MATCH_OFFSET                25
 783 #define MACB_RX_SA2_MATCH_SIZE                  1
 784 #define MACB_RX_SA1_MATCH_OFFSET                26
 785 #define MACB_RX_SA1_MATCH_SIZE                  1
 786 #define MACB_RX_EXT_MATCH_OFFSET                28
 787 #define MACB_RX_EXT_MATCH_SIZE                  1
 788 #define MACB_RX_UHASH_MATCH_OFFSET              29
 789 #define MACB_RX_UHASH_MATCH_SIZE                1
 790 #define MACB_RX_MHASH_MATCH_OFFSET              30
 791 #define MACB_RX_MHASH_MATCH_SIZE                1
 792 #define MACB_RX_BROADCAST_OFFSET                31
 793 #define MACB_RX_BROADCAST_SIZE                  1
 794 
 795 #define MACB_RX_FRMLEN_MASK                     0xFFF
 796 #define MACB_RX_JFRMLEN_MASK                    0x3FFF
 797 
 798 /* RX checksum offload disabled: bit 24 clear in NCFGR */
 799 #define GEM_RX_TYPEID_MATCH_OFFSET              22
 800 #define GEM_RX_TYPEID_MATCH_SIZE                2
 801 
 802 /* RX checksum offload enabled: bit 24 set in NCFGR */
 803 #define GEM_RX_CSUM_OFFSET                      22
 804 #define GEM_RX_CSUM_SIZE                        2
 805 
 806 #define MACB_TX_FRMLEN_OFFSET                   0
 807 #define MACB_TX_FRMLEN_SIZE                     11
 808 #define MACB_TX_LAST_OFFSET                     15
 809 #define MACB_TX_LAST_SIZE                       1
 810 #define MACB_TX_NOCRC_OFFSET                    16
 811 #define MACB_TX_NOCRC_SIZE                      1
 812 #define MACB_MSS_MFS_OFFSET                     16
 813 #define MACB_MSS_MFS_SIZE                       14
 814 #define MACB_TX_LSO_OFFSET                      17
 815 #define MACB_TX_LSO_SIZE                        2
 816 #define MACB_TX_TCP_SEQ_SRC_OFFSET              19
 817 #define MACB_TX_TCP_SEQ_SRC_SIZE                1
 818 #define MACB_TX_BUF_EXHAUSTED_OFFSET            27
 819 #define MACB_TX_BUF_EXHAUSTED_SIZE              1
 820 #define MACB_TX_UNDERRUN_OFFSET                 28
 821 #define MACB_TX_UNDERRUN_SIZE                   1
 822 #define MACB_TX_ERROR_OFFSET                    29
 823 #define MACB_TX_ERROR_SIZE                      1
 824 #define MACB_TX_WRAP_OFFSET                     30
 825 #define MACB_TX_WRAP_SIZE                       1
 826 #define MACB_TX_USED_OFFSET                     31
 827 #define MACB_TX_USED_SIZE                       1
 828 
 829 #define GEM_TX_FRMLEN_OFFSET                    0
 830 #define GEM_TX_FRMLEN_SIZE                      14
 831 
 832 /* Buffer descriptor constants */
 833 #define GEM_RX_CSUM_NONE                        0
 834 #define GEM_RX_CSUM_IP_ONLY                     1
 835 #define GEM_RX_CSUM_IP_TCP                      2
 836 #define GEM_RX_CSUM_IP_UDP                      3
 837 
 838 /* limit RX checksum offload to TCP and UDP packets */
 839 #define GEM_RX_CSUM_CHECKED_MASK                2
 840 
 841 /* Scaled PPM fraction */
 842 #define PPM_FRACTION    16
 843 
 844 /* struct macb_tx_skb - data about an skb which is being transmitted
 845  * @skb: skb currently being transmitted, only set for the last buffer
 846  *       of the frame
 847  * @mapping: DMA address of the skb's fragment buffer
 848  * @size: size of the DMA mapped buffer
 849  * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
 850  *                  false when buffer was mapped with dma_map_single()
 851  */
 852 struct macb_tx_skb {
 853         struct sk_buff          *skb;
 854         dma_addr_t              mapping;
 855         size_t                  size;
 856         bool                    mapped_as_page;
 857 };
 858 
 859 /* Hardware-collected statistics. Used when updating the network
 860  * device stats by a periodic timer.
 861  */
 862 struct macb_stats {
 863         u32     rx_pause_frames;
 864         u32     tx_ok;
 865         u32     tx_single_cols;
 866         u32     tx_multiple_cols;
 867         u32     rx_ok;
 868         u32     rx_fcs_errors;
 869         u32     rx_align_errors;
 870         u32     tx_deferred;
 871         u32     tx_late_cols;
 872         u32     tx_excessive_cols;
 873         u32     tx_underruns;
 874         u32     tx_carrier_errors;
 875         u32     rx_resource_errors;
 876         u32     rx_overruns;
 877         u32     rx_symbol_errors;
 878         u32     rx_oversize_pkts;
 879         u32     rx_jabbers;
 880         u32     rx_undersize_pkts;
 881         u32     sqe_test_errors;
 882         u32     rx_length_mismatch;
 883         u32     tx_pause_frames;
 884 };
 885 
 886 struct gem_stats {
 887         u32     tx_octets_31_0;
 888         u32     tx_octets_47_32;
 889         u32     tx_frames;
 890         u32     tx_broadcast_frames;
 891         u32     tx_multicast_frames;
 892         u32     tx_pause_frames;
 893         u32     tx_64_byte_frames;
 894         u32     tx_65_127_byte_frames;
 895         u32     tx_128_255_byte_frames;
 896         u32     tx_256_511_byte_frames;
 897         u32     tx_512_1023_byte_frames;
 898         u32     tx_1024_1518_byte_frames;
 899         u32     tx_greater_than_1518_byte_frames;
 900         u32     tx_underrun;
 901         u32     tx_single_collision_frames;
 902         u32     tx_multiple_collision_frames;
 903         u32     tx_excessive_collisions;
 904         u32     tx_late_collisions;
 905         u32     tx_deferred_frames;
 906         u32     tx_carrier_sense_errors;
 907         u32     rx_octets_31_0;
 908         u32     rx_octets_47_32;
 909         u32     rx_frames;
 910         u32     rx_broadcast_frames;
 911         u32     rx_multicast_frames;
 912         u32     rx_pause_frames;
 913         u32     rx_64_byte_frames;
 914         u32     rx_65_127_byte_frames;
 915         u32     rx_128_255_byte_frames;
 916         u32     rx_256_511_byte_frames;
 917         u32     rx_512_1023_byte_frames;
 918         u32     rx_1024_1518_byte_frames;
 919         u32     rx_greater_than_1518_byte_frames;
 920         u32     rx_undersized_frames;
 921         u32     rx_oversize_frames;
 922         u32     rx_jabbers;
 923         u32     rx_frame_check_sequence_errors;
 924         u32     rx_length_field_frame_errors;
 925         u32     rx_symbol_errors;
 926         u32     rx_alignment_errors;
 927         u32     rx_resource_errors;
 928         u32     rx_overruns;
 929         u32     rx_ip_header_checksum_errors;
 930         u32     rx_tcp_checksum_errors;
 931         u32     rx_udp_checksum_errors;
 932 };
 933 
 934 /* Describes the name and offset of an individual statistic register, as
 935  * returned by `ethtool -S`. Also describes which net_device_stats statistics
 936  * this register should contribute to.
 937  */
 938 struct gem_statistic {
 939         char stat_string[ETH_GSTRING_LEN];
 940         int offset;
 941         u32 stat_bits;
 942 };
 943 
 944 /* Bitfield defs for net_device_stat statistics */
 945 #define GEM_NDS_RXERR_OFFSET            0
 946 #define GEM_NDS_RXLENERR_OFFSET         1
 947 #define GEM_NDS_RXOVERERR_OFFSET        2
 948 #define GEM_NDS_RXCRCERR_OFFSET         3
 949 #define GEM_NDS_RXFRAMEERR_OFFSET       4
 950 #define GEM_NDS_RXFIFOERR_OFFSET        5
 951 #define GEM_NDS_TXERR_OFFSET            6
 952 #define GEM_NDS_TXABORTEDERR_OFFSET     7
 953 #define GEM_NDS_TXCARRIERERR_OFFSET     8
 954 #define GEM_NDS_TXFIFOERR_OFFSET        9
 955 #define GEM_NDS_COLLISIONS_OFFSET       10
 956 
 957 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
 958 #define GEM_STAT_TITLE_BITS(name, title, bits) {        \
 959         .stat_string = title,                           \
 960         .offset = GEM_##name,                           \
 961         .stat_bits = bits                               \
 962 }
 963 
 964 /* list of gem statistic registers. The names MUST match the
 965  * corresponding GEM_* definitions.
 966  */
 967 static const struct gem_statistic gem_statistics[] = {
 968         GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
 969         GEM_STAT_TITLE(TXCNT, "tx_frames"),
 970         GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
 971         GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
 972         GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
 973         GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
 974         GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
 975         GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
 976         GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
 977         GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
 978         GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
 979         GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
 980         GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
 981                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
 982         GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
 983                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 984         GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
 985                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 986         GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
 987                             GEM_BIT(NDS_TXERR)|
 988                             GEM_BIT(NDS_TXABORTEDERR)|
 989                             GEM_BIT(NDS_COLLISIONS)),
 990         GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
 991                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 992         GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
 993         GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
 994                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 995         GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
 996         GEM_STAT_TITLE(RXCNT, "rx_frames"),
 997         GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
 998         GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
 999         GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1000         GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1001         GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1002         GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1003         GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1004         GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1005         GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1006         GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1007         GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1008                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1009         GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1010                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1011         GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1012                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1013         GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1014                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1015         GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1016                             GEM_BIT(NDS_RXERR)),
1017         GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1018                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1019         GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1020                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1021         GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1022                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1023         GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1024                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1025         GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1026                             GEM_BIT(NDS_RXERR)),
1027         GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1028                             GEM_BIT(NDS_RXERR)),
1029         GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1030                             GEM_BIT(NDS_RXERR)),
1031 };
1032 
1033 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1034 
1035 #define QUEUE_STAT_TITLE(title) {       \
1036         .stat_string = title,                   \
1037 }
1038 
1039 /* per queue statistics, each should be unsigned long type */
1040 struct queue_stats {
1041         union {
1042                 unsigned long first;
1043                 unsigned long rx_packets;
1044         };
1045         unsigned long rx_bytes;
1046         unsigned long rx_dropped;
1047         unsigned long tx_packets;
1048         unsigned long tx_bytes;
1049         unsigned long tx_dropped;
1050 };
1051 
1052 static const struct gem_statistic queue_statistics[] = {
1053                 QUEUE_STAT_TITLE("rx_packets"),
1054                 QUEUE_STAT_TITLE("rx_bytes"),
1055                 QUEUE_STAT_TITLE("rx_dropped"),
1056                 QUEUE_STAT_TITLE("tx_packets"),
1057                 QUEUE_STAT_TITLE("tx_bytes"),
1058                 QUEUE_STAT_TITLE("tx_dropped"),
1059 };
1060 
1061 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1062 
1063 struct macb;
1064 struct macb_queue;
1065 
1066 struct macb_or_gem_ops {
1067         int     (*mog_alloc_rx_buffers)(struct macb *bp);
1068         void    (*mog_free_rx_buffers)(struct macb *bp);
1069         void    (*mog_init_rings)(struct macb *bp);
1070         int     (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1071                           int budget);
1072 };
1073 
1074 /* MACB-PTP interface: adapt to platform needs. */
1075 struct macb_ptp_info {
1076         void (*ptp_init)(struct net_device *ndev);
1077         void (*ptp_remove)(struct net_device *ndev);
1078         s32 (*get_ptp_max_adj)(void);
1079         unsigned int (*get_tsu_rate)(struct macb *bp);
1080         int (*get_ts_info)(struct net_device *dev,
1081                            struct ethtool_ts_info *info);
1082         int (*get_hwtst)(struct net_device *netdev,
1083                          struct ifreq *ifr);
1084         int (*set_hwtst)(struct net_device *netdev,
1085                          struct ifreq *ifr, int cmd);
1086 };
1087 
1088 struct macb_pm_data {
1089         u32 scrt2;
1090         u32 usrio;
1091 };
1092 
1093 struct macb_config {
1094         u32                     caps;
1095         unsigned int            dma_burst_length;
1096         int     (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1097                             struct clk **hclk, struct clk **tx_clk,
1098                             struct clk **rx_clk, struct clk **tsu_clk);
1099         int     (*init)(struct platform_device *pdev);
1100         int     jumbo_max_len;
1101 };
1102 
1103 struct tsu_incr {
1104         u32 sub_ns;
1105         u32 ns;
1106 };
1107 
1108 struct macb_queue {
1109         struct macb             *bp;
1110         int                     irq;
1111 
1112         unsigned int            ISR;
1113         unsigned int            IER;
1114         unsigned int            IDR;
1115         unsigned int            IMR;
1116         unsigned int            TBQP;
1117         unsigned int            TBQPH;
1118         unsigned int            RBQS;
1119         unsigned int            RBQP;
1120         unsigned int            RBQPH;
1121 
1122         unsigned int            tx_head, tx_tail;
1123         struct macb_dma_desc    *tx_ring;
1124         struct macb_tx_skb      *tx_skb;
1125         dma_addr_t              tx_ring_dma;
1126         struct work_struct      tx_error_task;
1127 
1128         dma_addr_t              rx_ring_dma;
1129         dma_addr_t              rx_buffers_dma;
1130         unsigned int            rx_tail;
1131         unsigned int            rx_prepared_head;
1132         struct macb_dma_desc    *rx_ring;
1133         struct sk_buff          **rx_skbuff;
1134         void                    *rx_buffers;
1135         struct napi_struct      napi;
1136         struct queue_stats stats;
1137 
1138 #ifdef CONFIG_MACB_USE_HWSTAMP
1139         struct work_struct      tx_ts_task;
1140         unsigned int            tx_ts_head, tx_ts_tail;
1141         struct gem_tx_ts        tx_timestamps[PTP_TS_BUFFER_SIZE];
1142 #endif
1143 };
1144 
1145 struct ethtool_rx_fs_item {
1146         struct ethtool_rx_flow_spec fs;
1147         struct list_head list;
1148 };
1149 
1150 struct ethtool_rx_fs_list {
1151         struct list_head list;
1152         unsigned int count;
1153 };
1154 
1155 struct macb {
1156         void __iomem            *regs;
1157         bool                    native_io;
1158 
1159         /* hardware IO accessors */
1160         u32     (*macb_reg_readl)(struct macb *bp, int offset);
1161         void    (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1162 
1163         size_t                  rx_buffer_size;
1164 
1165         unsigned int            rx_ring_size;
1166         unsigned int            tx_ring_size;
1167 
1168         unsigned int            num_queues;
1169         unsigned int            queue_mask;
1170         struct macb_queue       queues[MACB_MAX_QUEUES];
1171 
1172         spinlock_t              lock;
1173         struct platform_device  *pdev;
1174         struct clk              *pclk;
1175         struct clk              *hclk;
1176         struct clk              *tx_clk;
1177         struct clk              *rx_clk;
1178         struct clk              *tsu_clk;
1179         struct net_device       *dev;
1180         union {
1181                 struct macb_stats       macb;
1182                 struct gem_stats        gem;
1183         }                       hw_stats;
1184 
1185         struct macb_or_gem_ops  macbgem_ops;
1186 
1187         struct mii_bus          *mii_bus;
1188         struct device_node      *phy_node;
1189         int                     link;
1190         int                     speed;
1191         int                     duplex;
1192 
1193         u32                     caps;
1194         unsigned int            dma_burst_length;
1195 
1196         phy_interface_t         phy_interface;
1197 
1198         /* AT91RM9200 transmit */
1199         struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
1200         dma_addr_t skb_physaddr;                /* phys addr from pci_map_single */
1201         int skb_length;                         /* saved skb length for pci_unmap_single */
1202         unsigned int            max_tx_length;
1203 
1204         u64                     ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1205 
1206         unsigned int            rx_frm_len_mask;
1207         unsigned int            jumbo_max_len;
1208 
1209         u32                     wol;
1210 
1211         struct macb_ptp_info    *ptp_info;      /* macb-ptp interface */
1212 #ifdef MACB_EXT_DESC
1213         uint8_t hw_dma_cap;
1214 #endif
1215         spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1216         unsigned int tsu_rate;
1217         struct ptp_clock *ptp_clock;
1218         struct ptp_clock_info ptp_clock_info;
1219         struct tsu_incr tsu_incr;
1220         struct hwtstamp_config tstamp_config;
1221 
1222         /* RX queue filer rule set*/
1223         struct ethtool_rx_fs_list rx_fs_list;
1224         spinlock_t rx_fs_lock;
1225         unsigned int max_tuples;
1226 
1227         struct tasklet_struct   hresp_err_tasklet;
1228 
1229         int     rx_bd_rd_prefetch;
1230         int     tx_bd_rd_prefetch;
1231 
1232         u32     rx_intr_mask;
1233 
1234         struct macb_pm_data pm_data;
1235 };
1236 
1237 #ifdef CONFIG_MACB_USE_HWSTAMP
1238 #define GEM_TSEC_SIZE  (GEM_TSH_SIZE + GEM_TSL_SIZE)
1239 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1240 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1241 
1242 enum macb_bd_control {
1243         TSTAMP_DISABLED,
1244         TSTAMP_FRAME_PTP_EVENT_ONLY,
1245         TSTAMP_ALL_PTP_FRAMES,
1246         TSTAMP_ALL_FRAMES,
1247 };
1248 
1249 void gem_ptp_init(struct net_device *ndev);
1250 void gem_ptp_remove(struct net_device *ndev);
1251 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1252 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1253 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1254 {
1255         if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1256                 return -ENOTSUPP;
1257 
1258         return gem_ptp_txstamp(queue, skb, desc);
1259 }
1260 
1261 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1262 {
1263         if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1264                 return;
1265 
1266         gem_ptp_rxstamp(bp, skb, desc);
1267 }
1268 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1269 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1270 #else
1271 static inline void gem_ptp_init(struct net_device *ndev) { }
1272 static inline void gem_ptp_remove(struct net_device *ndev) { }
1273 
1274 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1275 {
1276         return -1;
1277 }
1278 
1279 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1280 #endif
1281 
1282 static inline bool macb_is_gem(struct macb *bp)
1283 {
1284         return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1285 }
1286 
1287 static inline bool gem_has_ptp(struct macb *bp)
1288 {
1289         return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1290 }
1291 
1292 #endif /* _MACB_H */
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