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8 #ifndef _MSCC_OCELOT_H_
9 #define _MSCC_OCELOT_H_
10
11 #include <linux/bitops.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/phy.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/ptp_clock_kernel.h>
19 #include <linux/regmap.h>
20
21 #include "ocelot_ana.h"
22 #include "ocelot_dev.h"
23 #include "ocelot_qsys.h"
24 #include "ocelot_rew.h"
25 #include "ocelot_sys.h"
26 #include "ocelot_qs.h"
27 #include "ocelot_tc.h"
28 #include "ocelot_ptp.h"
29
30 #define PGID_AGGR 64
31 #define PGID_SRC 80
32
33
34 #define PGID_CPU (PGID_AGGR - 5)
35 #define PGID_UC (PGID_AGGR - 4)
36 #define PGID_MC (PGID_AGGR - 3)
37 #define PGID_MCIPV4 (PGID_AGGR - 2)
38 #define PGID_MCIPV6 (PGID_AGGR - 1)
39
40 #define OCELOT_BUFFER_CELL_SZ 60
41
42 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
43
44 #define OCELOT_PTP_QUEUE_SZ 128
45
46 #define IFH_LEN 4
47
48 struct frame_info {
49 u32 len;
50 u16 port;
51 u16 vid;
52 u8 tag_type;
53 u16 rew_op;
54 u32 timestamp;
55 };
56
57 #define IFH_INJ_BYPASS BIT(31)
58 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
59
60 #define IFH_TAG_TYPE_C 0
61 #define IFH_TAG_TYPE_S 1
62
63 #define IFH_REW_OP_NOOP 0x0
64 #define IFH_REW_OP_DSCP 0x1
65 #define IFH_REW_OP_ONE_STEP_PTP 0x2
66 #define IFH_REW_OP_TWO_STEP_PTP 0x3
67 #define IFH_REW_OP_ORIGIN_PTP 0x5
68
69 #define OCELOT_SPEED_2500 0
70 #define OCELOT_SPEED_1000 1
71 #define OCELOT_SPEED_100 2
72 #define OCELOT_SPEED_10 3
73
74 #define TARGET_OFFSET 24
75 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
76 #define REG(reg, offset) [reg & REG_MASK] = offset
77
78 enum ocelot_target {
79 ANA = 1,
80 QS,
81 QSYS,
82 REW,
83 SYS,
84 S2,
85 HSIO,
86 PTP,
87 TARGET_MAX,
88 };
89
90 enum ocelot_reg {
91 ANA_ADVLEARN = ANA << TARGET_OFFSET,
92 ANA_VLANMASK,
93 ANA_PORT_B_DOMAIN,
94 ANA_ANAGEFIL,
95 ANA_ANEVENTS,
96 ANA_STORMLIMIT_BURST,
97 ANA_STORMLIMIT_CFG,
98 ANA_ISOLATED_PORTS,
99 ANA_COMMUNITY_PORTS,
100 ANA_AUTOAGE,
101 ANA_MACTOPTIONS,
102 ANA_LEARNDISC,
103 ANA_AGENCTRL,
104 ANA_MIRRORPORTS,
105 ANA_EMIRRORPORTS,
106 ANA_FLOODING,
107 ANA_FLOODING_IPMC,
108 ANA_SFLOW_CFG,
109 ANA_PORT_MODE,
110 ANA_CUT_THRU_CFG,
111 ANA_PGID_PGID,
112 ANA_TABLES_ANMOVED,
113 ANA_TABLES_MACHDATA,
114 ANA_TABLES_MACLDATA,
115 ANA_TABLES_STREAMDATA,
116 ANA_TABLES_MACACCESS,
117 ANA_TABLES_MACTINDX,
118 ANA_TABLES_VLANACCESS,
119 ANA_TABLES_VLANTIDX,
120 ANA_TABLES_ISDXACCESS,
121 ANA_TABLES_ISDXTIDX,
122 ANA_TABLES_ENTRYLIM,
123 ANA_TABLES_PTP_ID_HIGH,
124 ANA_TABLES_PTP_ID_LOW,
125 ANA_TABLES_STREAMACCESS,
126 ANA_TABLES_STREAMTIDX,
127 ANA_TABLES_SEQ_HISTORY,
128 ANA_TABLES_SEQ_MASK,
129 ANA_TABLES_SFID_MASK,
130 ANA_TABLES_SFIDACCESS,
131 ANA_TABLES_SFIDTIDX,
132 ANA_MSTI_STATE,
133 ANA_OAM_UPM_LM_CNT,
134 ANA_SG_ACCESS_CTRL,
135 ANA_SG_CONFIG_REG_1,
136 ANA_SG_CONFIG_REG_2,
137 ANA_SG_CONFIG_REG_3,
138 ANA_SG_CONFIG_REG_4,
139 ANA_SG_CONFIG_REG_5,
140 ANA_SG_GCL_GS_CONFIG,
141 ANA_SG_GCL_TI_CONFIG,
142 ANA_SG_STATUS_REG_1,
143 ANA_SG_STATUS_REG_2,
144 ANA_SG_STATUS_REG_3,
145 ANA_PORT_VLAN_CFG,
146 ANA_PORT_DROP_CFG,
147 ANA_PORT_QOS_CFG,
148 ANA_PORT_VCAP_CFG,
149 ANA_PORT_VCAP_S1_KEY_CFG,
150 ANA_PORT_VCAP_S2_CFG,
151 ANA_PORT_PCP_DEI_MAP,
152 ANA_PORT_CPU_FWD_CFG,
153 ANA_PORT_CPU_FWD_BPDU_CFG,
154 ANA_PORT_CPU_FWD_GARP_CFG,
155 ANA_PORT_CPU_FWD_CCM_CFG,
156 ANA_PORT_PORT_CFG,
157 ANA_PORT_POL_CFG,
158 ANA_PORT_PTP_CFG,
159 ANA_PORT_PTP_DLY1_CFG,
160 ANA_PORT_PTP_DLY2_CFG,
161 ANA_PORT_SFID_CFG,
162 ANA_PFC_PFC_CFG,
163 ANA_PFC_PFC_TIMER,
164 ANA_IPT_OAM_MEP_CFG,
165 ANA_IPT_IPT,
166 ANA_PPT_PPT,
167 ANA_FID_MAP_FID_MAP,
168 ANA_AGGR_CFG,
169 ANA_CPUQ_CFG,
170 ANA_CPUQ_CFG2,
171 ANA_CPUQ_8021_CFG,
172 ANA_DSCP_CFG,
173 ANA_DSCP_REWR_CFG,
174 ANA_VCAP_RNG_TYPE_CFG,
175 ANA_VCAP_RNG_VAL_CFG,
176 ANA_VRAP_CFG,
177 ANA_VRAP_HDR_DATA,
178 ANA_VRAP_HDR_MASK,
179 ANA_DISCARD_CFG,
180 ANA_FID_CFG,
181 ANA_POL_PIR_CFG,
182 ANA_POL_CIR_CFG,
183 ANA_POL_MODE_CFG,
184 ANA_POL_PIR_STATE,
185 ANA_POL_CIR_STATE,
186 ANA_POL_STATE,
187 ANA_POL_FLOWC,
188 ANA_POL_HYST,
189 ANA_POL_MISC_CFG,
190 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
191 QS_XTR_RD,
192 QS_XTR_FRM_PRUNING,
193 QS_XTR_FLUSH,
194 QS_XTR_DATA_PRESENT,
195 QS_XTR_CFG,
196 QS_INJ_GRP_CFG,
197 QS_INJ_WR,
198 QS_INJ_CTRL,
199 QS_INJ_STATUS,
200 QS_INJ_ERR,
201 QS_INH_DBG,
202 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
203 QSYS_SWITCH_PORT_MODE,
204 QSYS_STAT_CNT_CFG,
205 QSYS_EEE_CFG,
206 QSYS_EEE_THRES,
207 QSYS_IGR_NO_SHARING,
208 QSYS_EGR_NO_SHARING,
209 QSYS_SW_STATUS,
210 QSYS_EXT_CPU_CFG,
211 QSYS_PAD_CFG,
212 QSYS_CPU_GROUP_MAP,
213 QSYS_QMAP,
214 QSYS_ISDX_SGRP,
215 QSYS_TIMED_FRAME_ENTRY,
216 QSYS_TFRM_MISC,
217 QSYS_TFRM_PORT_DLY,
218 QSYS_TFRM_TIMER_CFG_1,
219 QSYS_TFRM_TIMER_CFG_2,
220 QSYS_TFRM_TIMER_CFG_3,
221 QSYS_TFRM_TIMER_CFG_4,
222 QSYS_TFRM_TIMER_CFG_5,
223 QSYS_TFRM_TIMER_CFG_6,
224 QSYS_TFRM_TIMER_CFG_7,
225 QSYS_TFRM_TIMER_CFG_8,
226 QSYS_RED_PROFILE,
227 QSYS_RES_QOS_MODE,
228 QSYS_RES_CFG,
229 QSYS_RES_STAT,
230 QSYS_EGR_DROP_MODE,
231 QSYS_EQ_CTRL,
232 QSYS_EVENTS_CORE,
233 QSYS_QMAXSDU_CFG_0,
234 QSYS_QMAXSDU_CFG_1,
235 QSYS_QMAXSDU_CFG_2,
236 QSYS_QMAXSDU_CFG_3,
237 QSYS_QMAXSDU_CFG_4,
238 QSYS_QMAXSDU_CFG_5,
239 QSYS_QMAXSDU_CFG_6,
240 QSYS_QMAXSDU_CFG_7,
241 QSYS_PREEMPTION_CFG,
242 QSYS_CIR_CFG,
243 QSYS_EIR_CFG,
244 QSYS_SE_CFG,
245 QSYS_SE_DWRR_CFG,
246 QSYS_SE_CONNECT,
247 QSYS_SE_DLB_SENSE,
248 QSYS_CIR_STATE,
249 QSYS_EIR_STATE,
250 QSYS_SE_STATE,
251 QSYS_HSCH_MISC_CFG,
252 QSYS_TAG_CONFIG,
253 QSYS_TAS_PARAM_CFG_CTRL,
254 QSYS_PORT_MAX_SDU,
255 QSYS_PARAM_CFG_REG_1,
256 QSYS_PARAM_CFG_REG_2,
257 QSYS_PARAM_CFG_REG_3,
258 QSYS_PARAM_CFG_REG_4,
259 QSYS_PARAM_CFG_REG_5,
260 QSYS_GCL_CFG_REG_1,
261 QSYS_GCL_CFG_REG_2,
262 QSYS_PARAM_STATUS_REG_1,
263 QSYS_PARAM_STATUS_REG_2,
264 QSYS_PARAM_STATUS_REG_3,
265 QSYS_PARAM_STATUS_REG_4,
266 QSYS_PARAM_STATUS_REG_5,
267 QSYS_PARAM_STATUS_REG_6,
268 QSYS_PARAM_STATUS_REG_7,
269 QSYS_PARAM_STATUS_REG_8,
270 QSYS_PARAM_STATUS_REG_9,
271 QSYS_GCL_STATUS_REG_1,
272 QSYS_GCL_STATUS_REG_2,
273 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
274 REW_TAG_CFG,
275 REW_PORT_CFG,
276 REW_DSCP_CFG,
277 REW_PCP_DEI_QOS_MAP_CFG,
278 REW_PTP_CFG,
279 REW_PTP_DLY1_CFG,
280 REW_RED_TAG_CFG,
281 REW_DSCP_REMAP_DP1_CFG,
282 REW_DSCP_REMAP_CFG,
283 REW_STAT_CFG,
284 REW_REW_STICKY,
285 REW_PPT,
286 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
287 SYS_COUNT_RX_UNICAST,
288 SYS_COUNT_RX_MULTICAST,
289 SYS_COUNT_RX_BROADCAST,
290 SYS_COUNT_RX_SHORTS,
291 SYS_COUNT_RX_FRAGMENTS,
292 SYS_COUNT_RX_JABBERS,
293 SYS_COUNT_RX_CRC_ALIGN_ERRS,
294 SYS_COUNT_RX_SYM_ERRS,
295 SYS_COUNT_RX_64,
296 SYS_COUNT_RX_65_127,
297 SYS_COUNT_RX_128_255,
298 SYS_COUNT_RX_256_1023,
299 SYS_COUNT_RX_1024_1526,
300 SYS_COUNT_RX_1527_MAX,
301 SYS_COUNT_RX_PAUSE,
302 SYS_COUNT_RX_CONTROL,
303 SYS_COUNT_RX_LONGS,
304 SYS_COUNT_RX_CLASSIFIED_DROPS,
305 SYS_COUNT_TX_OCTETS,
306 SYS_COUNT_TX_UNICAST,
307 SYS_COUNT_TX_MULTICAST,
308 SYS_COUNT_TX_BROADCAST,
309 SYS_COUNT_TX_COLLISION,
310 SYS_COUNT_TX_DROPS,
311 SYS_COUNT_TX_PAUSE,
312 SYS_COUNT_TX_64,
313 SYS_COUNT_TX_65_127,
314 SYS_COUNT_TX_128_511,
315 SYS_COUNT_TX_512_1023,
316 SYS_COUNT_TX_1024_1526,
317 SYS_COUNT_TX_1527_MAX,
318 SYS_COUNT_TX_AGING,
319 SYS_RESET_CFG,
320 SYS_SR_ETYPE_CFG,
321 SYS_VLAN_ETYPE_CFG,
322 SYS_PORT_MODE,
323 SYS_FRONT_PORT_MODE,
324 SYS_FRM_AGING,
325 SYS_STAT_CFG,
326 SYS_SW_STATUS,
327 SYS_MISC_CFG,
328 SYS_REW_MAC_HIGH_CFG,
329 SYS_REW_MAC_LOW_CFG,
330 SYS_TIMESTAMP_OFFSET,
331 SYS_CMID,
332 SYS_PAUSE_CFG,
333 SYS_PAUSE_TOT_CFG,
334 SYS_ATOP,
335 SYS_ATOP_TOT_CFG,
336 SYS_MAC_FC_CFG,
337 SYS_MMGT,
338 SYS_MMGT_FAST,
339 SYS_EVENTS_DIF,
340 SYS_EVENTS_CORE,
341 SYS_CNT,
342 SYS_PTP_STATUS,
343 SYS_PTP_TXSTAMP,
344 SYS_PTP_NXT,
345 SYS_PTP_CFG,
346 SYS_RAM_INIT,
347 SYS_CM_ADDR,
348 SYS_CM_DATA_WR,
349 SYS_CM_DATA_RD,
350 SYS_CM_OP,
351 SYS_CM_DATA,
352 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
353 S2_CORE_MV_CFG,
354 S2_CACHE_ENTRY_DAT,
355 S2_CACHE_MASK_DAT,
356 S2_CACHE_ACTION_DAT,
357 S2_CACHE_CNT_DAT,
358 S2_CACHE_TG_DAT,
359 PTP_PIN_CFG = PTP << TARGET_OFFSET,
360 PTP_PIN_TOD_SEC_MSB,
361 PTP_PIN_TOD_SEC_LSB,
362 PTP_PIN_TOD_NSEC,
363 PTP_CFG_MISC,
364 PTP_CLK_CFG_ADJ_CFG,
365 PTP_CLK_CFG_ADJ_FREQ,
366 };
367
368 enum ocelot_regfield {
369 ANA_ADVLEARN_VLAN_CHK,
370 ANA_ADVLEARN_LEARN_MIRROR,
371 ANA_ANEVENTS_FLOOD_DISCARD,
372 ANA_ANEVENTS_MSTI_DROP,
373 ANA_ANEVENTS_ACLKILL,
374 ANA_ANEVENTS_ACLUSED,
375 ANA_ANEVENTS_AUTOAGE,
376 ANA_ANEVENTS_VS2TTL1,
377 ANA_ANEVENTS_STORM_DROP,
378 ANA_ANEVENTS_LEARN_DROP,
379 ANA_ANEVENTS_AGED_ENTRY,
380 ANA_ANEVENTS_CPU_LEARN_FAILED,
381 ANA_ANEVENTS_AUTO_LEARN_FAILED,
382 ANA_ANEVENTS_LEARN_REMOVE,
383 ANA_ANEVENTS_AUTO_LEARNED,
384 ANA_ANEVENTS_AUTO_MOVED,
385 ANA_ANEVENTS_DROPPED,
386 ANA_ANEVENTS_CLASSIFIED_DROP,
387 ANA_ANEVENTS_CLASSIFIED_COPY,
388 ANA_ANEVENTS_VLAN_DISCARD,
389 ANA_ANEVENTS_FWD_DISCARD,
390 ANA_ANEVENTS_MULTICAST_FLOOD,
391 ANA_ANEVENTS_UNICAST_FLOOD,
392 ANA_ANEVENTS_DEST_KNOWN,
393 ANA_ANEVENTS_BUCKET3_MATCH,
394 ANA_ANEVENTS_BUCKET2_MATCH,
395 ANA_ANEVENTS_BUCKET1_MATCH,
396 ANA_ANEVENTS_BUCKET0_MATCH,
397 ANA_ANEVENTS_CPU_OPERATION,
398 ANA_ANEVENTS_DMAC_LOOKUP,
399 ANA_ANEVENTS_SMAC_LOOKUP,
400 ANA_ANEVENTS_SEQ_GEN_ERR_0,
401 ANA_ANEVENTS_SEQ_GEN_ERR_1,
402 ANA_TABLES_MACACCESS_B_DOM,
403 ANA_TABLES_MACTINDX_BUCKET,
404 ANA_TABLES_MACTINDX_M_INDEX,
405 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
406 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
407 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
408 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
409 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
410 SYS_RESET_CFG_CORE_ENA,
411 SYS_RESET_CFG_MEM_ENA,
412 SYS_RESET_CFG_MEM_INIT,
413 REGFIELD_MAX
414 };
415
416 enum ocelot_clk_pins {
417 ALT_PPS_PIN = 1,
418 EXT_CLK_PIN,
419 ALT_LDST_PIN,
420 TOD_ACC_PIN
421 };
422
423 struct ocelot_multicast {
424 struct list_head list;
425 unsigned char addr[ETH_ALEN];
426 u16 vid;
427 u16 ports;
428 };
429
430 struct ocelot_port;
431
432 struct ocelot_stat_layout {
433 u32 offset;
434 char name[ETH_GSTRING_LEN];
435 };
436
437 struct ocelot {
438 struct device *dev;
439
440 struct regmap *targets[TARGET_MAX];
441 struct regmap_field *regfields[REGFIELD_MAX];
442 const u32 *const *map;
443 const struct ocelot_stat_layout *stats_layout;
444 unsigned int num_stats;
445
446 u8 base_mac[ETH_ALEN];
447
448 struct net_device *hw_bridge_dev;
449 u16 bridge_mask;
450 u16 bridge_fwd_mask;
451
452 struct workqueue_struct *ocelot_owq;
453
454 int shared_queue_sz;
455
456 u8 num_phys_ports;
457 u8 num_cpu_ports;
458 struct ocelot_port **ports;
459
460 u32 *lags;
461
462
463 u32 vlan_mask[VLAN_N_VID];
464
465 struct list_head multicast;
466
467
468 struct mutex stats_lock;
469 u64 *stats;
470 struct delayed_work stats_work;
471 struct workqueue_struct *stats_queue;
472
473 u8 ptp:1;
474 struct ptp_clock *ptp_clock;
475 struct ptp_clock_info ptp_info;
476 struct hwtstamp_config hwtstamp_config;
477 struct mutex ptp_lock;
478 spinlock_t ptp_clock_lock;
479 };
480
481 struct ocelot_port {
482 struct net_device *dev;
483 struct ocelot *ocelot;
484 struct phy_device *phy;
485 void __iomem *regs;
486 u8 chip_port;
487
488
489 u16 pvid;
490
491
492 u16 vid;
493
494 u8 vlan_aware;
495
496 u64 *stats;
497
498 phy_interface_t phy_mode;
499 struct phy *serdes;
500
501 struct ocelot_port_tc tc;
502
503 u8 ptp_cmd;
504 struct list_head skbs;
505 u8 ts_id;
506 };
507
508 struct ocelot_skb {
509 struct list_head head;
510 struct sk_buff *skb;
511 u8 id;
512 };
513
514 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
515 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
516 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
517 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
518 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
519
520 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
521 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
522 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
523 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
524 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
525
526 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
527 u32 offset);
528 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
529 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
530 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
531 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
532
533 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
534 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
535
536 int ocelot_regfields_init(struct ocelot *ocelot,
537 const struct reg_field *const regfields);
538 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
539 struct platform_device *pdev,
540 const char *name);
541
542 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
543 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
544
545 int ocelot_init(struct ocelot *ocelot);
546 void ocelot_deinit(struct ocelot *ocelot);
547 int ocelot_chip_init(struct ocelot *ocelot);
548 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
549 void __iomem *regs,
550 struct phy_device *phy);
551
552 extern struct notifier_block ocelot_netdevice_nb;
553 extern struct notifier_block ocelot_switchdev_nb;
554 extern struct notifier_block ocelot_switchdev_blocking_nb;
555
556 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
557 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);
558
559 #endif