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8 #ifndef _MSCC_OCELOT_REW_H_
9 #define _MSCC_OCELOT_REW_H_
10
11 #define REW_PORT_VLAN_CFG_GSZ 0x80
12
13 #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16))
14 #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16)
15 #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16)
16 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(15)
17 #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12))
18 #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12)
19 #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
20 #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0))
21 #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0)
22
23 #define REW_TAG_CFG_GSZ 0x80
24
25 #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7))
26 #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7)
27 #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7)
28 #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5))
29 #define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5)
30 #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5)
31 #define REW_TAG_CFG_TAG_VID_CFG BIT(4)
32 #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2))
33 #define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2)
34 #define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
35 #define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0))
36 #define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0)
37
38 #define REW_PORT_CFG_GSZ 0x80
39
40 #define REW_PORT_CFG_ES0_EN BIT(5)
41 #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3))
42 #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3)
43 #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3)
44 #define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2)
45 #define REW_PORT_CFG_FLUSH_ENA BIT(1)
46 #define REW_PORT_CFG_AGE_DIS BIT(0)
47
48 #define REW_DSCP_CFG_GSZ 0x80
49
50 #define REW_PCP_DEI_QOS_MAP_CFG_GSZ 0x80
51 #define REW_PCP_DEI_QOS_MAP_CFG_RSZ 0x4
52
53 #define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3)
54 #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0))
55 #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0)
56
57 #define REW_PTP_CFG_GSZ 0x80
58
59 #define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7)
60 #define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3))
61 #define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3)
62 #define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3)
63 #define REW_PTP_CFG_PTP_1STEP_DIS BIT(2)
64 #define REW_PTP_CFG_PTP_2STEP_DIS BIT(1)
65 #define REW_PTP_CFG_PTP_UDP_KEEP BIT(0)
66
67 #define REW_PTP_DLY1_CFG_GSZ 0x80
68
69 #define REW_RED_TAG_CFG_GSZ 0x80
70
71 #define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0)
72
73 #define REW_DSCP_REMAP_DP1_CFG_RSZ 0x4
74
75 #define REW_DSCP_REMAP_CFG_RSZ 0x4
76
77 #define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0)
78
79 #define REW_PPT_RSZ 0x4
80
81 #endif