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8 #ifndef _MSCC_OCELOT_QSYS_H_
9 #define _MSCC_OCELOT_QSYS_H_
10
11 #define QSYS_PORT_MODE_RSZ 0x4
12
13 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14 #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
15
16 #define QSYS_SWITCH_PORT_MODE_RSZ 0x4
17
18 #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
19 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
20 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
21 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
22 #define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10)
23 #define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9)
24 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
25 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
26 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
27 #define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0)
28
29 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
30 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
31 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
32 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
33 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
34 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
35
36 #define QSYS_EEE_CFG_RSZ 0x4
37
38 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
39 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
40 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
41 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
42 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
43
44 #define QSYS_SW_STATUS_RSZ 0x4
45
46 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
47 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
48 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
49 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
50 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
51
52 #define QSYS_QMAP_GSZ 0x4
53
54 #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
55 #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
56 #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
57 #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
58 #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
59 #define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
60 #define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
61 #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
62
63 #define QSYS_ISDX_SGRP_GSZ 0x4
64
65 #define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
66
67 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
68 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
69 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
70 #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
71 #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
72 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
73 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
74
75 #define QSYS_RED_PROFILE_RSZ 0x4
76
77 #define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
78 #define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
79 #define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
80 #define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
81 #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
82
83 #define QSYS_RES_CFG_GSZ 0x8
84
85 #define QSYS_RES_STAT_GSZ 0x8
86
87 #define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12))
88 #define QSYS_RES_STAT_INUSE_M GENMASK(23, 12)
89 #define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12)
90 #define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0))
91 #define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0)
92
93 #define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
94 #define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
95 #define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
96 #define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
97 #define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
98
99 #define QSYS_QMAXSDU_CFG_0_RSZ 0x4
100
101 #define QSYS_QMAXSDU_CFG_1_RSZ 0x4
102
103 #define QSYS_QMAXSDU_CFG_2_RSZ 0x4
104
105 #define QSYS_QMAXSDU_CFG_3_RSZ 0x4
106
107 #define QSYS_QMAXSDU_CFG_4_RSZ 0x4
108
109 #define QSYS_QMAXSDU_CFG_5_RSZ 0x4
110
111 #define QSYS_QMAXSDU_CFG_6_RSZ 0x4
112
113 #define QSYS_QMAXSDU_CFG_7_RSZ 0x4
114
115 #define QSYS_PREEMPTION_CFG_RSZ 0x4
116
117 #define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
118 #define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
119 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
120 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
121 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
122 #define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
123 #define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
124 #define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
125 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
126 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
127 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
128
129 #define QSYS_CIR_CFG_GSZ 0x80
130
131 #define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
132 #define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
133 #define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
134 #define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
135 #define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
136
137 #define QSYS_EIR_CFG_GSZ 0x80
138
139 #define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
140 #define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
141 #define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
142 #define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
143 #define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
144 #define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
145 #define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
146
147 #define QSYS_SE_CFG_GSZ 0x80
148
149 #define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
150 #define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
151 #define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
152 #define QSYS_SE_CFG_SE_RR_ENA BIT(5)
153 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
154 #define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
155 #define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
156 #define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
157 #define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
158 #define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
159
160 #define QSYS_SE_DWRR_CFG_GSZ 0x80
161 #define QSYS_SE_DWRR_CFG_RSZ 0x4
162
163 #define QSYS_SE_CONNECT_GSZ 0x80
164
165 #define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
166 #define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
167 #define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
168 #define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
169 #define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
170 #define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
171 #define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
172 #define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
173 #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
174 #define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
175 #define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
176 #define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
177 #define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
178
179 #define QSYS_SE_DLB_SENSE_GSZ 0x80
180
181 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
182 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
183 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
184 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
185 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
186 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
187 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
188 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
189 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
190 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
191 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
192 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
193
194 #define QSYS_CIR_STATE_GSZ 0x80
195
196 #define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
197 #define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
198 #define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
199 #define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
200 #define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
201
202 #define QSYS_EIR_STATE_GSZ 0x80
203
204 #define QSYS_SE_STATE_GSZ 0x80
205
206 #define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
207 #define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
208 #define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
209 #define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
210
211 #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
212 #define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
213 #define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
214 #define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
215 #define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
216 #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
217 #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
218
219 #define QSYS_TAG_CONFIG_RSZ 0x4
220
221 #define QSYS_TAG_CONFIG_ENABLE BIT(0)
222 #define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
223 #define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
224 #define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
225 #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
226 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
227 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
228 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
229 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
230 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
231
232 #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
233 #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
234 #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
235 #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
236
237 #define QSYS_PORT_MAX_SDU_RSZ 0x4
238
239 #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
240 #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
241 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
242 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
243 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
244
245 #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
246 #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
247 #define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
248 #define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
249 #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
250
251 #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
252 #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
253 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
254 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
255 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
256
257 #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
258 #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
259 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
260 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
261 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
262 #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
263
264 #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
265 #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
266 #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
267 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
268 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
269
270 #endif