root/drivers/net/ethernet/marvell/skge.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. skge_read32
  2. skge_read16
  3. skge_read8
  4. skge_write32
  5. skge_write16
  6. skge_write8
  7. xm_read32
  8. xm_read16
  9. xm_write32
  10. xm_write16
  11. xm_outhash
  12. xm_outaddr
  13. gma_read16
  14. gma_read32
  15. gma_write16
  16. gma_set_addr

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the new Marvell Yukon / SysKonnect driver.
   4  */
   5 #ifndef _SKGE_H
   6 #define _SKGE_H
   7 #include <linux/interrupt.h>
   8 
   9 /* PCI config registers */
  10 #define PCI_DEV_REG1    0x40
  11 #define  PCI_PHY_COMA   0x8000000
  12 #define  PCI_VIO        0x2000000
  13 
  14 #define PCI_DEV_REG2    0x44
  15 #define  PCI_VPD_ROM_SZ 7L<<14  /* VPD ROM size 0=256, 1=512, ... */
  16 #define  PCI_REV_DESC   1<<2    /* Reverse Descriptor bytes */
  17 
  18 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
  19                                PCI_STATUS_SIG_SYSTEM_ERROR | \
  20                                PCI_STATUS_REC_MASTER_ABORT | \
  21                                PCI_STATUS_REC_TARGET_ABORT | \
  22                                PCI_STATUS_PARITY)
  23 
  24 enum csr_regs {
  25         B0_RAP  = 0x0000,
  26         B0_CTST = 0x0004,
  27         B0_LED  = 0x0006,
  28         B0_POWER_CTRL   = 0x0007,
  29         B0_ISRC = 0x0008,
  30         B0_IMSK = 0x000c,
  31         B0_HWE_ISRC     = 0x0010,
  32         B0_HWE_IMSK     = 0x0014,
  33         B0_SP_ISRC      = 0x0018,
  34         B0_XM1_IMSK     = 0x0020,
  35         B0_XM1_ISRC     = 0x0028,
  36         B0_XM1_PHY_ADDR = 0x0030,
  37         B0_XM1_PHY_DATA = 0x0034,
  38         B0_XM2_IMSK     = 0x0040,
  39         B0_XM2_ISRC     = 0x0048,
  40         B0_XM2_PHY_ADDR = 0x0050,
  41         B0_XM2_PHY_DATA = 0x0054,
  42         B0_R1_CSR       = 0x0060,
  43         B0_R2_CSR       = 0x0064,
  44         B0_XS1_CSR      = 0x0068,
  45         B0_XA1_CSR      = 0x006c,
  46         B0_XS2_CSR      = 0x0070,
  47         B0_XA2_CSR      = 0x0074,
  48 
  49         B2_MAC_1        = 0x0100,
  50         B2_MAC_2        = 0x0108,
  51         B2_MAC_3        = 0x0110,
  52         B2_CONN_TYP     = 0x0118,
  53         B2_PMD_TYP      = 0x0119,
  54         B2_MAC_CFG      = 0x011a,
  55         B2_CHIP_ID      = 0x011b,
  56         B2_E_0          = 0x011c,
  57         B2_E_1          = 0x011d,
  58         B2_E_2          = 0x011e,
  59         B2_E_3          = 0x011f,
  60         B2_FAR          = 0x0120,
  61         B2_FDP          = 0x0124,
  62         B2_LD_CTRL      = 0x0128,
  63         B2_LD_TEST      = 0x0129,
  64         B2_TI_INI       = 0x0130,
  65         B2_TI_VAL       = 0x0134,
  66         B2_TI_CTRL      = 0x0138,
  67         B2_TI_TEST      = 0x0139,
  68         B2_IRQM_INI     = 0x0140,
  69         B2_IRQM_VAL     = 0x0144,
  70         B2_IRQM_CTRL    = 0x0148,
  71         B2_IRQM_TEST    = 0x0149,
  72         B2_IRQM_MSK     = 0x014c,
  73         B2_IRQM_HWE_MSK = 0x0150,
  74         B2_TST_CTRL1    = 0x0158,
  75         B2_TST_CTRL2    = 0x0159,
  76         B2_GP_IO        = 0x015c,
  77         B2_I2C_CTRL     = 0x0160,
  78         B2_I2C_DATA     = 0x0164,
  79         B2_I2C_IRQ      = 0x0168,
  80         B2_I2C_SW       = 0x016c,
  81         B2_BSC_INI      = 0x0170,
  82         B2_BSC_VAL      = 0x0174,
  83         B2_BSC_CTRL     = 0x0178,
  84         B2_BSC_STAT     = 0x0179,
  85         B2_BSC_TST      = 0x017a,
  86 
  87         B3_RAM_ADDR     = 0x0180,
  88         B3_RAM_DATA_LO  = 0x0184,
  89         B3_RAM_DATA_HI  = 0x0188,
  90         B3_RI_WTO_R1    = 0x0190,
  91         B3_RI_WTO_XA1   = 0x0191,
  92         B3_RI_WTO_XS1   = 0x0192,
  93         B3_RI_RTO_R1    = 0x0193,
  94         B3_RI_RTO_XA1   = 0x0194,
  95         B3_RI_RTO_XS1   = 0x0195,
  96         B3_RI_WTO_R2    = 0x0196,
  97         B3_RI_WTO_XA2   = 0x0197,
  98         B3_RI_WTO_XS2   = 0x0198,
  99         B3_RI_RTO_R2    = 0x0199,
 100         B3_RI_RTO_XA2   = 0x019a,
 101         B3_RI_RTO_XS2   = 0x019b,
 102         B3_RI_TO_VAL    = 0x019c,
 103         B3_RI_CTRL      = 0x01a0,
 104         B3_RI_TEST      = 0x01a2,
 105         B3_MA_TOINI_RX1 = 0x01b0,
 106         B3_MA_TOINI_RX2 = 0x01b1,
 107         B3_MA_TOINI_TX1 = 0x01b2,
 108         B3_MA_TOINI_TX2 = 0x01b3,
 109         B3_MA_TOVAL_RX1 = 0x01b4,
 110         B3_MA_TOVAL_RX2 = 0x01b5,
 111         B3_MA_TOVAL_TX1 = 0x01b6,
 112         B3_MA_TOVAL_TX2 = 0x01b7,
 113         B3_MA_TO_CTRL   = 0x01b8,
 114         B3_MA_TO_TEST   = 0x01ba,
 115         B3_MA_RCINI_RX1 = 0x01c0,
 116         B3_MA_RCINI_RX2 = 0x01c1,
 117         B3_MA_RCINI_TX1 = 0x01c2,
 118         B3_MA_RCINI_TX2 = 0x01c3,
 119         B3_MA_RCVAL_RX1 = 0x01c4,
 120         B3_MA_RCVAL_RX2 = 0x01c5,
 121         B3_MA_RCVAL_TX1 = 0x01c6,
 122         B3_MA_RCVAL_TX2 = 0x01c7,
 123         B3_MA_RC_CTRL   = 0x01c8,
 124         B3_MA_RC_TEST   = 0x01ca,
 125         B3_PA_TOINI_RX1 = 0x01d0,
 126         B3_PA_TOINI_RX2 = 0x01d4,
 127         B3_PA_TOINI_TX1 = 0x01d8,
 128         B3_PA_TOINI_TX2 = 0x01dc,
 129         B3_PA_TOVAL_RX1 = 0x01e0,
 130         B3_PA_TOVAL_RX2 = 0x01e4,
 131         B3_PA_TOVAL_TX1 = 0x01e8,
 132         B3_PA_TOVAL_TX2 = 0x01ec,
 133         B3_PA_CTRL      = 0x01f0,
 134         B3_PA_TEST      = 0x01f2,
 135 };
 136 
 137 /*      B0_CTST                 16 bit  Control/Status register */
 138 enum {
 139         CS_CLK_RUN_HOT  = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
 140         CS_CLK_RUN_RST  = 1<<12,/* CLK_RUN reset  (YUKON-Lite only) */
 141         CS_CLK_RUN_ENA  = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
 142         CS_VAUX_AVAIL   = 1<<10,/* VAUX available (YUKON only) */
 143         CS_BUS_CLOCK    = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
 144         CS_BUS_SLOT_SZ  = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
 145         CS_ST_SW_IRQ    = 1<<7, /* Set IRQ SW Request */
 146         CS_CL_SW_IRQ    = 1<<6, /* Clear IRQ SW Request */
 147         CS_STOP_DONE    = 1<<5, /* Stop Master is finished */
 148         CS_STOP_MAST    = 1<<4, /* Command Bit to stop the master */
 149         CS_MRST_CLR     = 1<<3, /* Clear Master reset   */
 150         CS_MRST_SET     = 1<<2, /* Set Master reset     */
 151         CS_RST_CLR      = 1<<1, /* Clear Software reset */
 152         CS_RST_SET      = 1,    /* Set   Software reset */
 153 
 154 /*      B0_LED                   8 Bit  LED register */
 155 /* Bit  7.. 2:  reserved */
 156         LED_STAT_ON     = 1<<1, /* Status LED on        */
 157         LED_STAT_OFF    = 1,            /* Status LED off       */
 158 
 159 /*      B0_POWER_CTRL    8 Bit  Power Control reg (YUKON only) */
 160         PC_VAUX_ENA     = 1<<7, /* Switch VAUX Enable  */
 161         PC_VAUX_DIS     = 1<<6, /* Switch VAUX Disable */
 162         PC_VCC_ENA      = 1<<5, /* Switch VCC Enable  */
 163         PC_VCC_DIS      = 1<<4, /* Switch VCC Disable */
 164         PC_VAUX_ON      = 1<<3, /* Switch VAUX On  */
 165         PC_VAUX_OFF     = 1<<2, /* Switch VAUX Off */
 166         PC_VCC_ON       = 1<<1, /* Switch VCC On  */
 167         PC_VCC_OFF      = 1<<0, /* Switch VCC Off */
 168 };
 169 
 170 /*      B2_IRQM_MSK     32 bit  IRQ Moderation Mask */
 171 enum {
 172         IS_ALL_MSK      = 0xbffffffful, /* All Interrupt bits */
 173         IS_HW_ERR       = 1<<31,        /* Interrupt HW Error */
 174                                         /* Bit 30:      reserved */
 175         IS_PA_TO_RX1    = 1<<29,        /* Packet Arb Timeout Rx1 */
 176         IS_PA_TO_RX2    = 1<<28,        /* Packet Arb Timeout Rx2 */
 177         IS_PA_TO_TX1    = 1<<27,        /* Packet Arb Timeout Tx1 */
 178         IS_PA_TO_TX2    = 1<<26,        /* Packet Arb Timeout Tx2 */
 179         IS_I2C_READY    = 1<<25,        /* IRQ on end of I2C Tx */
 180         IS_IRQ_SW       = 1<<24,        /* SW forced IRQ        */
 181         IS_EXT_REG      = 1<<23,        /* IRQ from LM80 or PHY (GENESIS only) */
 182                                         /* IRQ from PHY (YUKON only) */
 183         IS_TIMINT       = 1<<22,        /* IRQ from Timer       */
 184         IS_MAC1         = 1<<21,        /* IRQ from MAC 1       */
 185         IS_LNK_SYNC_M1  = 1<<20,        /* Link Sync Cnt wrap MAC 1 */
 186         IS_MAC2         = 1<<19,        /* IRQ from MAC 2       */
 187         IS_LNK_SYNC_M2  = 1<<18,        /* Link Sync Cnt wrap MAC 2 */
 188 /* Receive Queue 1 */
 189         IS_R1_B         = 1<<17,        /* Q_R1 End of Buffer */
 190         IS_R1_F         = 1<<16,        /* Q_R1 End of Frame */
 191         IS_R1_C         = 1<<15,        /* Q_R1 Encoding Error */
 192 /* Receive Queue 2 */
 193         IS_R2_B         = 1<<14,        /* Q_R2 End of Buffer */
 194         IS_R2_F         = 1<<13,        /* Q_R2 End of Frame */
 195         IS_R2_C         = 1<<12,        /* Q_R2 Encoding Error */
 196 /* Synchronous Transmit Queue 1 */
 197         IS_XS1_B        = 1<<11,        /* Q_XS1 End of Buffer */
 198         IS_XS1_F        = 1<<10,        /* Q_XS1 End of Frame */
 199         IS_XS1_C        = 1<<9,         /* Q_XS1 Encoding Error */
 200 /* Asynchronous Transmit Queue 1 */
 201         IS_XA1_B        = 1<<8,         /* Q_XA1 End of Buffer */
 202         IS_XA1_F        = 1<<7,         /* Q_XA1 End of Frame */
 203         IS_XA1_C        = 1<<6,         /* Q_XA1 Encoding Error */
 204 /* Synchronous Transmit Queue 2 */
 205         IS_XS2_B        = 1<<5,         /* Q_XS2 End of Buffer */
 206         IS_XS2_F        = 1<<4,         /* Q_XS2 End of Frame */
 207         IS_XS2_C        = 1<<3,         /* Q_XS2 Encoding Error */
 208 /* Asynchronous Transmit Queue 2 */
 209         IS_XA2_B        = 1<<2,         /* Q_XA2 End of Buffer */
 210         IS_XA2_F        = 1<<1,         /* Q_XA2 End of Frame */
 211         IS_XA2_C        = 1<<0,         /* Q_XA2 Encoding Error */
 212 
 213         IS_TO_PORT1     = IS_PA_TO_RX1 | IS_PA_TO_TX1,
 214         IS_TO_PORT2     = IS_PA_TO_RX2 | IS_PA_TO_TX2,
 215 
 216         IS_PORT_1       = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
 217         IS_PORT_2       = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
 218 };
 219 
 220 
 221 /*      B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
 222 enum {
 223         IS_IRQ_TIST_OV  = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
 224         IS_IRQ_SENSOR   = 1<<12, /* IRQ from Sensor (YUKON only) */
 225         IS_IRQ_MST_ERR  = 1<<11, /* IRQ master error detected */
 226         IS_IRQ_STAT     = 1<<10, /* IRQ status exception */
 227         IS_NO_STAT_M1   = 1<<9, /* No Rx Status from MAC 1 */
 228         IS_NO_STAT_M2   = 1<<8, /* No Rx Status from MAC 2 */
 229         IS_NO_TIST_M1   = 1<<7, /* No Time Stamp from MAC 1 */
 230         IS_NO_TIST_M2   = 1<<6, /* No Time Stamp from MAC 2 */
 231         IS_RAM_RD_PAR   = 1<<5, /* RAM Read  Parity Error */
 232         IS_RAM_WR_PAR   = 1<<4, /* RAM Write Parity Error */
 233         IS_M1_PAR_ERR   = 1<<3, /* MAC 1 Parity Error */
 234         IS_M2_PAR_ERR   = 1<<2, /* MAC 2 Parity Error */
 235         IS_R1_PAR_ERR   = 1<<1, /* Queue R1 Parity Error */
 236         IS_R2_PAR_ERR   = 1<<0, /* Queue R2 Parity Error */
 237 
 238         IS_ERR_MSK      = IS_IRQ_MST_ERR | IS_IRQ_STAT
 239                         | IS_RAM_RD_PAR | IS_RAM_WR_PAR
 240                         | IS_M1_PAR_ERR | IS_M2_PAR_ERR
 241                         | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
 242 };
 243 
 244 /*      B2_TST_CTRL1     8 bit  Test Control Register 1 */
 245 enum {
 246         TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
 247         TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
 248         TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
 249         TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
 250         TST_FRC_APERR_M  = 1<<3, /* force ADDRPERR on MST */
 251         TST_FRC_APERR_T  = 1<<2, /* force ADDRPERR on TRG */
 252         TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
 253         TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
 254 };
 255 
 256 /*      B2_MAC_CFG               8 bit  MAC Configuration / Chip Revision */
 257 enum {
 258         CFG_CHIP_R_MSK    = 0xf<<4,     /* Bit 7.. 4: Chip Revision */
 259                                         /* Bit 3.. 2:   reserved */
 260         CFG_DIS_M2_CLK    = 1<<1,       /* Disable Clock for 2nd MAC */
 261         CFG_SNG_MAC       = 1<<0,       /* MAC Config: 0=2 MACs / 1=1 MAC*/
 262 };
 263 
 264 /*      B2_CHIP_ID               8 bit  Chip Identification Number */
 265 enum {
 266         CHIP_ID_GENESIS    = 0x0a, /* Chip ID for GENESIS */
 267         CHIP_ID_YUKON      = 0xb0, /* Chip ID for YUKON */
 268         CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
 269         CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
 270         CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
 271         CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
 272         CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
 273 
 274         CHIP_REV_YU_LITE_A1  = 3,       /* Chip Rev. for YUKON-Lite A1,A2 */
 275         CHIP_REV_YU_LITE_A3  = 7,       /* Chip Rev. for YUKON-Lite A3 */
 276 };
 277 
 278 /*      B2_TI_CTRL               8 bit  Timer control */
 279 /*      B2_IRQM_CTRL     8 bit  IRQ Moderation Timer Control */
 280 enum {
 281         TIM_START       = 1<<2, /* Start Timer */
 282         TIM_STOP        = 1<<1, /* Stop  Timer */
 283         TIM_CLR_IRQ     = 1<<0, /* Clear Timer IRQ (!IRQM) */
 284 };
 285 
 286 /*      B2_TI_TEST               8 Bit  Timer Test */
 287 /*      B2_IRQM_TEST     8 bit  IRQ Moderation Timer Test */
 288 /*      B28_DPT_TST              8 bit  Descriptor Poll Timer Test Reg */
 289 enum {
 290         TIM_T_ON        = 1<<2, /* Test mode on */
 291         TIM_T_OFF       = 1<<1, /* Test mode off */
 292         TIM_T_STEP      = 1<<0, /* Test step */
 293 };
 294 
 295 /*      B2_GP_IO                32 bit  General Purpose I/O Register */
 296 enum {
 297         GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
 298         GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
 299         GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
 300         GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
 301         GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
 302         GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
 303         GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
 304         GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
 305         GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
 306         GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
 307 
 308         GP_IO_9 = 1<<9, /* IO_9 pin */
 309         GP_IO_8 = 1<<8, /* IO_8 pin */
 310         GP_IO_7 = 1<<7, /* IO_7 pin */
 311         GP_IO_6 = 1<<6, /* IO_6 pin */
 312         GP_IO_5 = 1<<5, /* IO_5 pin */
 313         GP_IO_4 = 1<<4, /* IO_4 pin */
 314         GP_IO_3 = 1<<3, /* IO_3 pin */
 315         GP_IO_2 = 1<<2, /* IO_2 pin */
 316         GP_IO_1 = 1<<1, /* IO_1 pin */
 317         GP_IO_0 = 1<<0, /* IO_0 pin */
 318 };
 319 
 320 /* Descriptor Bit Definition */
 321 /*      TxCtrl          Transmit Buffer Control Field */
 322 /*      RxCtrl          Receive  Buffer Control Field */
 323 enum {
 324         BMU_OWN         = 1<<31, /* OWN bit: 0=host/1=BMU */
 325         BMU_STF         = 1<<30, /* Start of Frame */
 326         BMU_EOF         = 1<<29, /* End of Frame */
 327         BMU_IRQ_EOB     = 1<<28, /* Req "End of Buffer" IRQ */
 328         BMU_IRQ_EOF     = 1<<27, /* Req "End of Frame" IRQ */
 329                                 /* TxCtrl specific bits */
 330         BMU_STFWD       = 1<<26, /* (Tx)        Store & Forward Frame */
 331         BMU_NO_FCS      = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
 332         BMU_SW  = 1<<24, /* (Tx)        1 bit res. for SW use */
 333                                 /* RxCtrl specific bits */
 334         BMU_DEV_0       = 1<<26, /* (Rx)        Transfer data to Dev0 */
 335         BMU_STAT_VAL    = 1<<25, /* (Rx)        Rx Status Valid */
 336         BMU_TIST_VAL    = 1<<24, /* (Rx)        Rx TimeStamp Valid */
 337                         /* Bit 23..16:  BMU Check Opcodes */
 338         BMU_CHECK       = 0x55<<16, /* Default BMU check */
 339         BMU_TCP_CHECK   = 0x56<<16, /* Descr with TCP ext */
 340         BMU_UDP_CHECK   = 0x57<<16, /* Descr with UDP ext (YUKON only) */
 341         BMU_BBC         = 0xffffL, /* Bit 15.. 0:       Buffer Byte Counter */
 342 };
 343 
 344 /*      B2_BSC_CTRL              8 bit  Blink Source Counter Control */
 345 enum {
 346          BSC_START      = 1<<1, /* Start Blink Source Counter */
 347          BSC_STOP       = 1<<0, /* Stop  Blink Source Counter */
 348 };
 349 
 350 /*      B2_BSC_STAT              8 bit  Blink Source Counter Status */
 351 enum {
 352         BSC_SRC         = 1<<0, /* Blink Source, 0=Off / 1=On */
 353 };
 354 
 355 /*      B2_BSC_TST              16 bit  Blink Source Counter Test Reg */
 356 enum {
 357         BSC_T_ON        = 1<<2, /* Test mode on */
 358         BSC_T_OFF       = 1<<1, /* Test mode off */
 359         BSC_T_STEP      = 1<<0, /* Test step */
 360 };
 361 
 362 /*      B3_RAM_ADDR             32 bit  RAM Address, to read or write */
 363                                         /* Bit 31..19:  reserved */
 364 #define RAM_ADR_RAN     0x0007ffffL     /* Bit 18.. 0:  RAM Address Range */
 365 /* RAM Interface Registers */
 366 
 367 /*      B3_RI_CTRL              16 bit  RAM Iface Control Register */
 368 enum {
 369         RI_CLR_RD_PERR  = 1<<9, /* Clear IRQ RAM Read Parity Err */
 370         RI_CLR_WR_PERR  = 1<<8, /* Clear IRQ RAM Write Parity Err*/
 371 
 372         RI_RST_CLR      = 1<<1, /* Clear RAM Interface Reset */
 373         RI_RST_SET      = 1<<0, /* Set   RAM Interface Reset */
 374 };
 375 
 376 /* MAC Arbiter Registers */
 377 /*      B3_MA_TO_CTRL   16 bit  MAC Arbiter Timeout Ctrl Reg */
 378 enum {
 379         MA_FOE_ON       = 1<<3, /* XMAC Fast Output Enable ON */
 380         MA_FOE_OFF      = 1<<2, /* XMAC Fast Output Enable OFF */
 381         MA_RST_CLR      = 1<<1, /* Clear MAC Arbiter Reset */
 382         MA_RST_SET      = 1<<0, /* Set   MAC Arbiter Reset */
 383 
 384 };
 385 
 386 /* Timeout values */
 387 #define SK_MAC_TO_53    72              /* MAC arbiter timeout */
 388 #define SK_PKT_TO_53    0x2000          /* Packet arbiter timeout */
 389 #define SK_PKT_TO_MAX   0xffff          /* Maximum value */
 390 #define SK_RI_TO_53     36              /* RAM interface timeout */
 391 
 392 /* Packet Arbiter Registers */
 393 /*      B3_PA_CTRL              16 bit  Packet Arbiter Ctrl Register */
 394 enum {
 395         PA_CLR_TO_TX2   = 1<<13,/* Clear IRQ Packet Timeout TX2 */
 396         PA_CLR_TO_TX1   = 1<<12,/* Clear IRQ Packet Timeout TX1 */
 397         PA_CLR_TO_RX2   = 1<<11,/* Clear IRQ Packet Timeout RX2 */
 398         PA_CLR_TO_RX1   = 1<<10,/* Clear IRQ Packet Timeout RX1 */
 399         PA_ENA_TO_TX2   = 1<<9, /* Enable  Timeout Timer TX2 */
 400         PA_DIS_TO_TX2   = 1<<8, /* Disable Timeout Timer TX2 */
 401         PA_ENA_TO_TX1   = 1<<7, /* Enable  Timeout Timer TX1 */
 402         PA_DIS_TO_TX1   = 1<<6, /* Disable Timeout Timer TX1 */
 403         PA_ENA_TO_RX2   = 1<<5, /* Enable  Timeout Timer RX2 */
 404         PA_DIS_TO_RX2   = 1<<4, /* Disable Timeout Timer RX2 */
 405         PA_ENA_TO_RX1   = 1<<3, /* Enable  Timeout Timer RX1 */
 406         PA_DIS_TO_RX1   = 1<<2, /* Disable Timeout Timer RX1 */
 407         PA_RST_CLR      = 1<<1, /* Clear MAC Arbiter Reset */
 408         PA_RST_SET      = 1<<0, /* Set   MAC Arbiter Reset */
 409 };
 410 
 411 #define PA_ENA_TO_ALL   (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
 412                                                 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
 413 
 414 
 415 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 416 /*      TXA_ITI_INI             32 bit  Tx Arb Interval Timer Init Val */
 417 /*      TXA_ITI_VAL             32 bit  Tx Arb Interval Timer Value */
 418 /*      TXA_LIM_INI             32 bit  Tx Arb Limit Counter Init Val */
 419 /*      TXA_LIM_VAL             32 bit  Tx Arb Limit Counter Value */
 420 
 421 #define TXA_MAX_VAL     0x00ffffffUL    /* Bit 23.. 0:  Max TXA Timer/Cnt Val */
 422 
 423 /*      TXA_CTRL                 8 bit  Tx Arbiter Control Register */
 424 enum {
 425         TXA_ENA_FSYNC   = 1<<7, /* Enable  force of sync Tx queue */
 426         TXA_DIS_FSYNC   = 1<<6, /* Disable force of sync Tx queue */
 427         TXA_ENA_ALLOC   = 1<<5, /* Enable  alloc of free bandwidth */
 428         TXA_DIS_ALLOC   = 1<<4, /* Disable alloc of free bandwidth */
 429         TXA_START_RC    = 1<<3, /* Start sync Rate Control */
 430         TXA_STOP_RC     = 1<<2, /* Stop  sync Rate Control */
 431         TXA_ENA_ARB     = 1<<1, /* Enable  Tx Arbiter */
 432         TXA_DIS_ARB     = 1<<0, /* Disable Tx Arbiter */
 433 };
 434 
 435 /*
 436  *      Bank 4 - 5
 437  */
 438 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 439 enum {
 440         TXA_ITI_INI     = 0x0200,/* 32 bit      Tx Arb Interval Timer Init Val*/
 441         TXA_ITI_VAL     = 0x0204,/* 32 bit      Tx Arb Interval Timer Value */
 442         TXA_LIM_INI     = 0x0208,/* 32 bit      Tx Arb Limit Counter Init Val */
 443         TXA_LIM_VAL     = 0x020c,/* 32 bit      Tx Arb Limit Counter Value */
 444         TXA_CTRL        = 0x0210,/*  8 bit      Tx Arbiter Control Register */
 445         TXA_TEST        = 0x0211,/*  8 bit      Tx Arbiter Test Register */
 446         TXA_STAT        = 0x0212,/*  8 bit      Tx Arbiter Status Register */
 447 };
 448 
 449 
 450 enum {
 451         B6_EXT_REG      = 0x0300,/* External registers (GENESIS only) */
 452         B7_CFG_SPC      = 0x0380,/* copy of the Configuration register */
 453         B8_RQ1_REGS     = 0x0400,/* Receive Queue 1 */
 454         B8_RQ2_REGS     = 0x0480,/* Receive Queue 2 */
 455         B8_TS1_REGS     = 0x0600,/* Transmit sync queue 1 */
 456         B8_TA1_REGS     = 0x0680,/* Transmit async queue 1 */
 457         B8_TS2_REGS     = 0x0700,/* Transmit sync queue 2 */
 458         B8_TA2_REGS     = 0x0780,/* Transmit sync queue 2 */
 459         B16_RAM_REGS    = 0x0800,/* RAM Buffer Registers */
 460 };
 461 
 462 /* Queue Register Offsets, use Q_ADDR() to access */
 463 enum {
 464         B8_Q_REGS = 0x0400, /* base of Queue registers */
 465         Q_D     = 0x00, /* 8*32 bit     Current Descriptor */
 466         Q_DA_L  = 0x20, /* 32 bit       Current Descriptor Address Low dWord */
 467         Q_DA_H  = 0x24, /* 32 bit       Current Descriptor Address High dWord */
 468         Q_AC_L  = 0x28, /* 32 bit       Current Address Counter Low dWord */
 469         Q_AC_H  = 0x2c, /* 32 bit       Current Address Counter High dWord */
 470         Q_BC    = 0x30, /* 32 bit       Current Byte Counter */
 471         Q_CSR   = 0x34, /* 32 bit       BMU Control/Status Register */
 472         Q_F     = 0x38, /* 32 bit       Flag Register */
 473         Q_T1    = 0x3c, /* 32 bit       Test Register 1 */
 474         Q_T1_TR = 0x3c, /*  8 bit       Test Register 1 Transfer SM */
 475         Q_T1_WR = 0x3d, /*  8 bit       Test Register 1 Write Descriptor SM */
 476         Q_T1_RD = 0x3e, /*  8 bit       Test Register 1 Read Descriptor SM */
 477         Q_T1_SV = 0x3f, /*  8 bit       Test Register 1 Supervisor SM */
 478         Q_T2    = 0x40, /* 32 bit       Test Register 2 */
 479         Q_T3    = 0x44, /* 32 bit       Test Register 3 */
 480 
 481 };
 482 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
 483 
 484 /* RAM Buffer Register Offsets */
 485 enum {
 486 
 487         RB_START= 0x00,/* 32 bit        RAM Buffer Start Address */
 488         RB_END  = 0x04,/* 32 bit        RAM Buffer End Address */
 489         RB_WP   = 0x08,/* 32 bit        RAM Buffer Write Pointer */
 490         RB_RP   = 0x0c,/* 32 bit        RAM Buffer Read Pointer */
 491         RB_RX_UTPP= 0x10,/* 32 bit      Rx Upper Threshold, Pause Packet */
 492         RB_RX_LTPP= 0x14,/* 32 bit      Rx Lower Threshold, Pause Packet */
 493         RB_RX_UTHP= 0x18,/* 32 bit      Rx Upper Threshold, High Prio */
 494         RB_RX_LTHP= 0x1c,/* 32 bit      Rx Lower Threshold, High Prio */
 495         /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
 496         RB_PC   = 0x20,/* 32 bit        RAM Buffer Packet Counter */
 497         RB_LEV  = 0x24,/* 32 bit        RAM Buffer Level Register */
 498         RB_CTRL = 0x28,/* 32 bit        RAM Buffer Control Register */
 499         RB_TST1 = 0x29,/*  8 bit        RAM Buffer Test Register 1 */
 500         RB_TST2 = 0x2a,/*  8 bit        RAM Buffer Test Register 2 */
 501 };
 502 
 503 /* Receive and Transmit Queues */
 504 enum {
 505         Q_R1    = 0x0000,       /* Receive Queue 1 */
 506         Q_R2    = 0x0080,       /* Receive Queue 2 */
 507         Q_XS1   = 0x0200,       /* Synchronous Transmit Queue 1 */
 508         Q_XA1   = 0x0280,       /* Asynchronous Transmit Queue 1 */
 509         Q_XS2   = 0x0300,       /* Synchronous Transmit Queue 2 */
 510         Q_XA2   = 0x0380,       /* Asynchronous Transmit Queue 2 */
 511 };
 512 
 513 /* Different MAC Types */
 514 enum {
 515         SK_MAC_XMAC =   0,      /* Xaqti XMAC II */
 516         SK_MAC_GMAC =   1,      /* Marvell GMAC */
 517 };
 518 
 519 /* Different PHY Types */
 520 enum {
 521         SK_PHY_XMAC     = 0,/* integrated in XMAC II */
 522         SK_PHY_BCOM     = 1,/* Broadcom BCM5400 */
 523         SK_PHY_LONE     = 2,/* Level One LXT1000  [not supported]*/
 524         SK_PHY_NAT      = 3,/* National DP83891  [not supported] */
 525         SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
 526         SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
 527 };
 528 
 529 /* PHY addresses (bits 12..8 of PHY address reg) */
 530 enum {
 531         PHY_ADDR_XMAC   = 0<<8,
 532         PHY_ADDR_BCOM   = 1<<8,
 533 
 534 /* GPHY address (bits 15..11 of SMI control reg) */
 535         PHY_ADDR_MARV   = 0,
 536 };
 537 
 538 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
 539 
 540 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
 541 enum {
 542         RX_MFF_EA       = 0x0c00,/* 32 bit      Receive MAC FIFO End Address */
 543         RX_MFF_WP       = 0x0c04,/* 32 bit      Receive MAC FIFO Write Pointer */
 544 
 545         RX_MFF_RP       = 0x0c0c,/* 32 bit      Receive MAC FIFO Read Pointer */
 546         RX_MFF_PC       = 0x0c10,/* 32 bit      Receive MAC FIFO Packet Cnt */
 547         RX_MFF_LEV      = 0x0c14,/* 32 bit      Receive MAC FIFO Level */
 548         RX_MFF_CTRL1    = 0x0c18,/* 16 bit      Receive MAC FIFO Control Reg 1*/
 549         RX_MFF_STAT_TO  = 0x0c1a,/*  8 bit      Receive MAC Status Timeout */
 550         RX_MFF_TIST_TO  = 0x0c1b,/*  8 bit      Receive MAC Time Stamp Timeout */
 551         RX_MFF_CTRL2    = 0x0c1c,/*  8 bit      Receive MAC FIFO Control Reg 2*/
 552         RX_MFF_TST1     = 0x0c1d,/*  8 bit      Receive MAC FIFO Test Reg 1 */
 553         RX_MFF_TST2     = 0x0c1e,/*  8 bit      Receive MAC FIFO Test Reg 2 */
 554 
 555         RX_LED_INI      = 0x0c20,/* 32 bit      Receive LED Cnt Init Value */
 556         RX_LED_VAL      = 0x0c24,/* 32 bit      Receive LED Cnt Current Value */
 557         RX_LED_CTRL     = 0x0c28,/*  8 bit      Receive LED Cnt Control Reg */
 558         RX_LED_TST      = 0x0c29,/*  8 bit      Receive LED Cnt Test Register */
 559 
 560         LNK_SYNC_INI    = 0x0c30,/* 32 bit      Link Sync Cnt Init Value */
 561         LNK_SYNC_VAL    = 0x0c34,/* 32 bit      Link Sync Cnt Current Value */
 562         LNK_SYNC_CTRL   = 0x0c38,/*  8 bit      Link Sync Cnt Control Register */
 563         LNK_SYNC_TST    = 0x0c39,/*  8 bit      Link Sync Cnt Test Register */
 564         LNK_LED_REG     = 0x0c3c,/*  8 bit      Link LED Register */
 565 };
 566 
 567 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
 568 /*      RX_MFF_CTRL1    16 bit  Receive MAC FIFO Control Reg 1 */
 569 enum {
 570         MFF_ENA_RDY_PAT = 1<<13,        /* Enable  Ready Patch */
 571         MFF_DIS_RDY_PAT = 1<<12,        /* Disable Ready Patch */
 572         MFF_ENA_TIM_PAT = 1<<11,        /* Enable  Timing Patch */
 573         MFF_DIS_TIM_PAT = 1<<10,        /* Disable Timing Patch */
 574         MFF_ENA_ALM_FUL = 1<<9, /* Enable  AlmostFull Sign */
 575         MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
 576         MFF_ENA_PAUSE   = 1<<7, /* Enable  Pause Signaling */
 577         MFF_DIS_PAUSE   = 1<<6, /* Disable Pause Signaling */
 578         MFF_ENA_FLUSH   = 1<<5, /* Enable  Frame Flushing */
 579         MFF_DIS_FLUSH   = 1<<4, /* Disable Frame Flushing */
 580         MFF_ENA_TIST    = 1<<3, /* Enable  Time Stamp Gener */
 581         MFF_DIS_TIST    = 1<<2, /* Disable Time Stamp Gener */
 582         MFF_CLR_INTIST  = 1<<1, /* Clear IRQ No Time Stamp */
 583         MFF_CLR_INSTAT  = 1<<0, /* Clear IRQ No Status */
 584         MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
 585 };
 586 
 587 /*      TX_MFF_CTRL1    16 bit  Transmit MAC FIFO Control Reg 1 */
 588 enum {
 589         MFF_CLR_PERR    = 1<<15, /* Clear Parity Error IRQ */
 590 
 591         MFF_ENA_PKT_REC = 1<<13, /* Enable  Packet Recovery */
 592         MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
 593 
 594         MFF_ENA_W4E     = 1<<7, /* Enable  Wait for Empty */
 595         MFF_DIS_W4E     = 1<<6, /* Disable Wait for Empty */
 596 
 597         MFF_ENA_LOOPB   = 1<<3, /* Enable  Loopback */
 598         MFF_DIS_LOOPB   = 1<<2, /* Disable Loopback */
 599         MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
 600         MFF_SET_MAC_RST = 1<<0, /* Set   XMAC Reset */
 601 
 602         MFF_TX_CTRL_DEF  = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
 603 };
 604 
 605 
 606 /*      RX_MFF_TST2              8 bit  Receive MAC FIFO Test Register 2 */
 607 /*      TX_MFF_TST2              8 bit  Transmit MAC FIFO Test Register 2 */
 608 enum {
 609         MFF_WSP_T_ON    = 1<<6, /* Tx: Write Shadow Ptr TestOn */
 610         MFF_WSP_T_OFF   = 1<<5, /* Tx: Write Shadow Ptr TstOff */
 611         MFF_WSP_INC     = 1<<4, /* Tx: Write Shadow Ptr Increment */
 612         MFF_PC_DEC      = 1<<3, /* Packet Counter Decrement */
 613         MFF_PC_T_ON     = 1<<2, /* Packet Counter Test On */
 614         MFF_PC_T_OFF    = 1<<1, /* Packet Counter Test Off */
 615         MFF_PC_INC      = 1<<0, /* Packet Counter Increment */
 616 };
 617 
 618 /*      RX_MFF_TST1              8 bit  Receive MAC FIFO Test Register 1 */
 619 /*      TX_MFF_TST1              8 bit  Transmit MAC FIFO Test Register 1 */
 620 enum {
 621         MFF_WP_T_ON     = 1<<6, /* Write Pointer Test On */
 622         MFF_WP_T_OFF    = 1<<5, /* Write Pointer Test Off */
 623         MFF_WP_INC      = 1<<4, /* Write Pointer Increm */
 624 
 625         MFF_RP_T_ON     = 1<<2, /* Read Pointer Test On */
 626         MFF_RP_T_OFF    = 1<<1, /* Read Pointer Test Off */
 627         MFF_RP_DEC      = 1<<0, /* Read Pointer Decrement */
 628 };
 629 
 630 /*      RX_MFF_CTRL2     8 bit  Receive MAC FIFO Control Reg 2 */
 631 /*      TX_MFF_CTRL2     8 bit  Transmit MAC FIFO Control Reg 2 */
 632 enum {
 633         MFF_ENA_OP_MD   = 1<<3, /* Enable  Operation Mode */
 634         MFF_DIS_OP_MD   = 1<<2, /* Disable Operation Mode */
 635         MFF_RST_CLR     = 1<<1, /* Clear MAC FIFO Reset */
 636         MFF_RST_SET     = 1<<0, /* Set   MAC FIFO Reset */
 637 };
 638 
 639 
 640 /*      Link LED Counter Registers (GENESIS only) */
 641 
 642 /*      RX_LED_CTRL              8 bit  Receive LED Cnt Control Reg */
 643 /*      TX_LED_CTRL              8 bit  Transmit LED Cnt Control Reg */
 644 /*      LNK_SYNC_CTRL    8 bit  Link Sync Cnt Control Register */
 645 enum {
 646         LED_START       = 1<<2, /* Start Timer */
 647         LED_STOP        = 1<<1, /* Stop Timer */
 648         LED_STATE       = 1<<0, /* Rx/Tx: LED State, 1=LED on */
 649 };
 650 
 651 /*      RX_LED_TST               8 bit  Receive LED Cnt Test Register */
 652 /*      TX_LED_TST               8 bit  Transmit LED Cnt Test Register */
 653 /*      LNK_SYNC_TST     8 bit  Link Sync Cnt Test Register */
 654 enum {
 655         LED_T_ON        = 1<<2, /* LED Counter Test mode On */
 656         LED_T_OFF       = 1<<1, /* LED Counter Test mode Off */
 657         LED_T_STEP      = 1<<0, /* LED Counter Step */
 658 };
 659 
 660 /*      LNK_LED_REG              8 bit  Link LED Register */
 661 enum {
 662         LED_BLK_ON      = 1<<5, /* Link LED Blinking On */
 663         LED_BLK_OFF     = 1<<4, /* Link LED Blinking Off */
 664         LED_SYNC_ON     = 1<<3, /* Use Sync Wire to switch LED */
 665         LED_SYNC_OFF    = 1<<2, /* Disable Sync Wire Input */
 666         LED_REG_ON      = 1<<1, /* switch LED on */
 667         LED_REG_OFF     = 1<<0, /* switch LED off */
 668 };
 669 
 670 /* Receive GMAC FIFO (YUKON) */
 671 enum {
 672         RX_GMF_EA       = 0x0c40,/* 32 bit      Rx GMAC FIFO End Address */
 673         RX_GMF_AF_THR   = 0x0c44,/* 32 bit      Rx GMAC FIFO Almost Full Thresh. */
 674         RX_GMF_CTRL_T   = 0x0c48,/* 32 bit      Rx GMAC FIFO Control/Test */
 675         RX_GMF_FL_MSK   = 0x0c4c,/* 32 bit      Rx GMAC FIFO Flush Mask */
 676         RX_GMF_FL_THR   = 0x0c50,/* 32 bit      Rx GMAC FIFO Flush Threshold */
 677         RX_GMF_WP       = 0x0c60,/* 32 bit      Rx GMAC FIFO Write Pointer */
 678         RX_GMF_WLEV     = 0x0c68,/* 32 bit      Rx GMAC FIFO Write Level */
 679         RX_GMF_RP       = 0x0c70,/* 32 bit      Rx GMAC FIFO Read Pointer */
 680         RX_GMF_RLEV     = 0x0c78,/* 32 bit      Rx GMAC FIFO Read Level */
 681 };
 682 
 683 
 684 /*      TXA_TEST                 8 bit  Tx Arbiter Test Register */
 685 enum {
 686         TXA_INT_T_ON    = 1<<5, /* Tx Arb Interval Timer Test On */
 687         TXA_INT_T_OFF   = 1<<4, /* Tx Arb Interval Timer Test Off */
 688         TXA_INT_T_STEP  = 1<<3, /* Tx Arb Interval Timer Step */
 689         TXA_LIM_T_ON    = 1<<2, /* Tx Arb Limit Timer Test On */
 690         TXA_LIM_T_OFF   = 1<<1, /* Tx Arb Limit Timer Test Off */
 691         TXA_LIM_T_STEP  = 1<<0, /* Tx Arb Limit Timer Step */
 692 };
 693 
 694 /*      TXA_STAT                 8 bit  Tx Arbiter Status Register */
 695 enum {
 696         TXA_PRIO_XS     = 1<<0, /* sync queue has prio to send */
 697 };
 698 
 699 
 700 /*      Q_BC                    32 bit  Current Byte Counter */
 701 
 702 /* BMU Control Status Registers */
 703 /*      B0_R1_CSR               32 bit  BMU Ctrl/Stat Rx Queue 1 */
 704 /*      B0_R2_CSR               32 bit  BMU Ctrl/Stat Rx Queue 2 */
 705 /*      B0_XA1_CSR              32 bit  BMU Ctrl/Stat Sync Tx Queue 1 */
 706 /*      B0_XS1_CSR              32 bit  BMU Ctrl/Stat Async Tx Queue 1 */
 707 /*      B0_XA2_CSR              32 bit  BMU Ctrl/Stat Sync Tx Queue 2 */
 708 /*      B0_XS2_CSR              32 bit  BMU Ctrl/Stat Async Tx Queue 2 */
 709 /*      Q_CSR                   32 bit  BMU Control/Status Register */
 710 
 711 enum {
 712         CSR_SV_IDLE     = 1<<24,        /* BMU SM Idle */
 713 
 714         CSR_DESC_CLR    = 1<<21,        /* Clear Reset for Descr */
 715         CSR_DESC_SET    = 1<<20,        /* Set   Reset for Descr */
 716         CSR_FIFO_CLR    = 1<<19,        /* Clear Reset for FIFO */
 717         CSR_FIFO_SET    = 1<<18,        /* Set   Reset for FIFO */
 718         CSR_HPI_RUN     = 1<<17,        /* Release HPI SM */
 719         CSR_HPI_RST     = 1<<16,        /* Reset   HPI SM to Idle */
 720         CSR_SV_RUN      = 1<<15,        /* Release Supervisor SM */
 721         CSR_SV_RST      = 1<<14,        /* Reset   Supervisor SM */
 722         CSR_DREAD_RUN   = 1<<13,        /* Release Descr Read SM */
 723         CSR_DREAD_RST   = 1<<12,        /* Reset   Descr Read SM */
 724         CSR_DWRITE_RUN  = 1<<11,        /* Release Descr Write SM */
 725         CSR_DWRITE_RST  = 1<<10,        /* Reset   Descr Write SM */
 726         CSR_TRANS_RUN   = 1<<9,         /* Release Transfer SM */
 727         CSR_TRANS_RST   = 1<<8,         /* Reset   Transfer SM */
 728         CSR_ENA_POL     = 1<<7,         /* Enable  Descr Polling */
 729         CSR_DIS_POL     = 1<<6,         /* Disable Descr Polling */
 730         CSR_STOP        = 1<<5,         /* Stop  Rx/Tx Queue */
 731         CSR_START       = 1<<4,         /* Start Rx/Tx Queue */
 732         CSR_IRQ_CL_P    = 1<<3,         /* (Rx) Clear Parity IRQ */
 733         CSR_IRQ_CL_B    = 1<<2,         /* Clear EOB IRQ */
 734         CSR_IRQ_CL_F    = 1<<1,         /* Clear EOF IRQ */
 735         CSR_IRQ_CL_C    = 1<<0,         /* Clear ERR IRQ */
 736 };
 737 
 738 #define CSR_SET_RESET   (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
 739                         CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
 740                         CSR_TRANS_RST)
 741 #define CSR_CLR_RESET   (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
 742                         CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
 743                         CSR_TRANS_RUN)
 744 
 745 /*      Q_F                             32 bit  Flag Register */
 746 enum {
 747         F_ALM_FULL      = 1<<27,        /* Rx FIFO: almost full */
 748         F_EMPTY         = 1<<27,        /* Tx FIFO: empty flag */
 749         F_FIFO_EOF      = 1<<26,        /* Tag (EOF Flag) bit in FIFO */
 750         F_WM_REACHED    = 1<<25,        /* Watermark reached */
 751 
 752         F_FIFO_LEVEL    = 0x1fL<<16,    /* Bit 23..16:  # of Qwords in FIFO */
 753         F_WATER_MARK    = 0x0007ffL,    /* Bit 10.. 0:  Watermark */
 754 };
 755 
 756 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
 757 /*      RB_START                32 bit  RAM Buffer Start Address */
 758 /*      RB_END                  32 bit  RAM Buffer End Address */
 759 /*      RB_WP                   32 bit  RAM Buffer Write Pointer */
 760 /*      RB_RP                   32 bit  RAM Buffer Read Pointer */
 761 /*      RB_RX_UTPP              32 bit  Rx Upper Threshold, Pause Pack */
 762 /*      RB_RX_LTPP              32 bit  Rx Lower Threshold, Pause Pack */
 763 /*      RB_RX_UTHP              32 bit  Rx Upper Threshold, High Prio */
 764 /*      RB_RX_LTHP              32 bit  Rx Lower Threshold, High Prio */
 765 /*      RB_PC                   32 bit  RAM Buffer Packet Counter */
 766 /*      RB_LEV                  32 bit  RAM Buffer Level Register */
 767 
 768 #define RB_MSK  0x0007ffff      /* Bit 18.. 0:  RAM Buffer Pointer Bits */
 769 /*      RB_TST2                  8 bit  RAM Buffer Test Register 2 */
 770 /*      RB_TST1                  8 bit  RAM Buffer Test Register 1 */
 771 
 772 /*      RB_CTRL                  8 bit  RAM Buffer Control Register */
 773 enum {
 774         RB_ENA_STFWD    = 1<<5, /* Enable  Store & Forward */
 775         RB_DIS_STFWD    = 1<<4, /* Disable Store & Forward */
 776         RB_ENA_OP_MD    = 1<<3, /* Enable  Operation Mode */
 777         RB_DIS_OP_MD    = 1<<2, /* Disable Operation Mode */
 778         RB_RST_CLR      = 1<<1, /* Clear RAM Buf STM Reset */
 779         RB_RST_SET      = 1<<0, /* Set   RAM Buf STM Reset */
 780 };
 781 
 782 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
 783 enum {
 784         TX_MFF_EA       = 0x0d00,/* 32 bit      Transmit MAC FIFO End Address */
 785         TX_MFF_WP       = 0x0d04,/* 32 bit      Transmit MAC FIFO WR Pointer */
 786         TX_MFF_WSP      = 0x0d08,/* 32 bit      Transmit MAC FIFO WR Shadow Ptr */
 787         TX_MFF_RP       = 0x0d0c,/* 32 bit      Transmit MAC FIFO RD Pointer */
 788         TX_MFF_PC       = 0x0d10,/* 32 bit      Transmit MAC FIFO Packet Cnt */
 789         TX_MFF_LEV      = 0x0d14,/* 32 bit      Transmit MAC FIFO Level */
 790         TX_MFF_CTRL1    = 0x0d18,/* 16 bit      Transmit MAC FIFO Ctrl Reg 1 */
 791         TX_MFF_WAF      = 0x0d1a,/*  8 bit      Transmit MAC Wait after flush */
 792 
 793         TX_MFF_CTRL2    = 0x0d1c,/*  8 bit      Transmit MAC FIFO Ctrl Reg 2 */
 794         TX_MFF_TST1     = 0x0d1d,/*  8 bit      Transmit MAC FIFO Test Reg 1 */
 795         TX_MFF_TST2     = 0x0d1e,/*  8 bit      Transmit MAC FIFO Test Reg 2 */
 796 
 797         TX_LED_INI      = 0x0d20,/* 32 bit      Transmit LED Cnt Init Value */
 798         TX_LED_VAL      = 0x0d24,/* 32 bit      Transmit LED Cnt Current Val */
 799         TX_LED_CTRL     = 0x0d28,/*  8 bit      Transmit LED Cnt Control Reg */
 800         TX_LED_TST      = 0x0d29,/*  8 bit      Transmit LED Cnt Test Reg */
 801 };
 802 
 803 /* Counter and Timer constants, for a host clock of 62.5 MHz */
 804 #define SK_XMIT_DUR             0x002faf08UL    /*  50 ms */
 805 #define SK_BLK_DUR              0x01dcd650UL    /* 500 ms */
 806 
 807 #define SK_DPOLL_DEF    0x00ee6b28UL    /* 250 ms at 62.5 MHz */
 808 
 809 #define SK_DPOLL_MAX    0x00ffffffUL    /* 268 ms at 62.5 MHz */
 810                                         /* 215 ms at 78.12 MHz */
 811 
 812 #define SK_FACT_62              100     /* is given in percent */
 813 #define SK_FACT_53               85     /* on GENESIS:  53.12 MHz */
 814 #define SK_FACT_78              125     /* on YUKON:    78.12 MHz */
 815 
 816 
 817 /* Transmit GMAC FIFO (YUKON only) */
 818 enum {
 819         TX_GMF_EA       = 0x0d40,/* 32 bit      Tx GMAC FIFO End Address */
 820         TX_GMF_AE_THR   = 0x0d44,/* 32 bit      Tx GMAC FIFO Almost Empty Thresh.*/
 821         TX_GMF_CTRL_T   = 0x0d48,/* 32 bit      Tx GMAC FIFO Control/Test */
 822 
 823         TX_GMF_WP       = 0x0d60,/* 32 bit      Tx GMAC FIFO Write Pointer */
 824         TX_GMF_WSP      = 0x0d64,/* 32 bit      Tx GMAC FIFO Write Shadow Ptr. */
 825         TX_GMF_WLEV     = 0x0d68,/* 32 bit      Tx GMAC FIFO Write Level */
 826 
 827         TX_GMF_RP       = 0x0d70,/* 32 bit      Tx GMAC FIFO Read Pointer */
 828         TX_GMF_RSTP     = 0x0d74,/* 32 bit      Tx GMAC FIFO Restart Pointer */
 829         TX_GMF_RLEV     = 0x0d78,/* 32 bit      Tx GMAC FIFO Read Level */
 830 
 831         /* Descriptor Poll Timer Registers */
 832         B28_DPT_INI     = 0x0e00,/* 24 bit      Descriptor Poll Timer Init Val */
 833         B28_DPT_VAL     = 0x0e04,/* 24 bit      Descriptor Poll Timer Curr Val */
 834         B28_DPT_CTRL    = 0x0e08,/*  8 bit      Descriptor Poll Timer Ctrl Reg */
 835 
 836         B28_DPT_TST     = 0x0e0a,/*  8 bit      Descriptor Poll Timer Test Reg */
 837 
 838         /* Time Stamp Timer Registers (YUKON only) */
 839         GMAC_TI_ST_VAL  = 0x0e14,/* 32 bit      Time Stamp Timer Curr Val */
 840         GMAC_TI_ST_CTRL = 0x0e18,/*  8 bit      Time Stamp Timer Ctrl Reg */
 841         GMAC_TI_ST_TST  = 0x0e1a,/*  8 bit      Time Stamp Timer Test Reg */
 842 };
 843 
 844 
 845 enum {
 846         LINKLED_OFF          = 0x01,
 847         LINKLED_ON           = 0x02,
 848         LINKLED_LINKSYNC_OFF = 0x04,
 849         LINKLED_LINKSYNC_ON  = 0x08,
 850         LINKLED_BLINK_OFF    = 0x10,
 851         LINKLED_BLINK_ON     = 0x20,
 852 };
 853 
 854 /* GMAC and GPHY Control Registers (YUKON only) */
 855 enum {
 856         GMAC_CTRL       = 0x0f00,/* 32 bit      GMAC Control Reg */
 857         GPHY_CTRL       = 0x0f04,/* 32 bit      GPHY Control Reg */
 858         GMAC_IRQ_SRC    = 0x0f08,/*  8 bit      GMAC Interrupt Source Reg */
 859         GMAC_IRQ_MSK    = 0x0f0c,/*  8 bit      GMAC Interrupt Mask Reg */
 860         GMAC_LINK_CTRL  = 0x0f10,/* 16 bit      Link Control Reg */
 861 
 862 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
 863 
 864         WOL_REG_OFFS    = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
 865 
 866         WOL_CTRL_STAT   = 0x0f20,/* 16 bit      WOL Control/Status Reg */
 867         WOL_MATCH_CTL   = 0x0f22,/*  8 bit      WOL Match Control Reg */
 868         WOL_MATCH_RES   = 0x0f23,/*  8 bit      WOL Match Result Reg */
 869         WOL_MAC_ADDR    = 0x0f24,/* 32 bit      WOL MAC Address */
 870         WOL_PATT_RPTR   = 0x0f2c,/*  8 bit      WOL Pattern Read Pointer */
 871 
 872 /* WOL Pattern Length Registers (YUKON only) */
 873 
 874         WOL_PATT_LEN_LO = 0x0f30,/* 32 bit      WOL Pattern Length 3..0 */
 875         WOL_PATT_LEN_HI = 0x0f34,/* 24 bit      WOL Pattern Length 6..4 */
 876 
 877 /* WOL Pattern Counter Registers (YUKON only) */
 878 
 879         WOL_PATT_CNT_0  = 0x0f38,/* 32 bit      WOL Pattern Counter 3..0 */
 880         WOL_PATT_CNT_4  = 0x0f3c,/* 24 bit      WOL Pattern Counter 6..4 */
 881 };
 882 #define WOL_REGS(port, x)       (x + (port)*0x80)
 883 
 884 enum {
 885         WOL_PATT_RAM_1  = 0x1000,/*  WOL Pattern RAM Link 1 */
 886         WOL_PATT_RAM_2  = 0x1400,/*  WOL Pattern RAM Link 2 */
 887 };
 888 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
 889 
 890 enum {
 891         BASE_XMAC_1     = 0x2000,/* XMAC 1 registers */
 892         BASE_GMAC_1     = 0x2800,/* GMAC 1 registers */
 893         BASE_XMAC_2     = 0x3000,/* XMAC 2 registers */
 894         BASE_GMAC_2     = 0x3800,/* GMAC 2 registers */
 895 };
 896 
 897 /*
 898  * Receive Frame Status Encoding
 899  */
 900 enum {
 901         XMR_FS_LEN      = 0x3fff<<18,   /* Bit 31..18:  Rx Frame Length */
 902         XMR_FS_LEN_SHIFT = 18,
 903         XMR_FS_2L_VLAN  = 1<<17, /* Bit 17:     tagged wh 2Lev VLAN ID*/
 904         XMR_FS_1_VLAN   = 1<<16, /* Bit 16:     tagged wh 1ev VLAN ID*/
 905         XMR_FS_BC       = 1<<15, /* Bit 15:     Broadcast Frame */
 906         XMR_FS_MC       = 1<<14, /* Bit 14:     Multicast Frame */
 907         XMR_FS_UC       = 1<<13, /* Bit 13:     Unicast Frame */
 908 
 909         XMR_FS_BURST    = 1<<11, /* Bit 11:     Burst Mode */
 910         XMR_FS_CEX_ERR  = 1<<10, /* Bit 10:     Carrier Ext. Error */
 911         XMR_FS_802_3    = 1<<9, /* Bit  9:      802.3 Frame */
 912         XMR_FS_COL_ERR  = 1<<8, /* Bit  8:      Collision Error */
 913         XMR_FS_CAR_ERR  = 1<<7, /* Bit  7:      Carrier Event Error */
 914         XMR_FS_LEN_ERR  = 1<<6, /* Bit  6:      In-Range Length Error */
 915         XMR_FS_FRA_ERR  = 1<<5, /* Bit  5:      Framing Error */
 916         XMR_FS_RUNT     = 1<<4, /* Bit  4:      Runt Frame */
 917         XMR_FS_LNG_ERR  = 1<<3, /* Bit  3:      Giant (Jumbo) Frame */
 918         XMR_FS_FCS_ERR  = 1<<2, /* Bit  2:      Frame Check Sequ Err */
 919         XMR_FS_ERR      = 1<<1, /* Bit  1:      Frame Error */
 920         XMR_FS_MCTRL    = 1<<0, /* Bit  0:      MAC Control Packet */
 921 
 922 /*
 923  * XMR_FS_ERR will be set if
 924  *      XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
 925  *      XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
 926  * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
 927  * XMR_FS_ERR unless the corresponding bit in the Receive Command
 928  * Register is set.
 929  */
 930 };
 931 
 932 /*
 933 ,* XMAC-PHY Registers, indirect addressed over the XMAC
 934  */
 935 enum {
 936         PHY_XMAC_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
 937         PHY_XMAC_STAT           = 0x01,/* 16 bit r/w    PHY Status Register */
 938         PHY_XMAC_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
 939         PHY_XMAC_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
 940         PHY_XMAC_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
 941         PHY_XMAC_AUNE_LP        = 0x05,/* 16 bit r/o    Link Partner Abi Reg */
 942         PHY_XMAC_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
 943         PHY_XMAC_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
 944         PHY_XMAC_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
 945 
 946         PHY_XMAC_EXT_STAT       = 0x0f,/* 16 bit r/o    Ext Status Register */
 947         PHY_XMAC_RES_ABI        = 0x10,/* 16 bit r/o    PHY Resolved Ability */
 948 };
 949 /*
 950  * Broadcom-PHY Registers, indirect addressed over XMAC
 951  */
 952 enum {
 953         PHY_BCOM_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
 954         PHY_BCOM_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
 955         PHY_BCOM_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
 956         PHY_BCOM_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
 957         PHY_BCOM_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
 958         PHY_BCOM_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
 959         PHY_BCOM_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
 960         PHY_BCOM_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
 961         PHY_BCOM_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
 962         /* Broadcom-specific registers */
 963         PHY_BCOM_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
 964         PHY_BCOM_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
 965         PHY_BCOM_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
 966         PHY_BCOM_P_EXT_CTRL     = 0x10,/* 16 bit r/w    PHY Extended Ctrl Reg */
 967         PHY_BCOM_P_EXT_STAT     = 0x11,/* 16 bit r/o    PHY Extended Stat Reg */
 968         PHY_BCOM_RE_CTR         = 0x12,/* 16 bit r/w    Receive Error Counter */
 969         PHY_BCOM_FC_CTR         = 0x13,/* 16 bit r/w    False Carrier Sense Cnt */
 970         PHY_BCOM_RNO_CTR        = 0x14,/* 16 bit r/w    Receiver NOT_OK Cnt */
 971 
 972         PHY_BCOM_AUX_CTRL       = 0x18,/* 16 bit r/w    Auxiliary Control Reg */
 973         PHY_BCOM_AUX_STAT       = 0x19,/* 16 bit r/o    Auxiliary Stat Summary */
 974         PHY_BCOM_INT_STAT       = 0x1a,/* 16 bit r/o    Interrupt Status Reg */
 975         PHY_BCOM_INT_MASK       = 0x1b,/* 16 bit r/w    Interrupt Mask Reg */
 976 };
 977 
 978 /*
 979  * Marvel-PHY Registers, indirect addressed over GMAC
 980  */
 981 enum {
 982         PHY_MARV_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
 983         PHY_MARV_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
 984         PHY_MARV_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
 985         PHY_MARV_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
 986         PHY_MARV_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
 987         PHY_MARV_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
 988         PHY_MARV_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
 989         PHY_MARV_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
 990         PHY_MARV_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
 991         /* Marvel-specific registers */
 992         PHY_MARV_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
 993         PHY_MARV_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
 994         PHY_MARV_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
 995         PHY_MARV_PHY_CTRL       = 0x10,/* 16 bit r/w    PHY Specific Ctrl Reg */
 996         PHY_MARV_PHY_STAT       = 0x11,/* 16 bit r/o    PHY Specific Stat Reg */
 997         PHY_MARV_INT_MASK       = 0x12,/* 16 bit r/w    Interrupt Mask Reg */
 998         PHY_MARV_INT_STAT       = 0x13,/* 16 bit r/o    Interrupt Status Reg */
 999         PHY_MARV_EXT_CTRL       = 0x14,/* 16 bit r/w    Ext. PHY Specific Ctrl */
1000         PHY_MARV_RXE_CNT        = 0x15,/* 16 bit r/w    Receive Error Counter */
1001         PHY_MARV_EXT_ADR        = 0x16,/* 16 bit r/w    Ext. Ad. for Cable Diag. */
1002         PHY_MARV_PORT_IRQ       = 0x17,/* 16 bit r/o    Port 0 IRQ (88E1111 only) */
1003         PHY_MARV_LED_CTRL       = 0x18,/* 16 bit r/w    LED Control Reg */
1004         PHY_MARV_LED_OVER       = 0x19,/* 16 bit r/w    Manual LED Override Reg */
1005         PHY_MARV_EXT_CTRL_2     = 0x1a,/* 16 bit r/w    Ext. PHY Specific Ctrl 2 */
1006         PHY_MARV_EXT_P_STAT     = 0x1b,/* 16 bit r/w    Ext. PHY Spec. Stat Reg */
1007         PHY_MARV_CABLE_DIAG     = 0x1c,/* 16 bit r/o    Cable Diagnostic Reg */
1008         PHY_MARV_PAGE_ADDR      = 0x1d,/* 16 bit r/w    Extended Page Address Reg */
1009         PHY_MARV_PAGE_DATA      = 0x1e,/* 16 bit r/w    Extended Page Data Reg */
1010 
1011 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1012         PHY_MARV_FE_LED_PAR     = 0x16,/* 16 bit r/w    LED Parallel Select Reg. */
1013         PHY_MARV_FE_LED_SER     = 0x17,/* 16 bit r/w    LED Stream Select S. LED */
1014         PHY_MARV_FE_VCT_TX      = 0x1a,/* 16 bit r/w    VCT Reg. for TXP/N Pins */
1015         PHY_MARV_FE_VCT_RX      = 0x1b,/* 16 bit r/o    VCT Reg. for RXP/N Pins */
1016         PHY_MARV_FE_SPEC_2      = 0x1c,/* 16 bit r/w    Specific Control Reg. 2 */
1017 };
1018 
1019 enum {
1020         PHY_CT_RESET    = 1<<15, /* Bit 15: (sc)        clear all PHY related regs */
1021         PHY_CT_LOOP     = 1<<14, /* Bit 14:     enable Loopback over PHY */
1022         PHY_CT_SPS_LSB  = 1<<13, /* Bit 13:     Speed select, lower bit */
1023         PHY_CT_ANE      = 1<<12, /* Bit 12:     Auto-Negotiation Enabled */
1024         PHY_CT_PDOWN    = 1<<11, /* Bit 11:     Power Down Mode */
1025         PHY_CT_ISOL     = 1<<10, /* Bit 10:     Isolate Mode */
1026         PHY_CT_RE_CFG   = 1<<9, /* Bit  9:      (sc) Restart Auto-Negotiation */
1027         PHY_CT_DUP_MD   = 1<<8, /* Bit  8:      Duplex Mode */
1028         PHY_CT_COL_TST  = 1<<7, /* Bit  7:      Collision Test enabled */
1029         PHY_CT_SPS_MSB  = 1<<6, /* Bit  6:      Speed select, upper bit */
1030 };
1031 
1032 enum {
1033         PHY_CT_SP1000   = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1034         PHY_CT_SP100    = PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
1035         PHY_CT_SP10     = 0,              /* enable speed of   10 Mbps */
1036 };
1037 
1038 enum {
1039         PHY_ST_EXT_ST   = 1<<8, /* Bit  8:      Extended Status Present */
1040 
1041         PHY_ST_PRE_SUP  = 1<<6, /* Bit  6:      Preamble Suppression */
1042         PHY_ST_AN_OVER  = 1<<5, /* Bit  5:      Auto-Negotiation Over */
1043         PHY_ST_REM_FLT  = 1<<4, /* Bit  4:      Remote Fault Condition Occurred */
1044         PHY_ST_AN_CAP   = 1<<3, /* Bit  3:      Auto-Negotiation Capability */
1045         PHY_ST_LSYNC    = 1<<2, /* Bit  2:      Link Synchronized */
1046         PHY_ST_JAB_DET  = 1<<1, /* Bit  1:      Jabber Detected */
1047         PHY_ST_EXT_REG  = 1<<0, /* Bit  0:      Extended Register available */
1048 };
1049 
1050 enum {
1051         PHY_I1_OUI_MSK  = 0x3f<<10, /* Bit 15..10:      Organization Unique ID */
1052         PHY_I1_MOD_NUM  = 0x3f<<4, /* Bit  9.. 4:       Model Number */
1053         PHY_I1_REV_MSK  = 0xf, /* Bit  3.. 0:   Revision Number */
1054 };
1055 
1056 /* different Broadcom PHY Ids */
1057 enum {
1058         PHY_BCOM_ID1_A1 = 0x6041,
1059         PHY_BCOM_ID1_B2 = 0x6043,
1060         PHY_BCOM_ID1_C0 = 0x6044,
1061         PHY_BCOM_ID1_C5 = 0x6047,
1062 };
1063 
1064 /* different Marvell PHY Ids */
1065 enum {
1066         PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1067         PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1068         PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1069         PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1070         PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1071 };
1072 
1073 /* Advertisement register bits */
1074 enum {
1075         PHY_AN_NXT_PG   = 1<<15, /* Bit 15:     Request Next Page */
1076         PHY_AN_ACK      = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
1077         PHY_AN_RF       = 1<<13, /* Bit 13:     Remote Fault Bits */
1078 
1079         PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:    Try for asymmetric */
1080         PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:    Try for pause */
1081         PHY_AN_100BASE4 = 1<<9, /* Bit 9:       Try for 100mbps 4k packets */
1082         PHY_AN_100FULL  = 1<<8, /* Bit 8:       Try for 100mbps full-duplex */
1083         PHY_AN_100HALF  = 1<<7, /* Bit 7:       Try for 100mbps half-duplex */
1084         PHY_AN_10FULL   = 1<<6, /* Bit 6:       Try for 10mbps full-duplex */
1085         PHY_AN_10HALF   = 1<<5, /* Bit 5:       Try for 10mbps half-duplex */
1086         PHY_AN_CSMA     = 1<<0, /* Bit 0:       Only selector supported */
1087         PHY_AN_SEL      = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
1088         PHY_AN_FULL     = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1089         PHY_AN_ALL      = PHY_AN_10HALF | PHY_AN_10FULL |
1090                           PHY_AN_100HALF | PHY_AN_100FULL,
1091 };
1092 
1093 /* Xmac Specific */
1094 enum {
1095         PHY_X_AN_NXT_PG = 1<<15, /* Bit 15:     Request Next Page */
1096         PHY_X_AN_ACK    = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
1097         PHY_X_AN_RFB    = 3<<12,/* Bit 13..12:  Remote Fault Bits */
1098 
1099         PHY_X_AN_PAUSE  = 3<<7,/* Bit  8.. 7:   Pause Bits */
1100         PHY_X_AN_HD     = 1<<6, /* Bit  6:      Half Duplex */
1101         PHY_X_AN_FD     = 1<<5, /* Bit  5:      Full Duplex */
1102 };
1103 
1104 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1105 enum {
1106         PHY_X_P_NO_PAUSE= 0<<7,/* Bit  8..7:    no Pause Mode */
1107         PHY_X_P_SYM_MD  = 1<<7, /* Bit  8..7:   symmetric Pause Mode */
1108         PHY_X_P_ASYM_MD = 2<<7,/* Bit  8..7:    asymmetric Pause Mode */
1109         PHY_X_P_BOTH_MD = 3<<7,/* Bit  8..7:    both Pause Mode */
1110 };
1111 
1112 
1113 /*****  PHY_XMAC_EXT_STAT       16 bit r/w      Extended Status Register *****/
1114 enum {
1115         PHY_X_EX_FD     = 1<<15, /* Bit 15:     Device Supports Full Duplex */
1116         PHY_X_EX_HD     = 1<<14, /* Bit 14:     Device Supports Half Duplex */
1117 };
1118 
1119 /*****  PHY_XMAC_RES_ABI        16 bit r/o      PHY Resolved Ability *****/
1120 enum {
1121         PHY_X_RS_PAUSE  = 3<<7, /* Bit  8..7:   selected Pause Mode */
1122         PHY_X_RS_HD     = 1<<6, /* Bit  6:      Half Duplex Mode selected */
1123         PHY_X_RS_FD     = 1<<5, /* Bit  5:      Full Duplex Mode selected */
1124         PHY_X_RS_ABLMIS = 1<<4, /* Bit  4:      duplex or pause cap mismatch */
1125         PHY_X_RS_PAUMIS = 1<<3, /* Bit  3:      pause capability mismatch */
1126 };
1127 
1128 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1129 enum {
1130         X_RFB_OK        = 0<<12,/* Bit 13..12   No errors, Link OK */
1131         X_RFB_LF        = 1<<12,/* Bit 13..12   Link Failure */
1132         X_RFB_OFF       = 2<<12,/* Bit 13..12   Offline */
1133         X_RFB_AN_ERR    = 3<<12,/* Bit 13..12   Auto-Negotiation Error */
1134 };
1135 
1136 /* Broadcom-Specific */
1137 /*****  PHY_BCOM_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
1138 enum {
1139         PHY_B_1000C_TEST        = 7<<13,/* Bit 15..13:  Test Modes */
1140         PHY_B_1000C_MSE = 1<<12, /* Bit 12:     Master/Slave Enable */
1141         PHY_B_1000C_MSC = 1<<11, /* Bit 11:     M/S Configuration */
1142         PHY_B_1000C_RD  = 1<<10, /* Bit 10:     Repeater/DTE */
1143         PHY_B_1000C_AFD = 1<<9, /* Bit  9:      Advertise Full Duplex */
1144         PHY_B_1000C_AHD = 1<<8, /* Bit  8:      Advertise Half Duplex */
1145 };
1146 
1147 /*****  PHY_BCOM_1000T_STAT     16 bit r/o      1000Base-T Status Reg *****/
1148 /*****  PHY_MARV_1000T_STAT     16 bit r/o      1000Base-T Status Reg *****/
1149 enum {
1150         PHY_B_1000S_MSF = 1<<15, /* Bit 15:     Master/Slave Fault */
1151         PHY_B_1000S_MSR = 1<<14, /* Bit 14:     Master/Slave Result */
1152         PHY_B_1000S_LRS = 1<<13, /* Bit 13:     Local Receiver Status */
1153         PHY_B_1000S_RRS = 1<<12, /* Bit 12:     Remote Receiver Status */
1154         PHY_B_1000S_LP_FD       = 1<<11, /* Bit 11:     Link Partner can FD */
1155         PHY_B_1000S_LP_HD       = 1<<10, /* Bit 10:     Link Partner can HD */
1156                                                                         /* Bit  9..8:   reserved */
1157         PHY_B_1000S_IEC = 0xff, /* Bit  7..0:   Idle Error Count */
1158 };
1159 
1160 /*****  PHY_BCOM_EXT_STAT       16 bit r/o      Extended Status Register *****/
1161 enum {
1162         PHY_B_ES_X_FD_CAP       = 1<<15, /* Bit 15:     1000Base-X FD capable */
1163         PHY_B_ES_X_HD_CAP       = 1<<14, /* Bit 14:     1000Base-X HD capable */
1164         PHY_B_ES_T_FD_CAP       = 1<<13, /* Bit 13:     1000Base-T FD capable */
1165         PHY_B_ES_T_HD_CAP       = 1<<12, /* Bit 12:     1000Base-T HD capable */
1166 };
1167 
1168 /*****  PHY_BCOM_P_EXT_CTRL     16 bit r/w      PHY Extended Control Reg *****/
1169 enum {
1170         PHY_B_PEC_MAC_PHY       = 1<<15, /* Bit 15:     10BIT/GMI-Interface */
1171         PHY_B_PEC_DIS_CROSS     = 1<<14, /* Bit 14:     Disable MDI Crossover */
1172         PHY_B_PEC_TX_DIS        = 1<<13, /* Bit 13:     Tx output Disabled */
1173         PHY_B_PEC_INT_DIS       = 1<<12, /* Bit 12:     Interrupts Disabled */
1174         PHY_B_PEC_F_INT = 1<<11, /* Bit 11:     Force Interrupt */
1175         PHY_B_PEC_BY_45 = 1<<10, /* Bit 10:     Bypass 4B5B-Decoder */
1176         PHY_B_PEC_BY_SCR        = 1<<9, /* Bit  9:      Bypass Scrambler */
1177         PHY_B_PEC_BY_MLT3       = 1<<8, /* Bit  8:      Bypass MLT3 Encoder */
1178         PHY_B_PEC_BY_RXA        = 1<<7, /* Bit  7:      Bypass Rx Alignm. */
1179         PHY_B_PEC_RES_SCR       = 1<<6, /* Bit  6:      Reset Scrambler */
1180         PHY_B_PEC_EN_LTR        = 1<<5, /* Bit  5:      Ena LED Traffic Mode */
1181         PHY_B_PEC_LED_ON        = 1<<4, /* Bit  4:      Force LED's on */
1182         PHY_B_PEC_LED_OFF       = 1<<3, /* Bit  3:      Force LED's off */
1183         PHY_B_PEC_EX_IPG        = 1<<2, /* Bit  2:      Extend Tx IPG Mode */
1184         PHY_B_PEC_3_LED = 1<<1, /* Bit  1:      Three Link LED mode */
1185         PHY_B_PEC_HIGH_LA       = 1<<0, /* Bit  0:      GMII FIFO Elasticy */
1186 };
1187 
1188 /*****  PHY_BCOM_P_EXT_STAT     16 bit r/o      PHY Extended Status Reg *****/
1189 enum {
1190         PHY_B_PES_CROSS_STAT    = 1<<13, /* Bit 13:     MDI Crossover Status */
1191         PHY_B_PES_INT_STAT      = 1<<12, /* Bit 12:     Interrupt Status */
1192         PHY_B_PES_RRS   = 1<<11, /* Bit 11:     Remote Receiver Stat. */
1193         PHY_B_PES_LRS   = 1<<10, /* Bit 10:     Local Receiver Stat. */
1194         PHY_B_PES_LOCKED        = 1<<9, /* Bit  9:      Locked */
1195         PHY_B_PES_LS    = 1<<8, /* Bit  8:      Link Status */
1196         PHY_B_PES_RF    = 1<<7, /* Bit  7:      Remote Fault */
1197         PHY_B_PES_CE_ER = 1<<6, /* Bit  6:      Carrier Ext Error */
1198         PHY_B_PES_BAD_SSD       = 1<<5, /* Bit  5:      Bad SSD */
1199         PHY_B_PES_BAD_ESD       = 1<<4, /* Bit  4:      Bad ESD */
1200         PHY_B_PES_RX_ER = 1<<3, /* Bit  3:      Receive Error */
1201         PHY_B_PES_TX_ER = 1<<2, /* Bit  2:      Transmit Error */
1202         PHY_B_PES_LOCK_ER       = 1<<1, /* Bit  1:      Lock Error */
1203         PHY_B_PES_MLT3_ER       = 1<<0, /* Bit  0:      MLT3 code Error */
1204 };
1205 
1206 /*  PHY_BCOM_AUNE_ADV   16 bit r/w      Auto-Negotiation Advertisement *****/
1207 /*  PHY_BCOM_AUNE_LP    16 bit r/o      Link Partner Ability Reg *****/
1208 enum {
1209         PHY_B_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
1210 
1211         PHY_B_AN_ASP    = 1<<11, /* Bit 11:     Asymmetric Pause */
1212         PHY_B_AN_PC     = 1<<10, /* Bit 10:     Pause Capable */
1213 };
1214 
1215 
1216 /*****  PHY_BCOM_FC_CTR         16 bit r/w      False Carrier Counter *****/
1217 enum {
1218         PHY_B_FC_CTR    = 0xff, /* Bit  7..0:   False Carrier Counter */
1219 
1220 /*****  PHY_BCOM_RNO_CTR        16 bit r/w      Receive NOT_OK Counter *****/
1221         PHY_B_RC_LOC_MSK        = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1222         PHY_B_RC_REM_MSK        = 0x00ff, /* Bit  7..0: Remote Rx NOT_OK cnt */
1223 
1224 /*****  PHY_BCOM_AUX_CTRL       16 bit r/w      Auxiliary Control Reg *****/
1225         PHY_B_AC_L_SQE          = 1<<15, /* Bit 15:     Low Squelch */
1226         PHY_B_AC_LONG_PACK      = 1<<14, /* Bit 14:     Rx Long Packets */
1227         PHY_B_AC_ER_CTRL        = 3<<12,/* Bit 13..12:  Edgerate Control */
1228                                                                         /* Bit 11:      reserved */
1229         PHY_B_AC_TX_TST = 1<<10, /* Bit 10:     Tx test bit, always 1 */
1230                                                                         /* Bit  9.. 8:  reserved */
1231         PHY_B_AC_DIS_PRF        = 1<<7, /* Bit  7:      dis part resp filter */
1232                                                                         /* Bit  6:      reserved */
1233         PHY_B_AC_DIS_PM = 1<<5, /* Bit  5:      dis power management */
1234                                                                         /* Bit  4:      reserved */
1235         PHY_B_AC_DIAG   = 1<<3, /* Bit  3:      Diagnostic Mode */
1236 };
1237 
1238 /*****  PHY_BCOM_AUX_STAT       16 bit r/o      Auxiliary Status Reg *****/
1239 enum {
1240         PHY_B_AS_AN_C   = 1<<15, /* Bit 15:     AutoNeg complete */
1241         PHY_B_AS_AN_CA  = 1<<14, /* Bit 14:     AN Complete Ack */
1242         PHY_B_AS_ANACK_D        = 1<<13, /* Bit 13:     AN Ack Detect */
1243         PHY_B_AS_ANAB_D = 1<<12, /* Bit 12:     AN Ability Detect */
1244         PHY_B_AS_NPW    = 1<<11, /* Bit 11:     AN Next Page Wait */
1245         PHY_B_AS_AN_RES_MSK     = 7<<8,/* Bit 10..8:    AN HDC */
1246         PHY_B_AS_PDF    = 1<<7, /* Bit  7:      Parallel Detect. Fault */
1247         PHY_B_AS_RF     = 1<<6, /* Bit  6:      Remote Fault */
1248         PHY_B_AS_ANP_R  = 1<<5, /* Bit  5:      AN Page Received */
1249         PHY_B_AS_LP_ANAB        = 1<<4, /* Bit  4:      LP AN Ability */
1250         PHY_B_AS_LP_NPAB        = 1<<3, /* Bit  3:      LP Next Page Ability */
1251         PHY_B_AS_LS     = 1<<2, /* Bit  2:      Link Status */
1252         PHY_B_AS_PRR    = 1<<1, /* Bit  1:      Pause Resolution-Rx */
1253         PHY_B_AS_PRT    = 1<<0, /* Bit  0:      Pause Resolution-Tx */
1254 };
1255 #define PHY_B_AS_PAUSE_MSK      (PHY_B_AS_PRR | PHY_B_AS_PRT)
1256 
1257 /*****  PHY_BCOM_INT_STAT       16 bit r/o      Interrupt Status Reg *****/
1258 /*****  PHY_BCOM_INT_MASK       16 bit r/w      Interrupt Mask Reg *****/
1259 enum {
1260         PHY_B_IS_PSE    = 1<<14, /* Bit 14:     Pair Swap Error */
1261         PHY_B_IS_MDXI_SC        = 1<<13, /* Bit 13:     MDIX Status Change */
1262         PHY_B_IS_HCT    = 1<<12, /* Bit 12:     counter above 32k */
1263         PHY_B_IS_LCT    = 1<<11, /* Bit 11:     counter above 128 */
1264         PHY_B_IS_AN_PR  = 1<<10, /* Bit 10:     Page Received */
1265         PHY_B_IS_NO_HDCL        = 1<<9, /* Bit  9:      No HCD Link */
1266         PHY_B_IS_NO_HDC = 1<<8, /* Bit  8:      No HCD */
1267         PHY_B_IS_NEG_USHDC      = 1<<7, /* Bit  7:      Negotiated Unsup. HCD */
1268         PHY_B_IS_SCR_S_ER       = 1<<6, /* Bit  6:      Scrambler Sync Error */
1269         PHY_B_IS_RRS_CHANGE     = 1<<5, /* Bit  5:      Remote Rx Stat Change */
1270         PHY_B_IS_LRS_CHANGE     = 1<<4, /* Bit  4:      Local Rx Stat Change */
1271         PHY_B_IS_DUP_CHANGE     = 1<<3, /* Bit  3:      Duplex Mode Change */
1272         PHY_B_IS_LSP_CHANGE     = 1<<2, /* Bit  2:      Link Speed Change */
1273         PHY_B_IS_LST_CHANGE     = 1<<1, /* Bit  1:      Link Status Changed */
1274         PHY_B_IS_CRC_ER = 1<<0, /* Bit  0:      CRC Error */
1275 };
1276 #define PHY_B_DEF_MSK   \
1277         (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1278             PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1279 
1280 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1281 enum {
1282         PHY_B_P_NO_PAUSE        = 0<<10,/* Bit 11..10:  no Pause Mode */
1283         PHY_B_P_SYM_MD  = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1284         PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10:  asymmetric Pause Mode */
1285         PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10:  both Pause Mode */
1286 };
1287 /*
1288  * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1289  */
1290 enum {
1291         PHY_B_RES_1000FD        = 7<<8,/* Bit 10..8:    1000Base-T Full Dup. */
1292         PHY_B_RES_1000HD        = 6<<8,/* Bit 10..8:    1000Base-T Half Dup. */
1293 };
1294 
1295 /** Marvell-Specific */
1296 enum {
1297         PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1298         PHY_M_AN_ACK    = 1<<14, /* (ro)        Acknowledge Received */
1299         PHY_M_AN_RF     = 1<<13, /* Remote Fault */
1300 
1301         PHY_M_AN_ASP    = 1<<11, /* Asymmetric Pause */
1302         PHY_M_AN_PC     = 1<<10, /* MAC Pause implemented */
1303         PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1304         PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1305         PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1306         PHY_M_AN_10_FD  = 1<<6, /* Advertise 10Base-TX Full Duplex */
1307         PHY_M_AN_10_HD  = 1<<5, /* Advertise 10Base-TX Half Duplex */
1308         PHY_M_AN_SEL_MSK =0x1f<<4,      /* Bit  4.. 0: Selector Field Mask */
1309 };
1310 
1311 /* special defines for FIBER (88E1011S only) */
1312 enum {
1313         PHY_M_AN_ASP_X          = 1<<8, /* Asymmetric Pause */
1314         PHY_M_AN_PC_X           = 1<<7, /* MAC Pause implemented */
1315         PHY_M_AN_1000X_AHD      = 1<<6, /* Advertise 10000Base-X Half Duplex */
1316         PHY_M_AN_1000X_AFD      = 1<<5, /* Advertise 10000Base-X Full Duplex */
1317 };
1318 
1319 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1320 enum {
1321         PHY_M_P_NO_PAUSE_X      = 0<<7,/* Bit  8.. 7:   no Pause Mode */
1322         PHY_M_P_SYM_MD_X        = 1<<7, /* Bit  8.. 7:  symmetric Pause Mode */
1323         PHY_M_P_ASYM_MD_X       = 2<<7,/* Bit  8.. 7:   asymmetric Pause Mode */
1324         PHY_M_P_BOTH_MD_X       = 3<<7,/* Bit  8.. 7:   both Pause Mode */
1325 };
1326 
1327 /*****  PHY_MARV_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
1328 enum {
1329         PHY_M_1000C_TEST= 7<<13,/* Bit 15..13:  Test Modes */
1330         PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1331         PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1332         PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1333         PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1334         PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1335 };
1336 
1337 /*****  PHY_MARV_PHY_CTRL       16 bit r/w      PHY Specific Ctrl Reg *****/
1338 enum {
1339         PHY_M_PC_TX_FFD_MSK     = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1340         PHY_M_PC_RX_FFD_MSK     = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1341         PHY_M_PC_ASS_CRS_TX     = 1<<11, /* Assert CRS on Transmit */
1342         PHY_M_PC_FL_GOOD        = 1<<10, /* Force Link Good */
1343         PHY_M_PC_EN_DET_MSK     = 3<<8,/* Bit  9.. 8: Energy Detect Mask */
1344         PHY_M_PC_ENA_EXT_D      = 1<<7, /* Enable Ext. Distance (10BT) */
1345         PHY_M_PC_MDIX_MSK       = 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
1346         PHY_M_PC_DIS_125CLK     = 1<<4, /* Disable 125 CLK */
1347         PHY_M_PC_MAC_POW_UP     = 1<<3, /* MAC Power up */
1348         PHY_M_PC_SQE_T_ENA      = 1<<2, /* SQE Test Enabled */
1349         PHY_M_PC_POL_R_DIS      = 1<<1, /* Polarity Reversal Disabled */
1350         PHY_M_PC_DIS_JABBER     = 1<<0, /* Disable Jabber */
1351 };
1352 
1353 enum {
1354         PHY_M_PC_EN_DET         = 2<<8, /* Energy Detect (Mode 1) */
1355         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
1356 };
1357 
1358 enum {
1359         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
1360         PHY_M_PC_MAN_MDIX       = 1, /* 01 = Manual MDIX configuration */
1361         PHY_M_PC_ENA_AUTO       = 3, /* 11 = Enable Automatic Crossover */
1362 };
1363 
1364 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1365 enum {
1366         PHY_M_PC_ENA_DTE_DT     = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1367         PHY_M_PC_ENA_ENE_DT     = 1<<14, /* Enable Energy Detect (sense & pulse) */
1368         PHY_M_PC_DIS_NLP_CK     = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1369         PHY_M_PC_ENA_LIP_NP     = 1<<12, /* Enable Link Partner Next Page Reg. */
1370         PHY_M_PC_DIS_NLP_GN     = 1<<11, /* Disable Normal Link Puls Generation */
1371 
1372         PHY_M_PC_DIS_SCRAMB     = 1<<9, /* Disable Scrambler */
1373         PHY_M_PC_DIS_FEFI       = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1374 
1375         PHY_M_PC_SH_TP_SEL      = 1<<6, /* Shielded Twisted Pair Select */
1376         PHY_M_PC_RX_FD_MSK      = 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
1377 };
1378 
1379 /*****  PHY_MARV_PHY_STAT       16 bit r/o      PHY Specific Status Reg *****/
1380 enum {
1381         PHY_M_PS_SPEED_MSK      = 3<<14, /* Bit 15..14: Speed Mask */
1382         PHY_M_PS_SPEED_1000     = 1<<15, /*             10 = 1000 Mbps */
1383         PHY_M_PS_SPEED_100      = 1<<14, /*             01 =  100 Mbps */
1384         PHY_M_PS_SPEED_10       = 0,     /*             00 =   10 Mbps */
1385         PHY_M_PS_FULL_DUP       = 1<<13, /* Full Duplex */
1386         PHY_M_PS_PAGE_REC       = 1<<12, /* Page Received */
1387         PHY_M_PS_SPDUP_RES      = 1<<11, /* Speed & Duplex Resolved */
1388         PHY_M_PS_LINK_UP        = 1<<10, /* Link Up */
1389         PHY_M_PS_CABLE_MSK      = 7<<7,  /* Bit  9.. 7: Cable Length Mask */
1390         PHY_M_PS_MDI_X_STAT     = 1<<6,  /* MDI Crossover Stat (1=MDIX) */
1391         PHY_M_PS_DOWNS_STAT     = 1<<5,  /* Downshift Status (1=downsh.) */
1392         PHY_M_PS_ENDET_STAT     = 1<<4,  /* Energy Detect Status (1=act) */
1393         PHY_M_PS_TX_P_EN        = 1<<3,  /* Tx Pause Enabled */
1394         PHY_M_PS_RX_P_EN        = 1<<2,  /* Rx Pause Enabled */
1395         PHY_M_PS_POL_REV        = 1<<1,  /* Polarity Reversed */
1396         PHY_M_PS_JABBER         = 1<<0,  /* Jabber */
1397 };
1398 
1399 #define PHY_M_PS_PAUSE_MSK      (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1400 
1401 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1402 enum {
1403         PHY_M_PS_DTE_DETECT     = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1404         PHY_M_PS_RES_SPEED      = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1405 };
1406 
1407 enum {
1408         PHY_M_IS_AN_ERROR       = 1<<15, /* Auto-Negotiation Error */
1409         PHY_M_IS_LSP_CHANGE     = 1<<14, /* Link Speed Changed */
1410         PHY_M_IS_DUP_CHANGE     = 1<<13, /* Duplex Mode Changed */
1411         PHY_M_IS_AN_PR          = 1<<12, /* Page Received */
1412         PHY_M_IS_AN_COMPL       = 1<<11, /* Auto-Negotiation Completed */
1413         PHY_M_IS_LST_CHANGE     = 1<<10, /* Link Status Changed */
1414         PHY_M_IS_SYMB_ERROR     = 1<<9, /* Symbol Error */
1415         PHY_M_IS_FALSE_CARR     = 1<<8, /* False Carrier */
1416         PHY_M_IS_FIFO_ERROR     = 1<<7, /* FIFO Overflow/Underrun Error */
1417         PHY_M_IS_MDI_CHANGE     = 1<<6, /* MDI Crossover Changed */
1418         PHY_M_IS_DOWNSH_DET     = 1<<5, /* Downshift Detected */
1419         PHY_M_IS_END_CHANGE     = 1<<4, /* Energy Detect Changed */
1420 
1421         PHY_M_IS_DTE_CHANGE     = 1<<2, /* DTE Power Det. Status Changed */
1422         PHY_M_IS_POL_CHANGE     = 1<<1, /* Polarity Changed */
1423         PHY_M_IS_JABBER         = 1<<0, /* Jabber */
1424 
1425         PHY_M_IS_DEF_MSK        = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1426                                   PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1427 
1428         PHY_M_IS_AN_MSK         = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1429 };
1430 
1431 /*****  PHY_MARV_EXT_CTRL       16 bit r/w      Ext. PHY Specific Ctrl *****/
1432 enum {
1433         PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1434         PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1435 
1436         PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1437         PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:     Master Downshift Counter */
1438                                         /* (88E1011 only) */
1439         PHY_M_EC_S_DSC_MSK  = 3<<8,  /* Bit  9.. 8:     Slave  Downshift Counter */
1440                                        /* (88E1011 only) */
1441         PHY_M_EC_M_DSC_MSK2  = 7<<9, /* Bit 11.. 9:     Master Downshift Counter */
1442                                         /* (88E1111 only) */
1443         PHY_M_EC_DOWN_S_ENA  = 1<<8, /* Downshift Enable (88E1111 only) */
1444                                         /* !!! Errata in spec. (1 = disable) */
1445         PHY_M_EC_RX_TIM_CT   = 1<<7, /* RGMII Rx Timing Control*/
1446         PHY_M_EC_MAC_S_MSK   = 7<<4, /* Bit  6.. 4:     Def. MAC interface speed */
1447         PHY_M_EC_FIB_AN_ENA  = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1448         PHY_M_EC_DTE_D_ENA   = 1<<2, /* DTE Detect Enable (88E1111 only) */
1449         PHY_M_EC_TX_TIM_CT   = 1<<1, /* RGMII Tx Timing Control */
1450         PHY_M_EC_TRANS_DIS   = 1<<0, /* Transmitter Disable (88E1111 only) */};
1451 
1452 #define PHY_M_EC_M_DSC(x)       ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1453 #define PHY_M_EC_S_DSC(x)       ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1454 #define PHY_M_EC_MAC_S(x)       ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1455 
1456 #define PHY_M_EC_M_DSC_2(x)     ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1457                                                                                         /* 100=5x; 101=6x; 110=7x; 111=8x */
1458 enum {
1459         MAC_TX_CLK_0_MHZ        = 2,
1460         MAC_TX_CLK_2_5_MHZ      = 6,
1461         MAC_TX_CLK_25_MHZ       = 7,
1462 };
1463 
1464 /*****  PHY_MARV_LED_CTRL       16 bit r/w      LED Control Reg *****/
1465 enum {
1466         PHY_M_LEDC_DIS_LED      = 1<<15, /* Disable LED */
1467         PHY_M_LEDC_PULS_MSK     = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1468         PHY_M_LEDC_F_INT        = 1<<11, /* Force Interrupt */
1469         PHY_M_LEDC_BL_R_MSK     = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1470         PHY_M_LEDC_DP_C_LSB     = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1471         PHY_M_LEDC_TX_C_LSB     = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1472         PHY_M_LEDC_LK_C_MSK     = 7<<3,/* Bit  5.. 3: Link Control Mask */
1473                                         /* (88E1111 only) */
1474 };
1475 #define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1476 #define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1477 
1478 enum {
1479         PHY_M_LEDC_LINK_MSK     = 3<<3, /* Bit  4.. 3: Link Control Mask */
1480                                         /* (88E1011 only) */
1481         PHY_M_LEDC_DP_CTRL      = 1<<2, /* Duplex Control */
1482         PHY_M_LEDC_DP_C_MSB     = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1483         PHY_M_LEDC_RX_CTRL      = 1<<1, /* Rx Activity / Link */
1484         PHY_M_LEDC_TX_CTRL      = 1<<0, /* Tx Activity / Link */
1485         PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1486 };
1487 
1488 enum {
1489         PULS_NO_STR     = 0, /* no pulse stretching */
1490         PULS_21MS       = 1, /* 21 ms to 42 ms */
1491         PULS_42MS       = 2, /* 42 ms to 84 ms */
1492         PULS_84MS       = 3, /* 84 ms to 170 ms */
1493         PULS_170MS      = 4, /* 170 ms to 340 ms */
1494         PULS_340MS      = 5, /* 340 ms to 670 ms */
1495         PULS_670MS      = 6, /* 670 ms to 1.3 s */
1496         PULS_1300MS     = 7, /* 1.3 s to 2.7 s */
1497 };
1498 
1499 
1500 enum {
1501         BLINK_42MS      = 0, /* 42 ms */
1502         BLINK_84MS      = 1, /* 84 ms */
1503         BLINK_170MS     = 2, /* 170 ms */
1504         BLINK_340MS     = 3, /* 340 ms */
1505         BLINK_670MS     = 4, /* 670 ms */
1506 };
1507 
1508 /*****  PHY_MARV_LED_OVER       16 bit r/w      Manual LED Override Reg *****/
1509 #define PHY_M_LED_MO_SGMII(x)   ((x)<<14) /* Bit 15..14:  SGMII AN Timer */
1510                                                                                 /* Bit 13..12:  reserved */
1511 #define PHY_M_LED_MO_DUP(x)     ((x)<<10) /* Bit 11..10:  Duplex */
1512 #define PHY_M_LED_MO_10(x)      ((x)<<8) /* Bit  9.. 8:  Link 10 */
1513 #define PHY_M_LED_MO_100(x)     ((x)<<6) /* Bit  7.. 6:  Link 100 */
1514 #define PHY_M_LED_MO_1000(x)    ((x)<<4) /* Bit  5.. 4:  Link 1000 */
1515 #define PHY_M_LED_MO_RX(x)      ((x)<<2) /* Bit  3.. 2:  Rx */
1516 #define PHY_M_LED_MO_TX(x)      ((x)<<0) /* Bit  1.. 0:  Tx */
1517 
1518 enum {
1519         MO_LED_NORM     = 0,
1520         MO_LED_BLINK    = 1,
1521         MO_LED_OFF      = 2,
1522         MO_LED_ON       = 3,
1523 };
1524 
1525 /*****  PHY_MARV_EXT_CTRL_2     16 bit r/w      Ext. PHY Specific Ctrl 2 *****/
1526 enum {
1527         PHY_M_EC2_FI_IMPED      = 1<<6, /* Fiber Input  Impedance */
1528         PHY_M_EC2_FO_IMPED      = 1<<5, /* Fiber Output Impedance */
1529         PHY_M_EC2_FO_M_CLK      = 1<<4, /* Fiber Mode Clock Enable */
1530         PHY_M_EC2_FO_BOOST      = 1<<3, /* Fiber Output Boost */
1531         PHY_M_EC2_FO_AM_MSK     = 7, /* Bit  2.. 0:     Fiber Output Amplitude */
1532 };
1533 
1534 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
1535 enum {
1536         PHY_M_FC_AUTO_SEL       = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1537         PHY_M_FC_AN_REG_ACC     = 1<<14, /* Fiber/Copper AN Reg. Access */
1538         PHY_M_FC_RESOLUTION     = 1<<13, /* Fiber/Copper Resolution */
1539         PHY_M_SER_IF_AN_BP      = 1<<12, /* Ser. IF AN Bypass Enable */
1540         PHY_M_SER_IF_BP_ST      = 1<<11, /* Ser. IF AN Bypass Status */
1541         PHY_M_IRQ_POLARITY      = 1<<10, /* IRQ polarity */
1542         PHY_M_DIS_AUT_MED       = 1<<9, /* Disable Aut. Medium Reg. Selection */
1543                                                                         /* (88E1111 only) */
1544                                                                 /* Bit  9.. 4: reserved (88E1011 only) */
1545         PHY_M_UNDOC1    = 1<<7, /* undocumented bit !! */
1546         PHY_M_DTE_POW_STAT      = 1<<4, /* DTE Power Status (88E1111 only) */
1547         PHY_M_MODE_MASK = 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
1548 };
1549 
1550 /*****  PHY_MARV_CABLE_DIAG     16 bit r/o      Cable Diagnostic Reg *****/
1551 enum {
1552         PHY_M_CABD_ENA_TEST     = 1<<15, /* Enable Test (Page 0) */
1553         PHY_M_CABD_DIS_WAIT     = 1<<15, /* Disable Waiting Period (Page 1) */
1554                                         /* (88E1111 only) */
1555         PHY_M_CABD_STAT_MSK     = 3<<13, /* Bit 14..13: Status Mask */
1556         PHY_M_CABD_AMPL_MSK     = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1557                                         /* (88E1111 only) */
1558         PHY_M_CABD_DIST_MSK     = 0xff, /* Bit  7.. 0: Distance Mask */
1559 };
1560 
1561 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1562 enum {
1563         CABD_STAT_NORMAL= 0,
1564         CABD_STAT_SHORT = 1,
1565         CABD_STAT_OPEN  = 2,
1566         CABD_STAT_FAIL  = 3,
1567 };
1568 
1569 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1570 /*****  PHY_MARV_FE_LED_PAR             16 bit r/w      LED Parallel Select Reg. *****/
1571                                                                         /* Bit 15..12: reserved (used internally) */
1572 enum {
1573         PHY_M_FELP_LED2_MSK = 0xf<<8,   /* Bit 11.. 8: LED2 Mask (LINK) */
1574         PHY_M_FELP_LED1_MSK = 0xf<<4,   /* Bit  7.. 4: LED1 Mask (ACT) */
1575         PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
1576 };
1577 
1578 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1579 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1580 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1581 
1582 enum {
1583         LED_PAR_CTRL_COLX       = 0x00,
1584         LED_PAR_CTRL_ERROR      = 0x01,
1585         LED_PAR_CTRL_DUPLEX     = 0x02,
1586         LED_PAR_CTRL_DP_COL     = 0x03,
1587         LED_PAR_CTRL_SPEED      = 0x04,
1588         LED_PAR_CTRL_LINK       = 0x05,
1589         LED_PAR_CTRL_TX         = 0x06,
1590         LED_PAR_CTRL_RX         = 0x07,
1591         LED_PAR_CTRL_ACT        = 0x08,
1592         LED_PAR_CTRL_LNK_RX     = 0x09,
1593         LED_PAR_CTRL_LNK_AC     = 0x0a,
1594         LED_PAR_CTRL_ACT_BL     = 0x0b,
1595         LED_PAR_CTRL_TX_BL      = 0x0c,
1596         LED_PAR_CTRL_RX_BL      = 0x0d,
1597         LED_PAR_CTRL_COL_BL     = 0x0e,
1598         LED_PAR_CTRL_INACT      = 0x0f
1599 };
1600 
1601 /*****,PHY_MARV_FE_SPEC_2               16 bit r/w      Specific Control Reg. 2 *****/
1602 enum {
1603         PHY_M_FESC_DIS_WAIT     = 1<<2, /* Disable TDR Waiting Period */
1604         PHY_M_FESC_ENA_MCLK     = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1605         PHY_M_FESC_SEL_CL_A     = 1<<0, /* Select Class A driver (100B-TX) */
1606 };
1607 
1608 
1609 /*****  PHY_MARV_PHY_CTRL (page 3)              16 bit r/w      LED Control Reg. *****/
1610 enum {
1611         PHY_M_LEDC_LOS_MSK      = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1612         PHY_M_LEDC_INIT_MSK     = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1613         PHY_M_LEDC_STA1_MSK     = 0xf<<4, /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
1614         PHY_M_LEDC_STA0_MSK     = 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
1615 };
1616 
1617 #define PHY_M_LEDC_LOS_CTRL(x)  (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1618 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1619 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1620 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1621 
1622 /* GMAC registers  */
1623 /* Port Registers */
1624 enum {
1625         GM_GP_STAT      = 0x0000,       /* 16 bit r/o   General Purpose Status */
1626         GM_GP_CTRL      = 0x0004,       /* 16 bit r/w   General Purpose Control */
1627         GM_TX_CTRL      = 0x0008,       /* 16 bit r/w   Transmit Control Reg. */
1628         GM_RX_CTRL      = 0x000c,       /* 16 bit r/w   Receive Control Reg. */
1629         GM_TX_FLOW_CTRL = 0x0010,       /* 16 bit r/w   Transmit Flow-Control */
1630         GM_TX_PARAM     = 0x0014,       /* 16 bit r/w   Transmit Parameter Reg. */
1631         GM_SERIAL_MODE  = 0x0018,       /* 16 bit r/w   Serial Mode Register */
1632 /* Source Address Registers */
1633         GM_SRC_ADDR_1L  = 0x001c,       /* 16 bit r/w   Source Address 1 (low) */
1634         GM_SRC_ADDR_1M  = 0x0020,       /* 16 bit r/w   Source Address 1 (middle) */
1635         GM_SRC_ADDR_1H  = 0x0024,       /* 16 bit r/w   Source Address 1 (high) */
1636         GM_SRC_ADDR_2L  = 0x0028,       /* 16 bit r/w   Source Address 2 (low) */
1637         GM_SRC_ADDR_2M  = 0x002c,       /* 16 bit r/w   Source Address 2 (middle) */
1638         GM_SRC_ADDR_2H  = 0x0030,       /* 16 bit r/w   Source Address 2 (high) */
1639 
1640 /* Multicast Address Hash Registers */
1641         GM_MC_ADDR_H1   = 0x0034,       /* 16 bit r/w   Multicast Address Hash 1 */
1642         GM_MC_ADDR_H2   = 0x0038,       /* 16 bit r/w   Multicast Address Hash 2 */
1643         GM_MC_ADDR_H3   = 0x003c,       /* 16 bit r/w   Multicast Address Hash 3 */
1644         GM_MC_ADDR_H4   = 0x0040,       /* 16 bit r/w   Multicast Address Hash 4 */
1645 
1646 /* Interrupt Source Registers */
1647         GM_TX_IRQ_SRC   = 0x0044,       /* 16 bit r/o   Tx Overflow IRQ Source */
1648         GM_RX_IRQ_SRC   = 0x0048,       /* 16 bit r/o   Rx Overflow IRQ Source */
1649         GM_TR_IRQ_SRC   = 0x004c,       /* 16 bit r/o   Tx/Rx Over. IRQ Source */
1650 
1651 /* Interrupt Mask Registers */
1652         GM_TX_IRQ_MSK   = 0x0050,       /* 16 bit r/w   Tx Overflow IRQ Mask */
1653         GM_RX_IRQ_MSK   = 0x0054,       /* 16 bit r/w   Rx Overflow IRQ Mask */
1654         GM_TR_IRQ_MSK   = 0x0058,       /* 16 bit r/w   Tx/Rx Over. IRQ Mask */
1655 
1656 /* Serial Management Interface (SMI) Registers */
1657         GM_SMI_CTRL     = 0x0080,       /* 16 bit r/w   SMI Control Register */
1658         GM_SMI_DATA     = 0x0084,       /* 16 bit r/w   SMI Data Register */
1659         GM_PHY_ADDR     = 0x0088,       /* 16 bit r/w   GPHY Address Register */
1660 };
1661 
1662 /* MIB Counters */
1663 #define GM_MIB_CNT_BASE 0x0100          /* Base Address of MIB Counters */
1664 #define GM_MIB_CNT_SIZE 44              /* Number of MIB Counters */
1665 
1666 /*
1667  * MIB Counters base address definitions (low word) -
1668  * use offset 4 for access to high word (32 bit r/o)
1669  */
1670 enum {
1671         GM_RXF_UC_OK  = GM_MIB_CNT_BASE + 0,    /* Unicast Frames Received OK */
1672         GM_RXF_BC_OK    = GM_MIB_CNT_BASE + 8,  /* Broadcast Frames Received OK */
1673         GM_RXF_MPAUSE   = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1674         GM_RXF_MC_OK    = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1675         GM_RXF_FCS_ERR  = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1676         /* GM_MIB_CNT_BASE + 40:        reserved */
1677         GM_RXO_OK_LO    = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1678         GM_RXO_OK_HI    = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1679         GM_RXO_ERR_LO   = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1680         GM_RXO_ERR_HI   = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1681         GM_RXF_SHT      = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1682         GM_RXE_FRAG     = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1683         GM_RXF_64B      = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1684         GM_RXF_127B     = GM_MIB_CNT_BASE + 104,        /* 65-127 Byte Rx Frame */
1685         GM_RXF_255B     = GM_MIB_CNT_BASE + 112,        /* 128-255 Byte Rx Frame */
1686         GM_RXF_511B     = GM_MIB_CNT_BASE + 120,        /* 256-511 Byte Rx Frame */
1687         GM_RXF_1023B    = GM_MIB_CNT_BASE + 128,        /* 512-1023 Byte Rx Frame */
1688         GM_RXF_1518B    = GM_MIB_CNT_BASE + 136,        /* 1024-1518 Byte Rx Frame */
1689         GM_RXF_MAX_SZ   = GM_MIB_CNT_BASE + 144,        /* 1519-MaxSize Byte Rx Frame */
1690         GM_RXF_LNG_ERR  = GM_MIB_CNT_BASE + 152,        /* Rx Frame too Long Error */
1691         GM_RXF_JAB_PKT  = GM_MIB_CNT_BASE + 160,        /* Rx Jabber Packet Frame */
1692         /* GM_MIB_CNT_BASE + 168:       reserved */
1693         GM_RXE_FIFO_OV  = GM_MIB_CNT_BASE + 176,        /* Rx FIFO overflow Event */
1694         /* GM_MIB_CNT_BASE + 184:       reserved */
1695         GM_TXF_UC_OK    = GM_MIB_CNT_BASE + 192,        /* Unicast Frames Xmitted OK */
1696         GM_TXF_BC_OK    = GM_MIB_CNT_BASE + 200,        /* Broadcast Frames Xmitted OK */
1697         GM_TXF_MPAUSE   = GM_MIB_CNT_BASE + 208,        /* Pause MAC Ctrl Frames Xmitted */
1698         GM_TXF_MC_OK    = GM_MIB_CNT_BASE + 216,        /* Multicast Frames Xmitted OK */
1699         GM_TXO_OK_LO    = GM_MIB_CNT_BASE + 224,        /* Octets Transmitted OK Low */
1700         GM_TXO_OK_HI    = GM_MIB_CNT_BASE + 232,        /* Octets Transmitted OK High */
1701         GM_TXF_64B      = GM_MIB_CNT_BASE + 240,        /* 64 Byte Tx Frame */
1702         GM_TXF_127B     = GM_MIB_CNT_BASE + 248,        /* 65-127 Byte Tx Frame */
1703         GM_TXF_255B     = GM_MIB_CNT_BASE + 256,        /* 128-255 Byte Tx Frame */
1704         GM_TXF_511B     = GM_MIB_CNT_BASE + 264,        /* 256-511 Byte Tx Frame */
1705         GM_TXF_1023B    = GM_MIB_CNT_BASE + 272,        /* 512-1023 Byte Tx Frame */
1706         GM_TXF_1518B    = GM_MIB_CNT_BASE + 280,        /* 1024-1518 Byte Tx Frame */
1707         GM_TXF_MAX_SZ   = GM_MIB_CNT_BASE + 288,        /* 1519-MaxSize Byte Tx Frame */
1708 
1709         GM_TXF_COL      = GM_MIB_CNT_BASE + 304,        /* Tx Collision */
1710         GM_TXF_LAT_COL  = GM_MIB_CNT_BASE + 312,        /* Tx Late Collision */
1711         GM_TXF_ABO_COL  = GM_MIB_CNT_BASE + 320,        /* Tx aborted due to Exces. Col. */
1712         GM_TXF_MUL_COL  = GM_MIB_CNT_BASE + 328,        /* Tx Multiple Collision */
1713         GM_TXF_SNG_COL  = GM_MIB_CNT_BASE + 336,        /* Tx Single Collision */
1714         GM_TXE_FIFO_UR  = GM_MIB_CNT_BASE + 344,        /* Tx FIFO Underrun Event */
1715 };
1716 
1717 /* GMAC Bit Definitions */
1718 /*      GM_GP_STAT      16 bit r/o      General Purpose Status Register */
1719 enum {
1720         GM_GPSR_SPEED           = 1<<15, /* Bit 15:     Port Speed (1 = 100 Mbps) */
1721         GM_GPSR_DUPLEX          = 1<<14, /* Bit 14:     Duplex Mode (1 = Full) */
1722         GM_GPSR_FC_TX_DIS       = 1<<13, /* Bit 13:     Tx Flow-Control Mode Disabled */
1723         GM_GPSR_LINK_UP         = 1<<12, /* Bit 12:     Link Up Status */
1724         GM_GPSR_PAUSE           = 1<<11, /* Bit 11:     Pause State */
1725         GM_GPSR_TX_ACTIVE       = 1<<10, /* Bit 10:     Tx in Progress */
1726         GM_GPSR_EXC_COL         = 1<<9, /* Bit  9:      Excessive Collisions Occurred */
1727         GM_GPSR_LAT_COL         = 1<<8, /* Bit  8:      Late Collisions Occurred */
1728 
1729         GM_GPSR_PHY_ST_CH       = 1<<5, /* Bit  5:      PHY Status Change */
1730         GM_GPSR_GIG_SPEED       = 1<<4, /* Bit  4:      Gigabit Speed (1 = 1000 Mbps) */
1731         GM_GPSR_PART_MODE       = 1<<3, /* Bit  3:      Partition mode */
1732         GM_GPSR_FC_RX_DIS       = 1<<2, /* Bit  2:      Rx Flow-Control Mode Disabled */
1733         GM_GPSR_PROM_EN         = 1<<1, /* Bit  1:      Promiscuous Mode Enabled */
1734 };
1735 
1736 /*      GM_GP_CTRL      16 bit r/w      General Purpose Control Register */
1737 enum {
1738         GM_GPCR_PROM_ENA        = 1<<14,        /* Bit 14:      Enable Promiscuous Mode */
1739         GM_GPCR_FC_TX_DIS       = 1<<13, /* Bit 13:     Disable Tx Flow-Control Mode */
1740         GM_GPCR_TX_ENA          = 1<<12, /* Bit 12:     Enable Transmit */
1741         GM_GPCR_RX_ENA          = 1<<11, /* Bit 11:     Enable Receive */
1742         GM_GPCR_BURST_ENA       = 1<<10, /* Bit 10:     Enable Burst Mode */
1743         GM_GPCR_LOOP_ENA        = 1<<9, /* Bit  9:      Enable MAC Loopback Mode */
1744         GM_GPCR_PART_ENA        = 1<<8, /* Bit  8:      Enable Partition Mode */
1745         GM_GPCR_GIGS_ENA        = 1<<7, /* Bit  7:      Gigabit Speed (1000 Mbps) */
1746         GM_GPCR_FL_PASS         = 1<<6, /* Bit  6:      Force Link Pass */
1747         GM_GPCR_DUP_FULL        = 1<<5, /* Bit  5:      Full Duplex Mode */
1748         GM_GPCR_FC_RX_DIS       = 1<<4, /* Bit  4:      Disable Rx Flow-Control Mode */
1749         GM_GPCR_SPEED_100       = 1<<3,   /* Bit  3:    Port Speed 100 Mbps */
1750         GM_GPCR_AU_DUP_DIS      = 1<<2, /* Bit  2:      Disable Auto-Update Duplex */
1751         GM_GPCR_AU_FCT_DIS      = 1<<1, /* Bit  1:      Disable Auto-Update Flow-C. */
1752         GM_GPCR_AU_SPD_DIS      = 1<<0, /* Bit  0:      Disable Auto-Update Speed */
1753 };
1754 
1755 #define GM_GPCR_SPEED_1000      (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1756 #define GM_GPCR_AU_ALL_DIS      (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1757 
1758 /*      GM_TX_CTRL                      16 bit r/w      Transmit Control Register */
1759 enum {
1760         GM_TXCR_FORCE_JAM       = 1<<15, /* Bit 15:     Force Jam / Flow-Control */
1761         GM_TXCR_CRC_DIS         = 1<<14, /* Bit 14:     Disable insertion of CRC */
1762         GM_TXCR_PAD_DIS         = 1<<13, /* Bit 13:     Disable padding of packets */
1763         GM_TXCR_COL_THR_MSK     = 7<<10, /* Bit 12..10: Collision Threshold */
1764 };
1765 
1766 #define TX_COL_THR(x)           (((x)<<10) & GM_TXCR_COL_THR_MSK)
1767 #define TX_COL_DEF              0x04    /* late collision after 64 byte */
1768 
1769 /*      GM_RX_CTRL                      16 bit r/w      Receive Control Register */
1770 enum {
1771         GM_RXCR_UCF_ENA = 1<<15, /* Bit 15:     Enable Unicast filtering */
1772         GM_RXCR_MCF_ENA = 1<<14, /* Bit 14:     Enable Multicast filtering */
1773         GM_RXCR_CRC_DIS = 1<<13, /* Bit 13:     Remove 4-byte CRC */
1774         GM_RXCR_PASS_FC = 1<<12, /* Bit 12:     Pass FC packets to FIFO */
1775 };
1776 
1777 /*      GM_TX_PARAM             16 bit r/w      Transmit Parameter Register */
1778 enum {
1779         GM_TXPA_JAMLEN_MSK      = 0x03<<14,     /* Bit 15..14:  Jam Length */
1780         GM_TXPA_JAMIPG_MSK      = 0x1f<<9,      /* Bit 13..9:   Jam IPG */
1781         GM_TXPA_JAMDAT_MSK      = 0x1f<<4,      /* Bit  8..4:   IPG Jam to Data */
1782 
1783         TX_JAM_LEN_DEF          = 0x03,
1784         TX_JAM_IPG_DEF          = 0x0b,
1785         TX_IPG_JAM_DEF          = 0x1c,
1786 };
1787 
1788 #define TX_JAM_LEN_VAL(x)       (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1789 #define TX_JAM_IPG_VAL(x)       (((x)<<9)  & GM_TXPA_JAMIPG_MSK)
1790 #define TX_IPG_JAM_DATA(x)      (((x)<<4)  & GM_TXPA_JAMDAT_MSK)
1791 
1792 
1793 /*      GM_SERIAL_MODE                  16 bit r/w      Serial Mode Register */
1794 enum {
1795         GM_SMOD_DATABL_MSK      = 0x1f<<11, /* Bit 15..11:      Data Blinder (r/o) */
1796         GM_SMOD_LIMIT_4         = 1<<10, /* Bit 10:     4 consecutive Tx trials */
1797         GM_SMOD_VLAN_ENA        = 1<<9, /* Bit  9:      Enable VLAN  (Max. Frame Len) */
1798         GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
1799          GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
1800 };
1801 
1802 #define DATA_BLIND_VAL(x)       (((x)<<11) & GM_SMOD_DATABL_MSK)
1803 #define DATA_BLIND_DEF          0x04
1804 
1805 #define IPG_DATA_VAL(x)         (x & GM_SMOD_IPG_MSK)
1806 #define IPG_DATA_DEF            0x1e
1807 
1808 /*      GM_SMI_CTRL                     16 bit r/w      SMI Control Register */
1809 enum {
1810         GM_SMI_CT_PHY_A_MSK     = 0x1f<<11, /* Bit 15..11:      PHY Device Address */
1811         GM_SMI_CT_REG_A_MSK     = 0x1f<<6, /* Bit 10.. 6:       PHY Register Address */
1812         GM_SMI_CT_OP_RD         = 1<<5, /* Bit  5:      OpCode Read (0=Write)*/
1813         GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
1814         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
1815 };
1816 
1817 #define GM_SMI_CT_PHY_AD(x)     (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1818 #define GM_SMI_CT_REG_AD(x)     (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1819 
1820 /*      GM_PHY_ADDR                             16 bit r/w      GPHY Address Register */
1821 enum {
1822         GM_PAR_MIB_CLR  = 1<<5, /* Bit  5:      Set MIB Clear Counter Mode */
1823         GM_PAR_MIB_TST  = 1<<4, /* Bit  4:      MIB Load Counter (Test Mode) */
1824 };
1825 
1826 /* Receive Frame Status Encoding */
1827 enum {
1828         GMR_FS_LEN      = 0xffff<<16, /* Bit 31..16:    Rx Frame Length */
1829         GMR_FS_LEN_SHIFT = 16,
1830         GMR_FS_VLAN     = 1<<13, /* Bit 13:     VLAN Packet */
1831         GMR_FS_JABBER   = 1<<12, /* Bit 12:     Jabber Packet */
1832         GMR_FS_UN_SIZE  = 1<<11, /* Bit 11:     Undersize Packet */
1833         GMR_FS_MC       = 1<<10, /* Bit 10:     Multicast Packet */
1834         GMR_FS_BC       = 1<<9, /* Bit  9:      Broadcast Packet */
1835         GMR_FS_RX_OK    = 1<<8, /* Bit  8:      Receive OK (Good Packet) */
1836         GMR_FS_GOOD_FC  = 1<<7, /* Bit  7:      Good Flow-Control Packet */
1837         GMR_FS_BAD_FC   = 1<<6, /* Bit  6:      Bad  Flow-Control Packet */
1838         GMR_FS_MII_ERR  = 1<<5, /* Bit  5:      MII Error */
1839         GMR_FS_LONG_ERR = 1<<4, /* Bit  4:      Too Long Packet */
1840         GMR_FS_FRAGMENT = 1<<3, /* Bit  3:      Fragment */
1841 
1842         GMR_FS_CRC_ERR  = 1<<1, /* Bit  1:      CRC Error */
1843         GMR_FS_RX_FF_OV = 1<<0, /* Bit  0:      Rx FIFO Overflow */
1844 
1845 /*
1846  * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1847  */
1848         GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1849                           GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1850                           GMR_FS_JABBER,
1851 /* Rx GMAC FIFO Flush Mask (default) */
1852         RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1853                            GMR_FS_BAD_FC |  GMR_FS_UN_SIZE | GMR_FS_JABBER,
1854 };
1855 
1856 /*      RX_GMF_CTRL_T   32 bit  Rx GMAC FIFO Control/Test */
1857 enum {
1858         GMF_WP_TST_ON   = 1<<14,        /* Write Pointer Test On */
1859         GMF_WP_TST_OFF  = 1<<13,        /* Write Pointer Test Off */
1860         GMF_WP_STEP     = 1<<12,        /* Write Pointer Step/Increment */
1861 
1862         GMF_RP_TST_ON   = 1<<10,        /* Read Pointer Test On */
1863         GMF_RP_TST_OFF  = 1<<9,         /* Read Pointer Test Off */
1864         GMF_RP_STEP     = 1<<8,         /* Read Pointer Step/Increment */
1865         GMF_RX_F_FL_ON  = 1<<7,         /* Rx FIFO Flush Mode On */
1866         GMF_RX_F_FL_OFF = 1<<6,         /* Rx FIFO Flush Mode Off */
1867         GMF_CLI_RX_FO   = 1<<5,         /* Clear IRQ Rx FIFO Overrun */
1868         GMF_CLI_RX_FC   = 1<<4,         /* Clear IRQ Rx Frame Complete */
1869         GMF_OPER_ON     = 1<<3,         /* Operational Mode On */
1870         GMF_OPER_OFF    = 1<<2,         /* Operational Mode Off */
1871         GMF_RST_CLR     = 1<<1,         /* Clear GMAC FIFO Reset */
1872         GMF_RST_SET     = 1<<0,         /* Set   GMAC FIFO Reset */
1873 
1874         RX_GMF_FL_THR_DEF = 0xa,        /* flush threshold (default) */
1875 };
1876 
1877 
1878 /*      TX_GMF_CTRL_T   32 bit  Tx GMAC FIFO Control/Test */
1879 enum {
1880         GMF_WSP_TST_ON  = 1<<18, /* Write Shadow Pointer Test On */
1881         GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1882         GMF_WSP_STEP    = 1<<16, /* Write Shadow Pointer Step/Increment */
1883 
1884         GMF_CLI_TX_FU   = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1885         GMF_CLI_TX_FC   = 1<<5, /* Clear IRQ Tx Frame Complete */
1886         GMF_CLI_TX_PE   = 1<<4, /* Clear IRQ Tx Parity Error */
1887 };
1888 
1889 /*      GMAC_TI_ST_CTRL  8 bit  Time Stamp Timer Ctrl Reg (YUKON only) */
1890 enum {
1891         GMT_ST_START    = 1<<2, /* Start Time Stamp Timer */
1892         GMT_ST_STOP     = 1<<1, /* Stop  Time Stamp Timer */
1893         GMT_ST_CLR_IRQ  = 1<<0, /* Clear Time Stamp Timer IRQ */
1894 };
1895 
1896 /*      GMAC_CTRL               32 bit  GMAC Control Reg (YUKON only) */
1897 enum {
1898         GMC_H_BURST_ON  = 1<<7, /* Half Duplex Burst Mode On */
1899         GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1900         GMC_F_LOOPB_ON  = 1<<5, /* FIFO Loopback On */
1901         GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1902         GMC_PAUSE_ON    = 1<<3, /* Pause On */
1903         GMC_PAUSE_OFF   = 1<<2, /* Pause Off */
1904         GMC_RST_CLR     = 1<<1, /* Clear GMAC Reset */
1905         GMC_RST_SET     = 1<<0, /* Set   GMAC Reset */
1906 };
1907 
1908 /*      GPHY_CTRL               32 bit  GPHY Control Reg (YUKON only) */
1909 enum {
1910         GPC_SEL_BDT     = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1911         GPC_INT_POL_HI  = 1<<27, /* IRQ Polarity is Active HIGH */
1912         GPC_75_OHM      = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1913         GPC_DIS_FC      = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1914         GPC_DIS_SLEEP   = 1<<24, /* Disable Energy Detect */
1915         GPC_HWCFG_M_3   = 1<<23, /* HWCFG_MODE[3] */
1916         GPC_HWCFG_M_2   = 1<<22, /* HWCFG_MODE[2] */
1917         GPC_HWCFG_M_1   = 1<<21, /* HWCFG_MODE[1] */
1918         GPC_HWCFG_M_0   = 1<<20, /* HWCFG_MODE[0] */
1919         GPC_ANEG_0      = 1<<19, /* ANEG[0] */
1920         GPC_ENA_XC      = 1<<18, /* Enable MDI crossover */
1921         GPC_DIS_125     = 1<<17, /* Disable 125 MHz clock */
1922         GPC_ANEG_3      = 1<<16, /* ANEG[3] */
1923         GPC_ANEG_2      = 1<<15, /* ANEG[2] */
1924         GPC_ANEG_1      = 1<<14, /* ANEG[1] */
1925         GPC_ENA_PAUSE   = 1<<13, /* Enable Pause (SYM_OR_REM) */
1926         GPC_PHYADDR_4   = 1<<12, /* Bit 4 of Phy Addr */
1927         GPC_PHYADDR_3   = 1<<11, /* Bit 3 of Phy Addr */
1928         GPC_PHYADDR_2   = 1<<10, /* Bit 2 of Phy Addr */
1929         GPC_PHYADDR_1   = 1<<9,  /* Bit 1 of Phy Addr */
1930         GPC_PHYADDR_0   = 1<<8,  /* Bit 0 of Phy Addr */
1931                                                 /* Bits  7..2:  reserved */
1932         GPC_RST_CLR     = 1<<1, /* Clear GPHY Reset */
1933         GPC_RST_SET     = 1<<0, /* Set   GPHY Reset */
1934 };
1935 
1936 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1937 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1938 #define GPC_ANEG_ADV_ALL_M  (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1939 
1940 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1941 #define GPC_FRC10MBIT_HALF      0
1942 #define GPC_FRC10MBIT_FULL      GPC_ANEG_0
1943 #define GPC_FRC100MBIT_HALF     GPC_ANEG_1
1944 #define GPC_FRC100MBIT_FULL     (GPC_ANEG_0 | GPC_ANEG_1)
1945 
1946 /* auto-negotiation with limited advertised speeds */
1947 /* mix only with master/slave settings (for copper) */
1948 #define GPC_ADV_1000_HALF       GPC_ANEG_2
1949 #define GPC_ADV_1000_FULL       GPC_ANEG_3
1950 #define GPC_ADV_ALL             (GPC_ANEG_2 | GPC_ANEG_3)
1951 
1952 /* master/slave settings */
1953 /* only for copper with 1000 Mbps */
1954 #define GPC_FORCE_MASTER        0
1955 #define GPC_FORCE_SLAVE         GPC_ANEG_0
1956 #define GPC_PREF_MASTER         GPC_ANEG_1
1957 #define GPC_PREF_SLAVE          (GPC_ANEG_1 | GPC_ANEG_0)
1958 
1959 /*      GMAC_IRQ_SRC     8 bit  GMAC Interrupt Source Reg (YUKON only) */
1960 /*      GMAC_IRQ_MSK     8 bit  GMAC Interrupt Mask   Reg (YUKON only) */
1961 enum {
1962         GM_IS_TX_CO_OV  = 1<<5, /* Transmit Counter Overflow IRQ */
1963         GM_IS_RX_CO_OV  = 1<<4, /* Receive Counter Overflow IRQ */
1964         GM_IS_TX_FF_UR  = 1<<3, /* Transmit FIFO Underrun */
1965         GM_IS_TX_COMPL  = 1<<2, /* Frame Transmission Complete */
1966         GM_IS_RX_FF_OR  = 1<<1, /* Receive FIFO Overrun */
1967         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
1968 
1969 #define GMAC_DEF_MSK    (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
1970 
1971 /*      GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
1972                                                 /* Bits 15.. 2: reserved */
1973         GMLC_RST_CLR    = 1<<1, /* Clear GMAC Link Reset */
1974         GMLC_RST_SET    = 1<<0, /* Set   GMAC Link Reset */
1975 
1976 
1977 /*      WOL_CTRL_STAT   16 bit  WOL Control/Status Reg */
1978         WOL_CTL_LINK_CHG_OCC            = 1<<15,
1979         WOL_CTL_MAGIC_PKT_OCC           = 1<<14,
1980         WOL_CTL_PATTERN_OCC             = 1<<13,
1981         WOL_CTL_CLEAR_RESULT            = 1<<12,
1982         WOL_CTL_ENA_PME_ON_LINK_CHG     = 1<<11,
1983         WOL_CTL_DIS_PME_ON_LINK_CHG     = 1<<10,
1984         WOL_CTL_ENA_PME_ON_MAGIC_PKT    = 1<<9,
1985         WOL_CTL_DIS_PME_ON_MAGIC_PKT    = 1<<8,
1986         WOL_CTL_ENA_PME_ON_PATTERN      = 1<<7,
1987         WOL_CTL_DIS_PME_ON_PATTERN      = 1<<6,
1988         WOL_CTL_ENA_LINK_CHG_UNIT       = 1<<5,
1989         WOL_CTL_DIS_LINK_CHG_UNIT       = 1<<4,
1990         WOL_CTL_ENA_MAGIC_PKT_UNIT      = 1<<3,
1991         WOL_CTL_DIS_MAGIC_PKT_UNIT      = 1<<2,
1992         WOL_CTL_ENA_PATTERN_UNIT        = 1<<1,
1993         WOL_CTL_DIS_PATTERN_UNIT        = 1<<0,
1994 };
1995 
1996 #define WOL_CTL_DEFAULT                         \
1997         (WOL_CTL_DIS_PME_ON_LINK_CHG |  \
1998         WOL_CTL_DIS_PME_ON_PATTERN |    \
1999         WOL_CTL_DIS_PME_ON_MAGIC_PKT |  \
2000         WOL_CTL_DIS_LINK_CHG_UNIT |             \
2001         WOL_CTL_DIS_PATTERN_UNIT |              \
2002         WOL_CTL_DIS_MAGIC_PKT_UNIT)
2003 
2004 /*      WOL_MATCH_CTL    8 bit  WOL Match Control Reg */
2005 #define WOL_CTL_PATT_ENA(x)     (1 << (x))
2006 
2007 
2008 /* XMAC II registers                                  */
2009 enum {
2010         XM_MMU_CMD      = 0x0000, /* 16 bit r/w MMU Command Register */
2011         XM_POFF         = 0x0008, /* 32 bit r/w Packet Offset Register */
2012         XM_BURST        = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2013         XM_1L_VLAN_TAG  = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2014         XM_2L_VLAN_TAG  = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2015         XM_TX_CMD       = 0x0020, /* 16 bit r/w Transmit Command Register */
2016         XM_TX_RT_LIM    = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2017         XM_TX_STIME     = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2018         XM_TX_IPG       = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2019         XM_RX_CMD       = 0x0030, /* 16 bit r/w Receive Command Register */
2020         XM_PHY_ADDR     = 0x0034, /* 16 bit r/w PHY Address Register */
2021         XM_PHY_DATA     = 0x0038, /* 16 bit r/w PHY Data Register */
2022         XM_GP_PORT      = 0x0040, /* 32 bit r/w General Purpose Port Register */
2023         XM_IMSK         = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2024         XM_ISRC         = 0x0048, /* 16 bit r/o Interrupt Status Register */
2025         XM_HW_CFG       = 0x004c, /* 16 bit r/w Hardware Config Register */
2026         XM_TX_LO_WM     = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2027         XM_TX_HI_WM     = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2028         XM_TX_THR       = 0x0064, /* 16 bit r/w Tx Request Threshold */
2029         XM_HT_THR       = 0x0066, /* 16 bit r/w Host Request Threshold */
2030         XM_PAUSE_DA     = 0x0068, /* NA reg r/w Pause Destination Address */
2031         XM_CTL_PARA     = 0x0070, /* 32 bit r/w Control Parameter Register */
2032         XM_MAC_OPCODE   = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2033         XM_MAC_PTIME    = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2034         XM_TX_STAT      = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2035 
2036         XM_EXM_START    = 0x0080, /* r/w        Start Address of the EXM Regs */
2037 #define XM_EXM(reg)     (XM_EXM_START + ((reg) << 3))
2038 };
2039 
2040 enum {
2041         XM_SRC_CHK      = 0x0100, /* NA reg r/w Source Check Address Register */
2042         XM_SA           = 0x0108, /* NA reg r/w Station Address Register */
2043         XM_HSM          = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2044         XM_RX_LO_WM     = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2045         XM_RX_HI_WM     = 0x011a, /* 16 bit r/w Receive High Water Mark */
2046         XM_RX_THR       = 0x011c, /* 32 bit r/w Receive Request Threshold */
2047         XM_DEV_ID       = 0x0120, /* 32 bit r/o Device ID Register */
2048         XM_MODE         = 0x0124, /* 32 bit r/w Mode Register */
2049         XM_LSA          = 0x0128, /* NA reg r/o Last Source Register */
2050         XM_TS_READ      = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2051         XM_TS_LOAD      = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2052         XM_STAT_CMD     = 0x0200, /* 16 bit r/w Statistics Command Register */
2053         XM_RX_CNT_EV    = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2054         XM_TX_CNT_EV    = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2055         XM_RX_EV_MSK    = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2056         XM_TX_EV_MSK    = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2057         XM_TXF_OK       = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2058         XM_TXO_OK_HI    = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2059         XM_TXO_OK_LO    = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2060         XM_TXF_BC_OK    = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2061         XM_TXF_MC_OK    = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2062         XM_TXF_UC_OK    = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2063         XM_TXF_LONG     = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2064         XM_TXE_BURST    = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2065         XM_TXF_MPAUSE   = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2066         XM_TXF_MCTRL    = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2067         XM_TXF_SNG_COL  = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2068         XM_TXF_MUL_COL  = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2069         XM_TXF_ABO_COL  = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2070         XM_TXF_LAT_COL  = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2071         XM_TXF_DEF      = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2072         XM_TXF_EX_DEF   = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2073         XM_TXE_FIFO_UR  = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2074         XM_TXE_CS_ERR   = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2075         XM_TXP_UTIL     = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2076         XM_TXF_64B      = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2077         XM_TXF_127B     = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2078         XM_TXF_255B     = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2079         XM_TXF_511B     = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2080         XM_TXF_1023B    = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2081         XM_TXF_MAX_SZ   = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2082         XM_RXF_OK       = 0x0300, /* 32 bit r/o Frames Received OK */
2083         XM_RXO_OK_HI    = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2084         XM_RXO_OK_LO    = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2085         XM_RXF_BC_OK    = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2086         XM_RXF_MC_OK    = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2087         XM_RXF_UC_OK    = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2088         XM_RXF_MPAUSE   = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2089         XM_RXF_MCTRL    = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2090         XM_RXF_INV_MP   = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2091         XM_RXF_INV_MOC  = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2092         XM_RXE_BURST    = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2093         XM_RXE_FMISS    = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2094         XM_RXF_FRA_ERR  = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2095         XM_RXE_FIFO_OV  = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2096         XM_RXF_JAB_PKT  = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2097         XM_RXE_CAR_ERR  = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2098         XM_RXF_LEN_ERR  = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2099         XM_RXE_SYM_ERR  = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2100         XM_RXE_SHT_ERR  = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2101         XM_RXE_RUNT     = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2102         XM_RXF_LNG_ERR  = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2103         XM_RXF_FCS_ERR  = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2104         XM_RXF_CEX_ERR  = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2105         XM_RXP_UTIL     = 0x0360, /* 32 bit r/o Rx Utilization in % */
2106         XM_RXF_64B      = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2107         XM_RXF_127B     = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2108         XM_RXF_255B     = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2109         XM_RXF_511B     = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2110         XM_RXF_1023B    = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2111         XM_RXF_MAX_SZ   = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2112 };
2113 
2114 /*      XM_MMU_CMD      16 bit r/w      MMU Command Register */
2115 enum {
2116         XM_MMU_PHY_RDY  = 1<<12, /* Bit 12:     PHY Read Ready */
2117         XM_MMU_PHY_BUSY = 1<<11, /* Bit 11:     PHY Busy */
2118         XM_MMU_IGN_PF   = 1<<10, /* Bit 10:     Ignore Pause Frame */
2119         XM_MMU_MAC_LB   = 1<<9,  /* Bit  9:     Enable MAC Loopback */
2120         XM_MMU_FRC_COL  = 1<<7,  /* Bit  7:     Force Collision */
2121         XM_MMU_SIM_COL  = 1<<6,  /* Bit  6:     Simulate Collision */
2122         XM_MMU_NO_PRE   = 1<<5,  /* Bit  5:     No MDIO Preamble */
2123         XM_MMU_GMII_FD  = 1<<4,  /* Bit  4:     GMII uses Full Duplex */
2124         XM_MMU_RAT_CTRL = 1<<3,  /* Bit  3:     Enable Rate Control */
2125         XM_MMU_GMII_LOOP= 1<<2,  /* Bit  2:     PHY is in Loopback Mode */
2126         XM_MMU_ENA_RX   = 1<<1,  /* Bit  1:     Enable Receiver */
2127         XM_MMU_ENA_TX   = 1<<0,  /* Bit  0:     Enable Transmitter */
2128 };
2129 
2130 
2131 /*      XM_TX_CMD       16 bit r/w      Transmit Command Register */
2132 enum {
2133         XM_TX_BK2BK     = 1<<6, /* Bit  6:      Ignor Carrier Sense (Tx Bk2Bk)*/
2134         XM_TX_ENC_BYP   = 1<<5, /* Bit  5:      Set Encoder in Bypass Mode */
2135         XM_TX_SAM_LINE  = 1<<4, /* Bit  4: (sc) Start utilization calculation */
2136         XM_TX_NO_GIG_MD = 1<<3, /* Bit  3:      Disable Carrier Extension */
2137         XM_TX_NO_PRE    = 1<<2, /* Bit  2:      Disable Preamble Generation */
2138         XM_TX_NO_CRC    = 1<<1, /* Bit  1:      Disable CRC Generation */
2139         XM_TX_AUTO_PAD  = 1<<0, /* Bit  0:      Enable Automatic Padding */
2140 };
2141 
2142 /*      XM_TX_RT_LIM    16 bit r/w      Transmit Retry Limit Register */
2143 #define XM_RT_LIM_MSK   0x1f    /* Bit  4..0:   Tx Retry Limit */
2144 
2145 
2146 /*      XM_TX_STIME     16 bit r/w      Transmit Slottime Register */
2147 #define XM_STIME_MSK    0x7f    /* Bit  6..0:   Tx Slottime bits */
2148 
2149 
2150 /*      XM_TX_IPG       16 bit r/w      Transmit Inter Packet Gap */
2151 #define XM_IPG_MSK              0xff    /* Bit  7..0:   IPG value bits */
2152 
2153 
2154 /*      XM_RX_CMD       16 bit r/w      Receive Command Register */
2155 enum {
2156         XM_RX_LENERR_OK = 1<<8, /* Bit  8       don't set Rx Err bit for */
2157                                 /*              inrange error packets */
2158         XM_RX_BIG_PK_OK = 1<<7, /* Bit  7       don't set Rx Err bit for */
2159                                 /*              jumbo packets */
2160         XM_RX_IPG_CAP   = 1<<6, /* Bit  6       repl. type field with IPG */
2161         XM_RX_TP_MD     = 1<<5, /* Bit  5:      Enable transparent Mode */
2162         XM_RX_STRIP_FCS = 1<<4, /* Bit  4:      Enable FCS Stripping */
2163         XM_RX_SELF_RX   = 1<<3, /* Bit  3:      Enable Rx of own packets */
2164         XM_RX_SAM_LINE  = 1<<2, /* Bit  2: (sc) Start utilization calculation */
2165         XM_RX_STRIP_PAD = 1<<1, /* Bit  1:      Strip pad bytes of Rx frames */
2166         XM_RX_DIS_CEXT  = 1<<0, /* Bit  0:      Disable carrier ext. check */
2167 };
2168 
2169 
2170 /*      XM_GP_PORT      32 bit r/w      General Purpose Port Register */
2171 enum {
2172         XM_GP_ANIP      = 1<<6, /* Bit  6: (ro) Auto-Neg. in progress */
2173         XM_GP_FRC_INT   = 1<<5, /* Bit  5: (sc) Force Interrupt */
2174         XM_GP_RES_MAC   = 1<<3, /* Bit  3: (sc) Reset MAC and FIFOs */
2175         XM_GP_RES_STAT  = 1<<2, /* Bit  2: (sc) Reset the statistics module */
2176         XM_GP_INP_ASS   = 1<<0, /* Bit  0: (ro) GP Input Pin asserted */
2177 };
2178 
2179 
2180 /*      XM_IMSK         16 bit r/w      Interrupt Mask Register */
2181 /*      XM_ISRC         16 bit r/o      Interrupt Status Register */
2182 enum {
2183         XM_IS_LNK_AE    = 1<<14, /* Bit 14:     Link Asynchronous Event */
2184         XM_IS_TX_ABORT  = 1<<13, /* Bit 13:     Transmit Abort, late Col. etc */
2185         XM_IS_FRC_INT   = 1<<12, /* Bit 12:     Force INT bit set in GP */
2186         XM_IS_INP_ASS   = 1<<11, /* Bit 11:     Input Asserted, GP bit 0 set */
2187         XM_IS_LIPA_RC   = 1<<10, /* Bit 10:     Link Partner requests config */
2188         XM_IS_RX_PAGE   = 1<<9, /* Bit  9:      Page Received */
2189         XM_IS_TX_PAGE   = 1<<8, /* Bit  8:      Next Page Loaded for Transmit */
2190         XM_IS_AND       = 1<<7, /* Bit  7:      Auto-Negotiation Done */
2191         XM_IS_TSC_OV    = 1<<6, /* Bit  6:      Time Stamp Counter Overflow */
2192         XM_IS_RXC_OV    = 1<<5, /* Bit  5:      Rx Counter Event Overflow */
2193         XM_IS_TXC_OV    = 1<<4, /* Bit  4:      Tx Counter Event Overflow */
2194         XM_IS_RXF_OV    = 1<<3, /* Bit  3:      Receive FIFO Overflow */
2195         XM_IS_TXF_UR    = 1<<2, /* Bit  2:      Transmit FIFO Underrun */
2196         XM_IS_TX_COMP   = 1<<1, /* Bit  1:      Frame Tx Complete */
2197         XM_IS_RX_COMP   = 1<<0, /* Bit  0:      Frame Rx Complete */
2198 
2199         XM_IMSK_DISABLE = 0xffff,
2200 };
2201 
2202 /*      XM_HW_CFG       16 bit r/w      Hardware Config Register */
2203 enum {
2204         XM_HW_GEN_EOP   = 1<<3, /* Bit  3:      generate End of Packet pulse */
2205         XM_HW_COM4SIG   = 1<<2, /* Bit  2:      use Comma Detect for Sig. Det.*/
2206         XM_HW_GMII_MD   = 1<<0, /* Bit  0:      GMII Interface selected */
2207 };
2208 
2209 
2210 /*      XM_TX_LO_WM     16 bit r/w      Tx FIFO Low Water Mark */
2211 /*      XM_TX_HI_WM     16 bit r/w      Tx FIFO High Water Mark */
2212 #define XM_TX_WM_MSK    0x01ff  /* Bit  9.. 0   Tx FIFO Watermark bits */
2213 
2214 /*      XM_TX_THR       16 bit r/w      Tx Request Threshold */
2215 /*      XM_HT_THR       16 bit r/w      Host Request Threshold */
2216 /*      XM_RX_THR       16 bit r/w      Rx Request Threshold */
2217 #define XM_THR_MSK              0x03ff  /* Bit 10.. 0   Rx/Tx Request Threshold bits */
2218 
2219 
2220 /*      XM_TX_STAT      32 bit r/o      Tx Status LIFO Register */
2221 enum {
2222         XM_ST_VALID     = (1UL<<31),    /* Bit 31:      Status Valid */
2223         XM_ST_BYTE_CNT  = (0x3fffL<<17),        /* Bit 30..17:  Tx frame Length */
2224         XM_ST_RETRY_CNT = (0x1fL<<12),  /* Bit 16..12:  Retry Count */
2225         XM_ST_EX_COL    = 1<<11,        /* Bit 11:      Excessive Collisions */
2226         XM_ST_EX_DEF    = 1<<10,        /* Bit 10:      Excessive Deferral */
2227         XM_ST_BURST     = 1<<9,         /* Bit  9:      p. xmitted in burst md*/
2228         XM_ST_DEFER     = 1<<8,         /* Bit  8:      packet was defered */
2229         XM_ST_BC        = 1<<7,         /* Bit  7:      Broadcast packet */
2230         XM_ST_MC        = 1<<6,         /* Bit  6:      Multicast packet */
2231         XM_ST_UC        = 1<<5,         /* Bit  5:      Unicast packet */
2232         XM_ST_TX_UR     = 1<<4,         /* Bit  4:      FIFO Underrun occurred */
2233         XM_ST_CS_ERR    = 1<<3,         /* Bit  3:      Carrier Sense Error */
2234         XM_ST_LAT_COL   = 1<<2,         /* Bit  2:      Late Collision Error */
2235         XM_ST_MUL_COL   = 1<<1,         /* Bit  1:      Multiple Collisions */
2236         XM_ST_SGN_COL   = 1<<0,         /* Bit  0:      Single Collision */
2237 };
2238 
2239 /*      XM_RX_LO_WM     16 bit r/w      Receive Low Water Mark */
2240 /*      XM_RX_HI_WM     16 bit r/w      Receive High Water Mark */
2241 #define XM_RX_WM_MSK    0x03ff          /* Bit 11.. 0:  Rx FIFO Watermark bits */
2242 
2243 
2244 /*      XM_DEV_ID       32 bit r/o      Device ID Register */
2245 #define XM_DEV_OUI      (0x00ffffffUL<<8)       /* Bit 31..8:   Device OUI */
2246 #define XM_DEV_REV      (0x07L << 5)            /* Bit  7..5:   Chip Rev Num */
2247 
2248 
2249 /*      XM_MODE         32 bit r/w      Mode Register */
2250 enum {
2251         XM_MD_ENA_REJ   = 1<<26, /* Bit 26:     Enable Frame Reject */
2252         XM_MD_SPOE_E    = 1<<25, /* Bit 25:     Send Pause on Edge */
2253                                                                         /*              extern generated */
2254         XM_MD_TX_REP    = 1<<24, /* Bit 24:     Transmit Repeater Mode */
2255         XM_MD_SPOFF_I   = 1<<23, /* Bit 23:     Send Pause on FIFO full */
2256                                                                         /*              intern generated */
2257         XM_MD_LE_STW    = 1<<22, /* Bit 22:     Rx Stat Word in Little Endian */
2258         XM_MD_TX_CONT   = 1<<21, /* Bit 21:     Send Continuous */
2259         XM_MD_TX_PAUSE  = 1<<20, /* Bit 20: (sc)        Send Pause Frame */
2260         XM_MD_ATS       = 1<<19, /* Bit 19:     Append Time Stamp */
2261         XM_MD_SPOL_I    = 1<<18, /* Bit 18:     Send Pause on Low */
2262                                                                         /*              intern generated */
2263         XM_MD_SPOH_I    = 1<<17, /* Bit 17:     Send Pause on High */
2264                                                                         /*              intern generated */
2265         XM_MD_CAP       = 1<<16, /* Bit 16:     Check Address Pair */
2266         XM_MD_ENA_HASH  = 1<<15, /* Bit 15:     Enable Hashing */
2267         XM_MD_CSA       = 1<<14, /* Bit 14:     Check Station Address */
2268         XM_MD_CAA       = 1<<13, /* Bit 13:     Check Address Array */
2269         XM_MD_RX_MCTRL  = 1<<12, /* Bit 12:     Rx MAC Control Frame */
2270         XM_MD_RX_RUNT   = 1<<11, /* Bit 11:     Rx Runt Frames */
2271         XM_MD_RX_IRLE   = 1<<10, /* Bit 10:     Rx in Range Len Err Frame */
2272         XM_MD_RX_LONG   = 1<<9,  /* Bit  9:     Rx Long Frame */
2273         XM_MD_RX_CRCE   = 1<<8,  /* Bit  8:     Rx CRC Error Frame */
2274         XM_MD_RX_ERR    = 1<<7,  /* Bit  7:     Rx Error Frame */
2275         XM_MD_DIS_UC    = 1<<6,  /* Bit  6:     Disable Rx Unicast */
2276         XM_MD_DIS_MC    = 1<<5,  /* Bit  5:     Disable Rx Multicast */
2277         XM_MD_DIS_BC    = 1<<4,  /* Bit  4:     Disable Rx Broadcast */
2278         XM_MD_ENA_PROM  = 1<<3,  /* Bit  3:     Enable Promiscuous */
2279         XM_MD_ENA_BE    = 1<<2,  /* Bit  2:     Enable Big Endian */
2280         XM_MD_FTF       = 1<<1,  /* Bit  1: (sc)        Flush Tx FIFO */
2281         XM_MD_FRF       = 1<<0,  /* Bit  0: (sc)        Flush Rx FIFO */
2282 };
2283 
2284 #define XM_PAUSE_MODE   (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2285 #define XM_DEF_MODE     (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2286                          XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2287 
2288 /*      XM_STAT_CMD     16 bit r/w      Statistics Command Register */
2289 enum {
2290         XM_SC_SNP_RXC   = 1<<5, /* Bit  5: (sc) Snap Rx Counters */
2291         XM_SC_SNP_TXC   = 1<<4, /* Bit  4: (sc) Snap Tx Counters */
2292         XM_SC_CP_RXC    = 1<<3, /* Bit  3:      Copy Rx Counters Continuously */
2293         XM_SC_CP_TXC    = 1<<2, /* Bit  2:      Copy Tx Counters Continuously */
2294         XM_SC_CLR_RXC   = 1<<1, /* Bit  1: (sc) Clear Rx Counters */
2295         XM_SC_CLR_TXC   = 1<<0, /* Bit  0: (sc) Clear Tx Counters */
2296 };
2297 
2298 
2299 /*      XM_RX_CNT_EV    32 bit r/o      Rx Counter Event Register */
2300 /*      XM_RX_EV_MSK    32 bit r/w      Rx Counter Event Mask */
2301 enum {
2302         XMR_MAX_SZ_OV   = 1<<31, /* Bit 31:     1024-MaxSize Rx Cnt Ov*/
2303         XMR_1023B_OV    = 1<<30, /* Bit 30:     512-1023Byte Rx Cnt Ov*/
2304         XMR_511B_OV     = 1<<29, /* Bit 29:     256-511 Byte Rx Cnt Ov*/
2305         XMR_255B_OV     = 1<<28, /* Bit 28:     128-255 Byte Rx Cnt Ov*/
2306         XMR_127B_OV     = 1<<27, /* Bit 27:     65-127 Byte Rx Cnt Ov */
2307         XMR_64B_OV      = 1<<26, /* Bit 26:     64 Byte Rx Cnt Ov */
2308         XMR_UTIL_OV     = 1<<25, /* Bit 25:     Rx Util Cnt Overflow */
2309         XMR_UTIL_UR     = 1<<24, /* Bit 24:     Rx Util Cnt Underrun */
2310         XMR_CEX_ERR_OV  = 1<<23, /* Bit 23:     CEXT Err Cnt Ov */
2311         XMR_FCS_ERR_OV  = 1<<21, /* Bit 21:     Rx FCS Error Cnt Ov */
2312         XMR_LNG_ERR_OV  = 1<<20, /* Bit 20:     Rx too Long Err Cnt Ov*/
2313         XMR_RUNT_OV     = 1<<19, /* Bit 19:     Runt Event Cnt Ov */
2314         XMR_SHT_ERR_OV  = 1<<18, /* Bit 18:     Rx Short Ev Err Cnt Ov*/
2315         XMR_SYM_ERR_OV  = 1<<17, /* Bit 17:     Rx Sym Err Cnt Ov */
2316         XMR_CAR_ERR_OV  = 1<<15, /* Bit 15:     Rx Carr Ev Err Cnt Ov */
2317         XMR_JAB_PKT_OV  = 1<<14, /* Bit 14:     Rx Jabb Packet Cnt Ov */
2318         XMR_FIFO_OV     = 1<<13, /* Bit 13:     Rx FIFO Ov Ev Cnt Ov */
2319         XMR_FRA_ERR_OV  = 1<<12, /* Bit 12:     Rx Framing Err Cnt Ov */
2320         XMR_FMISS_OV    = 1<<11, /* Bit 11:     Rx Missed Ev Cnt Ov */
2321         XMR_BURST       = 1<<10, /* Bit 10:     Rx Burst Event Cnt Ov */
2322         XMR_INV_MOC     = 1<<9,  /* Bit  9:     Rx with inv. MAC OC Ov*/
2323         XMR_INV_MP      = 1<<8,  /* Bit  8:     Rx inv Pause Frame Ov */
2324         XMR_MCTRL_OV    = 1<<7,  /* Bit  7:     Rx MAC Ctrl-F Cnt Ov */
2325         XMR_MPAUSE_OV   = 1<<6,  /* Bit  6:     Rx Pause MAC Ctrl-F Ov*/
2326         XMR_UC_OK_OV    = 1<<5,  /* Bit  5:     Rx Unicast Frame CntOv*/
2327         XMR_MC_OK_OV    = 1<<4,  /* Bit  4:     Rx Multicast Cnt Ov */
2328         XMR_BC_OK_OV    = 1<<3,  /* Bit  3:     Rx Broadcast Cnt Ov */
2329         XMR_OK_LO_OV    = 1<<2,  /* Bit  2:     Octets Rx OK Low CntOv*/
2330         XMR_OK_HI_OV    = 1<<1,  /* Bit  1:     Octets Rx OK Hi Cnt Ov*/
2331         XMR_OK_OV       = 1<<0,  /* Bit  0:     Frames Received Ok Ov */
2332 };
2333 
2334 #define XMR_DEF_MSK             (XMR_OK_LO_OV | XMR_OK_HI_OV)
2335 
2336 /*      XM_TX_CNT_EV    32 bit r/o      Tx Counter Event Register */
2337 /*      XM_TX_EV_MSK    32 bit r/w      Tx Counter Event Mask */
2338 enum {
2339         XMT_MAX_SZ_OV   = 1<<25,        /* Bit 25:      1024-MaxSize Tx Cnt Ov*/
2340         XMT_1023B_OV    = 1<<24,        /* Bit 24:      512-1023Byte Tx Cnt Ov*/
2341         XMT_511B_OV     = 1<<23,        /* Bit 23:      256-511 Byte Tx Cnt Ov*/
2342         XMT_255B_OV     = 1<<22,        /* Bit 22:      128-255 Byte Tx Cnt Ov*/
2343         XMT_127B_OV     = 1<<21,        /* Bit 21:      65-127 Byte Tx Cnt Ov */
2344         XMT_64B_OV      = 1<<20,        /* Bit 20:      64 Byte Tx Cnt Ov */
2345         XMT_UTIL_OV     = 1<<19,        /* Bit 19:      Tx Util Cnt Overflow */
2346         XMT_UTIL_UR     = 1<<18,        /* Bit 18:      Tx Util Cnt Underrun */
2347         XMT_CS_ERR_OV   = 1<<17,        /* Bit 17:      Tx Carr Sen Err Cnt Ov*/
2348         XMT_FIFO_UR_OV  = 1<<16,        /* Bit 16:      Tx FIFO Ur Ev Cnt Ov */
2349         XMT_EX_DEF_OV   = 1<<15,        /* Bit 15:      Tx Ex Deferall Cnt Ov */
2350         XMT_DEF = 1<<14,        /* Bit 14:      Tx Deferred Cnt Ov */
2351         XMT_LAT_COL_OV  = 1<<13,        /* Bit 13:      Tx Late Col Cnt Ov */
2352         XMT_ABO_COL_OV  = 1<<12,        /* Bit 12:      Tx abo dueto Ex Col Ov*/
2353         XMT_MUL_COL_OV  = 1<<11,        /* Bit 11:      Tx Mult Col Cnt Ov */
2354         XMT_SNG_COL     = 1<<10,        /* Bit 10:      Tx Single Col Cnt Ov */
2355         XMT_MCTRL_OV    = 1<<9,         /* Bit  9:      Tx MAC Ctrl Counter Ov*/
2356         XMT_MPAUSE      = 1<<8,         /* Bit  8:      Tx Pause MAC Ctrl-F Ov*/
2357         XMT_BURST       = 1<<7,         /* Bit  7:      Tx Burst Event Cnt Ov */
2358         XMT_LONG        = 1<<6,         /* Bit  6:      Tx Long Frame Cnt Ov */
2359         XMT_UC_OK_OV    = 1<<5,         /* Bit  5:      Tx Unicast Cnt Ov */
2360         XMT_MC_OK_OV    = 1<<4,         /* Bit  4:      Tx Multicast Cnt Ov */
2361         XMT_BC_OK_OV    = 1<<3,         /* Bit  3:      Tx Broadcast Cnt Ov */
2362         XMT_OK_LO_OV    = 1<<2,         /* Bit  2:      Octets Tx OK Low CntOv*/
2363         XMT_OK_HI_OV    = 1<<1,         /* Bit  1:      Octets Tx OK Hi Cnt Ov*/
2364         XMT_OK_OV       = 1<<0,         /* Bit  0:      Frames Tx Ok Ov */
2365 };
2366 
2367 #define XMT_DEF_MSK             (XMT_OK_LO_OV | XMT_OK_HI_OV)
2368 
2369 struct skge_rx_desc {
2370         u32             control;
2371         u32             next_offset;
2372         u32             dma_lo;
2373         u32             dma_hi;
2374         u32             status;
2375         u32             timestamp;
2376         u16             csum2;
2377         u16             csum1;
2378         u16             csum2_start;
2379         u16             csum1_start;
2380 };
2381 
2382 struct skge_tx_desc {
2383         u32             control;
2384         u32             next_offset;
2385         u32             dma_lo;
2386         u32             dma_hi;
2387         u32             status;
2388         u32             csum_offs;
2389         u16             csum_write;
2390         u16             csum_start;
2391         u32             rsvd;
2392 };
2393 
2394 struct skge_element {
2395         struct skge_element     *next;
2396         void                    *desc;
2397         struct sk_buff          *skb;
2398         DEFINE_DMA_UNMAP_ADDR(mapaddr);
2399         DEFINE_DMA_UNMAP_LEN(maplen);
2400 };
2401 
2402 struct skge_ring {
2403         struct skge_element *to_clean;
2404         struct skge_element *to_use;
2405         struct skge_element *start;
2406         unsigned long       count;
2407 };
2408 
2409 
2410 struct skge_hw {
2411         void __iomem         *regs;
2412         struct pci_dev       *pdev;
2413         spinlock_t           hw_lock;
2414         u32                  intr_mask;
2415         struct net_device    *dev[2];
2416 
2417         u8                   chip_id;
2418         u8                   chip_rev;
2419         u8                   copper;
2420         u8                   ports;
2421         u8                   phy_type;
2422 
2423         u32                  ram_size;
2424         u32                  ram_offset;
2425         u16                  phy_addr;
2426         spinlock_t           phy_lock;
2427         struct tasklet_struct phy_task;
2428 
2429         char                 irq_name[0]; /* skge@pci:000:04:00.0 */
2430 };
2431 
2432 enum pause_control {
2433         FLOW_MODE_NONE          = 1, /* No Flow-Control */
2434         FLOW_MODE_LOC_SEND      = 2, /* Local station sends PAUSE */
2435         FLOW_MODE_SYMMETRIC     = 3, /* Both stations may send PAUSE */
2436         FLOW_MODE_SYM_OR_REM    = 4, /* Both stations may send PAUSE or
2437                                       * just the remote station may send PAUSE
2438                                       */
2439 };
2440 
2441 enum pause_status {
2442         FLOW_STAT_INDETERMINATED=0,     /* indeterminated */
2443         FLOW_STAT_NONE,                 /* No Flow Control */
2444         FLOW_STAT_REM_SEND,             /* Remote Station sends PAUSE */
2445         FLOW_STAT_LOC_SEND,             /* Local station sends PAUSE */
2446         FLOW_STAT_SYMMETRIC,            /* Both station may send PAUSE */
2447 };
2448 
2449 
2450 struct skge_port {
2451         struct skge_hw       *hw;
2452         struct net_device    *netdev;
2453         struct napi_struct   napi;
2454         int                  port;
2455         u32                  msg_enable;
2456 
2457         struct skge_ring     tx_ring;
2458 
2459         struct skge_ring     rx_ring ____cacheline_aligned_in_smp;
2460         unsigned int         rx_buf_size;
2461 
2462         struct timer_list    link_timer;
2463         enum pause_control   flow_control;
2464         enum pause_status    flow_status;
2465         u8                   blink_on;
2466         u8                   wol;
2467         u8                   autoneg;   /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2468         u8                   duplex;    /* DUPLEX_HALF, DUPLEX_FULL */
2469         u16                  speed;     /* SPEED_1000, SPEED_100, ... */
2470         u32                  advertising;
2471 
2472         void                 *mem;      /* PCI memory for rings */
2473         dma_addr_t           dma;
2474         unsigned long        mem_size;
2475 #ifdef CONFIG_SKGE_DEBUG
2476         struct dentry        *debugfs;
2477 #endif
2478 };
2479 
2480 
2481 /* Register accessor for memory mapped device */
2482 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2483 {
2484         return readl(hw->regs + reg);
2485 }
2486 
2487 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2488 {
2489         return readw(hw->regs + reg);
2490 }
2491 
2492 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2493 {
2494         return readb(hw->regs + reg);
2495 }
2496 
2497 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2498 {
2499         writel(val, hw->regs + reg);
2500 }
2501 
2502 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2503 {
2504         writew(val, hw->regs + reg);
2505 }
2506 
2507 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2508 {
2509         writeb(val, hw->regs + reg);
2510 }
2511 
2512 /* MAC Related Registers inside the device. */
2513 #define SK_REG(port,reg)        (((port)<<7)+(u16)(reg))
2514 #define SK_XMAC_REG(port, reg) \
2515         ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2516 
2517 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2518 {
2519         u32 v;
2520         v = skge_read16(hw, SK_XMAC_REG(port, reg));
2521         v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2522         return v;
2523 }
2524 
2525 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2526 {
2527         return skge_read16(hw, SK_XMAC_REG(port,reg));
2528 }
2529 
2530 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2531 {
2532         skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2533         skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2534 }
2535 
2536 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2537 {
2538         skge_write16(hw, SK_XMAC_REG(port,r), v);
2539 }
2540 
2541 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2542                                    const u8 *hash)
2543 {
2544         xm_write16(hw, port, reg,   (u16)hash[0] | ((u16)hash[1] << 8));
2545         xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2546         xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2547         xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2548 }
2549 
2550 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2551                                    const u8 *addr)
2552 {
2553         xm_write16(hw, port, reg,   (u16)addr[0] | ((u16)addr[1] << 8));
2554         xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2555         xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2556 }
2557 
2558 #define SK_GMAC_REG(port,reg) \
2559         (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2560 
2561 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2562 {
2563         return skge_read16(hw, SK_GMAC_REG(port,reg));
2564 }
2565 
2566 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2567 {
2568         return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2569                 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2570 }
2571 
2572 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2573 {
2574         skge_write16(hw, SK_GMAC_REG(port,r), v);
2575 }
2576 
2577 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2578                                     const u8 *addr)
2579 {
2580         gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
2581         gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2582         gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2583 }
2584 
2585 #endif

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