root/drivers/net/ethernet/marvell/octeontx2/af/npc.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*  Marvell OcteonTx2 RVU Admin Function driver
   3  *
   4  * Copyright (C) 2018 Marvell International Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 
  11 #ifndef NPC_H
  12 #define NPC_H
  13 
  14 enum NPC_LID_E {
  15         NPC_LID_LA = 0,
  16         NPC_LID_LB,
  17         NPC_LID_LC,
  18         NPC_LID_LD,
  19         NPC_LID_LE,
  20         NPC_LID_LF,
  21         NPC_LID_LG,
  22         NPC_LID_LH,
  23 };
  24 
  25 #define NPC_LT_NA 0
  26 
  27 enum npc_kpu_la_ltype {
  28         NPC_LT_LA_8023 = 1,
  29         NPC_LT_LA_ETHER,
  30 };
  31 
  32 enum npc_kpu_lb_ltype {
  33         NPC_LT_LB_ETAG = 1,
  34         NPC_LT_LB_CTAG,
  35         NPC_LT_LB_STAG,
  36         NPC_LT_LB_BTAG,
  37         NPC_LT_LB_QINQ,
  38         NPC_LT_LB_ITAG,
  39 };
  40 
  41 enum npc_kpu_lc_ltype {
  42         NPC_LT_LC_IP = 1,
  43         NPC_LT_LC_IP6,
  44         NPC_LT_LC_ARP,
  45         NPC_LT_LC_RARP,
  46         NPC_LT_LC_MPLS,
  47         NPC_LT_LC_NSH,
  48         NPC_LT_LC_PTP,
  49         NPC_LT_LC_FCOE,
  50 };
  51 
  52 /* Don't modify Ltypes upto SCTP, otherwise it will
  53  * effect flow tag calculation and thus RSS.
  54  */
  55 enum npc_kpu_ld_ltype {
  56         NPC_LT_LD_TCP = 1,
  57         NPC_LT_LD_UDP,
  58         NPC_LT_LD_ICMP,
  59         NPC_LT_LD_SCTP,
  60         NPC_LT_LD_IGMP,
  61         NPC_LT_LD_ICMP6,
  62         NPC_LT_LD_ESP,
  63         NPC_LT_LD_AH,
  64         NPC_LT_LD_GRE,
  65         NPC_LT_LD_GRE_MPLS,
  66         NPC_LT_LD_GRE_NSH,
  67         NPC_LT_LD_TU_MPLS,
  68 };
  69 
  70 enum npc_kpu_le_ltype {
  71         NPC_LT_LE_TU_ETHER = 1,
  72         NPC_LT_LE_TU_PPP,
  73         NPC_LT_LE_TU_MPLS_IN_NSH,
  74         NPC_LT_LE_TU_3RD_NSH,
  75 };
  76 
  77 enum npc_kpu_lf_ltype {
  78         NPC_LT_LF_TU_IP = 1,
  79         NPC_LT_LF_TU_IP6,
  80         NPC_LT_LF_TU_ARP,
  81         NPC_LT_LF_TU_MPLS_IP,
  82         NPC_LT_LF_TU_MPLS_IP6,
  83         NPC_LT_LF_TU_MPLS_ETHER,
  84 };
  85 
  86 enum npc_kpu_lg_ltype {
  87         NPC_LT_LG_TU_TCP = 1,
  88         NPC_LT_LG_TU_UDP,
  89         NPC_LT_LG_TU_SCTP,
  90         NPC_LT_LG_TU_ICMP,
  91         NPC_LT_LG_TU_IGMP,
  92         NPC_LT_LG_TU_ICMP6,
  93         NPC_LT_LG_TU_ESP,
  94         NPC_LT_LG_TU_AH,
  95 };
  96 
  97 enum npc_kpu_lh_ltype {
  98         NPC_LT_LH_TCP_DATA = 1,
  99         NPC_LT_LH_HTTP_DATA,
 100         NPC_LT_LH_HTTPS_DATA,
 101         NPC_LT_LH_PPTP_DATA,
 102         NPC_LT_LH_UDP_DATA,
 103 };
 104 
 105 struct npc_kpu_profile_cam {
 106         u8 state;
 107         u8 state_mask;
 108         u16 dp0;
 109         u16 dp0_mask;
 110         u16 dp1;
 111         u16 dp1_mask;
 112         u16 dp2;
 113         u16 dp2_mask;
 114 };
 115 
 116 struct npc_kpu_profile_action {
 117         u8 errlev;
 118         u8 errcode;
 119         u8 dp0_offset;
 120         u8 dp1_offset;
 121         u8 dp2_offset;
 122         u8 bypass_count;
 123         u8 parse_done;
 124         u8 next_state;
 125         u8 ptr_advance;
 126         u8 cap_ena;
 127         u8 lid;
 128         u8 ltype;
 129         u8 flags;
 130         u8 offset;
 131         u8 mask;
 132         u8 right;
 133         u8 shift;
 134 };
 135 
 136 struct npc_kpu_profile {
 137         int cam_entries;
 138         int action_entries;
 139         struct npc_kpu_profile_cam *cam;
 140         struct npc_kpu_profile_action *action;
 141 };
 142 
 143 /* NPC KPU register formats */
 144 struct npc_kpu_cam {
 145 #if defined(__BIG_ENDIAN_BITFIELD)
 146         u64 rsvd_63_56     : 8;
 147         u64 state          : 8;
 148         u64 dp2_data       : 16;
 149         u64 dp1_data       : 16;
 150         u64 dp0_data       : 16;
 151 #else
 152         u64 dp0_data       : 16;
 153         u64 dp1_data       : 16;
 154         u64 dp2_data       : 16;
 155         u64 state          : 8;
 156         u64 rsvd_63_56     : 8;
 157 #endif
 158 };
 159 
 160 struct npc_kpu_action0 {
 161 #if defined(__BIG_ENDIAN_BITFIELD)
 162         u64 rsvd_63_57     : 7;
 163         u64 byp_count      : 3;
 164         u64 capture_ena    : 1;
 165         u64 parse_done     : 1;
 166         u64 next_state     : 8;
 167         u64 rsvd_43        : 1;
 168         u64 capture_lid    : 3;
 169         u64 capture_ltype  : 4;
 170         u64 capture_flags  : 8;
 171         u64 ptr_advance    : 8;
 172         u64 var_len_offset : 8;
 173         u64 var_len_mask   : 8;
 174         u64 var_len_right  : 1;
 175         u64 var_len_shift  : 3;
 176 #else
 177         u64 var_len_shift  : 3;
 178         u64 var_len_right  : 1;
 179         u64 var_len_mask   : 8;
 180         u64 var_len_offset : 8;
 181         u64 ptr_advance    : 8;
 182         u64 capture_flags  : 8;
 183         u64 capture_ltype  : 4;
 184         u64 capture_lid    : 3;
 185         u64 rsvd_43        : 1;
 186         u64 next_state     : 8;
 187         u64 parse_done     : 1;
 188         u64 capture_ena    : 1;
 189         u64 byp_count      : 3;
 190         u64 rsvd_63_57     : 7;
 191 #endif
 192 };
 193 
 194 struct npc_kpu_action1 {
 195 #if defined(__BIG_ENDIAN_BITFIELD)
 196         u64 rsvd_63_36     : 28;
 197         u64 errlev         : 4;
 198         u64 errcode        : 8;
 199         u64 dp2_offset     : 8;
 200         u64 dp1_offset     : 8;
 201         u64 dp0_offset     : 8;
 202 #else
 203         u64 dp0_offset     : 8;
 204         u64 dp1_offset     : 8;
 205         u64 dp2_offset     : 8;
 206         u64 errcode        : 8;
 207         u64 errlev         : 4;
 208         u64 rsvd_63_36     : 28;
 209 #endif
 210 };
 211 
 212 struct npc_kpu_pkind_cpi_def {
 213 #if defined(__BIG_ENDIAN_BITFIELD)
 214         u64 ena            : 1;
 215         u64 rsvd_62_59     : 4;
 216         u64 lid            : 3;
 217         u64 ltype_match    : 4;
 218         u64 ltype_mask     : 4;
 219         u64 flags_match    : 8;
 220         u64 flags_mask     : 8;
 221         u64 add_offset     : 8;
 222         u64 add_mask       : 8;
 223         u64 rsvd_15        : 1;
 224         u64 add_shift      : 3;
 225         u64 rsvd_11_10     : 2;
 226         u64 cpi_base       : 10;
 227 #else
 228         u64 cpi_base       : 10;
 229         u64 rsvd_11_10     : 2;
 230         u64 add_shift      : 3;
 231         u64 rsvd_15        : 1;
 232         u64 add_mask       : 8;
 233         u64 add_offset     : 8;
 234         u64 flags_mask     : 8;
 235         u64 flags_match    : 8;
 236         u64 ltype_mask     : 4;
 237         u64 ltype_match    : 4;
 238         u64 lid            : 3;
 239         u64 rsvd_62_59     : 4;
 240         u64 ena            : 1;
 241 #endif
 242 };
 243 
 244 struct nix_rx_action {
 245 #if defined(__BIG_ENDIAN_BITFIELD)
 246         u64     rsvd_63_61      :3;
 247         u64     flow_key_alg    :5;
 248         u64     match_id        :16;
 249         u64     index           :20;
 250         u64     pf_func         :16;
 251         u64     op              :4;
 252 #else
 253         u64     op              :4;
 254         u64     pf_func         :16;
 255         u64     index           :20;
 256         u64     match_id        :16;
 257         u64     flow_key_alg    :5;
 258         u64     rsvd_63_61      :3;
 259 #endif
 260 };
 261 
 262 /* NIX Receive Vtag Action Structure */
 263 #define VTAG0_VALID_BIT         BIT_ULL(15)
 264 #define VTAG0_TYPE_MASK         GENMASK_ULL(14, 12)
 265 #define VTAG0_LID_MASK          GENMASK_ULL(10, 8)
 266 #define VTAG0_RELPTR_MASK       GENMASK_ULL(7, 0)
 267 
 268 struct npc_mcam_kex {
 269         /* MKEX Profle Header */
 270         u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
 271         u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
 272         u64 cpu_model;   /* Format as profiled by CPU hardware */
 273         u64 kpu_version; /* KPU firmware/profile version */
 274         u64 reserved; /* Reserved for extension */
 275 
 276         /* MKEX Profle Data */
 277         u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
 278         /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
 279         u64 kex_ld_flags[NPC_MAX_LD];
 280         /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
 281         u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
 282         /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
 283         u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
 284 } __packed;
 285 
 286 #endif /* NPC_H */