1 /*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef ENA_COM
34 #define ENA_COM
35
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/gfp.h>
40 #include <linux/io.h>
41 #include <linux/prefetch.h>
42 #include <linux/sched.h>
43 #include <linux/sizes.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46 #include <linux/wait.h>
47 #include <linux/netdevice.h>
48
49 #include "ena_common_defs.h"
50 #include "ena_admin_defs.h"
51 #include "ena_eth_io_defs.h"
52 #include "ena_regs_defs.h"
53
54 #undef pr_fmt
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
57 #define ENA_MAX_NUM_IO_QUEUES 128U
58 /* We need to queues for each IO (on for Tx and one for Rx) */
59 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
60
61 #define ENA_MAX_HANDLERS 256
62
63 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
64
65 /* Unit in usec */
66 #define ENA_REG_READ_TIMEOUT 200000
67
68 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry))
69 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry))
70 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry))
71
72 /*****************************************************************************/
73 /*****************************************************************************/
74 /* ENA adaptive interrupt moderation settings */
75
76 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64
77 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0
78 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
79
80 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
81
82 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
83
84 struct ena_llq_configurations {
85 enum ena_admin_llq_header_location llq_header_location;
86 enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
87 enum ena_admin_llq_stride_ctrl llq_stride_ctrl;
88 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
89 u16 llq_ring_entry_size_value;
90 };
91
92 enum queue_direction {
93 ENA_COM_IO_QUEUE_DIRECTION_TX,
94 ENA_COM_IO_QUEUE_DIRECTION_RX
95 };
96
97 struct ena_com_buf {
98 dma_addr_t paddr; /**< Buffer physical address */
99 u16 len; /**< Buffer length in bytes */
100 };
101
102 struct ena_com_rx_buf_info {
103 u16 len;
104 u16 req_id;
105 };
106
107 struct ena_com_io_desc_addr {
108 u8 __iomem *pbuf_dev_addr; /* LLQ address */
109 u8 *virt_addr;
110 dma_addr_t phys_addr;
111 };
112
113 struct ena_com_tx_meta {
114 u16 mss;
115 u16 l3_hdr_len;
116 u16 l3_hdr_offset;
117 u16 l4_hdr_len; /* In words */
118 };
119
120 struct ena_com_llq_info {
121 u16 header_location_ctrl;
122 u16 desc_stride_ctrl;
123 u16 desc_list_entry_size_ctrl;
124 u16 desc_list_entry_size;
125 u16 descs_num_before_header;
126 u16 descs_per_entry;
127 u16 max_entries_in_tx_burst;
128 };
129
130 struct ena_com_io_cq {
131 struct ena_com_io_desc_addr cdesc_addr;
132
133 /* Interrupt unmask register */
134 u32 __iomem *unmask_reg;
135
136 /* The completion queue head doorbell register */
137 u32 __iomem *cq_head_db_reg;
138
139 /* numa configuration register (for TPH) */
140 u32 __iomem *numa_node_cfg_reg;
141
142 /* The value to write to the above register to unmask
143 * the interrupt of this queue
144 */
145 u32 msix_vector;
146
147 enum queue_direction direction;
148
149 /* holds the number of cdesc of the current packet */
150 u16 cur_rx_pkt_cdesc_count;
151 /* save the firt cdesc idx of the current packet */
152 u16 cur_rx_pkt_cdesc_start_idx;
153
154 u16 q_depth;
155 /* Caller qid */
156 u16 qid;
157
158 /* Device queue index */
159 u16 idx;
160 u16 head;
161 u16 last_head_update;
162 u8 phase;
163 u8 cdesc_entry_size_in_bytes;
164
165 } ____cacheline_aligned;
166
167 struct ena_com_io_bounce_buffer_control {
168 u8 *base_buffer;
169 u16 next_to_use;
170 u16 buffer_size;
171 u16 buffers_num; /* Must be a power of 2 */
172 };
173
174 /* This struct is to keep tracking the current location of the next llq entry */
175 struct ena_com_llq_pkt_ctrl {
176 u8 *curr_bounce_buf;
177 u16 idx;
178 u16 descs_left_in_line;
179 };
180
181 struct ena_com_io_sq {
182 struct ena_com_io_desc_addr desc_addr;
183
184 u32 __iomem *db_addr;
185 u8 __iomem *header_addr;
186
187 enum queue_direction direction;
188 enum ena_admin_placement_policy_type mem_queue_type;
189
190 u32 msix_vector;
191 struct ena_com_tx_meta cached_tx_meta;
192 struct ena_com_llq_info llq_info;
193 struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
194 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
195
196 u16 q_depth;
197 u16 qid;
198
199 u16 idx;
200 u16 tail;
201 u16 next_to_comp;
202 u16 llq_last_copy_tail;
203 u32 tx_max_header_size;
204 u8 phase;
205 u8 desc_entry_size;
206 u8 dma_addr_bits;
207 u16 entries_in_tx_burst_left;
208 } ____cacheline_aligned;
209
210 struct ena_com_admin_cq {
211 struct ena_admin_acq_entry *entries;
212 dma_addr_t dma_addr;
213
214 u16 head;
215 u8 phase;
216 };
217
218 struct ena_com_admin_sq {
219 struct ena_admin_aq_entry *entries;
220 dma_addr_t dma_addr;
221
222 u32 __iomem *db_addr;
223
224 u16 head;
225 u16 tail;
226 u8 phase;
227
228 };
229
230 struct ena_com_stats_admin {
231 u32 aborted_cmd;
232 u32 submitted_cmd;
233 u32 completed_cmd;
234 u32 out_of_space;
235 u32 no_completion;
236 };
237
238 struct ena_com_admin_queue {
239 void *q_dmadev;
240 spinlock_t q_lock; /* spinlock for the admin queue */
241
242 struct ena_comp_ctx *comp_ctx;
243 u32 completion_timeout;
244 u16 q_depth;
245 struct ena_com_admin_cq cq;
246 struct ena_com_admin_sq sq;
247
248 /* Indicate if the admin queue should poll for completion */
249 bool polling;
250
251 /* Define if fallback to polling mode should occur */
252 bool auto_polling;
253
254 u16 curr_cmd_id;
255
256 /* Indicate that the ena was initialized and can
257 * process new admin commands
258 */
259 bool running_state;
260
261 /* Count the number of outstanding admin commands */
262 atomic_t outstanding_cmds;
263
264 struct ena_com_stats_admin stats;
265 };
266
267 struct ena_aenq_handlers;
268
269 struct ena_com_aenq {
270 u16 head;
271 u8 phase;
272 struct ena_admin_aenq_entry *entries;
273 dma_addr_t dma_addr;
274 u16 q_depth;
275 struct ena_aenq_handlers *aenq_handlers;
276 };
277
278 struct ena_com_mmio_read {
279 struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
280 dma_addr_t read_resp_dma_addr;
281 u32 reg_read_to; /* in us */
282 u16 seq_num;
283 bool readless_supported;
284 /* spin lock to ensure a single outstanding read */
285 spinlock_t lock;
286 };
287
288 struct ena_rss {
289 /* Indirect table */
290 u16 *host_rss_ind_tbl;
291 struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
292 dma_addr_t rss_ind_tbl_dma_addr;
293 u16 tbl_log_size;
294
295 /* Hash key */
296 enum ena_admin_hash_functions hash_func;
297 struct ena_admin_feature_rss_flow_hash_control *hash_key;
298 dma_addr_t hash_key_dma_addr;
299 u32 hash_init_val;
300
301 /* Flow Control */
302 struct ena_admin_feature_rss_hash_control *hash_ctrl;
303 dma_addr_t hash_ctrl_dma_addr;
304
305 };
306
307 struct ena_host_attribute {
308 /* Debug area */
309 u8 *debug_area_virt_addr;
310 dma_addr_t debug_area_dma_addr;
311 u32 debug_area_size;
312
313 /* Host information */
314 struct ena_admin_host_info *host_info;
315 dma_addr_t host_info_dma_addr;
316 };
317
318 /* Each ena_dev is a PCI function. */
319 struct ena_com_dev {
320 struct ena_com_admin_queue admin_queue;
321 struct ena_com_aenq aenq;
322 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
323 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
324 u8 __iomem *reg_bar;
325 void __iomem *mem_bar;
326 void *dmadev;
327
328 enum ena_admin_placement_policy_type tx_mem_queue_type;
329 u32 tx_max_header_size;
330 u16 stats_func; /* Selected function for extended statistic dump */
331 u16 stats_queue; /* Selected queue for extended statistic dump */
332
333 struct ena_com_mmio_read mmio_read;
334
335 struct ena_rss rss;
336 u32 supported_features;
337 u32 dma_addr_bits;
338
339 struct ena_host_attribute host_attr;
340 bool adaptive_coalescing;
341 u16 intr_delay_resolution;
342
343 /* interrupt moderation intervals are in usec divided by
344 * intr_delay_resolution, which is supplied by the device.
345 */
346 u32 intr_moder_tx_interval;
347 u32 intr_moder_rx_interval;
348
349 struct ena_intr_moder_entry *intr_moder_tbl;
350
351 struct ena_com_llq_info llq_info;
352 };
353
354 struct ena_com_dev_get_features_ctx {
355 struct ena_admin_queue_feature_desc max_queues;
356 struct ena_admin_queue_ext_feature_desc max_queue_ext;
357 struct ena_admin_device_attr_feature_desc dev_attr;
358 struct ena_admin_feature_aenq_desc aenq;
359 struct ena_admin_feature_offload_desc offload;
360 struct ena_admin_ena_hw_hints hw_hints;
361 struct ena_admin_feature_llq_desc llq;
362 };
363
364 struct ena_com_create_io_ctx {
365 enum ena_admin_placement_policy_type mem_queue_type;
366 enum queue_direction direction;
367 int numa_node;
368 u32 msix_vector;
369 u16 queue_size;
370 u16 qid;
371 };
372
373 typedef void (*ena_aenq_handler)(void *data,
374 struct ena_admin_aenq_entry *aenq_e);
375
376 /* Holds aenq handlers. Indexed by AENQ event group */
377 struct ena_aenq_handlers {
378 ena_aenq_handler handlers[ENA_MAX_HANDLERS];
379 ena_aenq_handler unimplemented_handler;
380 };
381
382 /*****************************************************************************/
383 /*****************************************************************************/
384
385 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
386 * @ena_dev: ENA communication layer struct
387 *
388 * Initialize the register read mechanism.
389 *
390 * @note: This method must be the first stage in the initialization sequence.
391 *
392 * @return - 0 on success, negative value on failure.
393 */
394 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
395
396 /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
397 * @ena_dev: ENA communication layer struct
398 * @readless_supported: readless mode (enable/disable)
399 */
400 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
401 bool readless_supported);
402
403 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
404 * value physical address.
405 * @ena_dev: ENA communication layer struct
406 */
407 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
408
409 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
410 * @ena_dev: ENA communication layer struct
411 */
412 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
413
414 /* ena_com_admin_init - Init the admin and the async queues
415 * @ena_dev: ENA communication layer struct
416 * @aenq_handlers: Those handlers to be called upon event.
417 *
418 * Initialize the admin submission and completion queues.
419 * Initialize the asynchronous events notification queues.
420 *
421 * @return - 0 on success, negative value on failure.
422 */
423 int ena_com_admin_init(struct ena_com_dev *ena_dev,
424 struct ena_aenq_handlers *aenq_handlers);
425
426 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
427 * @ena_dev: ENA communication layer struct
428 *
429 * @note: Before calling this method, the caller must validate that the device
430 * won't send any additional admin completions/aenq.
431 * To achieve that, a FLR is recommended.
432 */
433 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
434
435 /* ena_com_dev_reset - Perform device FLR to the device.
436 * @ena_dev: ENA communication layer struct
437 * @reset_reason: Specify what is the trigger for the reset in case of an error.
438 *
439 * @return - 0 on success, negative value on failure.
440 */
441 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
442 enum ena_regs_reset_reason_types reset_reason);
443
444 /* ena_com_create_io_queue - Create io queue.
445 * @ena_dev: ENA communication layer struct
446 * @ctx - create context structure
447 *
448 * Create the submission and the completion queues.
449 *
450 * @return - 0 on success, negative value on failure.
451 */
452 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
453 struct ena_com_create_io_ctx *ctx);
454
455 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
456 * @ena_dev: ENA communication layer struct
457 * @qid - the caller virtual queue id.
458 */
459 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
460
461 /* ena_com_get_io_handlers - Return the io queue handlers
462 * @ena_dev: ENA communication layer struct
463 * @qid - the caller virtual queue id.
464 * @io_sq - IO submission queue handler
465 * @io_cq - IO completion queue handler.
466 *
467 * @return - 0 on success, negative value on failure.
468 */
469 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
470 struct ena_com_io_sq **io_sq,
471 struct ena_com_io_cq **io_cq);
472
473 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
474 * @ena_dev: ENA communication layer struct
475 *
476 * After this method, aenq event can be received via AENQ.
477 */
478 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
479
480 /* ena_com_set_admin_running_state - Set the state of the admin queue
481 * @ena_dev: ENA communication layer struct
482 *
483 * Change the state of the admin queue (enable/disable)
484 */
485 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
486
487 /* ena_com_get_admin_running_state - Get the admin queue state
488 * @ena_dev: ENA communication layer struct
489 *
490 * Retrieve the state of the admin queue (enable/disable)
491 *
492 * @return - current polling mode (enable/disable)
493 */
494 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
495
496 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
497 * @ena_dev: ENA communication layer struct
498 * @polling: ENAble/Disable polling mode
499 *
500 * Set the admin completion mode.
501 */
502 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
503
504 /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode
505 * @ena_dev: ENA communication layer struct
506 *
507 * Get the admin completion mode.
508 * If polling mode is on, ena_com_execute_admin_command will perform a
509 * polling on the admin completion queue for the commands completion,
510 * otherwise it will wait on wait event.
511 *
512 * @return state
513 */
514 bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev);
515
516 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode
517 * @ena_dev: ENA communication layer struct
518 * @polling: Enable/Disable polling mode
519 *
520 * Set the autopolling mode.
521 * If autopolling is on:
522 * In case of missing interrupt when data is available switch to polling.
523 */
524 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
525 bool polling);
526
527 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
528 * @ena_dev: ENA communication layer struct
529 *
530 * This method go over the admin completion queue and wake up all the pending
531 * threads that wait on the commands wait event.
532 *
533 * @note: Should be called after MSI-X interrupt.
534 */
535 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
536
537 /* ena_com_aenq_intr_handler - AENQ interrupt handler
538 * @ena_dev: ENA communication layer struct
539 *
540 * This method go over the async event notification queue and call the proper
541 * aenq handler.
542 */
543 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
544
545 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
546 * @ena_dev: ENA communication layer struct
547 *
548 * This method aborts all the outstanding admin commands.
549 * The caller should then call ena_com_wait_for_abort_completion to make sure
550 * all the commands were completed.
551 */
552 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
553
554 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
555 * @ena_dev: ENA communication layer struct
556 *
557 * This method wait until all the outstanding admin commands will be completed.
558 */
559 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
560
561 /* ena_com_validate_version - Validate the device parameters
562 * @ena_dev: ENA communication layer struct
563 *
564 * This method validate the device parameters are the same as the saved
565 * parameters in ena_dev.
566 * This method is useful after device reset, to validate the device mac address
567 * and the device offloads are the same as before the reset.
568 *
569 * @return - 0 on success negative value otherwise.
570 */
571 int ena_com_validate_version(struct ena_com_dev *ena_dev);
572
573 /* ena_com_get_link_params - Retrieve physical link parameters.
574 * @ena_dev: ENA communication layer struct
575 * @resp: Link parameters
576 *
577 * Retrieve the physical link parameters,
578 * like speed, auto-negotiation and full duplex support.
579 *
580 * @return - 0 on Success negative value otherwise.
581 */
582 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
583 struct ena_admin_get_feat_resp *resp);
584
585 /* ena_com_get_dma_width - Retrieve physical dma address width the device
586 * supports.
587 * @ena_dev: ENA communication layer struct
588 *
589 * Retrieve the maximum physical address bits the device can handle.
590 *
591 * @return: > 0 on Success and negative value otherwise.
592 */
593 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
594
595 /* ena_com_set_aenq_config - Set aenq groups configurations
596 * @ena_dev: ENA communication layer struct
597 * @groups flag: bit fields flags of enum ena_admin_aenq_group.
598 *
599 * Configure which aenq event group the driver would like to receive.
600 *
601 * @return: 0 on Success and negative value otherwise.
602 */
603 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
604
605 /* ena_com_get_dev_attr_feat - Get device features
606 * @ena_dev: ENA communication layer struct
607 * @get_feat_ctx: returned context that contain the get features.
608 *
609 * @return: 0 on Success and negative value otherwise.
610 */
611 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
612 struct ena_com_dev_get_features_ctx *get_feat_ctx);
613
614 /* ena_com_get_dev_basic_stats - Get device basic statistics
615 * @ena_dev: ENA communication layer struct
616 * @stats: stats return value
617 *
618 * @return: 0 on Success and negative value otherwise.
619 */
620 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
621 struct ena_admin_basic_stats *stats);
622
623 /* ena_com_set_dev_mtu - Configure the device mtu.
624 * @ena_dev: ENA communication layer struct
625 * @mtu: mtu value
626 *
627 * @return: 0 on Success and negative value otherwise.
628 */
629 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
630
631 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
632 * @ena_dev: ENA communication layer struct
633 * @offlad: offload return value
634 *
635 * @return: 0 on Success and negative value otherwise.
636 */
637 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
638 struct ena_admin_feature_offload_desc *offload);
639
640 /* ena_com_rss_init - Init RSS
641 * @ena_dev: ENA communication layer struct
642 * @log_size: indirection log size
643 *
644 * Allocate RSS/RFS resources.
645 * The caller then can configure rss using ena_com_set_hash_function,
646 * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
647 *
648 * @return: 0 on Success and negative value otherwise.
649 */
650 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
651
652 /* ena_com_rss_destroy - Destroy rss
653 * @ena_dev: ENA communication layer struct
654 *
655 * Free all the RSS/RFS resources.
656 */
657 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
658
659 /* ena_com_get_current_hash_function - Get RSS hash function
660 * @ena_dev: ENA communication layer struct
661 *
662 * Return the current hash function.
663 * @return: 0 or one of the ena_admin_hash_functions values.
664 */
665 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev);
666
667 /* ena_com_fill_hash_function - Fill RSS hash function
668 * @ena_dev: ENA communication layer struct
669 * @func: The hash function (Toeplitz or crc)
670 * @key: Hash key (for toeplitz hash)
671 * @key_len: key length (max length 10 DW)
672 * @init_val: initial value for the hash function
673 *
674 * Fill the ena_dev resources with the desire hash function, hash key, key_len
675 * and key initial value (if needed by the hash function).
676 * To flush the key into the device the caller should call
677 * ena_com_set_hash_function.
678 *
679 * @return: 0 on Success and negative value otherwise.
680 */
681 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
682 enum ena_admin_hash_functions func,
683 const u8 *key, u16 key_len, u32 init_val);
684
685 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
686 * the device.
687 * @ena_dev: ENA communication layer struct
688 *
689 * Flush the hash function and it dependencies (key, key length and
690 * initial value) if needed.
691 *
692 * @note: Prior to this method the caller should call ena_com_fill_hash_function
693 *
694 * @return: 0 on Success and negative value otherwise.
695 */
696 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
697
698 /* ena_com_get_hash_function - Retrieve the hash function and the hash key
699 * from the device.
700 * @ena_dev: ENA communication layer struct
701 * @func: hash function
702 * @key: hash key
703 *
704 * Retrieve the hash function and the hash key from the device.
705 *
706 * @note: If the caller called ena_com_fill_hash_function but didn't flash
707 * it to the device, the new configuration will be lost.
708 *
709 * @return: 0 on Success and negative value otherwise.
710 */
711 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
712 enum ena_admin_hash_functions *func,
713 u8 *key);
714
715 /* ena_com_fill_hash_ctrl - Fill RSS hash control
716 * @ena_dev: ENA communication layer struct.
717 * @proto: The protocol to configure.
718 * @hash_fields: bit mask of ena_admin_flow_hash_fields
719 *
720 * Fill the ena_dev resources with the desire hash control (the ethernet
721 * fields that take part of the hash) for a specific protocol.
722 * To flush the hash control to the device, the caller should call
723 * ena_com_set_hash_ctrl.
724 *
725 * @return: 0 on Success and negative value otherwise.
726 */
727 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
728 enum ena_admin_flow_hash_proto proto,
729 u16 hash_fields);
730
731 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
732 * @ena_dev: ENA communication layer struct
733 *
734 * Flush the hash control (the ethernet fields that take part of the hash)
735 *
736 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
737 *
738 * @return: 0 on Success and negative value otherwise.
739 */
740 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
741
742 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
743 * @ena_dev: ENA communication layer struct
744 * @proto: The protocol to retrieve.
745 * @fields: bit mask of ena_admin_flow_hash_fields.
746 *
747 * Retrieve the hash control from the device.
748 *
749 * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash
750 * it to the device, the new configuration will be lost.
751 *
752 * @return: 0 on Success and negative value otherwise.
753 */
754 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
755 enum ena_admin_flow_hash_proto proto,
756 u16 *fields);
757
758 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
759 * configuration.
760 * @ena_dev: ENA communication layer struct
761 *
762 * Fill the ena_dev resources with the default hash control configuration.
763 * To flush the hash control to the device, the caller should call
764 * ena_com_set_hash_ctrl.
765 *
766 * @return: 0 on Success and negative value otherwise.
767 */
768 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
769
770 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
771 * indirection table
772 * @ena_dev: ENA communication layer struct.
773 * @entry_idx - indirection table entry.
774 * @entry_value - redirection value
775 *
776 * Fill a single entry of the RSS indirection table in the ena_dev resources.
777 * To flush the indirection table to the device, the called should call
778 * ena_com_indirect_table_set.
779 *
780 * @return: 0 on Success and negative value otherwise.
781 */
782 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
783 u16 entry_idx, u16 entry_value);
784
785 /* ena_com_indirect_table_set - Flush the indirection table to the device.
786 * @ena_dev: ENA communication layer struct
787 *
788 * Flush the indirection hash control to the device.
789 * Prior to this method the caller should call ena_com_indirect_table_fill_entry
790 *
791 * @return: 0 on Success and negative value otherwise.
792 */
793 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
794
795 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
796 * @ena_dev: ENA communication layer struct
797 * @ind_tbl: indirection table
798 *
799 * Retrieve the RSS indirection table from the device.
800 *
801 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
802 * it to the device, the new configuration will be lost.
803 *
804 * @return: 0 on Success and negative value otherwise.
805 */
806 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
807
808 /* ena_com_allocate_host_info - Allocate host info resources.
809 * @ena_dev: ENA communication layer struct
810 *
811 * @return: 0 on Success and negative value otherwise.
812 */
813 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
814
815 /* ena_com_allocate_debug_area - Allocate debug area.
816 * @ena_dev: ENA communication layer struct
817 * @debug_area_size - debug area size.
818 *
819 * @return: 0 on Success and negative value otherwise.
820 */
821 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
822 u32 debug_area_size);
823
824 /* ena_com_delete_debug_area - Free the debug area resources.
825 * @ena_dev: ENA communication layer struct
826 *
827 * Free the allocate debug area.
828 */
829 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
830
831 /* ena_com_delete_host_info - Free the host info resources.
832 * @ena_dev: ENA communication layer struct
833 *
834 * Free the allocate host info.
835 */
836 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
837
838 /* ena_com_set_host_attributes - Update the device with the host
839 * attributes (debug area and host info) base address.
840 * @ena_dev: ENA communication layer struct
841 *
842 * @return: 0 on Success and negative value otherwise.
843 */
844 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
845
846 /* ena_com_create_io_cq - Create io completion queue.
847 * @ena_dev: ENA communication layer struct
848 * @io_cq - io completion queue handler
849
850 * Create IO completion queue.
851 *
852 * @return - 0 on success, negative value on failure.
853 */
854 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
855 struct ena_com_io_cq *io_cq);
856
857 /* ena_com_destroy_io_cq - Destroy io completion queue.
858 * @ena_dev: ENA communication layer struct
859 * @io_cq - io completion queue handler
860
861 * Destroy IO completion queue.
862 *
863 * @return - 0 on success, negative value on failure.
864 */
865 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
866 struct ena_com_io_cq *io_cq);
867
868 /* ena_com_execute_admin_command - Execute admin command
869 * @admin_queue: admin queue.
870 * @cmd: the admin command to execute.
871 * @cmd_size: the command size.
872 * @cmd_completion: command completion return value.
873 * @cmd_comp_size: command completion size.
874
875 * Submit an admin command and then wait until the device will return a
876 * completion.
877 * The completion will be copyed into cmd_comp.
878 *
879 * @return - 0 on success, negative value on failure.
880 */
881 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
882 struct ena_admin_aq_entry *cmd,
883 size_t cmd_size,
884 struct ena_admin_acq_entry *cmd_comp,
885 size_t cmd_comp_size);
886
887 /* ena_com_init_interrupt_moderation - Init interrupt moderation
888 * @ena_dev: ENA communication layer struct
889 *
890 * @return - 0 on success, negative value on failure.
891 */
892 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
893
894 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
895 * capability is supported by the device.
896 *
897 * @return - supported or not.
898 */
899 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
900
901 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
902 * non-adaptive interval in Tx direction.
903 * @ena_dev: ENA communication layer struct
904 * @tx_coalesce_usecs: Interval in usec.
905 *
906 * @return - 0 on success, negative value on failure.
907 */
908 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
909 u32 tx_coalesce_usecs);
910
911 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
912 * non-adaptive interval in Rx direction.
913 * @ena_dev: ENA communication layer struct
914 * @rx_coalesce_usecs: Interval in usec.
915 *
916 * @return - 0 on success, negative value on failure.
917 */
918 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
919 u32 rx_coalesce_usecs);
920
921 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
922 * non-adaptive interval in Tx direction.
923 * @ena_dev: ENA communication layer struct
924 *
925 * @return - interval in usec
926 */
927 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
928
929 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
930 * non-adaptive interval in Rx direction.
931 * @ena_dev: ENA communication layer struct
932 *
933 * @return - interval in usec
934 */
935 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
936
937 /* ena_com_config_dev_mode - Configure the placement policy of the device.
938 * @ena_dev: ENA communication layer struct
939 * @llq_features: LLQ feature descriptor, retrieve via
940 * ena_com_get_dev_attr_feat.
941 * @ena_llq_config: The default driver LLQ parameters configurations
942 */
943 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
944 struct ena_admin_feature_llq_desc *llq_features,
945 struct ena_llq_configurations *llq_default_config);
946
947 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
948 {
949 return ena_dev->adaptive_coalescing;
950 }
951
952 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
953 {
954 ena_dev->adaptive_coalescing = true;
955 }
956
957 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
958 {
959 ena_dev->adaptive_coalescing = false;
960 }
961
962 /* ena_com_update_intr_reg - Prepare interrupt register
963 * @intr_reg: interrupt register to update.
964 * @rx_delay_interval: Rx interval in usecs
965 * @tx_delay_interval: Tx interval in usecs
966 * @unmask: unask enable/disable
967 *
968 * Prepare interrupt update register with the supplied parameters.
969 */
970 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
971 u32 rx_delay_interval,
972 u32 tx_delay_interval,
973 bool unmask)
974 {
975 intr_reg->intr_control = 0;
976 intr_reg->intr_control |= rx_delay_interval &
977 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
978
979 intr_reg->intr_control |=
980 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
981 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
982
983 if (unmask)
984 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
985 }
986
987 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
988 {
989 u16 size, buffers_num;
990 u8 *buf;
991
992 size = bounce_buf_ctrl->buffer_size;
993 buffers_num = bounce_buf_ctrl->buffers_num;
994
995 buf = bounce_buf_ctrl->base_buffer +
996 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
997
998 prefetchw(bounce_buf_ctrl->base_buffer +
999 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1000
1001 return buf;
1002 }
1003
1004 #endif /* !(ENA_COM) */