This source file includes following definitions.
- ena_tx_timeout
- update_rx_ring_mtu
- ena_change_mtu
- ena_init_rx_cpu_rmap
- ena_init_io_rings_common
- ena_init_io_rings
- ena_setup_tx_resources
- ena_free_tx_resources
- ena_setup_all_tx_resources
- ena_free_all_io_tx_resources
- validate_rx_req_id
- ena_setup_rx_resources
- ena_free_rx_resources
- ena_setup_all_rx_resources
- ena_free_all_io_rx_resources
- ena_alloc_rx_page
- ena_free_rx_page
- ena_refill_rx_bufs
- ena_free_rx_bufs
- ena_refill_all_rx_bufs
- ena_free_all_rx_bufs
- ena_unmap_tx_skb
- ena_free_tx_bufs
- ena_free_all_tx_bufs
- ena_destroy_all_tx_queues
- ena_destroy_all_rx_queues
- ena_destroy_all_io_queues
- validate_tx_req_id
- ena_clean_tx_irq
- ena_alloc_skb
- ena_rx_skb
- ena_rx_checksum
- ena_set_rx_hash
- ena_clean_rx_irq
- ena_dim_work
- ena_adjust_adaptive_rx_intr_moderation
- ena_unmask_interrupt
- ena_update_ring_numa_node
- ena_io_poll
- ena_intr_msix_mgmnt
- ena_intr_msix_io
- ena_enable_msix
- ena_setup_mgmnt_intr
- ena_setup_io_intr
- ena_request_mgmnt_irq
- ena_request_io_irq
- ena_free_mgmnt_irq
- ena_free_io_irq
- ena_disable_msix
- ena_disable_io_intr_sync
- ena_del_napi
- ena_init_napi
- ena_napi_disable_all
- ena_napi_enable_all
- ena_rss_configure
- ena_up_complete
- ena_create_io_tx_queue
- ena_create_all_io_tx_queues
- ena_create_io_rx_queue
- ena_create_all_io_rx_queues
- set_io_rings_size
- create_queues_with_size_backoff
- ena_up
- ena_down
- ena_open
- ena_close
- ena_update_queue_sizes
- ena_tx_csum
- ena_check_and_linearize_skb
- ena_tx_map_skb
- ena_start_xmit
- ena_select_queue
- ena_config_host_info
- ena_config_debug_area
- ena_get_stats64
- ena_device_validate_params
- ena_device_init
- ena_enable_msix_and_set_admin_interrupts
- ena_destroy_device
- ena_restore_device
- ena_fw_reset_device
- check_for_rx_interrupt_queue
- check_missing_comp_in_tx_queue
- check_for_missing_completions
- check_for_empty_rx_ring
- check_for_missing_keep_alive
- check_for_admin_com_state
- ena_update_hints
- ena_update_host_info
- ena_timer_service
- ena_calc_io_queue_num
- ena_set_queues_placement_policy
- ena_set_dev_offloads
- ena_set_conf_feat_params
- ena_rss_init_default
- ena_release_bars
- set_default_llq_configurations
- ena_calc_queue_size
- ena_probe
- __ena_shutoff
- ena_remove
- ena_shutdown
- ena_suspend
- ena_resume
- ena_init
- ena_cleanup
- ena_update_on_link_change
- ena_keep_alive_wd
- ena_notification
- unimplemented_aenq_handler
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32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #ifdef CONFIG_RFS_ACCEL
36 #include <linux/cpu_rmap.h>
37 #endif
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/numa.h>
43 #include <linux/pci.h>
44 #include <linux/utsname.h>
45 #include <linux/version.h>
46 #include <linux/vmalloc.h>
47 #include <net/ip.h>
48
49 #include "ena_netdev.h"
50 #include "ena_pci_id_tbl.h"
51
52 static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
53
54 MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
55 MODULE_DESCRIPTION(DEVICE_NAME);
56 MODULE_LICENSE("GPL");
57 MODULE_VERSION(DRV_MODULE_VERSION);
58
59
60 #define TX_TIMEOUT (5 * HZ)
61
62 #define ENA_NAPI_BUDGET 64
63
64 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
65 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
66 static int debug = -1;
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 static struct ena_aenq_handlers aenq_handlers;
71
72 static struct workqueue_struct *ena_wq;
73
74 MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
75
76 static int ena_rss_init_default(struct ena_adapter *adapter);
77 static void check_for_admin_com_state(struct ena_adapter *adapter);
78 static void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
79 static int ena_restore_device(struct ena_adapter *adapter);
80
81 static void ena_tx_timeout(struct net_device *dev)
82 {
83 struct ena_adapter *adapter = netdev_priv(dev);
84
85
86
87
88
89 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
90 return;
91
92 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
93 u64_stats_update_begin(&adapter->syncp);
94 adapter->dev_stats.tx_timeout++;
95 u64_stats_update_end(&adapter->syncp);
96
97 netif_err(adapter, tx_err, dev, "Transmit time out\n");
98 }
99
100 static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
101 {
102 int i;
103
104 for (i = 0; i < adapter->num_queues; i++)
105 adapter->rx_ring[i].mtu = mtu;
106 }
107
108 static int ena_change_mtu(struct net_device *dev, int new_mtu)
109 {
110 struct ena_adapter *adapter = netdev_priv(dev);
111 int ret;
112
113 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
114 if (!ret) {
115 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
116 update_rx_ring_mtu(adapter, new_mtu);
117 dev->mtu = new_mtu;
118 } else {
119 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
120 new_mtu);
121 }
122
123 return ret;
124 }
125
126 static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
127 {
128 #ifdef CONFIG_RFS_ACCEL
129 u32 i;
130 int rc;
131
132 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
133 if (!adapter->netdev->rx_cpu_rmap)
134 return -ENOMEM;
135 for (i = 0; i < adapter->num_queues; i++) {
136 int irq_idx = ENA_IO_IRQ_IDX(i);
137
138 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
139 pci_irq_vector(adapter->pdev, irq_idx));
140 if (rc) {
141 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
142 adapter->netdev->rx_cpu_rmap = NULL;
143 return rc;
144 }
145 }
146 #endif
147 return 0;
148 }
149
150 static void ena_init_io_rings_common(struct ena_adapter *adapter,
151 struct ena_ring *ring, u16 qid)
152 {
153 ring->qid = qid;
154 ring->pdev = adapter->pdev;
155 ring->dev = &adapter->pdev->dev;
156 ring->netdev = adapter->netdev;
157 ring->napi = &adapter->ena_napi[qid].napi;
158 ring->adapter = adapter;
159 ring->ena_dev = adapter->ena_dev;
160 ring->per_napi_packets = 0;
161 ring->cpu = 0;
162 ring->first_interrupt = false;
163 ring->no_interrupt_event_cnt = 0;
164 u64_stats_init(&ring->syncp);
165 }
166
167 static void ena_init_io_rings(struct ena_adapter *adapter)
168 {
169 struct ena_com_dev *ena_dev;
170 struct ena_ring *txr, *rxr;
171 int i;
172
173 ena_dev = adapter->ena_dev;
174
175 for (i = 0; i < adapter->num_queues; i++) {
176 txr = &adapter->tx_ring[i];
177 rxr = &adapter->rx_ring[i];
178
179
180 ena_init_io_rings_common(adapter, txr, i);
181 ena_init_io_rings_common(adapter, rxr, i);
182
183
184 txr->ring_size = adapter->requested_tx_ring_size;
185 txr->tx_max_header_size = ena_dev->tx_max_header_size;
186 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
187 txr->sgl_size = adapter->max_tx_sgl_size;
188 txr->smoothed_interval =
189 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
190
191
192 rxr->ring_size = adapter->requested_rx_ring_size;
193 rxr->rx_copybreak = adapter->rx_copybreak;
194 rxr->sgl_size = adapter->max_rx_sgl_size;
195 rxr->smoothed_interval =
196 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
197 rxr->empty_rx_queue = 0;
198 adapter->ena_napi[i].dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
199 }
200 }
201
202
203
204
205
206
207
208 static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
209 {
210 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
211 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
212 int size, i, node;
213
214 if (tx_ring->tx_buffer_info) {
215 netif_err(adapter, ifup,
216 adapter->netdev, "tx_buffer_info info is not NULL");
217 return -EEXIST;
218 }
219
220 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
221 node = cpu_to_node(ena_irq->cpu);
222
223 tx_ring->tx_buffer_info = vzalloc_node(size, node);
224 if (!tx_ring->tx_buffer_info) {
225 tx_ring->tx_buffer_info = vzalloc(size);
226 if (!tx_ring->tx_buffer_info)
227 goto err_tx_buffer_info;
228 }
229
230 size = sizeof(u16) * tx_ring->ring_size;
231 tx_ring->free_ids = vzalloc_node(size, node);
232 if (!tx_ring->free_ids) {
233 tx_ring->free_ids = vzalloc(size);
234 if (!tx_ring->free_ids)
235 goto err_tx_free_ids;
236 }
237
238 size = tx_ring->tx_max_header_size;
239 tx_ring->push_buf_intermediate_buf = vzalloc_node(size, node);
240 if (!tx_ring->push_buf_intermediate_buf) {
241 tx_ring->push_buf_intermediate_buf = vzalloc(size);
242 if (!tx_ring->push_buf_intermediate_buf)
243 goto err_push_buf_intermediate_buf;
244 }
245
246
247 for (i = 0; i < tx_ring->ring_size; i++)
248 tx_ring->free_ids[i] = i;
249
250
251 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
252
253 tx_ring->next_to_use = 0;
254 tx_ring->next_to_clean = 0;
255 tx_ring->cpu = ena_irq->cpu;
256 return 0;
257
258 err_push_buf_intermediate_buf:
259 vfree(tx_ring->free_ids);
260 tx_ring->free_ids = NULL;
261 err_tx_free_ids:
262 vfree(tx_ring->tx_buffer_info);
263 tx_ring->tx_buffer_info = NULL;
264 err_tx_buffer_info:
265 return -ENOMEM;
266 }
267
268
269
270
271
272
273
274 static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
275 {
276 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
277
278 vfree(tx_ring->tx_buffer_info);
279 tx_ring->tx_buffer_info = NULL;
280
281 vfree(tx_ring->free_ids);
282 tx_ring->free_ids = NULL;
283
284 vfree(tx_ring->push_buf_intermediate_buf);
285 tx_ring->push_buf_intermediate_buf = NULL;
286 }
287
288
289
290
291
292
293 static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
294 {
295 int i, rc = 0;
296
297 for (i = 0; i < adapter->num_queues; i++) {
298 rc = ena_setup_tx_resources(adapter, i);
299 if (rc)
300 goto err_setup_tx;
301 }
302
303 return 0;
304
305 err_setup_tx:
306
307 netif_err(adapter, ifup, adapter->netdev,
308 "Tx queue %d: allocation failed\n", i);
309
310
311 while (i--)
312 ena_free_tx_resources(adapter, i);
313 return rc;
314 }
315
316
317
318
319
320
321 static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
322 {
323 int i;
324
325 for (i = 0; i < adapter->num_queues; i++)
326 ena_free_tx_resources(adapter, i);
327 }
328
329 static int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id)
330 {
331 if (likely(req_id < rx_ring->ring_size))
332 return 0;
333
334 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
335 "Invalid rx req_id: %hu\n", req_id);
336
337 u64_stats_update_begin(&rx_ring->syncp);
338 rx_ring->rx_stats.bad_req_id++;
339 u64_stats_update_end(&rx_ring->syncp);
340
341
342 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
343 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags);
344 return -EFAULT;
345 }
346
347
348
349
350
351
352
353 static int ena_setup_rx_resources(struct ena_adapter *adapter,
354 u32 qid)
355 {
356 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
357 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
358 int size, node, i;
359
360 if (rx_ring->rx_buffer_info) {
361 netif_err(adapter, ifup, adapter->netdev,
362 "rx_buffer_info is not NULL");
363 return -EEXIST;
364 }
365
366
367
368
369 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
370 node = cpu_to_node(ena_irq->cpu);
371
372 rx_ring->rx_buffer_info = vzalloc_node(size, node);
373 if (!rx_ring->rx_buffer_info) {
374 rx_ring->rx_buffer_info = vzalloc(size);
375 if (!rx_ring->rx_buffer_info)
376 return -ENOMEM;
377 }
378
379 size = sizeof(u16) * rx_ring->ring_size;
380 rx_ring->free_ids = vzalloc_node(size, node);
381 if (!rx_ring->free_ids) {
382 rx_ring->free_ids = vzalloc(size);
383 if (!rx_ring->free_ids) {
384 vfree(rx_ring->rx_buffer_info);
385 rx_ring->rx_buffer_info = NULL;
386 return -ENOMEM;
387 }
388 }
389
390
391 for (i = 0; i < rx_ring->ring_size; i++)
392 rx_ring->free_ids[i] = i;
393
394
395 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
396
397 rx_ring->next_to_clean = 0;
398 rx_ring->next_to_use = 0;
399 rx_ring->cpu = ena_irq->cpu;
400
401 return 0;
402 }
403
404
405
406
407
408
409
410 static void ena_free_rx_resources(struct ena_adapter *adapter,
411 u32 qid)
412 {
413 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
414
415 vfree(rx_ring->rx_buffer_info);
416 rx_ring->rx_buffer_info = NULL;
417
418 vfree(rx_ring->free_ids);
419 rx_ring->free_ids = NULL;
420 }
421
422
423
424
425
426
427 static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
428 {
429 int i, rc = 0;
430
431 for (i = 0; i < adapter->num_queues; i++) {
432 rc = ena_setup_rx_resources(adapter, i);
433 if (rc)
434 goto err_setup_rx;
435 }
436
437 return 0;
438
439 err_setup_rx:
440
441 netif_err(adapter, ifup, adapter->netdev,
442 "Rx queue %d: allocation failed\n", i);
443
444
445 while (i--)
446 ena_free_rx_resources(adapter, i);
447 return rc;
448 }
449
450
451
452
453
454
455 static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
456 {
457 int i;
458
459 for (i = 0; i < adapter->num_queues; i++)
460 ena_free_rx_resources(adapter, i);
461 }
462
463 static int ena_alloc_rx_page(struct ena_ring *rx_ring,
464 struct ena_rx_buffer *rx_info, gfp_t gfp)
465 {
466 struct ena_com_buf *ena_buf;
467 struct page *page;
468 dma_addr_t dma;
469
470
471 if (unlikely(rx_info->page))
472 return 0;
473
474 page = alloc_page(gfp);
475 if (unlikely(!page)) {
476 u64_stats_update_begin(&rx_ring->syncp);
477 rx_ring->rx_stats.page_alloc_fail++;
478 u64_stats_update_end(&rx_ring->syncp);
479 return -ENOMEM;
480 }
481
482 dma = dma_map_page(rx_ring->dev, page, 0, ENA_PAGE_SIZE,
483 DMA_FROM_DEVICE);
484 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
485 u64_stats_update_begin(&rx_ring->syncp);
486 rx_ring->rx_stats.dma_mapping_err++;
487 u64_stats_update_end(&rx_ring->syncp);
488
489 __free_page(page);
490 return -EIO;
491 }
492 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
493 "alloc page %p, rx_info %p\n", page, rx_info);
494
495 rx_info->page = page;
496 rx_info->page_offset = 0;
497 ena_buf = &rx_info->ena_buf;
498 ena_buf->paddr = dma;
499 ena_buf->len = ENA_PAGE_SIZE;
500
501 return 0;
502 }
503
504 static void ena_free_rx_page(struct ena_ring *rx_ring,
505 struct ena_rx_buffer *rx_info)
506 {
507 struct page *page = rx_info->page;
508 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
509
510 if (unlikely(!page)) {
511 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
512 "Trying to free unallocated buffer\n");
513 return;
514 }
515
516 dma_unmap_page(rx_ring->dev, ena_buf->paddr, ENA_PAGE_SIZE,
517 DMA_FROM_DEVICE);
518
519 __free_page(page);
520 rx_info->page = NULL;
521 }
522
523 static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
524 {
525 u16 next_to_use, req_id;
526 u32 i;
527 int rc;
528
529 next_to_use = rx_ring->next_to_use;
530
531 for (i = 0; i < num; i++) {
532 struct ena_rx_buffer *rx_info;
533
534 req_id = rx_ring->free_ids[next_to_use];
535 rc = validate_rx_req_id(rx_ring, req_id);
536 if (unlikely(rc < 0))
537 break;
538
539 rx_info = &rx_ring->rx_buffer_info[req_id];
540
541
542 rc = ena_alloc_rx_page(rx_ring, rx_info,
543 GFP_ATOMIC | __GFP_COMP);
544 if (unlikely(rc < 0)) {
545 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
546 "failed to alloc buffer for rx queue %d\n",
547 rx_ring->qid);
548 break;
549 }
550 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
551 &rx_info->ena_buf,
552 req_id);
553 if (unlikely(rc)) {
554 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
555 "failed to add buffer for rx queue %d\n",
556 rx_ring->qid);
557 break;
558 }
559 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
560 rx_ring->ring_size);
561 }
562
563 if (unlikely(i < num)) {
564 u64_stats_update_begin(&rx_ring->syncp);
565 rx_ring->rx_stats.refil_partial++;
566 u64_stats_update_end(&rx_ring->syncp);
567 netdev_warn(rx_ring->netdev,
568 "refilled rx qid %d with only %d buffers (from %d)\n",
569 rx_ring->qid, i, num);
570 }
571
572
573 if (likely(i))
574 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
575
576 rx_ring->next_to_use = next_to_use;
577
578 return i;
579 }
580
581 static void ena_free_rx_bufs(struct ena_adapter *adapter,
582 u32 qid)
583 {
584 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
585 u32 i;
586
587 for (i = 0; i < rx_ring->ring_size; i++) {
588 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
589
590 if (rx_info->page)
591 ena_free_rx_page(rx_ring, rx_info);
592 }
593 }
594
595
596
597
598 static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
599 {
600 struct ena_ring *rx_ring;
601 int i, rc, bufs_num;
602
603 for (i = 0; i < adapter->num_queues; i++) {
604 rx_ring = &adapter->rx_ring[i];
605 bufs_num = rx_ring->ring_size - 1;
606 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
607
608 if (unlikely(rc != bufs_num))
609 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
610 "refilling Queue %d failed. allocated %d buffers from: %d\n",
611 i, rc, bufs_num);
612 }
613 }
614
615 static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
616 {
617 int i;
618
619 for (i = 0; i < adapter->num_queues; i++)
620 ena_free_rx_bufs(adapter, i);
621 }
622
623 static void ena_unmap_tx_skb(struct ena_ring *tx_ring,
624 struct ena_tx_buffer *tx_info)
625 {
626 struct ena_com_buf *ena_buf;
627 u32 cnt;
628 int i;
629
630 ena_buf = tx_info->bufs;
631 cnt = tx_info->num_of_bufs;
632
633 if (unlikely(!cnt))
634 return;
635
636 if (tx_info->map_linear_data) {
637 dma_unmap_single(tx_ring->dev,
638 dma_unmap_addr(ena_buf, paddr),
639 dma_unmap_len(ena_buf, len),
640 DMA_TO_DEVICE);
641 ena_buf++;
642 cnt--;
643 }
644
645
646 for (i = 0; i < cnt; i++) {
647 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
648 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
649 ena_buf++;
650 }
651 }
652
653
654
655
656 static void ena_free_tx_bufs(struct ena_ring *tx_ring)
657 {
658 bool print_once = true;
659 u32 i;
660
661 for (i = 0; i < tx_ring->ring_size; i++) {
662 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
663
664 if (!tx_info->skb)
665 continue;
666
667 if (print_once) {
668 netdev_notice(tx_ring->netdev,
669 "free uncompleted tx skb qid %d idx 0x%x\n",
670 tx_ring->qid, i);
671 print_once = false;
672 } else {
673 netdev_dbg(tx_ring->netdev,
674 "free uncompleted tx skb qid %d idx 0x%x\n",
675 tx_ring->qid, i);
676 }
677
678 ena_unmap_tx_skb(tx_ring, tx_info);
679
680 dev_kfree_skb_any(tx_info->skb);
681 }
682 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
683 tx_ring->qid));
684 }
685
686 static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
687 {
688 struct ena_ring *tx_ring;
689 int i;
690
691 for (i = 0; i < adapter->num_queues; i++) {
692 tx_ring = &adapter->tx_ring[i];
693 ena_free_tx_bufs(tx_ring);
694 }
695 }
696
697 static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
698 {
699 u16 ena_qid;
700 int i;
701
702 for (i = 0; i < adapter->num_queues; i++) {
703 ena_qid = ENA_IO_TXQ_IDX(i);
704 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
705 }
706 }
707
708 static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
709 {
710 u16 ena_qid;
711 int i;
712
713 for (i = 0; i < adapter->num_queues; i++) {
714 ena_qid = ENA_IO_RXQ_IDX(i);
715 cancel_work_sync(&adapter->ena_napi[i].dim.work);
716 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
717 }
718 }
719
720 static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
721 {
722 ena_destroy_all_tx_queues(adapter);
723 ena_destroy_all_rx_queues(adapter);
724 }
725
726 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
727 {
728 struct ena_tx_buffer *tx_info = NULL;
729
730 if (likely(req_id < tx_ring->ring_size)) {
731 tx_info = &tx_ring->tx_buffer_info[req_id];
732 if (likely(tx_info->skb))
733 return 0;
734 }
735
736 if (tx_info)
737 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
738 "tx_info doesn't have valid skb\n");
739 else
740 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
741 "Invalid req_id: %hu\n", req_id);
742
743 u64_stats_update_begin(&tx_ring->syncp);
744 tx_ring->tx_stats.bad_req_id++;
745 u64_stats_update_end(&tx_ring->syncp);
746
747
748 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
749 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
750 return -EFAULT;
751 }
752
753 static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
754 {
755 struct netdev_queue *txq;
756 bool above_thresh;
757 u32 tx_bytes = 0;
758 u32 total_done = 0;
759 u16 next_to_clean;
760 u16 req_id;
761 int tx_pkts = 0;
762 int rc;
763
764 next_to_clean = tx_ring->next_to_clean;
765 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
766
767 while (tx_pkts < budget) {
768 struct ena_tx_buffer *tx_info;
769 struct sk_buff *skb;
770
771 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
772 &req_id);
773 if (rc)
774 break;
775
776 rc = validate_tx_req_id(tx_ring, req_id);
777 if (rc)
778 break;
779
780 tx_info = &tx_ring->tx_buffer_info[req_id];
781 skb = tx_info->skb;
782
783
784 prefetch(&skb->end);
785
786 tx_info->skb = NULL;
787 tx_info->last_jiffies = 0;
788
789 ena_unmap_tx_skb(tx_ring, tx_info);
790
791 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
792 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
793 skb);
794
795 tx_bytes += skb->len;
796 dev_kfree_skb(skb);
797 tx_pkts++;
798 total_done += tx_info->tx_descs;
799
800 tx_ring->free_ids[next_to_clean] = req_id;
801 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
802 tx_ring->ring_size);
803 }
804
805 tx_ring->next_to_clean = next_to_clean;
806 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
807 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
808
809 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
810
811 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
812 "tx_poll: q %d done. total pkts: %d\n",
813 tx_ring->qid, tx_pkts);
814
815
816
817
818 smp_mb();
819
820 above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
821 ENA_TX_WAKEUP_THRESH);
822 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
823 __netif_tx_lock(txq, smp_processor_id());
824 above_thresh =
825 ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
826 ENA_TX_WAKEUP_THRESH);
827 if (netif_tx_queue_stopped(txq) && above_thresh &&
828 test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags)) {
829 netif_tx_wake_queue(txq);
830 u64_stats_update_begin(&tx_ring->syncp);
831 tx_ring->tx_stats.queue_wakeup++;
832 u64_stats_update_end(&tx_ring->syncp);
833 }
834 __netif_tx_unlock(txq);
835 }
836
837 return tx_pkts;
838 }
839
840 static struct sk_buff *ena_alloc_skb(struct ena_ring *rx_ring, bool frags)
841 {
842 struct sk_buff *skb;
843
844 if (frags)
845 skb = napi_get_frags(rx_ring->napi);
846 else
847 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
848 rx_ring->rx_copybreak);
849
850 if (unlikely(!skb)) {
851 u64_stats_update_begin(&rx_ring->syncp);
852 rx_ring->rx_stats.skb_alloc_fail++;
853 u64_stats_update_end(&rx_ring->syncp);
854 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
855 "Failed to allocate skb. frags: %d\n", frags);
856 return NULL;
857 }
858
859 return skb;
860 }
861
862 static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
863 struct ena_com_rx_buf_info *ena_bufs,
864 u32 descs,
865 u16 *next_to_clean)
866 {
867 struct sk_buff *skb;
868 struct ena_rx_buffer *rx_info;
869 u16 len, req_id, buf = 0;
870 void *va;
871
872 len = ena_bufs[buf].len;
873 req_id = ena_bufs[buf].req_id;
874 rx_info = &rx_ring->rx_buffer_info[req_id];
875
876 if (unlikely(!rx_info->page)) {
877 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
878 "Page is NULL\n");
879 return NULL;
880 }
881
882 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
883 "rx_info %p page %p\n",
884 rx_info, rx_info->page);
885
886
887 va = page_address(rx_info->page) + rx_info->page_offset;
888 prefetch(va + NET_IP_ALIGN);
889
890 if (len <= rx_ring->rx_copybreak) {
891 skb = ena_alloc_skb(rx_ring, false);
892 if (unlikely(!skb))
893 return NULL;
894
895 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
896 "rx allocated small packet. len %d. data_len %d\n",
897 skb->len, skb->data_len);
898
899
900 dma_sync_single_for_cpu(rx_ring->dev,
901 dma_unmap_addr(&rx_info->ena_buf, paddr),
902 len,
903 DMA_FROM_DEVICE);
904 skb_copy_to_linear_data(skb, va, len);
905 dma_sync_single_for_device(rx_ring->dev,
906 dma_unmap_addr(&rx_info->ena_buf, paddr),
907 len,
908 DMA_FROM_DEVICE);
909
910 skb_put(skb, len);
911 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
912 rx_ring->free_ids[*next_to_clean] = req_id;
913 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
914 rx_ring->ring_size);
915 return skb;
916 }
917
918 skb = ena_alloc_skb(rx_ring, true);
919 if (unlikely(!skb))
920 return NULL;
921
922 do {
923 dma_unmap_page(rx_ring->dev,
924 dma_unmap_addr(&rx_info->ena_buf, paddr),
925 ENA_PAGE_SIZE, DMA_FROM_DEVICE);
926
927 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
928 rx_info->page_offset, len, ENA_PAGE_SIZE);
929
930 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
931 "rx skb updated. len %d. data_len %d\n",
932 skb->len, skb->data_len);
933
934 rx_info->page = NULL;
935
936 rx_ring->free_ids[*next_to_clean] = req_id;
937 *next_to_clean =
938 ENA_RX_RING_IDX_NEXT(*next_to_clean,
939 rx_ring->ring_size);
940 if (likely(--descs == 0))
941 break;
942
943 buf++;
944 len = ena_bufs[buf].len;
945 req_id = ena_bufs[buf].req_id;
946 rx_info = &rx_ring->rx_buffer_info[req_id];
947 } while (1);
948
949 return skb;
950 }
951
952
953
954
955
956
957 static void ena_rx_checksum(struct ena_ring *rx_ring,
958 struct ena_com_rx_ctx *ena_rx_ctx,
959 struct sk_buff *skb)
960 {
961
962 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
963 skb->ip_summed = CHECKSUM_NONE;
964 return;
965 }
966
967
968 if (ena_rx_ctx->frag) {
969 skb->ip_summed = CHECKSUM_NONE;
970 return;
971 }
972
973
974 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
975 (ena_rx_ctx->l3_csum_err))) {
976
977 skb->ip_summed = CHECKSUM_NONE;
978 u64_stats_update_begin(&rx_ring->syncp);
979 rx_ring->rx_stats.bad_csum++;
980 u64_stats_update_end(&rx_ring->syncp);
981 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
982 "RX IPv4 header checksum error\n");
983 return;
984 }
985
986
987 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
988 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
989 if (unlikely(ena_rx_ctx->l4_csum_err)) {
990
991 u64_stats_update_begin(&rx_ring->syncp);
992 rx_ring->rx_stats.bad_csum++;
993 u64_stats_update_end(&rx_ring->syncp);
994 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
995 "RX L4 checksum error\n");
996 skb->ip_summed = CHECKSUM_NONE;
997 return;
998 }
999
1000 if (likely(ena_rx_ctx->l4_csum_checked)) {
1001 skb->ip_summed = CHECKSUM_UNNECESSARY;
1002 u64_stats_update_begin(&rx_ring->syncp);
1003 rx_ring->rx_stats.csum_good++;
1004 u64_stats_update_end(&rx_ring->syncp);
1005 } else {
1006 u64_stats_update_begin(&rx_ring->syncp);
1007 rx_ring->rx_stats.csum_unchecked++;
1008 u64_stats_update_end(&rx_ring->syncp);
1009 skb->ip_summed = CHECKSUM_NONE;
1010 }
1011 } else {
1012 skb->ip_summed = CHECKSUM_NONE;
1013 return;
1014 }
1015
1016 }
1017
1018 static void ena_set_rx_hash(struct ena_ring *rx_ring,
1019 struct ena_com_rx_ctx *ena_rx_ctx,
1020 struct sk_buff *skb)
1021 {
1022 enum pkt_hash_types hash_type;
1023
1024 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
1025 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
1026 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
1027
1028 hash_type = PKT_HASH_TYPE_L4;
1029 else
1030 hash_type = PKT_HASH_TYPE_NONE;
1031
1032
1033 if (ena_rx_ctx->frag)
1034 hash_type = PKT_HASH_TYPE_NONE;
1035
1036 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
1037 }
1038 }
1039
1040
1041
1042
1043
1044
1045
1046
1047 static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
1048 u32 budget)
1049 {
1050 u16 next_to_clean = rx_ring->next_to_clean;
1051 u32 res_budget, work_done;
1052
1053 struct ena_com_rx_ctx ena_rx_ctx;
1054 struct ena_adapter *adapter;
1055 struct sk_buff *skb;
1056 int refill_required;
1057 int refill_threshold;
1058 int rc = 0;
1059 int total_len = 0;
1060 int rx_copybreak_pkt = 0;
1061 int i;
1062
1063 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1064 "%s qid %d\n", __func__, rx_ring->qid);
1065 res_budget = budget;
1066
1067 do {
1068 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1069 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1070 ena_rx_ctx.descs = 0;
1071 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1072 rx_ring->ena_com_io_sq,
1073 &ena_rx_ctx);
1074 if (unlikely(rc))
1075 goto error;
1076
1077 if (unlikely(ena_rx_ctx.descs == 0))
1078 break;
1079
1080 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1081 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
1082 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
1083 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
1084
1085
1086 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1087 &next_to_clean);
1088
1089
1090 if (unlikely(!skb)) {
1091 for (i = 0; i < ena_rx_ctx.descs; i++) {
1092 rx_ring->free_ids[next_to_clean] =
1093 rx_ring->ena_bufs[i].req_id;
1094 next_to_clean =
1095 ENA_RX_RING_IDX_NEXT(next_to_clean,
1096 rx_ring->ring_size);
1097 }
1098 break;
1099 }
1100
1101 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1102
1103 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1104
1105 skb_record_rx_queue(skb, rx_ring->qid);
1106
1107 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1108 total_len += rx_ring->ena_bufs[0].len;
1109 rx_copybreak_pkt++;
1110 napi_gro_receive(napi, skb);
1111 } else {
1112 total_len += skb->len;
1113 napi_gro_frags(napi);
1114 }
1115
1116 res_budget--;
1117 } while (likely(res_budget));
1118
1119 work_done = budget - res_budget;
1120 rx_ring->per_napi_packets += work_done;
1121 u64_stats_update_begin(&rx_ring->syncp);
1122 rx_ring->rx_stats.bytes += total_len;
1123 rx_ring->rx_stats.cnt += work_done;
1124 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1125 u64_stats_update_end(&rx_ring->syncp);
1126
1127 rx_ring->next_to_clean = next_to_clean;
1128
1129 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq);
1130 refill_threshold =
1131 min_t(int, rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER,
1132 ENA_RX_REFILL_THRESH_PACKET);
1133
1134
1135 if (refill_required > refill_threshold) {
1136 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1137 ena_refill_rx_bufs(rx_ring, refill_required);
1138 }
1139
1140 return work_done;
1141
1142 error:
1143 adapter = netdev_priv(rx_ring->netdev);
1144
1145 u64_stats_update_begin(&rx_ring->syncp);
1146 rx_ring->rx_stats.bad_desc_num++;
1147 u64_stats_update_end(&rx_ring->syncp);
1148
1149
1150 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1151 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1152
1153 return 0;
1154 }
1155
1156 static void ena_dim_work(struct work_struct *w)
1157 {
1158 struct dim *dim = container_of(w, struct dim, work);
1159 struct dim_cq_moder cur_moder =
1160 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1161 struct ena_napi *ena_napi = container_of(dim, struct ena_napi, dim);
1162
1163 ena_napi->rx_ring->smoothed_interval = cur_moder.usec;
1164 dim->state = DIM_START_MEASURE;
1165 }
1166
1167 static void ena_adjust_adaptive_rx_intr_moderation(struct ena_napi *ena_napi)
1168 {
1169 struct dim_sample dim_sample;
1170 struct ena_ring *rx_ring = ena_napi->rx_ring;
1171
1172 if (!rx_ring->per_napi_packets)
1173 return;
1174
1175 rx_ring->non_empty_napi_events++;
1176
1177 dim_update_sample(rx_ring->non_empty_napi_events,
1178 rx_ring->rx_stats.cnt,
1179 rx_ring->rx_stats.bytes,
1180 &dim_sample);
1181
1182 net_dim(&ena_napi->dim, dim_sample);
1183
1184 rx_ring->per_napi_packets = 0;
1185 }
1186
1187 static void ena_unmask_interrupt(struct ena_ring *tx_ring,
1188 struct ena_ring *rx_ring)
1189 {
1190 struct ena_eth_io_intr_reg intr_reg;
1191 u32 rx_interval = ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev) ?
1192 rx_ring->smoothed_interval :
1193 ena_com_get_nonadaptive_moderation_interval_rx(rx_ring->ena_dev);
1194
1195
1196
1197
1198 ena_com_update_intr_reg(&intr_reg,
1199 rx_interval,
1200 tx_ring->smoothed_interval,
1201 true);
1202
1203
1204
1205
1206
1207 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1208 }
1209
1210 static void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1211 struct ena_ring *rx_ring)
1212 {
1213 int cpu = get_cpu();
1214 int numa_node;
1215
1216
1217 if (likely(tx_ring->cpu == cpu))
1218 goto out;
1219
1220 numa_node = cpu_to_node(cpu);
1221 put_cpu();
1222
1223 if (numa_node != NUMA_NO_NODE) {
1224 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1225 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1226 }
1227
1228 tx_ring->cpu = cpu;
1229 rx_ring->cpu = cpu;
1230
1231 return;
1232 out:
1233 put_cpu();
1234 }
1235
1236 static int ena_io_poll(struct napi_struct *napi, int budget)
1237 {
1238 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1239 struct ena_ring *tx_ring, *rx_ring;
1240
1241 int tx_work_done;
1242 int rx_work_done = 0;
1243 int tx_budget;
1244 int napi_comp_call = 0;
1245 int ret;
1246
1247 tx_ring = ena_napi->tx_ring;
1248 rx_ring = ena_napi->rx_ring;
1249
1250 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1251
1252 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1253 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1254 napi_complete_done(napi, 0);
1255 return 0;
1256 }
1257
1258 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1259
1260
1261
1262 if (likely(budget))
1263 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1264
1265
1266
1267
1268 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1269 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1270 napi_complete_done(napi, 0);
1271 ret = 0;
1272
1273 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1274 napi_comp_call = 1;
1275
1276
1277
1278
1279 if (napi_complete_done(napi, rx_work_done)) {
1280
1281
1282
1283 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1284 ena_adjust_adaptive_rx_intr_moderation(ena_napi);
1285
1286 ena_unmask_interrupt(tx_ring, rx_ring);
1287 }
1288
1289 ena_update_ring_numa_node(tx_ring, rx_ring);
1290
1291 ret = rx_work_done;
1292 } else {
1293 ret = budget;
1294 }
1295
1296 u64_stats_update_begin(&tx_ring->syncp);
1297 tx_ring->tx_stats.napi_comp += napi_comp_call;
1298 tx_ring->tx_stats.tx_poll++;
1299 u64_stats_update_end(&tx_ring->syncp);
1300
1301 return ret;
1302 }
1303
1304 static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1305 {
1306 struct ena_adapter *adapter = (struct ena_adapter *)data;
1307
1308 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1309
1310
1311 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1312 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1313
1314 return IRQ_HANDLED;
1315 }
1316
1317
1318
1319
1320
1321 static irqreturn_t ena_intr_msix_io(int irq, void *data)
1322 {
1323 struct ena_napi *ena_napi = data;
1324
1325 ena_napi->tx_ring->first_interrupt = true;
1326 ena_napi->rx_ring->first_interrupt = true;
1327
1328 napi_schedule_irqoff(&ena_napi->napi);
1329
1330 return IRQ_HANDLED;
1331 }
1332
1333
1334
1335
1336
1337
1338 static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1339 {
1340 int msix_vecs, irq_cnt;
1341
1342 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1343 netif_err(adapter, probe, adapter->netdev,
1344 "Error, MSI-X is already enabled\n");
1345 return -EPERM;
1346 }
1347
1348
1349 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1350 netif_dbg(adapter, probe, adapter->netdev,
1351 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1352
1353 irq_cnt = pci_alloc_irq_vectors(adapter->pdev, ENA_MIN_MSIX_VEC,
1354 msix_vecs, PCI_IRQ_MSIX);
1355
1356 if (irq_cnt < 0) {
1357 netif_err(adapter, probe, adapter->netdev,
1358 "Failed to enable MSI-X. irq_cnt %d\n", irq_cnt);
1359 return -ENOSPC;
1360 }
1361
1362 if (irq_cnt != msix_vecs) {
1363 netif_notice(adapter, probe, adapter->netdev,
1364 "enable only %d MSI-X (out of %d), reduce the number of queues\n",
1365 irq_cnt, msix_vecs);
1366 adapter->num_queues = irq_cnt - ENA_ADMIN_MSIX_VEC;
1367 }
1368
1369 if (ena_init_rx_cpu_rmap(adapter))
1370 netif_warn(adapter, probe, adapter->netdev,
1371 "Failed to map IRQs to CPUs\n");
1372
1373 adapter->msix_vecs = irq_cnt;
1374 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags);
1375
1376 return 0;
1377 }
1378
1379 static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1380 {
1381 u32 cpu;
1382
1383 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1384 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1385 pci_name(adapter->pdev));
1386 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1387 ena_intr_msix_mgmnt;
1388 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1389 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
1390 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1391 cpu = cpumask_first(cpu_online_mask);
1392 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1393 cpumask_set_cpu(cpu,
1394 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1395 }
1396
1397 static void ena_setup_io_intr(struct ena_adapter *adapter)
1398 {
1399 struct net_device *netdev;
1400 int irq_idx, i, cpu;
1401
1402 netdev = adapter->netdev;
1403
1404 for (i = 0; i < adapter->num_queues; i++) {
1405 irq_idx = ENA_IO_IRQ_IDX(i);
1406 cpu = i % num_online_cpus();
1407
1408 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1409 "%s-Tx-Rx-%d", netdev->name, i);
1410 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1411 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1412 adapter->irq_tbl[irq_idx].vector =
1413 pci_irq_vector(adapter->pdev, irq_idx);
1414 adapter->irq_tbl[irq_idx].cpu = cpu;
1415
1416 cpumask_set_cpu(cpu,
1417 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1418 }
1419 }
1420
1421 static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1422 {
1423 unsigned long flags = 0;
1424 struct ena_irq *irq;
1425 int rc;
1426
1427 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1428 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1429 irq->data);
1430 if (rc) {
1431 netif_err(adapter, probe, adapter->netdev,
1432 "failed to request admin irq\n");
1433 return rc;
1434 }
1435
1436 netif_dbg(adapter, probe, adapter->netdev,
1437 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1438 irq->affinity_hint_mask.bits[0], irq->vector);
1439
1440 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1441
1442 return rc;
1443 }
1444
1445 static int ena_request_io_irq(struct ena_adapter *adapter)
1446 {
1447 unsigned long flags = 0;
1448 struct ena_irq *irq;
1449 int rc = 0, i, k;
1450
1451 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1452 netif_err(adapter, ifup, adapter->netdev,
1453 "Failed to request I/O IRQ: MSI-X is not enabled\n");
1454 return -EINVAL;
1455 }
1456
1457 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1458 irq = &adapter->irq_tbl[i];
1459 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1460 irq->data);
1461 if (rc) {
1462 netif_err(adapter, ifup, adapter->netdev,
1463 "Failed to request I/O IRQ. index %d rc %d\n",
1464 i, rc);
1465 goto err;
1466 }
1467
1468 netif_dbg(adapter, ifup, adapter->netdev,
1469 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1470 i, irq->affinity_hint_mask.bits[0], irq->vector);
1471
1472 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1473 }
1474
1475 return rc;
1476
1477 err:
1478 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1479 irq = &adapter->irq_tbl[k];
1480 free_irq(irq->vector, irq->data);
1481 }
1482
1483 return rc;
1484 }
1485
1486 static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1487 {
1488 struct ena_irq *irq;
1489
1490 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1491 synchronize_irq(irq->vector);
1492 irq_set_affinity_hint(irq->vector, NULL);
1493 free_irq(irq->vector, irq->data);
1494 }
1495
1496 static void ena_free_io_irq(struct ena_adapter *adapter)
1497 {
1498 struct ena_irq *irq;
1499 int i;
1500
1501 #ifdef CONFIG_RFS_ACCEL
1502 if (adapter->msix_vecs >= 1) {
1503 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1504 adapter->netdev->rx_cpu_rmap = NULL;
1505 }
1506 #endif
1507
1508 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1509 irq = &adapter->irq_tbl[i];
1510 irq_set_affinity_hint(irq->vector, NULL);
1511 free_irq(irq->vector, irq->data);
1512 }
1513 }
1514
1515 static void ena_disable_msix(struct ena_adapter *adapter)
1516 {
1517 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags))
1518 pci_free_irq_vectors(adapter->pdev);
1519 }
1520
1521 static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1522 {
1523 int i;
1524
1525 if (!netif_running(adapter->netdev))
1526 return;
1527
1528 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1529 synchronize_irq(adapter->irq_tbl[i].vector);
1530 }
1531
1532 static void ena_del_napi(struct ena_adapter *adapter)
1533 {
1534 int i;
1535
1536 for (i = 0; i < adapter->num_queues; i++)
1537 netif_napi_del(&adapter->ena_napi[i].napi);
1538 }
1539
1540 static void ena_init_napi(struct ena_adapter *adapter)
1541 {
1542 struct ena_napi *napi;
1543 int i;
1544
1545 for (i = 0; i < adapter->num_queues; i++) {
1546 napi = &adapter->ena_napi[i];
1547
1548 netif_napi_add(adapter->netdev,
1549 &adapter->ena_napi[i].napi,
1550 ena_io_poll,
1551 ENA_NAPI_BUDGET);
1552 napi->rx_ring = &adapter->rx_ring[i];
1553 napi->tx_ring = &adapter->tx_ring[i];
1554 napi->qid = i;
1555 }
1556 }
1557
1558 static void ena_napi_disable_all(struct ena_adapter *adapter)
1559 {
1560 int i;
1561
1562 for (i = 0; i < adapter->num_queues; i++)
1563 napi_disable(&adapter->ena_napi[i].napi);
1564 }
1565
1566 static void ena_napi_enable_all(struct ena_adapter *adapter)
1567 {
1568 int i;
1569
1570 for (i = 0; i < adapter->num_queues; i++)
1571 napi_enable(&adapter->ena_napi[i].napi);
1572 }
1573
1574
1575 static int ena_rss_configure(struct ena_adapter *adapter)
1576 {
1577 struct ena_com_dev *ena_dev = adapter->ena_dev;
1578 int rc;
1579
1580
1581 if (!ena_dev->rss.tbl_log_size) {
1582 rc = ena_rss_init_default(adapter);
1583 if (rc && (rc != -EOPNOTSUPP)) {
1584 netif_err(adapter, ifup, adapter->netdev,
1585 "Failed to init RSS rc: %d\n", rc);
1586 return rc;
1587 }
1588 }
1589
1590
1591 rc = ena_com_indirect_table_set(ena_dev);
1592 if (unlikely(rc && rc != -EOPNOTSUPP))
1593 return rc;
1594
1595
1596 rc = ena_com_set_hash_function(ena_dev);
1597 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1598 return rc;
1599
1600
1601 rc = ena_com_set_hash_ctrl(ena_dev);
1602 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1603 return rc;
1604
1605 return 0;
1606 }
1607
1608 static int ena_up_complete(struct ena_adapter *adapter)
1609 {
1610 int rc;
1611
1612 rc = ena_rss_configure(adapter);
1613 if (rc)
1614 return rc;
1615
1616 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1617
1618 ena_refill_all_rx_bufs(adapter);
1619
1620
1621 netif_tx_start_all_queues(adapter->netdev);
1622
1623 ena_napi_enable_all(adapter);
1624
1625 return 0;
1626 }
1627
1628 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1629 {
1630 struct ena_com_create_io_ctx ctx;
1631 struct ena_com_dev *ena_dev;
1632 struct ena_ring *tx_ring;
1633 u32 msix_vector;
1634 u16 ena_qid;
1635 int rc;
1636
1637 ena_dev = adapter->ena_dev;
1638
1639 tx_ring = &adapter->tx_ring[qid];
1640 msix_vector = ENA_IO_IRQ_IDX(qid);
1641 ena_qid = ENA_IO_TXQ_IDX(qid);
1642
1643 memset(&ctx, 0x0, sizeof(ctx));
1644
1645 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1646 ctx.qid = ena_qid;
1647 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1648 ctx.msix_vector = msix_vector;
1649 ctx.queue_size = tx_ring->ring_size;
1650 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1651
1652 rc = ena_com_create_io_queue(ena_dev, &ctx);
1653 if (rc) {
1654 netif_err(adapter, ifup, adapter->netdev,
1655 "Failed to create I/O TX queue num %d rc: %d\n",
1656 qid, rc);
1657 return rc;
1658 }
1659
1660 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1661 &tx_ring->ena_com_io_sq,
1662 &tx_ring->ena_com_io_cq);
1663 if (rc) {
1664 netif_err(adapter, ifup, adapter->netdev,
1665 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1666 qid, rc);
1667 ena_com_destroy_io_queue(ena_dev, ena_qid);
1668 return rc;
1669 }
1670
1671 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1672 return rc;
1673 }
1674
1675 static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1676 {
1677 struct ena_com_dev *ena_dev = adapter->ena_dev;
1678 int rc, i;
1679
1680 for (i = 0; i < adapter->num_queues; i++) {
1681 rc = ena_create_io_tx_queue(adapter, i);
1682 if (rc)
1683 goto create_err;
1684 }
1685
1686 return 0;
1687
1688 create_err:
1689 while (i--)
1690 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1691
1692 return rc;
1693 }
1694
1695 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1696 {
1697 struct ena_com_dev *ena_dev;
1698 struct ena_com_create_io_ctx ctx;
1699 struct ena_ring *rx_ring;
1700 u32 msix_vector;
1701 u16 ena_qid;
1702 int rc;
1703
1704 ena_dev = adapter->ena_dev;
1705
1706 rx_ring = &adapter->rx_ring[qid];
1707 msix_vector = ENA_IO_IRQ_IDX(qid);
1708 ena_qid = ENA_IO_RXQ_IDX(qid);
1709
1710 memset(&ctx, 0x0, sizeof(ctx));
1711
1712 ctx.qid = ena_qid;
1713 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1714 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1715 ctx.msix_vector = msix_vector;
1716 ctx.queue_size = rx_ring->ring_size;
1717 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1718
1719 rc = ena_com_create_io_queue(ena_dev, &ctx);
1720 if (rc) {
1721 netif_err(adapter, ifup, adapter->netdev,
1722 "Failed to create I/O RX queue num %d rc: %d\n",
1723 qid, rc);
1724 return rc;
1725 }
1726
1727 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1728 &rx_ring->ena_com_io_sq,
1729 &rx_ring->ena_com_io_cq);
1730 if (rc) {
1731 netif_err(adapter, ifup, adapter->netdev,
1732 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1733 qid, rc);
1734 ena_com_destroy_io_queue(ena_dev, ena_qid);
1735 return rc;
1736 }
1737
1738 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1739
1740 return rc;
1741 }
1742
1743 static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1744 {
1745 struct ena_com_dev *ena_dev = adapter->ena_dev;
1746 int rc, i;
1747
1748 for (i = 0; i < adapter->num_queues; i++) {
1749 rc = ena_create_io_rx_queue(adapter, i);
1750 if (rc)
1751 goto create_err;
1752 INIT_WORK(&adapter->ena_napi[i].dim.work, ena_dim_work);
1753 }
1754
1755 return 0;
1756
1757 create_err:
1758 while (i--) {
1759 cancel_work_sync(&adapter->ena_napi[i].dim.work);
1760 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1761 }
1762
1763 return rc;
1764 }
1765
1766 static void set_io_rings_size(struct ena_adapter *adapter,
1767 int new_tx_size, int new_rx_size)
1768 {
1769 int i;
1770
1771 for (i = 0; i < adapter->num_queues; i++) {
1772 adapter->tx_ring[i].ring_size = new_tx_size;
1773 adapter->rx_ring[i].ring_size = new_rx_size;
1774 }
1775 }
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792 static int create_queues_with_size_backoff(struct ena_adapter *adapter)
1793 {
1794 int rc, cur_rx_ring_size, cur_tx_ring_size;
1795 int new_rx_ring_size, new_tx_ring_size;
1796
1797
1798
1799
1800 set_io_rings_size(adapter, adapter->requested_tx_ring_size,
1801 adapter->requested_rx_ring_size);
1802
1803 while (1) {
1804 rc = ena_setup_all_tx_resources(adapter);
1805 if (rc)
1806 goto err_setup_tx;
1807
1808 rc = ena_create_all_io_tx_queues(adapter);
1809 if (rc)
1810 goto err_create_tx_queues;
1811
1812 rc = ena_setup_all_rx_resources(adapter);
1813 if (rc)
1814 goto err_setup_rx;
1815
1816 rc = ena_create_all_io_rx_queues(adapter);
1817 if (rc)
1818 goto err_create_rx_queues;
1819
1820 return 0;
1821
1822 err_create_rx_queues:
1823 ena_free_all_io_rx_resources(adapter);
1824 err_setup_rx:
1825 ena_destroy_all_tx_queues(adapter);
1826 err_create_tx_queues:
1827 ena_free_all_io_tx_resources(adapter);
1828 err_setup_tx:
1829 if (rc != -ENOMEM) {
1830 netif_err(adapter, ifup, adapter->netdev,
1831 "Queue creation failed with error code %d\n",
1832 rc);
1833 return rc;
1834 }
1835
1836 cur_tx_ring_size = adapter->tx_ring[0].ring_size;
1837 cur_rx_ring_size = adapter->rx_ring[0].ring_size;
1838
1839 netif_err(adapter, ifup, adapter->netdev,
1840 "Not enough memory to create queues with sizes TX=%d, RX=%d\n",
1841 cur_tx_ring_size, cur_rx_ring_size);
1842
1843 new_tx_ring_size = cur_tx_ring_size;
1844 new_rx_ring_size = cur_rx_ring_size;
1845
1846
1847
1848
1849 if (cur_rx_ring_size <= cur_tx_ring_size)
1850 new_tx_ring_size = cur_tx_ring_size / 2;
1851 if (cur_rx_ring_size >= cur_tx_ring_size)
1852 new_rx_ring_size = cur_rx_ring_size / 2;
1853
1854 if (new_tx_ring_size < ENA_MIN_RING_SIZE ||
1855 new_rx_ring_size < ENA_MIN_RING_SIZE) {
1856 netif_err(adapter, ifup, adapter->netdev,
1857 "Queue creation failed with the smallest possible queue size of %d for both queues. Not retrying with smaller queues\n",
1858 ENA_MIN_RING_SIZE);
1859 return rc;
1860 }
1861
1862 netif_err(adapter, ifup, adapter->netdev,
1863 "Retrying queue creation with sizes TX=%d, RX=%d\n",
1864 new_tx_ring_size,
1865 new_rx_ring_size);
1866
1867 set_io_rings_size(adapter, new_tx_ring_size,
1868 new_rx_ring_size);
1869 }
1870 }
1871
1872 static int ena_up(struct ena_adapter *adapter)
1873 {
1874 int rc, i;
1875
1876 netdev_dbg(adapter->netdev, "%s\n", __func__);
1877
1878 ena_setup_io_intr(adapter);
1879
1880
1881
1882
1883
1884
1885 ena_init_napi(adapter);
1886
1887 rc = ena_request_io_irq(adapter);
1888 if (rc)
1889 goto err_req_irq;
1890
1891 rc = create_queues_with_size_backoff(adapter);
1892 if (rc)
1893 goto err_create_queues_with_backoff;
1894
1895 rc = ena_up_complete(adapter);
1896 if (rc)
1897 goto err_up;
1898
1899 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1900 netif_carrier_on(adapter->netdev);
1901
1902 u64_stats_update_begin(&adapter->syncp);
1903 adapter->dev_stats.interface_up++;
1904 u64_stats_update_end(&adapter->syncp);
1905
1906 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1907
1908
1909 for (i = 0; i < adapter->num_queues; i++)
1910 ena_unmask_interrupt(&adapter->tx_ring[i],
1911 &adapter->rx_ring[i]);
1912
1913
1914
1915
1916 for (i = 0; i < adapter->num_queues; i++)
1917 napi_schedule(&adapter->ena_napi[i].napi);
1918
1919 return rc;
1920
1921 err_up:
1922 ena_destroy_all_tx_queues(adapter);
1923 ena_free_all_io_tx_resources(adapter);
1924 ena_destroy_all_rx_queues(adapter);
1925 ena_free_all_io_rx_resources(adapter);
1926 err_create_queues_with_backoff:
1927 ena_free_io_irq(adapter);
1928 err_req_irq:
1929 ena_del_napi(adapter);
1930
1931 return rc;
1932 }
1933
1934 static void ena_down(struct ena_adapter *adapter)
1935 {
1936 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1937
1938 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1939
1940 u64_stats_update_begin(&adapter->syncp);
1941 adapter->dev_stats.interface_down++;
1942 u64_stats_update_end(&adapter->syncp);
1943
1944 netif_carrier_off(adapter->netdev);
1945 netif_tx_disable(adapter->netdev);
1946
1947
1948 ena_napi_disable_all(adapter);
1949
1950
1951
1952 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1953 int rc;
1954
1955 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
1956 if (rc)
1957 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1958
1959 ena_com_set_admin_running_state(adapter->ena_dev, false);
1960 }
1961
1962 ena_destroy_all_io_queues(adapter);
1963
1964 ena_disable_io_intr_sync(adapter);
1965 ena_free_io_irq(adapter);
1966 ena_del_napi(adapter);
1967
1968 ena_free_all_tx_bufs(adapter);
1969 ena_free_all_rx_bufs(adapter);
1970 ena_free_all_io_tx_resources(adapter);
1971 ena_free_all_io_rx_resources(adapter);
1972 }
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985 static int ena_open(struct net_device *netdev)
1986 {
1987 struct ena_adapter *adapter = netdev_priv(netdev);
1988 int rc;
1989
1990
1991 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1992 if (rc) {
1993 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1994 return rc;
1995 }
1996
1997 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1998 if (rc) {
1999 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
2000 return rc;
2001 }
2002
2003 rc = ena_up(adapter);
2004 if (rc)
2005 return rc;
2006
2007 return rc;
2008 }
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020 static int ena_close(struct net_device *netdev)
2021 {
2022 struct ena_adapter *adapter = netdev_priv(netdev);
2023
2024 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
2025
2026 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
2027 return 0;
2028
2029 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2030 ena_down(adapter);
2031
2032
2033 check_for_admin_com_state(adapter);
2034 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2035 netif_err(adapter, ifdown, adapter->netdev,
2036 "Destroy failure, restarting device\n");
2037 ena_dump_stats_to_dmesg(adapter);
2038
2039 ena_destroy_device(adapter, false);
2040 ena_restore_device(adapter);
2041 }
2042
2043 return 0;
2044 }
2045
2046 int ena_update_queue_sizes(struct ena_adapter *adapter,
2047 u32 new_tx_size,
2048 u32 new_rx_size)
2049 {
2050 bool dev_up;
2051
2052 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2053 ena_close(adapter->netdev);
2054 adapter->requested_tx_ring_size = new_tx_size;
2055 adapter->requested_rx_ring_size = new_rx_size;
2056 ena_init_io_rings(adapter);
2057 return dev_up ? ena_up(adapter) : 0;
2058 }
2059
2060 static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
2061 {
2062 u32 mss = skb_shinfo(skb)->gso_size;
2063 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
2064 u8 l4_protocol = 0;
2065
2066 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
2067 ena_tx_ctx->l4_csum_enable = 1;
2068 if (mss) {
2069 ena_tx_ctx->tso_enable = 1;
2070 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
2071 ena_tx_ctx->l4_csum_partial = 0;
2072 } else {
2073 ena_tx_ctx->tso_enable = 0;
2074 ena_meta->l4_hdr_len = 0;
2075 ena_tx_ctx->l4_csum_partial = 1;
2076 }
2077
2078 switch (ip_hdr(skb)->version) {
2079 case IPVERSION:
2080 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
2081 if (ip_hdr(skb)->frag_off & htons(IP_DF))
2082 ena_tx_ctx->df = 1;
2083 if (mss)
2084 ena_tx_ctx->l3_csum_enable = 1;
2085 l4_protocol = ip_hdr(skb)->protocol;
2086 break;
2087 case 6:
2088 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
2089 l4_protocol = ipv6_hdr(skb)->nexthdr;
2090 break;
2091 default:
2092 break;
2093 }
2094
2095 if (l4_protocol == IPPROTO_TCP)
2096 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
2097 else
2098 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
2099
2100 ena_meta->mss = mss;
2101 ena_meta->l3_hdr_len = skb_network_header_len(skb);
2102 ena_meta->l3_hdr_offset = skb_network_offset(skb);
2103 ena_tx_ctx->meta_valid = 1;
2104
2105 } else {
2106 ena_tx_ctx->meta_valid = 0;
2107 }
2108 }
2109
2110 static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
2111 struct sk_buff *skb)
2112 {
2113 int num_frags, header_len, rc;
2114
2115 num_frags = skb_shinfo(skb)->nr_frags;
2116 header_len = skb_headlen(skb);
2117
2118 if (num_frags < tx_ring->sgl_size)
2119 return 0;
2120
2121 if ((num_frags == tx_ring->sgl_size) &&
2122 (header_len < tx_ring->tx_max_header_size))
2123 return 0;
2124
2125 u64_stats_update_begin(&tx_ring->syncp);
2126 tx_ring->tx_stats.linearize++;
2127 u64_stats_update_end(&tx_ring->syncp);
2128
2129 rc = skb_linearize(skb);
2130 if (unlikely(rc)) {
2131 u64_stats_update_begin(&tx_ring->syncp);
2132 tx_ring->tx_stats.linearize_failed++;
2133 u64_stats_update_end(&tx_ring->syncp);
2134 }
2135
2136 return rc;
2137 }
2138
2139 static int ena_tx_map_skb(struct ena_ring *tx_ring,
2140 struct ena_tx_buffer *tx_info,
2141 struct sk_buff *skb,
2142 void **push_hdr,
2143 u16 *header_len)
2144 {
2145 struct ena_adapter *adapter = tx_ring->adapter;
2146 struct ena_com_buf *ena_buf;
2147 dma_addr_t dma;
2148 u32 skb_head_len, frag_len, last_frag;
2149 u16 push_len = 0;
2150 u16 delta = 0;
2151 int i = 0;
2152
2153 skb_head_len = skb_headlen(skb);
2154 tx_info->skb = skb;
2155 ena_buf = tx_info->bufs;
2156
2157 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168 push_len = min_t(u32, skb->len, tx_ring->tx_max_header_size);
2169 *push_hdr = skb_header_pointer(skb, 0, push_len,
2170 tx_ring->push_buf_intermediate_buf);
2171 *header_len = push_len;
2172 if (unlikely(skb->data != *push_hdr)) {
2173 u64_stats_update_begin(&tx_ring->syncp);
2174 tx_ring->tx_stats.llq_buffer_copy++;
2175 u64_stats_update_end(&tx_ring->syncp);
2176
2177 delta = push_len - skb_head_len;
2178 }
2179 } else {
2180 *push_hdr = NULL;
2181 *header_len = min_t(u32, skb_head_len,
2182 tx_ring->tx_max_header_size);
2183 }
2184
2185 netif_dbg(adapter, tx_queued, adapter->netdev,
2186 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
2187 *push_hdr, push_len);
2188
2189 if (skb_head_len > push_len) {
2190 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
2191 skb_head_len - push_len, DMA_TO_DEVICE);
2192 if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
2193 goto error_report_dma_error;
2194
2195 ena_buf->paddr = dma;
2196 ena_buf->len = skb_head_len - push_len;
2197
2198 ena_buf++;
2199 tx_info->num_of_bufs++;
2200 tx_info->map_linear_data = 1;
2201 } else {
2202 tx_info->map_linear_data = 0;
2203 }
2204
2205 last_frag = skb_shinfo(skb)->nr_frags;
2206
2207 for (i = 0; i < last_frag; i++) {
2208 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2209
2210 frag_len = skb_frag_size(frag);
2211
2212 if (unlikely(delta >= frag_len)) {
2213 delta -= frag_len;
2214 continue;
2215 }
2216
2217 dma = skb_frag_dma_map(tx_ring->dev, frag, delta,
2218 frag_len - delta, DMA_TO_DEVICE);
2219 if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
2220 goto error_report_dma_error;
2221
2222 ena_buf->paddr = dma;
2223 ena_buf->len = frag_len - delta;
2224 ena_buf++;
2225 tx_info->num_of_bufs++;
2226 delta = 0;
2227 }
2228
2229 return 0;
2230
2231 error_report_dma_error:
2232 u64_stats_update_begin(&tx_ring->syncp);
2233 tx_ring->tx_stats.dma_mapping_err++;
2234 u64_stats_update_end(&tx_ring->syncp);
2235 netdev_warn(adapter->netdev, "failed to map skb\n");
2236
2237 tx_info->skb = NULL;
2238
2239 tx_info->num_of_bufs += i;
2240 ena_unmap_tx_skb(tx_ring, tx_info);
2241
2242 return -EINVAL;
2243 }
2244
2245
2246 static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
2247 {
2248 struct ena_adapter *adapter = netdev_priv(dev);
2249 struct ena_tx_buffer *tx_info;
2250 struct ena_com_tx_ctx ena_tx_ctx;
2251 struct ena_ring *tx_ring;
2252 struct netdev_queue *txq;
2253 void *push_hdr;
2254 u16 next_to_use, req_id, header_len;
2255 int qid, rc, nb_hw_desc;
2256
2257 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
2258
2259 qid = skb_get_queue_mapping(skb);
2260 tx_ring = &adapter->tx_ring[qid];
2261 txq = netdev_get_tx_queue(dev, qid);
2262
2263 rc = ena_check_and_linearize_skb(tx_ring, skb);
2264 if (unlikely(rc))
2265 goto error_drop_packet;
2266
2267 skb_tx_timestamp(skb);
2268
2269 next_to_use = tx_ring->next_to_use;
2270 req_id = tx_ring->free_ids[next_to_use];
2271 tx_info = &tx_ring->tx_buffer_info[req_id];
2272 tx_info->num_of_bufs = 0;
2273
2274 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
2275
2276 rc = ena_tx_map_skb(tx_ring, tx_info, skb, &push_hdr, &header_len);
2277 if (unlikely(rc))
2278 goto error_drop_packet;
2279
2280 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2281 ena_tx_ctx.ena_bufs = tx_info->bufs;
2282 ena_tx_ctx.push_header = push_hdr;
2283 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2284 ena_tx_ctx.req_id = req_id;
2285 ena_tx_ctx.header_len = header_len;
2286
2287
2288 ena_tx_csum(&ena_tx_ctx, skb);
2289
2290 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx))) {
2291 netif_dbg(adapter, tx_queued, dev,
2292 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2293 qid);
2294 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2295 }
2296
2297
2298 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2299 &nb_hw_desc);
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309 if (unlikely(rc)) {
2310 netif_err(adapter, tx_queued, dev,
2311 "failed to prepare tx bufs\n");
2312 u64_stats_update_begin(&tx_ring->syncp);
2313 tx_ring->tx_stats.prepare_ctx_err++;
2314 u64_stats_update_end(&tx_ring->syncp);
2315 adapter->reset_reason = ENA_REGS_RESET_DRIVER_INVALID_STATE;
2316 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2317 goto error_unmap_dma;
2318 }
2319
2320 netdev_tx_sent_queue(txq, skb->len);
2321
2322 u64_stats_update_begin(&tx_ring->syncp);
2323 tx_ring->tx_stats.cnt++;
2324 tx_ring->tx_stats.bytes += skb->len;
2325 u64_stats_update_end(&tx_ring->syncp);
2326
2327 tx_info->tx_descs = nb_hw_desc;
2328 tx_info->last_jiffies = jiffies;
2329 tx_info->print_once = 0;
2330
2331 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2332 tx_ring->ring_size);
2333
2334
2335
2336
2337
2338 if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2339 tx_ring->sgl_size + 2))) {
2340 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2341 __func__, qid);
2342
2343 netif_tx_stop_queue(txq);
2344 u64_stats_update_begin(&tx_ring->syncp);
2345 tx_ring->tx_stats.queue_stop++;
2346 u64_stats_update_end(&tx_ring->syncp);
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356 smp_mb();
2357
2358 if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2359 ENA_TX_WAKEUP_THRESH)) {
2360 netif_tx_wake_queue(txq);
2361 u64_stats_update_begin(&tx_ring->syncp);
2362 tx_ring->tx_stats.queue_wakeup++;
2363 u64_stats_update_end(&tx_ring->syncp);
2364 }
2365 }
2366
2367 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) {
2368
2369
2370
2371 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2372 u64_stats_update_begin(&tx_ring->syncp);
2373 tx_ring->tx_stats.doorbells++;
2374 u64_stats_update_end(&tx_ring->syncp);
2375 }
2376
2377 return NETDEV_TX_OK;
2378
2379 error_unmap_dma:
2380 ena_unmap_tx_skb(tx_ring, tx_info);
2381 tx_info->skb = NULL;
2382
2383 error_drop_packet:
2384 dev_kfree_skb(skb);
2385 return NETDEV_TX_OK;
2386 }
2387
2388 static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2389 struct net_device *sb_dev)
2390 {
2391 u16 qid;
2392
2393
2394
2395
2396 if (skb_rx_queue_recorded(skb))
2397 qid = skb_get_rx_queue(skb);
2398 else
2399 qid = netdev_pick_tx(dev, skb, NULL);
2400
2401 return qid;
2402 }
2403
2404 static void ena_config_host_info(struct ena_com_dev *ena_dev,
2405 struct pci_dev *pdev)
2406 {
2407 struct ena_admin_host_info *host_info;
2408 int rc;
2409
2410
2411 rc = ena_com_allocate_host_info(ena_dev);
2412 if (rc) {
2413 pr_err("Cannot allocate host info\n");
2414 return;
2415 }
2416
2417 host_info = ena_dev->host_attr.host_info;
2418
2419 host_info->bdf = (pdev->bus->number << 8) | pdev->devfn;
2420 host_info->os_type = ENA_ADMIN_OS_LINUX;
2421 host_info->kernel_ver = LINUX_VERSION_CODE;
2422 strlcpy(host_info->kernel_ver_str, utsname()->version,
2423 sizeof(host_info->kernel_ver_str) - 1);
2424 host_info->os_dist = 0;
2425 strncpy(host_info->os_dist_str, utsname()->release,
2426 sizeof(host_info->os_dist_str) - 1);
2427 host_info->driver_version =
2428 (DRV_MODULE_VER_MAJOR) |
2429 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2430 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) |
2431 ("K"[0] << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT);
2432 host_info->num_cpus = num_online_cpus();
2433
2434 host_info->driver_supported_features =
2435 ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
2436
2437 rc = ena_com_set_host_attributes(ena_dev);
2438 if (rc) {
2439 if (rc == -EOPNOTSUPP)
2440 pr_warn("Cannot set host attributes\n");
2441 else
2442 pr_err("Cannot set host attributes\n");
2443
2444 goto err;
2445 }
2446
2447 return;
2448
2449 err:
2450 ena_com_delete_host_info(ena_dev);
2451 }
2452
2453 static void ena_config_debug_area(struct ena_adapter *adapter)
2454 {
2455 u32 debug_area_size;
2456 int rc, ss_count;
2457
2458 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2459 if (ss_count <= 0) {
2460 netif_err(adapter, drv, adapter->netdev,
2461 "SS count is negative\n");
2462 return;
2463 }
2464
2465
2466 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2467
2468 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2469 if (rc) {
2470 pr_err("Cannot allocate debug area\n");
2471 return;
2472 }
2473
2474 rc = ena_com_set_host_attributes(adapter->ena_dev);
2475 if (rc) {
2476 if (rc == -EOPNOTSUPP)
2477 netif_warn(adapter, drv, adapter->netdev,
2478 "Cannot set host attributes\n");
2479 else
2480 netif_err(adapter, drv, adapter->netdev,
2481 "Cannot set host attributes\n");
2482 goto err;
2483 }
2484
2485 return;
2486 err:
2487 ena_com_delete_debug_area(adapter->ena_dev);
2488 }
2489
2490 static void ena_get_stats64(struct net_device *netdev,
2491 struct rtnl_link_stats64 *stats)
2492 {
2493 struct ena_adapter *adapter = netdev_priv(netdev);
2494 struct ena_ring *rx_ring, *tx_ring;
2495 unsigned int start;
2496 u64 rx_drops;
2497 int i;
2498
2499 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2500 return;
2501
2502 for (i = 0; i < adapter->num_queues; i++) {
2503 u64 bytes, packets;
2504
2505 tx_ring = &adapter->tx_ring[i];
2506
2507 do {
2508 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2509 packets = tx_ring->tx_stats.cnt;
2510 bytes = tx_ring->tx_stats.bytes;
2511 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
2512
2513 stats->tx_packets += packets;
2514 stats->tx_bytes += bytes;
2515
2516 rx_ring = &adapter->rx_ring[i];
2517
2518 do {
2519 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2520 packets = rx_ring->rx_stats.cnt;
2521 bytes = rx_ring->rx_stats.bytes;
2522 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2523
2524 stats->rx_packets += packets;
2525 stats->rx_bytes += bytes;
2526 }
2527
2528 do {
2529 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2530 rx_drops = adapter->dev_stats.rx_drops;
2531 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
2532
2533 stats->rx_dropped = rx_drops;
2534
2535 stats->multicast = 0;
2536 stats->collisions = 0;
2537
2538 stats->rx_length_errors = 0;
2539 stats->rx_crc_errors = 0;
2540 stats->rx_frame_errors = 0;
2541 stats->rx_fifo_errors = 0;
2542 stats->rx_missed_errors = 0;
2543 stats->tx_window_errors = 0;
2544
2545 stats->rx_errors = 0;
2546 stats->tx_errors = 0;
2547 }
2548
2549 static const struct net_device_ops ena_netdev_ops = {
2550 .ndo_open = ena_open,
2551 .ndo_stop = ena_close,
2552 .ndo_start_xmit = ena_start_xmit,
2553 .ndo_select_queue = ena_select_queue,
2554 .ndo_get_stats64 = ena_get_stats64,
2555 .ndo_tx_timeout = ena_tx_timeout,
2556 .ndo_change_mtu = ena_change_mtu,
2557 .ndo_set_mac_address = NULL,
2558 .ndo_validate_addr = eth_validate_addr,
2559 };
2560
2561 static int ena_device_validate_params(struct ena_adapter *adapter,
2562 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2563 {
2564 struct net_device *netdev = adapter->netdev;
2565 int rc;
2566
2567 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2568 adapter->mac_addr);
2569 if (!rc) {
2570 netif_err(adapter, drv, netdev,
2571 "Error, mac address are different\n");
2572 return -EINVAL;
2573 }
2574
2575 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2576 netif_err(adapter, drv, netdev,
2577 "Error, device max mtu is smaller than netdev MTU\n");
2578 return -EINVAL;
2579 }
2580
2581 return 0;
2582 }
2583
2584 static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2585 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2586 bool *wd_state)
2587 {
2588 struct device *dev = &pdev->dev;
2589 bool readless_supported;
2590 u32 aenq_groups;
2591 int dma_width;
2592 int rc;
2593
2594 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2595 if (rc) {
2596 dev_err(dev, "failed to init mmio read less\n");
2597 return rc;
2598 }
2599
2600
2601
2602
2603 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2604 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2605
2606 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
2607 if (rc) {
2608 dev_err(dev, "Can not reset device\n");
2609 goto err_mmio_read_less;
2610 }
2611
2612 rc = ena_com_validate_version(ena_dev);
2613 if (rc) {
2614 dev_err(dev, "device version is too low\n");
2615 goto err_mmio_read_less;
2616 }
2617
2618 dma_width = ena_com_get_dma_width(ena_dev);
2619 if (dma_width < 0) {
2620 dev_err(dev, "Invalid dma width value %d", dma_width);
2621 rc = dma_width;
2622 goto err_mmio_read_less;
2623 }
2624
2625 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2626 if (rc) {
2627 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2628 goto err_mmio_read_less;
2629 }
2630
2631 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2632 if (rc) {
2633 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2634 rc);
2635 goto err_mmio_read_less;
2636 }
2637
2638
2639 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
2640 if (rc) {
2641 dev_err(dev,
2642 "Can not initialize ena admin queue with device\n");
2643 goto err_mmio_read_less;
2644 }
2645
2646
2647
2648
2649
2650 ena_com_set_admin_polling_mode(ena_dev, true);
2651
2652 ena_config_host_info(ena_dev, pdev);
2653
2654
2655 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2656 if (rc) {
2657 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2658 goto err_admin_init;
2659 }
2660
2661
2662 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2663 BIT(ENA_ADMIN_FATAL_ERROR) |
2664 BIT(ENA_ADMIN_WARNING) |
2665 BIT(ENA_ADMIN_NOTIFICATION) |
2666 BIT(ENA_ADMIN_KEEP_ALIVE);
2667
2668 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2669
2670 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2671 if (rc) {
2672 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2673 goto err_admin_init;
2674 }
2675
2676 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2677
2678 return 0;
2679
2680 err_admin_init:
2681 ena_com_delete_host_info(ena_dev);
2682 ena_com_admin_destroy(ena_dev);
2683 err_mmio_read_less:
2684 ena_com_mmio_reg_read_request_destroy(ena_dev);
2685
2686 return rc;
2687 }
2688
2689 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2690 int io_vectors)
2691 {
2692 struct ena_com_dev *ena_dev = adapter->ena_dev;
2693 struct device *dev = &adapter->pdev->dev;
2694 int rc;
2695
2696 rc = ena_enable_msix(adapter, io_vectors);
2697 if (rc) {
2698 dev_err(dev, "Can not reserve msix vectors\n");
2699 return rc;
2700 }
2701
2702 ena_setup_mgmnt_intr(adapter);
2703
2704 rc = ena_request_mgmnt_irq(adapter);
2705 if (rc) {
2706 dev_err(dev, "Can not setup management interrupts\n");
2707 goto err_disable_msix;
2708 }
2709
2710 ena_com_set_admin_polling_mode(ena_dev, false);
2711
2712 ena_com_admin_aenq_enable(ena_dev);
2713
2714 return 0;
2715
2716 err_disable_msix:
2717 ena_disable_msix(adapter);
2718
2719 return rc;
2720 }
2721
2722 static void ena_destroy_device(struct ena_adapter *adapter, bool graceful)
2723 {
2724 struct net_device *netdev = adapter->netdev;
2725 struct ena_com_dev *ena_dev = adapter->ena_dev;
2726 bool dev_up;
2727
2728 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
2729 return;
2730
2731 netif_carrier_off(netdev);
2732
2733 del_timer_sync(&adapter->timer_service);
2734
2735 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2736 adapter->dev_up_before_reset = dev_up;
2737 if (!graceful)
2738 ena_com_set_admin_running_state(ena_dev, false);
2739
2740 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2741 ena_down(adapter);
2742
2743
2744
2745
2746 if (!(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags) && dev_up))
2747 ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
2748
2749 ena_free_mgmnt_irq(adapter);
2750
2751 ena_disable_msix(adapter);
2752
2753 ena_com_abort_admin_commands(ena_dev);
2754
2755 ena_com_wait_for_abort_completion(ena_dev);
2756
2757 ena_com_admin_destroy(ena_dev);
2758
2759 ena_com_mmio_reg_read_request_destroy(ena_dev);
2760
2761 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
2762
2763 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2764 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2765 }
2766
2767 static int ena_restore_device(struct ena_adapter *adapter)
2768 {
2769 struct ena_com_dev_get_features_ctx get_feat_ctx;
2770 struct ena_com_dev *ena_dev = adapter->ena_dev;
2771 struct pci_dev *pdev = adapter->pdev;
2772 bool wd_state;
2773 int rc;
2774
2775 set_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2776 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2777 if (rc) {
2778 dev_err(&pdev->dev, "Can not initialize device\n");
2779 goto err;
2780 }
2781 adapter->wd_state = wd_state;
2782
2783 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2784 if (rc) {
2785 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2786 goto err_device_destroy;
2787 }
2788
2789 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2790 adapter->num_queues);
2791 if (rc) {
2792 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2793 goto err_device_destroy;
2794 }
2795
2796 if (adapter->dev_up_before_reset) {
2797 rc = ena_up(adapter);
2798 if (rc) {
2799 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2800 goto err_disable_msix;
2801 }
2802 }
2803
2804 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2805
2806 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2807 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
2808 netif_carrier_on(adapter->netdev);
2809
2810 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2811 dev_err(&pdev->dev,
2812 "Device reset completed successfully, Driver info: %s\n",
2813 version);
2814
2815 return rc;
2816 err_disable_msix:
2817 ena_free_mgmnt_irq(adapter);
2818 ena_disable_msix(adapter);
2819 err_device_destroy:
2820 ena_com_abort_admin_commands(ena_dev);
2821 ena_com_wait_for_abort_completion(ena_dev);
2822 ena_com_admin_destroy(ena_dev);
2823 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_DRIVER_INVALID_STATE);
2824 ena_com_mmio_reg_read_request_destroy(ena_dev);
2825 err:
2826 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2827 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2828 dev_err(&pdev->dev,
2829 "Reset attempt failed. Can not reset the device\n");
2830
2831 return rc;
2832 }
2833
2834 static void ena_fw_reset_device(struct work_struct *work)
2835 {
2836 struct ena_adapter *adapter =
2837 container_of(work, struct ena_adapter, reset_task);
2838 struct pci_dev *pdev = adapter->pdev;
2839
2840 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2841 dev_err(&pdev->dev,
2842 "device reset schedule while reset bit is off\n");
2843 return;
2844 }
2845 rtnl_lock();
2846 ena_destroy_device(adapter, false);
2847 ena_restore_device(adapter);
2848 rtnl_unlock();
2849 }
2850
2851 static int check_for_rx_interrupt_queue(struct ena_adapter *adapter,
2852 struct ena_ring *rx_ring)
2853 {
2854 if (likely(rx_ring->first_interrupt))
2855 return 0;
2856
2857 if (ena_com_cq_empty(rx_ring->ena_com_io_cq))
2858 return 0;
2859
2860 rx_ring->no_interrupt_event_cnt++;
2861
2862 if (rx_ring->no_interrupt_event_cnt == ENA_MAX_NO_INTERRUPT_ITERATIONS) {
2863 netif_err(adapter, rx_err, adapter->netdev,
2864 "Potential MSIX issue on Rx side Queue = %d. Reset the device\n",
2865 rx_ring->qid);
2866 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2867 smp_mb__before_atomic();
2868 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2869 return -EIO;
2870 }
2871
2872 return 0;
2873 }
2874
2875 static int check_missing_comp_in_tx_queue(struct ena_adapter *adapter,
2876 struct ena_ring *tx_ring)
2877 {
2878 struct ena_tx_buffer *tx_buf;
2879 unsigned long last_jiffies;
2880 u32 missed_tx = 0;
2881 int i, rc = 0;
2882
2883 for (i = 0; i < tx_ring->ring_size; i++) {
2884 tx_buf = &tx_ring->tx_buffer_info[i];
2885 last_jiffies = tx_buf->last_jiffies;
2886
2887 if (last_jiffies == 0)
2888
2889 continue;
2890
2891 if (unlikely(!tx_ring->first_interrupt && time_is_before_jiffies(last_jiffies +
2892 2 * adapter->missing_tx_completion_to))) {
2893
2894
2895
2896 netif_err(adapter, tx_err, adapter->netdev,
2897 "Potential MSIX issue on Tx side Queue = %d. Reset the device\n",
2898 tx_ring->qid);
2899 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2900 smp_mb__before_atomic();
2901 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2902 return -EIO;
2903 }
2904
2905 if (unlikely(time_is_before_jiffies(last_jiffies +
2906 adapter->missing_tx_completion_to))) {
2907 if (!tx_buf->print_once)
2908 netif_notice(adapter, tx_err, adapter->netdev,
2909 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2910 tx_ring->qid, i);
2911
2912 tx_buf->print_once = 1;
2913 missed_tx++;
2914 }
2915 }
2916
2917 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) {
2918 netif_err(adapter, tx_err, adapter->netdev,
2919 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
2920 missed_tx,
2921 adapter->missing_tx_completion_threshold);
2922 adapter->reset_reason =
2923 ENA_REGS_RESET_MISS_TX_CMPL;
2924 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2925 rc = -EIO;
2926 }
2927
2928 u64_stats_update_begin(&tx_ring->syncp);
2929 tx_ring->tx_stats.missed_tx = missed_tx;
2930 u64_stats_update_end(&tx_ring->syncp);
2931
2932 return rc;
2933 }
2934
2935 static void check_for_missing_completions(struct ena_adapter *adapter)
2936 {
2937 struct ena_ring *tx_ring;
2938 struct ena_ring *rx_ring;
2939 int i, budget, rc;
2940
2941
2942 smp_rmb();
2943
2944 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2945 return;
2946
2947 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2948 return;
2949
2950 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
2951 return;
2952
2953 budget = ENA_MONITORED_TX_QUEUES;
2954
2955 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2956 tx_ring = &adapter->tx_ring[i];
2957 rx_ring = &adapter->rx_ring[i];
2958
2959 rc = check_missing_comp_in_tx_queue(adapter, tx_ring);
2960 if (unlikely(rc))
2961 return;
2962
2963 rc = check_for_rx_interrupt_queue(adapter, rx_ring);
2964 if (unlikely(rc))
2965 return;
2966
2967 budget--;
2968 if (!budget)
2969 break;
2970 }
2971
2972 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2973 }
2974
2975
2976 #define EMPTY_RX_REFILL 2
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991 static void check_for_empty_rx_ring(struct ena_adapter *adapter)
2992 {
2993 struct ena_ring *rx_ring;
2994 int i, refill_required;
2995
2996 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2997 return;
2998
2999 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
3000 return;
3001
3002 for (i = 0; i < adapter->num_queues; i++) {
3003 rx_ring = &adapter->rx_ring[i];
3004
3005 refill_required =
3006 ena_com_free_desc(rx_ring->ena_com_io_sq);
3007 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
3008 rx_ring->empty_rx_queue++;
3009
3010 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
3011 u64_stats_update_begin(&rx_ring->syncp);
3012 rx_ring->rx_stats.empty_rx_ring++;
3013 u64_stats_update_end(&rx_ring->syncp);
3014
3015 netif_err(adapter, drv, adapter->netdev,
3016 "trigger refill for ring %d\n", i);
3017
3018 napi_schedule(rx_ring->napi);
3019 rx_ring->empty_rx_queue = 0;
3020 }
3021 } else {
3022 rx_ring->empty_rx_queue = 0;
3023 }
3024 }
3025 }
3026
3027
3028 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
3029 {
3030 unsigned long keep_alive_expired;
3031
3032 if (!adapter->wd_state)
3033 return;
3034
3035 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3036 return;
3037
3038 keep_alive_expired = adapter->last_keep_alive_jiffies +
3039 adapter->keep_alive_timeout;
3040 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
3041 netif_err(adapter, drv, adapter->netdev,
3042 "Keep alive watchdog timeout.\n");
3043 u64_stats_update_begin(&adapter->syncp);
3044 adapter->dev_stats.wd_expired++;
3045 u64_stats_update_end(&adapter->syncp);
3046 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
3047 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3048 }
3049 }
3050
3051 static void check_for_admin_com_state(struct ena_adapter *adapter)
3052 {
3053 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
3054 netif_err(adapter, drv, adapter->netdev,
3055 "ENA admin queue is not in running state!\n");
3056 u64_stats_update_begin(&adapter->syncp);
3057 adapter->dev_stats.admin_q_pause++;
3058 u64_stats_update_end(&adapter->syncp);
3059 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
3060 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3061 }
3062 }
3063
3064 static void ena_update_hints(struct ena_adapter *adapter,
3065 struct ena_admin_ena_hw_hints *hints)
3066 {
3067 struct net_device *netdev = adapter->netdev;
3068
3069 if (hints->admin_completion_tx_timeout)
3070 adapter->ena_dev->admin_queue.completion_timeout =
3071 hints->admin_completion_tx_timeout * 1000;
3072
3073 if (hints->mmio_read_timeout)
3074
3075 adapter->ena_dev->mmio_read.reg_read_to =
3076 hints->mmio_read_timeout * 1000;
3077
3078 if (hints->missed_tx_completion_count_threshold_to_reset)
3079 adapter->missing_tx_completion_threshold =
3080 hints->missed_tx_completion_count_threshold_to_reset;
3081
3082 if (hints->missing_tx_completion_timeout) {
3083 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3084 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT;
3085 else
3086 adapter->missing_tx_completion_to =
3087 msecs_to_jiffies(hints->missing_tx_completion_timeout);
3088 }
3089
3090 if (hints->netdev_wd_timeout)
3091 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout);
3092
3093 if (hints->driver_watchdog_timeout) {
3094 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3095 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
3096 else
3097 adapter->keep_alive_timeout =
3098 msecs_to_jiffies(hints->driver_watchdog_timeout);
3099 }
3100 }
3101
3102 static void ena_update_host_info(struct ena_admin_host_info *host_info,
3103 struct net_device *netdev)
3104 {
3105 host_info->supported_network_features[0] =
3106 netdev->features & GENMASK_ULL(31, 0);
3107 host_info->supported_network_features[1] =
3108 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
3109 }
3110
3111 static void ena_timer_service(struct timer_list *t)
3112 {
3113 struct ena_adapter *adapter = from_timer(adapter, t, timer_service);
3114 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
3115 struct ena_admin_host_info *host_info =
3116 adapter->ena_dev->host_attr.host_info;
3117
3118 check_for_missing_keep_alive(adapter);
3119
3120 check_for_admin_com_state(adapter);
3121
3122 check_for_missing_completions(adapter);
3123
3124 check_for_empty_rx_ring(adapter);
3125
3126 if (debug_area)
3127 ena_dump_stats_to_buf(adapter, debug_area);
3128
3129 if (host_info)
3130 ena_update_host_info(host_info, adapter->netdev);
3131
3132 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
3133 netif_err(adapter, drv, adapter->netdev,
3134 "Trigger reset is on\n");
3135 ena_dump_stats_to_dmesg(adapter);
3136 queue_work(ena_wq, &adapter->reset_task);
3137 return;
3138 }
3139
3140
3141 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
3142 }
3143
3144 static int ena_calc_io_queue_num(struct pci_dev *pdev,
3145 struct ena_com_dev *ena_dev,
3146 struct ena_com_dev_get_features_ctx *get_feat_ctx)
3147 {
3148 int io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
3149
3150 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
3151 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
3152 &get_feat_ctx->max_queue_ext.max_queue_ext;
3153 io_rx_num = min_t(int, max_queue_ext->max_rx_sq_num,
3154 max_queue_ext->max_rx_cq_num);
3155
3156 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
3157 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
3158 } else {
3159 struct ena_admin_queue_feature_desc *max_queues =
3160 &get_feat_ctx->max_queues;
3161 io_tx_sq_num = max_queues->max_sq_num;
3162 io_tx_cq_num = max_queues->max_cq_num;
3163 io_rx_num = min_t(int, io_tx_sq_num, io_tx_cq_num);
3164 }
3165
3166
3167 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3168 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
3169
3170 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
3171 io_queue_num = min_t(int, io_queue_num, io_rx_num);
3172 io_queue_num = min_t(int, io_queue_num, io_tx_sq_num);
3173 io_queue_num = min_t(int, io_queue_num, io_tx_cq_num);
3174
3175 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
3176 if (unlikely(!io_queue_num)) {
3177 dev_err(&pdev->dev, "The device doesn't have io queues\n");
3178 return -EFAULT;
3179 }
3180
3181 return io_queue_num;
3182 }
3183
3184 static int ena_set_queues_placement_policy(struct pci_dev *pdev,
3185 struct ena_com_dev *ena_dev,
3186 struct ena_admin_feature_llq_desc *llq,
3187 struct ena_llq_configurations *llq_default_configurations)
3188 {
3189 bool has_mem_bar;
3190 int rc;
3191 u32 llq_feature_mask;
3192
3193 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
3194 if (!(ena_dev->supported_features & llq_feature_mask)) {
3195 dev_err(&pdev->dev,
3196 "LLQ is not supported Fallback to host mode policy.\n");
3197 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3198 return 0;
3199 }
3200
3201 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
3202
3203 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
3204 if (unlikely(rc)) {
3205 dev_err(&pdev->dev,
3206 "Failed to configure the device mode. Fallback to host mode policy.\n");
3207 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3208 return 0;
3209 }
3210
3211
3212 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
3213 return 0;
3214
3215 if (!has_mem_bar) {
3216 dev_err(&pdev->dev,
3217 "ENA device does not expose LLQ bar. Fallback to host mode policy.\n");
3218 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3219 return 0;
3220 }
3221
3222 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3223 pci_resource_start(pdev, ENA_MEM_BAR),
3224 pci_resource_len(pdev, ENA_MEM_BAR));
3225
3226 if (!ena_dev->mem_bar)
3227 return -EFAULT;
3228
3229 return 0;
3230 }
3231
3232 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
3233 struct net_device *netdev)
3234 {
3235 netdev_features_t dev_features = 0;
3236
3237
3238 if (feat->offload.tx &
3239 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
3240 dev_features |= NETIF_F_IP_CSUM;
3241
3242 if (feat->offload.tx &
3243 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
3244 dev_features |= NETIF_F_IPV6_CSUM;
3245
3246 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
3247 dev_features |= NETIF_F_TSO;
3248
3249 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
3250 dev_features |= NETIF_F_TSO6;
3251
3252 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
3253 dev_features |= NETIF_F_TSO_ECN;
3254
3255 if (feat->offload.rx_supported &
3256 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
3257 dev_features |= NETIF_F_RXCSUM;
3258
3259 if (feat->offload.rx_supported &
3260 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
3261 dev_features |= NETIF_F_RXCSUM;
3262
3263 netdev->features =
3264 dev_features |
3265 NETIF_F_SG |
3266 NETIF_F_RXHASH |
3267 NETIF_F_HIGHDMA;
3268
3269 netdev->hw_features |= netdev->features;
3270 netdev->vlan_features |= netdev->features;
3271 }
3272
3273 static void ena_set_conf_feat_params(struct ena_adapter *adapter,
3274 struct ena_com_dev_get_features_ctx *feat)
3275 {
3276 struct net_device *netdev = adapter->netdev;
3277
3278
3279 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
3280 eth_hw_addr_random(netdev);
3281 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
3282 } else {
3283 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
3284 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
3285 }
3286
3287
3288 ena_set_dev_offloads(feat, netdev);
3289
3290 adapter->max_mtu = feat->dev_attr.max_mtu;
3291 netdev->max_mtu = adapter->max_mtu;
3292 netdev->min_mtu = ENA_MIN_MTU;
3293 }
3294
3295 static int ena_rss_init_default(struct ena_adapter *adapter)
3296 {
3297 struct ena_com_dev *ena_dev = adapter->ena_dev;
3298 struct device *dev = &adapter->pdev->dev;
3299 int rc, i;
3300 u32 val;
3301
3302 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
3303 if (unlikely(rc)) {
3304 dev_err(dev, "Cannot init indirect table\n");
3305 goto err_rss_init;
3306 }
3307
3308 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
3309 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
3310 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
3311 ENA_IO_RXQ_IDX(val));
3312 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3313 dev_err(dev, "Cannot fill indirect table\n");
3314 goto err_fill_indir;
3315 }
3316 }
3317
3318 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
3319 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
3320 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3321 dev_err(dev, "Cannot fill hash function\n");
3322 goto err_fill_indir;
3323 }
3324
3325 rc = ena_com_set_default_hash_ctrl(ena_dev);
3326 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3327 dev_err(dev, "Cannot fill hash control\n");
3328 goto err_fill_indir;
3329 }
3330
3331 return 0;
3332
3333 err_fill_indir:
3334 ena_com_rss_destroy(ena_dev);
3335 err_rss_init:
3336
3337 return rc;
3338 }
3339
3340 static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
3341 {
3342 int release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3343
3344 pci_release_selected_regions(pdev, release_bars);
3345 }
3346
3347 static void set_default_llq_configurations(struct ena_llq_configurations *llq_config)
3348 {
3349 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
3350 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
3351 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
3352 llq_config->llq_num_decs_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
3353 llq_config->llq_ring_entry_size_value = 128;
3354 }
3355
3356 static int ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
3357 {
3358 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
3359 struct ena_com_dev *ena_dev = ctx->ena_dev;
3360 u32 tx_queue_size = ENA_DEFAULT_RING_SIZE;
3361 u32 rx_queue_size = ENA_DEFAULT_RING_SIZE;
3362 u32 max_tx_queue_size;
3363 u32 max_rx_queue_size;
3364
3365 if (ctx->ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
3366 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
3367 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
3368 max_rx_queue_size = min_t(u32, max_queue_ext->max_rx_cq_depth,
3369 max_queue_ext->max_rx_sq_depth);
3370 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
3371
3372 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3373 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3374 llq->max_llq_depth);
3375 else
3376 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3377 max_queue_ext->max_tx_sq_depth);
3378
3379 ctx->max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3380 max_queue_ext->max_per_packet_tx_descs);
3381 ctx->max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3382 max_queue_ext->max_per_packet_rx_descs);
3383 } else {
3384 struct ena_admin_queue_feature_desc *max_queues =
3385 &ctx->get_feat_ctx->max_queues;
3386 max_rx_queue_size = min_t(u32, max_queues->max_cq_depth,
3387 max_queues->max_sq_depth);
3388 max_tx_queue_size = max_queues->max_cq_depth;
3389
3390 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3391 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3392 llq->max_llq_depth);
3393 else
3394 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3395 max_queues->max_sq_depth);
3396
3397 ctx->max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3398 max_queues->max_packet_tx_descs);
3399 ctx->max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3400 max_queues->max_packet_rx_descs);
3401 }
3402
3403 max_tx_queue_size = rounddown_pow_of_two(max_tx_queue_size);
3404 max_rx_queue_size = rounddown_pow_of_two(max_rx_queue_size);
3405
3406 tx_queue_size = clamp_val(tx_queue_size, ENA_MIN_RING_SIZE,
3407 max_tx_queue_size);
3408 rx_queue_size = clamp_val(rx_queue_size, ENA_MIN_RING_SIZE,
3409 max_rx_queue_size);
3410
3411 tx_queue_size = rounddown_pow_of_two(tx_queue_size);
3412 rx_queue_size = rounddown_pow_of_two(rx_queue_size);
3413
3414 ctx->max_tx_queue_size = max_tx_queue_size;
3415 ctx->max_rx_queue_size = max_rx_queue_size;
3416 ctx->tx_queue_size = tx_queue_size;
3417 ctx->rx_queue_size = rx_queue_size;
3418
3419 return 0;
3420 }
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432 static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3433 {
3434 struct ena_com_dev_get_features_ctx get_feat_ctx;
3435 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
3436 struct ena_llq_configurations llq_config;
3437 struct ena_com_dev *ena_dev = NULL;
3438 struct ena_adapter *adapter;
3439 int io_queue_num, bars, rc;
3440 struct net_device *netdev;
3441 static int adapters_found;
3442 char *queue_type_str;
3443 bool wd_state;
3444
3445 dev_dbg(&pdev->dev, "%s\n", __func__);
3446
3447 dev_info_once(&pdev->dev, "%s", version);
3448
3449 rc = pci_enable_device_mem(pdev);
3450 if (rc) {
3451 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
3452 return rc;
3453 }
3454
3455 pci_set_master(pdev);
3456
3457 ena_dev = vzalloc(sizeof(*ena_dev));
3458 if (!ena_dev) {
3459 rc = -ENOMEM;
3460 goto err_disable_device;
3461 }
3462
3463 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3464 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
3465 if (rc) {
3466 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3467 rc);
3468 goto err_free_ena_dev;
3469 }
3470
3471 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3472 pci_resource_start(pdev, ENA_REG_BAR),
3473 pci_resource_len(pdev, ENA_REG_BAR));
3474 if (!ena_dev->reg_bar) {
3475 dev_err(&pdev->dev, "failed to remap regs bar\n");
3476 rc = -EFAULT;
3477 goto err_free_region;
3478 }
3479
3480 ena_dev->dmadev = &pdev->dev;
3481
3482 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3483 if (rc) {
3484 dev_err(&pdev->dev, "ena device init failed\n");
3485 if (rc == -ETIME)
3486 rc = -EPROBE_DEFER;
3487 goto err_free_region;
3488 }
3489
3490 set_default_llq_configurations(&llq_config);
3491
3492 rc = ena_set_queues_placement_policy(pdev, ena_dev, &get_feat_ctx.llq,
3493 &llq_config);
3494 if (rc) {
3495 dev_err(&pdev->dev, "ena device init failed\n");
3496 goto err_device_destroy;
3497 }
3498
3499 calc_queue_ctx.ena_dev = ena_dev;
3500 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
3501 calc_queue_ctx.pdev = pdev;
3502
3503
3504
3505
3506 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
3507 ena_dev->intr_moder_rx_interval = ENA_INTR_INITIAL_RX_INTERVAL_USECS;
3508 ena_dev->intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
3509 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
3510 rc = ena_calc_queue_size(&calc_queue_ctx);
3511 if (rc || io_queue_num <= 0) {
3512 rc = -EFAULT;
3513 goto err_device_destroy;
3514 }
3515
3516 dev_info(&pdev->dev, "creating %d io queues. rx queue size: %d tx queue size. %d LLQ is %s\n",
3517 io_queue_num,
3518 calc_queue_ctx.rx_queue_size,
3519 calc_queue_ctx.tx_queue_size,
3520 (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) ?
3521 "ENABLED" : "DISABLED");
3522
3523
3524 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3525 if (!netdev) {
3526 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3527 rc = -ENOMEM;
3528 goto err_device_destroy;
3529 }
3530
3531 SET_NETDEV_DEV(netdev, &pdev->dev);
3532
3533 adapter = netdev_priv(netdev);
3534 pci_set_drvdata(pdev, adapter);
3535
3536 adapter->ena_dev = ena_dev;
3537 adapter->netdev = netdev;
3538 adapter->pdev = pdev;
3539
3540 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3541
3542 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3543 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
3544
3545 adapter->requested_tx_ring_size = calc_queue_ctx.tx_queue_size;
3546 adapter->requested_rx_ring_size = calc_queue_ctx.rx_queue_size;
3547 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
3548 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
3549 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
3550 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
3551
3552 adapter->num_queues = io_queue_num;
3553 adapter->last_monitored_tx_qid = 0;
3554
3555 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3556 adapter->wd_state = wd_state;
3557
3558 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3559
3560 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3561 if (rc) {
3562 dev_err(&pdev->dev,
3563 "Failed to query interrupt moderation feature\n");
3564 goto err_netdev_destroy;
3565 }
3566 ena_init_io_rings(adapter);
3567
3568 netdev->netdev_ops = &ena_netdev_ops;
3569 netdev->watchdog_timeo = TX_TIMEOUT;
3570 ena_set_ethtool_ops(netdev);
3571
3572 netdev->priv_flags |= IFF_UNICAST_FLT;
3573
3574 u64_stats_init(&adapter->syncp);
3575
3576 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3577 if (rc) {
3578 dev_err(&pdev->dev,
3579 "Failed to enable and set the admin interrupts\n");
3580 goto err_worker_destroy;
3581 }
3582 rc = ena_rss_init_default(adapter);
3583 if (rc && (rc != -EOPNOTSUPP)) {
3584 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3585 goto err_free_msix;
3586 }
3587
3588 ena_config_debug_area(adapter);
3589
3590 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3591
3592 netif_carrier_off(netdev);
3593
3594 rc = register_netdev(netdev);
3595 if (rc) {
3596 dev_err(&pdev->dev, "Cannot register net device\n");
3597 goto err_rss;
3598 }
3599
3600 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3601
3602 adapter->last_keep_alive_jiffies = jiffies;
3603 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
3604 adapter->missing_tx_completion_to = TX_TIMEOUT;
3605 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS;
3606
3607 ena_update_hints(adapter, &get_feat_ctx.hw_hints);
3608
3609 timer_setup(&adapter->timer_service, ena_timer_service, 0);
3610 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
3611
3612 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
3613 queue_type_str = "Regular";
3614 else
3615 queue_type_str = "Low Latency";
3616
3617 dev_info(&pdev->dev,
3618 "%s found at mem %lx, mac addr %pM Queues %d, Placement policy: %s\n",
3619 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3620 netdev->dev_addr, io_queue_num, queue_type_str);
3621
3622 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3623
3624 adapters_found++;
3625
3626 return 0;
3627
3628 err_rss:
3629 ena_com_delete_debug_area(ena_dev);
3630 ena_com_rss_destroy(ena_dev);
3631 err_free_msix:
3632 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
3633
3634 ena_com_set_admin_running_state(ena_dev, false);
3635 ena_free_mgmnt_irq(adapter);
3636 ena_disable_msix(adapter);
3637 err_worker_destroy:
3638 del_timer(&adapter->timer_service);
3639 err_netdev_destroy:
3640 free_netdev(netdev);
3641 err_device_destroy:
3642 ena_com_delete_host_info(ena_dev);
3643 ena_com_admin_destroy(ena_dev);
3644 err_free_region:
3645 ena_release_bars(ena_dev, pdev);
3646 err_free_ena_dev:
3647 vfree(ena_dev);
3648 err_disable_device:
3649 pci_disable_device(pdev);
3650 return rc;
3651 }
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663 static void __ena_shutoff(struct pci_dev *pdev, bool shutdown)
3664 {
3665 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3666 struct ena_com_dev *ena_dev;
3667 struct net_device *netdev;
3668
3669 ena_dev = adapter->ena_dev;
3670 netdev = adapter->netdev;
3671
3672 #ifdef CONFIG_RFS_ACCEL
3673 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3674 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3675 netdev->rx_cpu_rmap = NULL;
3676 }
3677 #endif
3678 del_timer_sync(&adapter->timer_service);
3679
3680 cancel_work_sync(&adapter->reset_task);
3681
3682 rtnl_lock();
3683 ena_destroy_device(adapter, true);
3684 if (shutdown) {
3685 netif_device_detach(netdev);
3686 dev_close(netdev);
3687 rtnl_unlock();
3688 } else {
3689 rtnl_unlock();
3690 unregister_netdev(netdev);
3691 free_netdev(netdev);
3692 }
3693
3694 ena_com_rss_destroy(ena_dev);
3695
3696 ena_com_delete_debug_area(ena_dev);
3697
3698 ena_com_delete_host_info(ena_dev);
3699
3700 ena_release_bars(ena_dev, pdev);
3701
3702 pci_disable_device(pdev);
3703
3704 vfree(ena_dev);
3705 }
3706
3707
3708
3709
3710
3711
3712
3713
3714 static void ena_remove(struct pci_dev *pdev)
3715 {
3716 __ena_shutoff(pdev, false);
3717 }
3718
3719
3720
3721
3722
3723
3724
3725
3726 static void ena_shutdown(struct pci_dev *pdev)
3727 {
3728 __ena_shutoff(pdev, true);
3729 }
3730
3731 #ifdef CONFIG_PM
3732
3733
3734
3735
3736 static int ena_suspend(struct pci_dev *pdev, pm_message_t state)
3737 {
3738 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3739
3740 u64_stats_update_begin(&adapter->syncp);
3741 adapter->dev_stats.suspend++;
3742 u64_stats_update_end(&adapter->syncp);
3743
3744 rtnl_lock();
3745 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
3746 dev_err(&pdev->dev,
3747 "ignoring device reset request as the device is being suspended\n");
3748 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3749 }
3750 ena_destroy_device(adapter, true);
3751 rtnl_unlock();
3752 return 0;
3753 }
3754
3755
3756
3757
3758
3759 static int ena_resume(struct pci_dev *pdev)
3760 {
3761 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3762 int rc;
3763
3764 u64_stats_update_begin(&adapter->syncp);
3765 adapter->dev_stats.resume++;
3766 u64_stats_update_end(&adapter->syncp);
3767
3768 rtnl_lock();
3769 rc = ena_restore_device(adapter);
3770 rtnl_unlock();
3771 return rc;
3772 }
3773 #endif
3774
3775 static struct pci_driver ena_pci_driver = {
3776 .name = DRV_MODULE_NAME,
3777 .id_table = ena_pci_tbl,
3778 .probe = ena_probe,
3779 .remove = ena_remove,
3780 .shutdown = ena_shutdown,
3781 #ifdef CONFIG_PM
3782 .suspend = ena_suspend,
3783 .resume = ena_resume,
3784 #endif
3785 .sriov_configure = pci_sriov_configure_simple,
3786 };
3787
3788 static int __init ena_init(void)
3789 {
3790 pr_info("%s", version);
3791
3792 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3793 if (!ena_wq) {
3794 pr_err("Failed to create workqueue\n");
3795 return -ENOMEM;
3796 }
3797
3798 return pci_register_driver(&ena_pci_driver);
3799 }
3800
3801 static void __exit ena_cleanup(void)
3802 {
3803 pci_unregister_driver(&ena_pci_driver);
3804
3805 if (ena_wq) {
3806 destroy_workqueue(ena_wq);
3807 ena_wq = NULL;
3808 }
3809 }
3810
3811
3812
3813
3814
3815
3816
3817 static void ena_update_on_link_change(void *adapter_data,
3818 struct ena_admin_aenq_entry *aenq_e)
3819 {
3820 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3821 struct ena_admin_aenq_link_change_desc *aenq_desc =
3822 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3823 int status = aenq_desc->flags &
3824 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3825
3826 if (status) {
3827 netdev_dbg(adapter->netdev, "%s\n", __func__);
3828 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3829 if (!test_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags))
3830 netif_carrier_on(adapter->netdev);
3831 } else {
3832 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3833 netif_carrier_off(adapter->netdev);
3834 }
3835 }
3836
3837 static void ena_keep_alive_wd(void *adapter_data,
3838 struct ena_admin_aenq_entry *aenq_e)
3839 {
3840 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3841 struct ena_admin_aenq_keep_alive_desc *desc;
3842 u64 rx_drops;
3843
3844 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3845 adapter->last_keep_alive_jiffies = jiffies;
3846
3847 rx_drops = ((u64)desc->rx_drops_high << 32) | desc->rx_drops_low;
3848
3849 u64_stats_update_begin(&adapter->syncp);
3850 adapter->dev_stats.rx_drops = rx_drops;
3851 u64_stats_update_end(&adapter->syncp);
3852 }
3853
3854 static void ena_notification(void *adapter_data,
3855 struct ena_admin_aenq_entry *aenq_e)
3856 {
3857 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3858 struct ena_admin_ena_hw_hints *hints;
3859
3860 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3861 "Invalid group(%x) expected %x\n",
3862 aenq_e->aenq_common_desc.group,
3863 ENA_ADMIN_NOTIFICATION);
3864
3865 switch (aenq_e->aenq_common_desc.syndrom) {
3866 case ENA_ADMIN_UPDATE_HINTS:
3867 hints = (struct ena_admin_ena_hw_hints *)
3868 (&aenq_e->inline_data_w4);
3869 ena_update_hints(adapter, hints);
3870 break;
3871 default:
3872 netif_err(adapter, drv, adapter->netdev,
3873 "Invalid aenq notification link state %d\n",
3874 aenq_e->aenq_common_desc.syndrom);
3875 }
3876 }
3877
3878
3879 static void unimplemented_aenq_handler(void *data,
3880 struct ena_admin_aenq_entry *aenq_e)
3881 {
3882 struct ena_adapter *adapter = (struct ena_adapter *)data;
3883
3884 netif_err(adapter, drv, adapter->netdev,
3885 "Unknown event was received or event with unimplemented handler\n");
3886 }
3887
3888 static struct ena_aenq_handlers aenq_handlers = {
3889 .handlers = {
3890 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3891 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3892 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3893 },
3894 .unimplemented_handler = unimplemented_aenq_handler
3895 };
3896
3897 module_init(ena_init);
3898 module_exit(ena_cleanup);