root/drivers/net/ethernet/amazon/ena/ena_admin_defs.h

INCLUDED FROM

   1 /*
   2  * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef _ENA_ADMIN_H_
  33 #define _ENA_ADMIN_H_
  34 
  35 
  36 enum ena_admin_aq_opcode {
  37         ENA_ADMIN_CREATE_SQ                         = 1,
  38         ENA_ADMIN_DESTROY_SQ                        = 2,
  39         ENA_ADMIN_CREATE_CQ                         = 3,
  40         ENA_ADMIN_DESTROY_CQ                        = 4,
  41         ENA_ADMIN_GET_FEATURE                       = 8,
  42         ENA_ADMIN_SET_FEATURE                       = 9,
  43         ENA_ADMIN_GET_STATS                         = 11,
  44 };
  45 
  46 enum ena_admin_aq_completion_status {
  47         ENA_ADMIN_SUCCESS                           = 0,
  48         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
  49         ENA_ADMIN_BAD_OPCODE                        = 2,
  50         ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
  51         ENA_ADMIN_MALFORMED_REQUEST                 = 4,
  52         /* Additional status is provided in ACQ entry extended_status */
  53         ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
  54         ENA_ADMIN_UNKNOWN_ERROR                     = 6,
  55         ENA_ADMIN_RESOURCE_BUSY                     = 7,
  56 };
  57 
  58 enum ena_admin_aq_feature_id {
  59         ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
  60         ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
  61         ENA_ADMIN_HW_HINTS                          = 3,
  62         ENA_ADMIN_LLQ                               = 4,
  63         ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
  64         ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
  65         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
  66         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
  67         ENA_ADMIN_MTU                               = 14,
  68         ENA_ADMIN_RSS_HASH_INPUT                    = 18,
  69         ENA_ADMIN_INTERRUPT_MODERATION              = 20,
  70         ENA_ADMIN_AENQ_CONFIG                       = 26,
  71         ENA_ADMIN_LINK_CONFIG                       = 27,
  72         ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
  73         ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
  74 };
  75 
  76 enum ena_admin_placement_policy_type {
  77         /* descriptors and headers are in host memory */
  78         ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
  79         /* descriptors and headers are in device memory (a.k.a Low Latency
  80          * Queue)
  81          */
  82         ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
  83 };
  84 
  85 enum ena_admin_link_types {
  86         ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
  87         ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
  88         ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
  89         ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
  90         ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
  91         ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
  92         ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
  93         ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
  94         ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
  95         ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
  96 };
  97 
  98 enum ena_admin_completion_policy_type {
  99         /* completion queue entry for each sq descriptor */
 100         ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
 101         /* completion queue entry upon request in sq descriptor */
 102         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
 103         /* current queue head pointer is updated in OS memory upon sq
 104          * descriptor request
 105          */
 106         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
 107         /* current queue head pointer is updated in OS memory for each sq
 108          * descriptor
 109          */
 110         ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
 111 };
 112 
 113 /* basic stats return ena_admin_basic_stats while extanded stats return a
 114  * buffer (string format) with additional statistics per queue and per
 115  * device id
 116  */
 117 enum ena_admin_get_stats_type {
 118         ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
 119         ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
 120 };
 121 
 122 enum ena_admin_get_stats_scope {
 123         ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
 124         ENA_ADMIN_ETH_TRAFFIC                       = 1,
 125 };
 126 
 127 struct ena_admin_aq_common_desc {
 128         /* 11:0 : command_id
 129          * 15:12 : reserved12
 130          */
 131         u16 command_id;
 132 
 133         /* as appears in ena_admin_aq_opcode */
 134         u8 opcode;
 135 
 136         /* 0 : phase
 137          * 1 : ctrl_data - control buffer address valid
 138          * 2 : ctrl_data_indirect - control buffer address
 139          *    points to list of pages with addresses of control
 140          *    buffers
 141          * 7:3 : reserved3
 142          */
 143         u8 flags;
 144 };
 145 
 146 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 147  * page list chunk. Used also at the end of indirect mode page list chunks,
 148  * for chaining.
 149  */
 150 struct ena_admin_ctrl_buff_info {
 151         u32 length;
 152 
 153         struct ena_common_mem_addr address;
 154 };
 155 
 156 struct ena_admin_sq {
 157         u16 sq_idx;
 158 
 159         /* 4:0 : reserved
 160          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 161          */
 162         u8 sq_identity;
 163 
 164         u8 reserved1;
 165 };
 166 
 167 struct ena_admin_aq_entry {
 168         struct ena_admin_aq_common_desc aq_common_descriptor;
 169 
 170         union {
 171                 u32 inline_data_w1[3];
 172 
 173                 struct ena_admin_ctrl_buff_info control_buffer;
 174         } u;
 175 
 176         u32 inline_data_w4[12];
 177 };
 178 
 179 struct ena_admin_acq_common_desc {
 180         /* command identifier to associate it with the aq descriptor
 181          * 11:0 : command_id
 182          * 15:12 : reserved12
 183          */
 184         u16 command;
 185 
 186         u8 status;
 187 
 188         /* 0 : phase
 189          * 7:1 : reserved1
 190          */
 191         u8 flags;
 192 
 193         u16 extended_status;
 194 
 195         /* indicates to the driver which AQ entry has been consumed by the
 196          *    device and could be reused
 197          */
 198         u16 sq_head_indx;
 199 };
 200 
 201 struct ena_admin_acq_entry {
 202         struct ena_admin_acq_common_desc acq_common_descriptor;
 203 
 204         u32 response_specific_data[14];
 205 };
 206 
 207 struct ena_admin_aq_create_sq_cmd {
 208         struct ena_admin_aq_common_desc aq_common_descriptor;
 209 
 210         /* 4:0 : reserved0_w1
 211          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 212          */
 213         u8 sq_identity;
 214 
 215         u8 reserved8_w1;
 216 
 217         /* 3:0 : placement_policy - Describing where the SQ
 218          *    descriptor ring and the SQ packet headers reside:
 219          *    0x1 - descriptors and headers are in OS memory,
 220          *    0x3 - descriptors and headers in device memory
 221          *    (a.k.a Low Latency Queue)
 222          * 6:4 : completion_policy - Describing what policy
 223          *    to use for generation completion entry (cqe) in
 224          *    the CQ associated with this SQ: 0x0 - cqe for each
 225          *    sq descriptor, 0x1 - cqe upon request in sq
 226          *    descriptor, 0x2 - current queue head pointer is
 227          *    updated in OS memory upon sq descriptor request
 228          *    0x3 - current queue head pointer is updated in OS
 229          *    memory for each sq descriptor
 230          * 7 : reserved15_w1
 231          */
 232         u8 sq_caps_2;
 233 
 234         /* 0 : is_physically_contiguous - Described if the
 235          *    queue ring memory is allocated in physical
 236          *    contiguous pages or split.
 237          * 7:1 : reserved17_w1
 238          */
 239         u8 sq_caps_3;
 240 
 241         /* associated completion queue id. This CQ must be created prior to
 242          *    SQ creation
 243          */
 244         u16 cq_idx;
 245 
 246         /* submission queue depth in entries */
 247         u16 sq_depth;
 248 
 249         /* SQ physical base address in OS memory. This field should not be
 250          * used for Low Latency queues. Has to be page aligned.
 251          */
 252         struct ena_common_mem_addr sq_ba;
 253 
 254         /* specifies queue head writeback location in OS memory. Valid if
 255          * completion_policy is set to completion_policy_head_on_demand or
 256          * completion_policy_head. Has to be cache aligned
 257          */
 258         struct ena_common_mem_addr sq_head_writeback;
 259 
 260         u32 reserved0_w7;
 261 
 262         u32 reserved0_w8;
 263 };
 264 
 265 enum ena_admin_sq_direction {
 266         ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
 267         ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
 268 };
 269 
 270 struct ena_admin_acq_create_sq_resp_desc {
 271         struct ena_admin_acq_common_desc acq_common_desc;
 272 
 273         u16 sq_idx;
 274 
 275         u16 reserved;
 276 
 277         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 278         u32 sq_doorbell_offset;
 279 
 280         /* low latency queue ring base address as an offset to PCIe MMIO
 281          * LLQ_MEM BAR
 282          */
 283         u32 llq_descriptors_offset;
 284 
 285         /* low latency queue headers' memory as an offset to PCIe MMIO
 286          * LLQ_MEM BAR
 287          */
 288         u32 llq_headers_offset;
 289 };
 290 
 291 struct ena_admin_aq_destroy_sq_cmd {
 292         struct ena_admin_aq_common_desc aq_common_descriptor;
 293 
 294         struct ena_admin_sq sq;
 295 };
 296 
 297 struct ena_admin_acq_destroy_sq_resp_desc {
 298         struct ena_admin_acq_common_desc acq_common_desc;
 299 };
 300 
 301 struct ena_admin_aq_create_cq_cmd {
 302         struct ena_admin_aq_common_desc aq_common_descriptor;
 303 
 304         /* 4:0 : reserved5
 305          * 5 : interrupt_mode_enabled - if set, cq operates
 306          *    in interrupt mode, otherwise - polling
 307          * 7:6 : reserved6
 308          */
 309         u8 cq_caps_1;
 310 
 311         /* 4:0 : cq_entry_size_words - size of CQ entry in
 312          *    32-bit words, valid values: 4, 8.
 313          * 7:5 : reserved7
 314          */
 315         u8 cq_caps_2;
 316 
 317         /* completion queue depth in # of entries. must be power of 2 */
 318         u16 cq_depth;
 319 
 320         /* msix vector assigned to this cq */
 321         u32 msix_vector;
 322 
 323         /* cq physical base address in OS memory. CQ must be physically
 324          * contiguous
 325          */
 326         struct ena_common_mem_addr cq_ba;
 327 };
 328 
 329 struct ena_admin_acq_create_cq_resp_desc {
 330         struct ena_admin_acq_common_desc acq_common_desc;
 331 
 332         u16 cq_idx;
 333 
 334         /* actual cq depth in number of entries */
 335         u16 cq_actual_depth;
 336 
 337         u32 numa_node_register_offset;
 338 
 339         u32 cq_head_db_register_offset;
 340 
 341         u32 cq_interrupt_unmask_register_offset;
 342 };
 343 
 344 struct ena_admin_aq_destroy_cq_cmd {
 345         struct ena_admin_aq_common_desc aq_common_descriptor;
 346 
 347         u16 cq_idx;
 348 
 349         u16 reserved1;
 350 };
 351 
 352 struct ena_admin_acq_destroy_cq_resp_desc {
 353         struct ena_admin_acq_common_desc acq_common_desc;
 354 };
 355 
 356 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 357  * buffer pointed by AQ entry
 358  */
 359 struct ena_admin_aq_get_stats_cmd {
 360         struct ena_admin_aq_common_desc aq_common_descriptor;
 361 
 362         union {
 363                 /* command specific inline data */
 364                 u32 inline_data_w1[3];
 365 
 366                 struct ena_admin_ctrl_buff_info control_buffer;
 367         } u;
 368 
 369         /* stats type as defined in enum ena_admin_get_stats_type */
 370         u8 type;
 371 
 372         /* stats scope defined in enum ena_admin_get_stats_scope */
 373         u8 scope;
 374 
 375         u16 reserved3;
 376 
 377         /* queue id. used when scope is specific_queue */
 378         u16 queue_idx;
 379 
 380         /* device id, value 0xFFFF means mine. only privileged device can get
 381          *    stats of other device
 382          */
 383         u16 device_id;
 384 };
 385 
 386 /* Basic Statistics Command. */
 387 struct ena_admin_basic_stats {
 388         u32 tx_bytes_low;
 389 
 390         u32 tx_bytes_high;
 391 
 392         u32 tx_pkts_low;
 393 
 394         u32 tx_pkts_high;
 395 
 396         u32 rx_bytes_low;
 397 
 398         u32 rx_bytes_high;
 399 
 400         u32 rx_pkts_low;
 401 
 402         u32 rx_pkts_high;
 403 
 404         u32 rx_drops_low;
 405 
 406         u32 rx_drops_high;
 407 };
 408 
 409 struct ena_admin_acq_get_stats_resp {
 410         struct ena_admin_acq_common_desc acq_common_desc;
 411 
 412         struct ena_admin_basic_stats basic_stats;
 413 };
 414 
 415 struct ena_admin_get_set_feature_common_desc {
 416         /* 1:0 : select - 0x1 - current value; 0x3 - default
 417          *    value
 418          * 7:3 : reserved3
 419          */
 420         u8 flags;
 421 
 422         /* as appears in ena_admin_aq_feature_id */
 423         u8 feature_id;
 424 
 425         /* The driver specifies the max feature version it supports and the
 426          * device responds with the currently supported feature version. The
 427          * field is zero based
 428          */
 429         u8 feature_version;
 430 
 431         u8 reserved8;
 432 };
 433 
 434 struct ena_admin_device_attr_feature_desc {
 435         u32 impl_id;
 436 
 437         u32 device_version;
 438 
 439         /* bitmap of ena_admin_aq_feature_id */
 440         u32 supported_features;
 441 
 442         u32 reserved3;
 443 
 444         /* Indicates how many bits are used physical address access. */
 445         u32 phys_addr_width;
 446 
 447         /* Indicates how many bits are used virtual address access. */
 448         u32 virt_addr_width;
 449 
 450         /* unicast MAC address (in Network byte order) */
 451         u8 mac_addr[6];
 452 
 453         u8 reserved7[2];
 454 
 455         u32 max_mtu;
 456 };
 457 
 458 enum ena_admin_llq_header_location {
 459         /* header is in descriptor list */
 460         ENA_ADMIN_INLINE_HEADER                     = 1,
 461         /* header in a separate ring, implies 16B descriptor list entry */
 462         ENA_ADMIN_HEADER_RING                       = 2,
 463 };
 464 
 465 enum ena_admin_llq_ring_entry_size {
 466         ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
 467         ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
 468         ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
 469 };
 470 
 471 enum ena_admin_llq_num_descs_before_header {
 472         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
 473         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
 474         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
 475         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
 476         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
 477 };
 478 
 479 /* packet descriptor list entry always starts with one or more descriptors,
 480  * followed by a header. The rest of the descriptors are located in the
 481  * beginning of the subsequent entry. Stride refers to how the rest of the
 482  * descriptors are placed. This field is relevant only for inline header
 483  * mode
 484  */
 485 enum ena_admin_llq_stride_ctrl {
 486         ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
 487         ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
 488 };
 489 
 490 struct ena_admin_feature_llq_desc {
 491         u32 max_llq_num;
 492 
 493         u32 max_llq_depth;
 494 
 495         /*  specify the header locations the device supports. bitfield of
 496          *    enum ena_admin_llq_header_location.
 497          */
 498         u16 header_location_ctrl_supported;
 499 
 500         /* the header location the driver selected to use. */
 501         u16 header_location_ctrl_enabled;
 502 
 503         /* if inline header is specified - this is the size of descriptor
 504          *    list entry. If header in a separate ring is specified - this is
 505          *    the size of header ring entry. bitfield of enum
 506          *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
 507          *    supports
 508          */
 509         u16 entry_size_ctrl_supported;
 510 
 511         /* the entry size the driver selected to use. */
 512         u16 entry_size_ctrl_enabled;
 513 
 514         /* valid only if inline header is specified. First entry associated
 515          *    with the packet includes descriptors and header. Rest of the
 516          *    entries occupied by descriptors. This parameter defines the max
 517          *    number of descriptors precedding the header in the first entry.
 518          *    The field is bitfield of enum
 519          *    ena_admin_llq_num_descs_before_header and specify the values the
 520          *    device supports
 521          */
 522         u16 desc_num_before_header_supported;
 523 
 524         /* the desire field the driver selected to use */
 525         u16 desc_num_before_header_enabled;
 526 
 527         /* valid only if inline was chosen. bitfield of enum
 528          *    ena_admin_llq_stride_ctrl
 529          */
 530         u16 descriptors_stride_ctrl_supported;
 531 
 532         /* the stride control the driver selected to use */
 533         u16 descriptors_stride_ctrl_enabled;
 534 
 535         /* Maximum size in bytes taken by llq entries in a single tx burst.
 536          * Set to 0 when there is no such limit.
 537          */
 538         u32 max_tx_burst_size;
 539 };
 540 
 541 struct ena_admin_queue_ext_feature_fields {
 542         u32 max_tx_sq_num;
 543 
 544         u32 max_tx_cq_num;
 545 
 546         u32 max_rx_sq_num;
 547 
 548         u32 max_rx_cq_num;
 549 
 550         u32 max_tx_sq_depth;
 551 
 552         u32 max_tx_cq_depth;
 553 
 554         u32 max_rx_sq_depth;
 555 
 556         u32 max_rx_cq_depth;
 557 
 558         u32 max_tx_header_size;
 559 
 560         /* Maximum Descriptors number, including meta descriptor, allowed for
 561          * a single Tx packet
 562          */
 563         u16 max_per_packet_tx_descs;
 564 
 565         /* Maximum Descriptors number allowed for a single Rx packet */
 566         u16 max_per_packet_rx_descs;
 567 };
 568 
 569 struct ena_admin_queue_feature_desc {
 570         u32 max_sq_num;
 571 
 572         u32 max_sq_depth;
 573 
 574         u32 max_cq_num;
 575 
 576         u32 max_cq_depth;
 577 
 578         u32 max_legacy_llq_num;
 579 
 580         u32 max_legacy_llq_depth;
 581 
 582         u32 max_header_size;
 583 
 584         /* Maximum Descriptors number, including meta descriptor, allowed for
 585          *    a single Tx packet
 586          */
 587         u16 max_packet_tx_descs;
 588 
 589         /* Maximum Descriptors number allowed for a single Rx packet */
 590         u16 max_packet_rx_descs;
 591 };
 592 
 593 struct ena_admin_set_feature_mtu_desc {
 594         /* exclude L2 */
 595         u32 mtu;
 596 };
 597 
 598 struct ena_admin_set_feature_host_attr_desc {
 599         /* host OS info base address in OS memory. host info is 4KB of
 600          * physically contiguous
 601          */
 602         struct ena_common_mem_addr os_info_ba;
 603 
 604         /* host debug area base address in OS memory. debug area must be
 605          * physically contiguous
 606          */
 607         struct ena_common_mem_addr debug_ba;
 608 
 609         /* debug area size */
 610         u32 debug_area_size;
 611 };
 612 
 613 struct ena_admin_feature_intr_moder_desc {
 614         /* interrupt delay granularity in usec */
 615         u16 intr_delay_resolution;
 616 
 617         u16 reserved;
 618 };
 619 
 620 struct ena_admin_get_feature_link_desc {
 621         /* Link speed in Mb */
 622         u32 speed;
 623 
 624         /* bit field of enum ena_admin_link types */
 625         u32 supported;
 626 
 627         /* 0 : autoneg
 628          * 1 : duplex - Full Duplex
 629          * 31:2 : reserved2
 630          */
 631         u32 flags;
 632 };
 633 
 634 struct ena_admin_feature_aenq_desc {
 635         /* bitmask for AENQ groups the device can report */
 636         u32 supported_groups;
 637 
 638         /* bitmask for AENQ groups to report */
 639         u32 enabled_groups;
 640 };
 641 
 642 struct ena_admin_feature_offload_desc {
 643         /* 0 : TX_L3_csum_ipv4
 644          * 1 : TX_L4_ipv4_csum_part - The checksum field
 645          *    should be initialized with pseudo header checksum
 646          * 2 : TX_L4_ipv4_csum_full
 647          * 3 : TX_L4_ipv6_csum_part - The checksum field
 648          *    should be initialized with pseudo header checksum
 649          * 4 : TX_L4_ipv6_csum_full
 650          * 5 : tso_ipv4
 651          * 6 : tso_ipv6
 652          * 7 : tso_ecn
 653          */
 654         u32 tx;
 655 
 656         /* Receive side supported stateless offload
 657          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 658          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 659          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 660          * 3 : RX_hash - Hash calculation
 661          */
 662         u32 rx_supported;
 663 
 664         u32 rx_enabled;
 665 };
 666 
 667 enum ena_admin_hash_functions {
 668         ENA_ADMIN_TOEPLITZ                          = 1,
 669         ENA_ADMIN_CRC32                             = 2,
 670 };
 671 
 672 struct ena_admin_feature_rss_flow_hash_control {
 673         u32 keys_num;
 674 
 675         u32 reserved;
 676 
 677         u32 key[10];
 678 };
 679 
 680 struct ena_admin_feature_rss_flow_hash_function {
 681         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 682         u32 supported_func;
 683 
 684         /* 7:0 : selected_func - bitmask of
 685          *    ena_admin_hash_functions
 686          */
 687         u32 selected_func;
 688 
 689         /* initial value */
 690         u32 init_val;
 691 };
 692 
 693 /* RSS flow hash protocols */
 694 enum ena_admin_flow_hash_proto {
 695         ENA_ADMIN_RSS_TCP4                          = 0,
 696         ENA_ADMIN_RSS_UDP4                          = 1,
 697         ENA_ADMIN_RSS_TCP6                          = 2,
 698         ENA_ADMIN_RSS_UDP6                          = 3,
 699         ENA_ADMIN_RSS_IP4                           = 4,
 700         ENA_ADMIN_RSS_IP6                           = 5,
 701         ENA_ADMIN_RSS_IP4_FRAG                      = 6,
 702         ENA_ADMIN_RSS_NOT_IP                        = 7,
 703         /* TCPv6 with extension header */
 704         ENA_ADMIN_RSS_TCP6_EX                       = 8,
 705         /* IPv6 with extension header */
 706         ENA_ADMIN_RSS_IP6_EX                        = 9,
 707         ENA_ADMIN_RSS_PROTO_NUM                     = 16,
 708 };
 709 
 710 /* RSS flow hash fields */
 711 enum ena_admin_flow_hash_fields {
 712         /* Ethernet Dest Addr */
 713         ENA_ADMIN_RSS_L2_DA                         = BIT(0),
 714         /* Ethernet Src Addr */
 715         ENA_ADMIN_RSS_L2_SA                         = BIT(1),
 716         /* ipv4/6 Dest Addr */
 717         ENA_ADMIN_RSS_L3_DA                         = BIT(2),
 718         /* ipv4/6 Src Addr */
 719         ENA_ADMIN_RSS_L3_SA                         = BIT(3),
 720         /* tcp/udp Dest Port */
 721         ENA_ADMIN_RSS_L4_DP                         = BIT(4),
 722         /* tcp/udp Src Port */
 723         ENA_ADMIN_RSS_L4_SP                         = BIT(5),
 724 };
 725 
 726 struct ena_admin_proto_input {
 727         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 728         u16 fields;
 729 
 730         u16 reserved2;
 731 };
 732 
 733 struct ena_admin_feature_rss_hash_control {
 734         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 735 
 736         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 737 
 738         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 739 
 740         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 741 };
 742 
 743 struct ena_admin_feature_rss_flow_hash_input {
 744         /* supported hash input sorting
 745          * 1 : L3_sort - support swap L3 addresses if DA is
 746          *    smaller than SA
 747          * 2 : L4_sort - support swap L4 ports if DP smaller
 748          *    SP
 749          */
 750         u16 supported_input_sort;
 751 
 752         /* enabled hash input sorting
 753          * 1 : enable_L3_sort - enable swap L3 addresses if
 754          *    DA smaller than SA
 755          * 2 : enable_L4_sort - enable swap L4 ports if DP
 756          *    smaller than SP
 757          */
 758         u16 enabled_input_sort;
 759 };
 760 
 761 enum ena_admin_os_type {
 762         ENA_ADMIN_OS_LINUX                          = 1,
 763         ENA_ADMIN_OS_WIN                            = 2,
 764         ENA_ADMIN_OS_DPDK                           = 3,
 765         ENA_ADMIN_OS_FREEBSD                        = 4,
 766         ENA_ADMIN_OS_IPXE                           = 5,
 767         ENA_ADMIN_OS_ESXI                           = 6,
 768         ENA_ADMIN_OS_GROUPS_NUM                     = 6,
 769 };
 770 
 771 struct ena_admin_host_info {
 772         /* defined in enum ena_admin_os_type */
 773         u32 os_type;
 774 
 775         /* os distribution string format */
 776         u8 os_dist_str[128];
 777 
 778         /* OS distribution numeric format */
 779         u32 os_dist;
 780 
 781         /* kernel version string format */
 782         u8 kernel_ver_str[32];
 783 
 784         /* Kernel version numeric format */
 785         u32 kernel_ver;
 786 
 787         /* 7:0 : major
 788          * 15:8 : minor
 789          * 23:16 : sub_minor
 790          * 31:24 : module_type
 791          */
 792         u32 driver_version;
 793 
 794         /* features bitmap */
 795         u32 supported_network_features[2];
 796 
 797         /* ENA spec version of driver */
 798         u16 ena_spec_version;
 799 
 800         /* ENA device's Bus, Device and Function
 801          * 2:0 : function
 802          * 7:3 : device
 803          * 15:8 : bus
 804          */
 805         u16 bdf;
 806 
 807         /* Number of CPUs */
 808         u16 num_cpus;
 809 
 810         u16 reserved;
 811 
 812         /* 1 :0 : reserved
 813          * 2 : interrupt_moderation
 814          * 31:3 : reserved
 815          */
 816         u32 driver_supported_features;
 817 };
 818 
 819 struct ena_admin_rss_ind_table_entry {
 820         u16 cq_idx;
 821 
 822         u16 reserved;
 823 };
 824 
 825 struct ena_admin_feature_rss_ind_table {
 826         /* min supported table size (2^min_size) */
 827         u16 min_size;
 828 
 829         /* max supported table size (2^max_size) */
 830         u16 max_size;
 831 
 832         /* table size (2^size) */
 833         u16 size;
 834 
 835         u16 reserved;
 836 
 837         /* index of the inline entry. 0xFFFFFFFF means invalid */
 838         u32 inline_index;
 839 
 840         /* used for updating single entry, ignored when setting the entire
 841          * table through the control buffer.
 842          */
 843         struct ena_admin_rss_ind_table_entry inline_entry;
 844 };
 845 
 846 /* When hint value is 0, driver should use it's own predefined value */
 847 struct ena_admin_ena_hw_hints {
 848         /* value in ms */
 849         u16 mmio_read_timeout;
 850 
 851         /* value in ms */
 852         u16 driver_watchdog_timeout;
 853 
 854         /* Per packet tx completion timeout. value in ms */
 855         u16 missing_tx_completion_timeout;
 856 
 857         u16 missed_tx_completion_count_threshold_to_reset;
 858 
 859         /* value in ms */
 860         u16 admin_completion_tx_timeout;
 861 
 862         u16 netdev_wd_timeout;
 863 
 864         u16 max_tx_sgl_size;
 865 
 866         u16 max_rx_sgl_size;
 867 
 868         u16 reserved[8];
 869 };
 870 
 871 struct ena_admin_get_feat_cmd {
 872         struct ena_admin_aq_common_desc aq_common_descriptor;
 873 
 874         struct ena_admin_ctrl_buff_info control_buffer;
 875 
 876         struct ena_admin_get_set_feature_common_desc feat_common;
 877 
 878         u32 raw[11];
 879 };
 880 
 881 struct ena_admin_queue_ext_feature_desc {
 882         /* version */
 883         u8 version;
 884 
 885         u8 reserved1[3];
 886 
 887         union {
 888                 struct ena_admin_queue_ext_feature_fields max_queue_ext;
 889 
 890                 u32 raw[10];
 891         };
 892 };
 893 
 894 struct ena_admin_get_feat_resp {
 895         struct ena_admin_acq_common_desc acq_common_desc;
 896 
 897         union {
 898                 u32 raw[14];
 899 
 900                 struct ena_admin_device_attr_feature_desc dev_attr;
 901 
 902                 struct ena_admin_feature_llq_desc llq;
 903 
 904                 struct ena_admin_queue_feature_desc max_queue;
 905 
 906                 struct ena_admin_queue_ext_feature_desc max_queue_ext;
 907 
 908                 struct ena_admin_feature_aenq_desc aenq;
 909 
 910                 struct ena_admin_get_feature_link_desc link;
 911 
 912                 struct ena_admin_feature_offload_desc offload;
 913 
 914                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 915 
 916                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 917 
 918                 struct ena_admin_feature_rss_ind_table ind_table;
 919 
 920                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 921 
 922                 struct ena_admin_ena_hw_hints hw_hints;
 923         } u;
 924 };
 925 
 926 struct ena_admin_set_feat_cmd {
 927         struct ena_admin_aq_common_desc aq_common_descriptor;
 928 
 929         struct ena_admin_ctrl_buff_info control_buffer;
 930 
 931         struct ena_admin_get_set_feature_common_desc feat_common;
 932 
 933         union {
 934                 u32 raw[11];
 935 
 936                 /* mtu size */
 937                 struct ena_admin_set_feature_mtu_desc mtu;
 938 
 939                 /* host attributes */
 940                 struct ena_admin_set_feature_host_attr_desc host_attr;
 941 
 942                 /* AENQ configuration */
 943                 struct ena_admin_feature_aenq_desc aenq;
 944 
 945                 /* rss flow hash function */
 946                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 947 
 948                 /* rss flow hash input */
 949                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 950 
 951                 /* rss indirection table */
 952                 struct ena_admin_feature_rss_ind_table ind_table;
 953 
 954                 /* LLQ configuration */
 955                 struct ena_admin_feature_llq_desc llq;
 956         } u;
 957 };
 958 
 959 struct ena_admin_set_feat_resp {
 960         struct ena_admin_acq_common_desc acq_common_desc;
 961 
 962         union {
 963                 u32 raw[14];
 964         } u;
 965 };
 966 
 967 struct ena_admin_aenq_common_desc {
 968         u16 group;
 969 
 970         u16 syndrom;
 971 
 972         /* 0 : phase
 973          * 7:1 : reserved - MBZ
 974          */
 975         u8 flags;
 976 
 977         u8 reserved1[3];
 978 
 979         u32 timestamp_low;
 980 
 981         u32 timestamp_high;
 982 };
 983 
 984 /* asynchronous event notification groups */
 985 enum ena_admin_aenq_group {
 986         ENA_ADMIN_LINK_CHANGE                       = 0,
 987         ENA_ADMIN_FATAL_ERROR                       = 1,
 988         ENA_ADMIN_WARNING                           = 2,
 989         ENA_ADMIN_NOTIFICATION                      = 3,
 990         ENA_ADMIN_KEEP_ALIVE                        = 4,
 991         ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
 992 };
 993 
 994 enum ena_admin_aenq_notification_syndrom {
 995         ENA_ADMIN_SUSPEND                           = 0,
 996         ENA_ADMIN_RESUME                            = 1,
 997         ENA_ADMIN_UPDATE_HINTS                      = 2,
 998 };
 999 
1000 struct ena_admin_aenq_entry {
1001         struct ena_admin_aenq_common_desc aenq_common_desc;
1002 
1003         /* command specific inline data */
1004         u32 inline_data_w4[12];
1005 };
1006 
1007 struct ena_admin_aenq_link_change_desc {
1008         struct ena_admin_aenq_common_desc aenq_common_desc;
1009 
1010         /* 0 : link_status */
1011         u32 flags;
1012 };
1013 
1014 struct ena_admin_aenq_keep_alive_desc {
1015         struct ena_admin_aenq_common_desc aenq_common_desc;
1016 
1017         u32 rx_drops_low;
1018 
1019         u32 rx_drops_high;
1020 };
1021 
1022 struct ena_admin_ena_mmio_req_read_less_resp {
1023         u16 req_id;
1024 
1025         u16 reg_off;
1026 
1027         /* value is valid when poll is cleared */
1028         u32 reg_val;
1029 };
1030 
1031 /* aq_common_desc */
1032 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1033 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1034 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1035 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1036 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1037 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1038 
1039 /* sq */
1040 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1041 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1042 
1043 /* acq_common_desc */
1044 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1045 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1046 
1047 /* aq_create_sq_cmd */
1048 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1049 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1050 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1051 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1052 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1053 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1054 
1055 /* aq_create_cq_cmd */
1056 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1057 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1058 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1059 
1060 /* get_set_feature_common_desc */
1061 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1062 
1063 /* get_feature_link_desc */
1064 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1065 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1066 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1067 
1068 /* feature_offload_desc */
1069 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1070 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1071 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1072 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1073 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1074 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1075 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1076 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1077 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1078 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1080 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1081 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1082 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1083 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1084 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1091 
1092 /* feature_rss_flow_hash_function */
1093 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1094 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1095 
1096 /* feature_rss_flow_hash_input */
1097 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1098 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1099 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1100 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1101 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1102 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1103 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1104 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1105 
1106 /* host_info */
1107 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1108 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1109 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1110 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1111 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1112 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1113 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1114 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1115 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1116 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1117 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1118 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1119 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT      2
1120 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK       BIT(2)
1121 
1122 /* aenq_common_desc */
1123 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1124 
1125 /* aenq_link_change_desc */
1126 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1127 
1128 #endif /*_ENA_ADMIN_H_ */