drivers/net/ethernet/amazon/ena/ena

/* [<][>][^][v][top][bottom][index][help] */
   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 
  33 #ifndef ENA_H
  34 #define ENA_H
  35 
  36 #include <linux/bitops.h>
  37 #include <linux/dim.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/inetdevice.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/skbuff.h>
  43 
  44 #include "ena_com.h"
  45 #include "ena_eth_com.h"
  46 
  47 #define DRV_MODULE_VER_MAJOR    2
  48 #define DRV_MODULE_VER_MINOR    1
  49 #define DRV_MODULE_VER_SUBMINOR 0
  50 
  51 #define DRV_MODULE_NAME         "ena"
  52 #ifndef DRV_MODULE_VERSION
  53 #define DRV_MODULE_VERSION \
  54         __stringify(DRV_MODULE_VER_MAJOR) "."   \
  55         __stringify(DRV_MODULE_VER_MINOR) "."   \
  56         __stringify(DRV_MODULE_VER_SUBMINOR) "K"
  57 #endif
  58 
  59 #define DEVICE_NAME     "Elastic Network Adapter (ENA)"
  60 
  61 /* 1 for AENQ + ADMIN */
  62 #define ENA_ADMIN_MSIX_VEC              1
  63 #define ENA_MAX_MSIX_VEC(io_queues)     (ENA_ADMIN_MSIX_VEC + (io_queues))
  64 
  65 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
  66  * driver passes 0.
  67  * Since the max packet size the ENA handles is ~9kB limit the buffer length to
  68  * 16kB.
  69  */
  70 #if PAGE_SIZE > SZ_16K
  71 #define ENA_PAGE_SIZE (_AC(SZ_16K, UL))
  72 #else
  73 #define ENA_PAGE_SIZE PAGE_SIZE
  74 #endif
  75 
  76 #define ENA_MIN_MSIX_VEC                2
  77 
  78 #define ENA_REG_BAR                     0
  79 #define ENA_MEM_BAR                     2
  80 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
  81 
  82 #define ENA_DEFAULT_RING_SIZE   (1024)
  83 #define ENA_MIN_RING_SIZE       (256)
  84 
  85 #define ENA_TX_WAKEUP_THRESH            (MAX_SKB_FRAGS + 2)
  86 #define ENA_DEFAULT_RX_COPYBREAK        (256 - NET_IP_ALIGN)
  87 
  88 /* limit the buffer size to 600 bytes to handle MTU changes from very
  89  * small to very large, in which case the number of buffers per packet
  90  * could exceed ENA_PKT_MAX_BUFS
  91  */
  92 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
  93 
  94 #define ENA_MIN_MTU             128
  95 
  96 #define ENA_NAME_MAX_LEN        20
  97 #define ENA_IRQNAME_SIZE        40
  98 
  99 #define ENA_PKT_MAX_BUFS        19
 100 
 101 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
 102 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
 103 
 104 #define ENA_HASH_KEY_SIZE       40
 105 
 106 /* The number of tx packet completions that will be handled each NAPI poll
 107  * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
 108  */
 109 #define ENA_TX_POLL_BUDGET_DIVIDER      4
 110 
 111 /* Refill Rx queue when number of required descriptors is above
 112  * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
 113  */
 114 #define ENA_RX_REFILL_THRESH_DIVIDER    8
 115 #define ENA_RX_REFILL_THRESH_PACKET     256
 116 
 117 /* Number of queues to check for missing queues per timer service */
 118 #define ENA_MONITORED_TX_QUEUES 4
 119 /* Max timeout packets before device reset */
 120 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128
 121 
 122 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 123 
 124 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 125 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
 126         (((idx) + (n)) & ((ring_size) - 1))
 127 
 128 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
 129 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
 130 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q)       ((q) / 2)
 131 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q)       (((q) - 1) / 2)
 132 
 133 #define ENA_MGMNT_IRQ_IDX               0
 134 #define ENA_IO_IRQ_FIRST_IDX            1
 135 #define ENA_IO_IRQ_IDX(q)               (ENA_IO_IRQ_FIRST_IDX + (q))
 136 
 137 /* ENA device should send keep alive msg every 1 sec.
 138  * We wait for 6 sec just to be on the safe side.
 139  */
 140 #define ENA_DEVICE_KALIVE_TIMEOUT       (6 * HZ)
 141 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
 142 
 143 #define ENA_MMIO_DISABLE_REG_READ       BIT(0)
 144 
 145 struct ena_irq {
 146         irq_handler_t handler;
 147         void *data;
 148         int cpu;
 149         u32 vector;
 150         cpumask_t affinity_hint_mask;
 151         char name[ENA_IRQNAME_SIZE];
 152 };
 153 
 154 struct ena_napi {
 155         struct napi_struct napi ____cacheline_aligned;
 156         struct ena_ring *tx_ring;
 157         struct ena_ring *rx_ring;
 158         u32 qid;
 159         struct dim dim;
 160 };
 161 
 162 struct ena_calc_queue_size_ctx {
 163         struct ena_com_dev_get_features_ctx *get_feat_ctx;
 164         struct ena_com_dev *ena_dev;
 165         struct pci_dev *pdev;
 166         u16 tx_queue_size;
 167         u16 rx_queue_size;
 168         u16 max_tx_queue_size;
 169         u16 max_rx_queue_size;
 170         u16 max_tx_sgl_size;
 171         u16 max_rx_sgl_size;
 172 };
 173 
 174 struct ena_tx_buffer {
 175         struct sk_buff *skb;
 176         /* num of ena desc for this specific skb
 177          * (includes data desc and metadata desc)
 178          */
 179         u32 tx_descs;
 180         /* num of buffers used by this skb */
 181         u32 num_of_bufs;
 182 
 183         /* Indicate if bufs[0] map the linear data of the skb. */
 184         u8 map_linear_data;
 185 
 186         /* Used for detect missing tx packets to limit the number of prints */
 187         u32 print_once;
 188         /* Save the last jiffies to detect missing tx packets
 189          *
 190          * sets to non zero value on ena_start_xmit and set to zero on
 191          * napi and timer_Service_routine.
 192          *
 193          * while this value is not protected by lock,
 194          * a given packet is not expected to be handled by ena_start_xmit
 195          * and by napi/timer_service at the same time.
 196          */
 197         unsigned long last_jiffies;
 198         struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
 199 } ____cacheline_aligned;
 200 
 201 struct ena_rx_buffer {
 202         struct sk_buff *skb;
 203         struct page *page;
 204         u32 page_offset;
 205         struct ena_com_buf ena_buf;
 206 } ____cacheline_aligned;
 207 
 208 struct ena_stats_tx {
 209         u64 cnt;
 210         u64 bytes;
 211         u64 queue_stop;
 212         u64 prepare_ctx_err;
 213         u64 queue_wakeup;
 214         u64 dma_mapping_err;
 215         u64 linearize;
 216         u64 linearize_failed;
 217         u64 napi_comp;
 218         u64 tx_poll;
 219         u64 doorbells;
 220         u64 bad_req_id;
 221         u64 llq_buffer_copy;
 222         u64 missed_tx;
 223 };
 224 
 225 struct ena_stats_rx {
 226         u64 cnt;
 227         u64 bytes;
 228         u64 rx_copybreak_pkt;
 229         u64 csum_good;
 230         u64 refil_partial;
 231         u64 bad_csum;
 232         u64 page_alloc_fail;
 233         u64 skb_alloc_fail;
 234         u64 dma_mapping_err;
 235         u64 bad_desc_num;
 236         u64 bad_req_id;
 237         u64 empty_rx_ring;
 238         u64 csum_unchecked;
 239 };
 240 
 241 struct ena_ring {
 242         /* Holds the empty requests for TX/RX
 243          * out of order completions
 244          */
 245         u16 *free_ids;
 246 
 247         union {
 248                 struct ena_tx_buffer *tx_buffer_info;
 249                 struct ena_rx_buffer *rx_buffer_info;
 250         };
 251 
 252         /* cache ptr to avoid using the adapter */
 253         struct device *dev;
 254         struct pci_dev *pdev;
 255         struct napi_struct *napi;
 256         struct net_device *netdev;
 257         struct ena_com_dev *ena_dev;
 258         struct ena_adapter *adapter;
 259         struct ena_com_io_cq *ena_com_io_cq;
 260         struct ena_com_io_sq *ena_com_io_sq;
 261 
 262         u16 next_to_use;
 263         u16 next_to_clean;
 264         u16 rx_copybreak;
 265         u16 qid;
 266         u16 mtu;
 267         u16 sgl_size;
 268 
 269         /* The maximum header length the device can handle */
 270         u8 tx_max_header_size;
 271 
 272         bool first_interrupt;
 273         u16 no_interrupt_event_cnt;
 274 
 275         /* cpu for TPH */
 276         int cpu;
 277          /* number of tx/rx_buffer_info's entries */
 278         int ring_size;
 279 
 280         enum ena_admin_placement_policy_type tx_mem_queue_type;
 281 
 282         struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
 283         u32  smoothed_interval;
 284         u32  per_napi_packets;
 285         u16 non_empty_napi_events;
 286         struct u64_stats_sync syncp;
 287         union {
 288                 struct ena_stats_tx tx_stats;
 289                 struct ena_stats_rx rx_stats;
 290         };
 291 
 292         u8 *push_buf_intermediate_buf;
 293         int empty_rx_queue;
 294 } ____cacheline_aligned;
 295 
 296 struct ena_stats_dev {
 297         u64 tx_timeout;
 298         u64 suspend;
 299         u64 resume;
 300         u64 wd_expired;
 301         u64 interface_up;
 302         u64 interface_down;
 303         u64 admin_q_pause;
 304         u64 rx_drops;
 305 };
 306 
 307 enum ena_flags_t {
 308         ENA_FLAG_DEVICE_RUNNING,
 309         ENA_FLAG_DEV_UP,
 310         ENA_FLAG_LINK_UP,
 311         ENA_FLAG_MSIX_ENABLED,
 312         ENA_FLAG_TRIGGER_RESET,
 313         ENA_FLAG_ONGOING_RESET
 314 };
 315 
 316 /* adapter specific private data structure */
 317 struct ena_adapter {
 318         struct ena_com_dev *ena_dev;
 319         /* OS defined structs */
 320         struct net_device *netdev;
 321         struct pci_dev *pdev;
 322 
 323         /* rx packets that shorter that this len will be copied to the skb
 324          * header
 325          */
 326         u32 rx_copybreak;
 327         u32 max_mtu;
 328 
 329         int num_queues;
 330 
 331         int msix_vecs;
 332 
 333         u32 missing_tx_completion_threshold;
 334 
 335         u32 requested_tx_ring_size;
 336         u32 requested_rx_ring_size;
 337 
 338         u32 max_tx_ring_size;
 339         u32 max_rx_ring_size;
 340 
 341         u32 msg_enable;
 342 
 343         u16 max_tx_sgl_size;
 344         u16 max_rx_sgl_size;
 345 
 346         u8 mac_addr[ETH_ALEN];
 347 
 348         unsigned long keep_alive_timeout;
 349         unsigned long missing_tx_completion_to;
 350 
 351         char name[ENA_NAME_MAX_LEN];
 352 
 353         unsigned long flags;
 354         /* TX */
 355         struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
 356                 ____cacheline_aligned_in_smp;
 357 
 358         /* RX */
 359         struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
 360                 ____cacheline_aligned_in_smp;
 361 
 362         struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
 363 
 364         struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
 365 
 366         /* timer service */
 367         struct work_struct reset_task;
 368         struct timer_list timer_service;
 369 
 370         bool wd_state;
 371         bool dev_up_before_reset;
 372         unsigned long last_keep_alive_jiffies;
 373 
 374         struct u64_stats_sync syncp;
 375         struct ena_stats_dev dev_stats;
 376 
 377         /* last queue index that was checked for uncompleted tx packets */
 378         u32 last_monitored_tx_qid;
 379 
 380         enum ena_regs_reset_reason_types reset_reason;
 381 };
 382 
 383 void ena_set_ethtool_ops(struct net_device *netdev);
 384 
 385 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
 386 
 387 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
 388 
 389 int ena_update_queue_sizes(struct ena_adapter *adapter,
 390                            u32 new_tx_size,
 391                            u32 new_rx_size);
 392 
 393 int ena_get_sset_count(struct net_device *netdev, int sset);
 394 
 395 #endif /* !(ENA_H) */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/amazon/ena/ena_netdev.h

INCLUDED FROM
