1 /*
2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef _ENA_ETH_IO_H_
33 #define _ENA_ETH_IO_H_
34
35 enum ena_eth_io_l3_proto_index {
36 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
37 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
38 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
39 ENA_ETH_IO_L3_PROTO_FCOE = 21,
40 ENA_ETH_IO_L3_PROTO_ROCE = 22,
41 };
42
43 enum ena_eth_io_l4_proto_index {
44 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
45 ENA_ETH_IO_L4_PROTO_TCP = 12,
46 ENA_ETH_IO_L4_PROTO_UDP = 13,
47 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
48 };
49
50 struct ena_eth_io_tx_desc {
51 /* 15:0 : length - Buffer length in bytes, must
52 * include any packet trailers that the ENA supposed
53 * to update like End-to-End CRC, Authentication GMAC
54 * etc. This length must not include the
55 * 'Push_Buffer' length. This length must not include
56 * the 4-byte added in the end for 802.3 Ethernet FCS
57 * 21:16 : req_id_hi - Request ID[15:10]
58 * 22 : reserved22 - MBZ
59 * 23 : meta_desc - MBZ
60 * 24 : phase
61 * 25 : reserved1 - MBZ
62 * 26 : first - Indicates first descriptor in
63 * transaction
64 * 27 : last - Indicates last descriptor in
65 * transaction
66 * 28 : comp_req - Indicates whether completion
67 * should be posted, after packet is transmitted.
68 * Valid only for first descriptor
69 * 30:29 : reserved29 - MBZ
70 * 31 : reserved31 - MBZ
71 */
72 u32 len_ctrl;
73
74 /* 3:0 : l3_proto_idx - L3 protocol. This field
75 * required when l3_csum_en,l3_csum or tso_en are set.
76 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
77 * DF flags of the IPv4 header is 0. Otherwise must
78 * be set to 1
79 * 6:5 : reserved5
80 * 7 : tso_en - Enable TSO, For TCP only.
81 * 12:8 : l4_proto_idx - L4 protocol. This field need
82 * to be set when l4_csum_en or tso_en are set.
83 * 13 : l3_csum_en - enable IPv4 header checksum.
84 * 14 : l4_csum_en - enable TCP/UDP checksum.
85 * 15 : ethernet_fcs_dis - when set, the controller
86 * will not append the 802.3 Ethernet Frame Check
87 * Sequence to the packet
88 * 16 : reserved16
89 * 17 : l4_csum_partial - L4 partial checksum. when
90 * set to 0, the ENA calculates the L4 checksum,
91 * where the Destination Address required for the
92 * TCP/UDP pseudo-header is taken from the actual
93 * packet L3 header. when set to 1, the ENA doesn't
94 * calculate the sum of the pseudo-header, instead,
95 * the checksum field of the L4 is used instead. When
96 * TSO enabled, the checksum of the pseudo-header
97 * must not include the tcp length field. L4 partial
98 * checksum should be used for IPv6 packet that
99 * contains Routing Headers.
100 * 20:18 : reserved18 - MBZ
101 * 21 : reserved21 - MBZ
102 * 31:22 : req_id_lo - Request ID[9:0]
103 */
104 u32 meta_ctrl;
105
106 u32 buff_addr_lo;
107
108 /* address high and header size
109 * 15:0 : addr_hi - Buffer Pointer[47:32]
110 * 23:16 : reserved16_w2
111 * 31:24 : header_length - Header length. For Low
112 * Latency Queues, this fields indicates the number
113 * of bytes written to the headers' memory. For
114 * normal queues, if packet is TCP or UDP, and longer
115 * than max_header_size, then this field should be
116 * set to the sum of L4 header offset and L4 header
117 * size(without options), otherwise, this field
118 * should be set to 0. For both modes, this field
119 * must not exceed the max_header_size.
120 * max_header_size value is reported by the Max
121 * Queues Feature descriptor
122 */
123 u32 buff_addr_hi_hdr_sz;
124 };
125
126 struct ena_eth_io_tx_meta_desc {
127 /* 9:0 : req_id_lo - Request ID[9:0]
128 * 11:10 : reserved10 - MBZ
129 * 12 : reserved12 - MBZ
130 * 13 : reserved13 - MBZ
131 * 14 : ext_valid - if set, offset fields in Word2
132 * are valid Also MSS High in Word 0 and bits [31:24]
133 * in Word 3
134 * 15 : reserved15
135 * 19:16 : mss_hi
136 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
137 * Extended Metadata Descriptor
138 * 21 : meta_store - Store extended metadata in queue
139 * cache
140 * 22 : reserved22 - MBZ
141 * 23 : meta_desc - MBO
142 * 24 : phase
143 * 25 : reserved25 - MBZ
144 * 26 : first - Indicates first descriptor in
145 * transaction
146 * 27 : last - Indicates last descriptor in
147 * transaction
148 * 28 : comp_req - Indicates whether completion
149 * should be posted, after packet is transmitted.
150 * Valid only for first descriptor
151 * 30:29 : reserved29 - MBZ
152 * 31 : reserved31 - MBZ
153 */
154 u32 len_ctrl;
155
156 /* 5:0 : req_id_hi
157 * 31:6 : reserved6 - MBZ
158 */
159 u32 word1;
160
161 /* 7:0 : l3_hdr_len
162 * 15:8 : l3_hdr_off
163 * 21:16 : l4_hdr_len_in_words - counts the L4 header
164 * length in words. there is an explicit assumption
165 * that L4 header appears right after L3 header and
166 * L4 offset is based on l3_hdr_off+l3_hdr_len
167 * 31:22 : mss_lo
168 */
169 u32 word2;
170
171 u32 reserved;
172 };
173
174 struct ena_eth_io_tx_cdesc {
175 /* Request ID[15:0] */
176 u16 req_id;
177
178 u8 status;
179
180 /* flags
181 * 0 : phase
182 * 7:1 : reserved1
183 */
184 u8 flags;
185
186 u16 sub_qid;
187
188 u16 sq_head_idx;
189 };
190
191 struct ena_eth_io_rx_desc {
192 /* In bytes. 0 means 64KB */
193 u16 length;
194
195 /* MBZ */
196 u8 reserved2;
197
198 /* 0 : phase
199 * 1 : reserved1 - MBZ
200 * 2 : first - Indicates first descriptor in
201 * transaction
202 * 3 : last - Indicates last descriptor in transaction
203 * 4 : comp_req
204 * 5 : reserved5 - MBO
205 * 7:6 : reserved6 - MBZ
206 */
207 u8 ctrl;
208
209 u16 req_id;
210
211 /* MBZ */
212 u16 reserved6;
213
214 u32 buff_addr_lo;
215
216 u16 buff_addr_hi;
217
218 /* MBZ */
219 u16 reserved16_w3;
220 };
221
222 /* 4-word format Note: all ethernet parsing information are valid only when
223 * last=1
224 */
225 struct ena_eth_io_rx_cdesc_base {
226 /* 4:0 : l3_proto_idx
227 * 6:5 : src_vlan_cnt
228 * 7 : reserved7 - MBZ
229 * 12:8 : l4_proto_idx
230 * 13 : l3_csum_err - when set, either the L3
231 * checksum error detected, or, the controller didn't
232 * validate the checksum. This bit is valid only when
233 * l3_proto_idx indicates IPv4 packet
234 * 14 : l4_csum_err - when set, either the L4
235 * checksum error detected, or, the controller didn't
236 * validate the checksum. This bit is valid only when
237 * l4_proto_idx indicates TCP/UDP packet, and,
238 * ipv4_frag is not set. This bit is valid only when
239 * l4_csum_checked below is set.
240 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
241 * 16 : l4_csum_checked - L4 checksum was verified
242 * (could be OK or error), when cleared the status of
243 * checksum is unknown
244 * 23:17 : reserved17 - MBZ
245 * 24 : phase
246 * 25 : l3_csum2 - second checksum engine result
247 * 26 : first - Indicates first descriptor in
248 * transaction
249 * 27 : last - Indicates last descriptor in
250 * transaction
251 * 29:28 : reserved28
252 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
253 * Descriptor was used
254 * 31 : reserved31
255 */
256 u32 status;
257
258 u16 length;
259
260 u16 req_id;
261
262 /* 32-bit hash result */
263 u32 hash;
264
265 u16 sub_qid;
266
267 u16 reserved;
268 };
269
270 /* 8-word format */
271 struct ena_eth_io_rx_cdesc_ext {
272 struct ena_eth_io_rx_cdesc_base base;
273
274 u32 buff_addr_lo;
275
276 u16 buff_addr_hi;
277
278 u16 reserved16;
279
280 u32 reserved_w6;
281
282 u32 reserved_w7;
283 };
284
285 struct ena_eth_io_intr_reg {
286 /* 14:0 : rx_intr_delay
287 * 29:15 : tx_intr_delay
288 * 30 : intr_unmask
289 * 31 : reserved
290 */
291 u32 intr_control;
292 };
293
294 struct ena_eth_io_numa_node_cfg_reg {
295 /* 7:0 : numa
296 * 30:8 : reserved
297 * 31 : enabled
298 */
299 u32 numa_cfg;
300 };
301
302 /* tx_desc */
303 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
304 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
305 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
306 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
307 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
308 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
309 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
310 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
311 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
312 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
313 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
314 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
315 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
316 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
317 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
318 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
319 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
320 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
321 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
322 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
323 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
324 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
325 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
326 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
327 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
328 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
329 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
330 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
331 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
332 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
333 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
334 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
335 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
336
337 /* tx_meta_desc */
338 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
339 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
340 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
341 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
342 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
343 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
344 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
345 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
346 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
347 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
348 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
349 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
350 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
351 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
352 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
353 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
354 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
355 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
356 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
357 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
358 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
359 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
360 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
361 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
362 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
363 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
364 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
365
366 /* tx_cdesc */
367 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
368
369 /* rx_desc */
370 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
371 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
372 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
373 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
374 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
375 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
376 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
377
378 /* rx_cdesc_base */
379 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
380 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
381 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
382 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
383 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
384 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
385 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
386 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
387 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
388 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
389 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
390 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
391 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
392 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
393 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
394 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
395 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
396 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
397 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
398 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
399 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
400 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
401 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
402
403 /* intr_reg */
404 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
405 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
406 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
407 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
408 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
409
410 /* numa_node_cfg_reg */
411 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
412 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
413 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
414
415 #endif /*_ENA_ETH_IO_H_ */