drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c

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This source file includes following definitions.
xgbe_phy_i2c_xfer
xgbe_phy_redrv_write
xgbe_phy_i2c_write
xgbe_phy_i2c_read
xgbe_phy_sfp_put_mux
xgbe_phy_sfp_get_mux
xgbe_phy_put_comm_ownership
xgbe_phy_get_comm_ownership
xgbe_phy_mdio_mii_write
xgbe_phy_i2c_mii_write
xgbe_phy_mii_write
xgbe_phy_mdio_mii_read
xgbe_phy_i2c_mii_read
xgbe_phy_mii_read
xgbe_phy_sfp_phy_settings
xgbe_phy_sfp_bit_rate
xgbe_phy_free_phy_device
xgbe_phy_finisar_phy_quirks
xgbe_phy_belfuse_phy_quirks
xgbe_phy_external_phy_quirks
xgbe_phy_find_phy_device
xgbe_phy_sfp_external_phy
xgbe_phy_check_sfp_rx_los
xgbe_phy_check_sfp_tx_fault
xgbe_phy_check_sfp_mod_absent
xgbe_phy_sfp_parse_eeprom
xgbe_phy_sfp_eeprom_info
xgbe_phy_sfp_verify_eeprom
xgbe_phy_sfp_read_eeprom
xgbe_phy_sfp_signals
xgbe_phy_sfp_mod_absent
xgbe_phy_sfp_reset
xgbe_phy_sfp_detect
xgbe_phy_module_eeprom
xgbe_phy_module_info
xgbe_phy_phydev_flowctrl
xgbe_phy_an37_sgmii_outcome
xgbe_phy_an37_outcome
xgbe_phy_an73_redrv_outcome
xgbe_phy_an73_outcome
xgbe_phy_an_outcome
xgbe_phy_an_advertising
xgbe_phy_an_config
xgbe_phy_an_sfp_mode
xgbe_phy_an_mode
xgbe_phy_set_redrv_mode_mdio
xgbe_phy_set_redrv_mode_i2c
xgbe_phy_set_redrv_mode
xgbe_phy_perform_ratechange
xgbe_phy_rrc
xgbe_phy_power_off
xgbe_phy_sfi_mode
xgbe_phy_x_mode
xgbe_phy_sgmii_1000_mode
xgbe_phy_sgmii_100_mode
xgbe_phy_kr_mode
xgbe_phy_kx_2500_mode
xgbe_phy_kx_1000_mode
xgbe_phy_cur_mode
xgbe_phy_switch_baset_mode
xgbe_phy_switch_bp_2500_mode
xgbe_phy_switch_bp_mode
xgbe_phy_switch_mode
xgbe_phy_get_basex_mode
xgbe_phy_get_baset_mode
xgbe_phy_get_sfp_mode
xgbe_phy_get_bp_2500_mode
xgbe_phy_get_bp_mode
xgbe_phy_get_mode
xgbe_phy_set_mode
xgbe_phy_check_mode
xgbe_phy_use_basex_mode
xgbe_phy_use_baset_mode
xgbe_phy_use_sfp_mode
xgbe_phy_use_bp_2500_mode
xgbe_phy_use_bp_mode
xgbe_phy_use_mode
xgbe_phy_valid_speed_basex_mode
xgbe_phy_valid_speed_baset_mode
xgbe_phy_valid_speed_sfp_mode
xgbe_phy_valid_speed_bp_2500_mode
xgbe_phy_valid_speed_bp_mode
xgbe_phy_valid_speed
xgbe_phy_link_status
xgbe_phy_sfp_gpio_setup
xgbe_phy_sfp_comm_setup
xgbe_phy_sfp_setup
xgbe_phy_int_mdio_reset
xgbe_phy_i2c_mdio_reset
xgbe_phy_mdio_reset
xgbe_phy_redrv_error
xgbe_phy_mdio_reset_setup
xgbe_phy_port_mode_mismatch
xgbe_phy_conn_type_mismatch
xgbe_phy_port_enabled
xgbe_phy_cdr_track
xgbe_phy_cdr_notrack
xgbe_phy_kr_training_post
xgbe_phy_kr_training_pre
xgbe_phy_an_post
xgbe_phy_an_pre
xgbe_phy_stop
xgbe_phy_start
xgbe_phy_reset
xgbe_phy_exit
xgbe_phy_init
xgbe_init_function_ptrs_phy_v2
   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116 
 117 #include <linux/module.h>
 118 #include <linux/device.h>
 119 #include <linux/kmod.h>
 120 #include <linux/mdio.h>
 121 #include <linux/phy.h>
 122 #include <linux/ethtool.h>
 123 
 124 #include "xgbe.h"
 125 #include "xgbe-common.h"
 126 
 127 #define XGBE_PHY_PORT_SPEED_100         BIT(0)
 128 #define XGBE_PHY_PORT_SPEED_1000        BIT(1)
 129 #define XGBE_PHY_PORT_SPEED_2500        BIT(2)
 130 #define XGBE_PHY_PORT_SPEED_10000       BIT(3)
 131 
 132 #define XGBE_MUTEX_RELEASE              0x80000000
 133 
 134 #define XGBE_SFP_DIRECT                 7
 135 
 136 /* I2C target addresses */
 137 #define XGBE_SFP_SERIAL_ID_ADDRESS      0x50
 138 #define XGBE_SFP_DIAG_INFO_ADDRESS      0x51
 139 #define XGBE_SFP_PHY_ADDRESS            0x56
 140 #define XGBE_GPIO_ADDRESS_PCA9555       0x20
 141 
 142 /* SFP sideband signal indicators */
 143 #define XGBE_GPIO_NO_TX_FAULT           BIT(0)
 144 #define XGBE_GPIO_NO_RATE_SELECT        BIT(1)
 145 #define XGBE_GPIO_NO_MOD_ABSENT         BIT(2)
 146 #define XGBE_GPIO_NO_RX_LOS             BIT(3)
 147 
 148 /* Rate-change complete wait/retry count */
 149 #define XGBE_RATECHANGE_COUNT           500
 150 
 151 /* CDR delay values for KR support (in usec) */
 152 #define XGBE_CDR_DELAY_INIT             10000
 153 #define XGBE_CDR_DELAY_INC              10000
 154 #define XGBE_CDR_DELAY_MAX              100000
 155 
 156 /* RRC frequency during link status check */
 157 #define XGBE_RRC_FREQUENCY              10
 158 
 159 enum xgbe_port_mode {
 160         XGBE_PORT_MODE_RSVD = 0,
 161         XGBE_PORT_MODE_BACKPLANE,
 162         XGBE_PORT_MODE_BACKPLANE_2500,
 163         XGBE_PORT_MODE_1000BASE_T,
 164         XGBE_PORT_MODE_1000BASE_X,
 165         XGBE_PORT_MODE_NBASE_T,
 166         XGBE_PORT_MODE_10GBASE_T,
 167         XGBE_PORT_MODE_10GBASE_R,
 168         XGBE_PORT_MODE_SFP,
 169         XGBE_PORT_MODE_MAX,
 170 };
 171 
 172 enum xgbe_conn_type {
 173         XGBE_CONN_TYPE_NONE = 0,
 174         XGBE_CONN_TYPE_SFP,
 175         XGBE_CONN_TYPE_MDIO,
 176         XGBE_CONN_TYPE_RSVD1,
 177         XGBE_CONN_TYPE_BACKPLANE,
 178         XGBE_CONN_TYPE_MAX,
 179 };
 180 
 181 /* SFP/SFP+ related definitions */
 182 enum xgbe_sfp_comm {
 183         XGBE_SFP_COMM_DIRECT = 0,
 184         XGBE_SFP_COMM_PCA9545,
 185 };
 186 
 187 enum xgbe_sfp_cable {
 188         XGBE_SFP_CABLE_UNKNOWN = 0,
 189         XGBE_SFP_CABLE_ACTIVE,
 190         XGBE_SFP_CABLE_PASSIVE,
 191 };
 192 
 193 enum xgbe_sfp_base {
 194         XGBE_SFP_BASE_UNKNOWN = 0,
 195         XGBE_SFP_BASE_1000_T,
 196         XGBE_SFP_BASE_1000_SX,
 197         XGBE_SFP_BASE_1000_LX,
 198         XGBE_SFP_BASE_1000_CX,
 199         XGBE_SFP_BASE_10000_SR,
 200         XGBE_SFP_BASE_10000_LR,
 201         XGBE_SFP_BASE_10000_LRM,
 202         XGBE_SFP_BASE_10000_ER,
 203         XGBE_SFP_BASE_10000_CR,
 204 };
 205 
 206 enum xgbe_sfp_speed {
 207         XGBE_SFP_SPEED_UNKNOWN = 0,
 208         XGBE_SFP_SPEED_100_1000,
 209         XGBE_SFP_SPEED_1000,
 210         XGBE_SFP_SPEED_10000,
 211 };
 212 
 213 /* SFP Serial ID Base ID values relative to an offset of 0 */
 214 #define XGBE_SFP_BASE_ID                        0
 215 #define XGBE_SFP_ID_SFP                         0x03
 216 
 217 #define XGBE_SFP_BASE_EXT_ID                    1
 218 #define XGBE_SFP_EXT_ID_SFP                     0x04
 219 
 220 #define XGBE_SFP_BASE_10GBE_CC                  3
 221 #define XGBE_SFP_BASE_10GBE_CC_SR               BIT(4)
 222 #define XGBE_SFP_BASE_10GBE_CC_LR               BIT(5)
 223 #define XGBE_SFP_BASE_10GBE_CC_LRM              BIT(6)
 224 #define XGBE_SFP_BASE_10GBE_CC_ER               BIT(7)
 225 
 226 #define XGBE_SFP_BASE_1GBE_CC                   6
 227 #define XGBE_SFP_BASE_1GBE_CC_SX                BIT(0)
 228 #define XGBE_SFP_BASE_1GBE_CC_LX                BIT(1)
 229 #define XGBE_SFP_BASE_1GBE_CC_CX                BIT(2)
 230 #define XGBE_SFP_BASE_1GBE_CC_T                 BIT(3)
 231 
 232 #define XGBE_SFP_BASE_CABLE                     8
 233 #define XGBE_SFP_BASE_CABLE_PASSIVE             BIT(2)
 234 #define XGBE_SFP_BASE_CABLE_ACTIVE              BIT(3)
 235 
 236 #define XGBE_SFP_BASE_BR                        12
 237 #define XGBE_SFP_BASE_BR_1GBE_MIN               0x0a
 238 #define XGBE_SFP_BASE_BR_1GBE_MAX               0x0d
 239 #define XGBE_SFP_BASE_BR_10GBE_MIN              0x64
 240 #define XGBE_SFP_BASE_BR_10GBE_MAX              0x68
 241 
 242 #define XGBE_SFP_BASE_CU_CABLE_LEN              18
 243 
 244 #define XGBE_SFP_BASE_VENDOR_NAME               20
 245 #define XGBE_SFP_BASE_VENDOR_NAME_LEN           16
 246 #define XGBE_SFP_BASE_VENDOR_PN                 40
 247 #define XGBE_SFP_BASE_VENDOR_PN_LEN             16
 248 #define XGBE_SFP_BASE_VENDOR_REV                56
 249 #define XGBE_SFP_BASE_VENDOR_REV_LEN            4
 250 
 251 #define XGBE_SFP_BASE_CC                        63
 252 
 253 /* SFP Serial ID Extended ID values relative to an offset of 64 */
 254 #define XGBE_SFP_BASE_VENDOR_SN                 4
 255 #define XGBE_SFP_BASE_VENDOR_SN_LEN             16
 256 
 257 #define XGBE_SFP_EXTD_OPT1                      1
 258 #define XGBE_SFP_EXTD_OPT1_RX_LOS               BIT(1)
 259 #define XGBE_SFP_EXTD_OPT1_TX_FAULT             BIT(3)
 260 
 261 #define XGBE_SFP_EXTD_DIAG                      28
 262 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE          BIT(2)
 263 
 264 #define XGBE_SFP_EXTD_SFF_8472                  30
 265 
 266 #define XGBE_SFP_EXTD_CC                        31
 267 
 268 struct xgbe_sfp_eeprom {
 269         u8 base[64];
 270         u8 extd[32];
 271         u8 vendor[32];
 272 };
 273 
 274 #define XGBE_SFP_DIAGS_SUPPORTED(_x)                    \
 275         ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] &&          \
 276          !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
 277 
 278 #define XGBE_SFP_EEPROM_BASE_LEN        256
 279 #define XGBE_SFP_EEPROM_DIAG_LEN        256
 280 #define XGBE_SFP_EEPROM_MAX             (XGBE_SFP_EEPROM_BASE_LEN +     \
 281                                          XGBE_SFP_EEPROM_DIAG_LEN)
 282 
 283 #define XGBE_BEL_FUSE_VENDOR    "BEL-FUSE        "
 284 #define XGBE_BEL_FUSE_PARTNO    "1GBT-SFP06      "
 285 
 286 struct xgbe_sfp_ascii {
 287         union {
 288                 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
 289                 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
 290                 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
 291                 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
 292         } u;
 293 };
 294 
 295 /* MDIO PHY reset types */
 296 enum xgbe_mdio_reset {
 297         XGBE_MDIO_RESET_NONE = 0,
 298         XGBE_MDIO_RESET_I2C_GPIO,
 299         XGBE_MDIO_RESET_INT_GPIO,
 300         XGBE_MDIO_RESET_MAX,
 301 };
 302 
 303 /* Re-driver related definitions */
 304 enum xgbe_phy_redrv_if {
 305         XGBE_PHY_REDRV_IF_MDIO = 0,
 306         XGBE_PHY_REDRV_IF_I2C,
 307         XGBE_PHY_REDRV_IF_MAX,
 308 };
 309 
 310 enum xgbe_phy_redrv_model {
 311         XGBE_PHY_REDRV_MODEL_4223 = 0,
 312         XGBE_PHY_REDRV_MODEL_4227,
 313         XGBE_PHY_REDRV_MODEL_MAX,
 314 };
 315 
 316 enum xgbe_phy_redrv_mode {
 317         XGBE_PHY_REDRV_MODE_CX = 5,
 318         XGBE_PHY_REDRV_MODE_SR = 9,
 319 };
 320 
 321 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
 322 
 323 /* PHY related configuration information */
 324 struct xgbe_phy_data {
 325         enum xgbe_port_mode port_mode;
 326 
 327         unsigned int port_id;
 328 
 329         unsigned int port_speeds;
 330 
 331         enum xgbe_conn_type conn_type;
 332 
 333         enum xgbe_mode cur_mode;
 334         enum xgbe_mode start_mode;
 335 
 336         unsigned int rrc_count;
 337 
 338         unsigned int mdio_addr;
 339 
 340         /* SFP Support */
 341         enum xgbe_sfp_comm sfp_comm;
 342         unsigned int sfp_mux_address;
 343         unsigned int sfp_mux_channel;
 344 
 345         unsigned int sfp_gpio_address;
 346         unsigned int sfp_gpio_mask;
 347         unsigned int sfp_gpio_inputs;
 348         unsigned int sfp_gpio_rx_los;
 349         unsigned int sfp_gpio_tx_fault;
 350         unsigned int sfp_gpio_mod_absent;
 351         unsigned int sfp_gpio_rate_select;
 352 
 353         unsigned int sfp_rx_los;
 354         unsigned int sfp_tx_fault;
 355         unsigned int sfp_mod_absent;
 356         unsigned int sfp_changed;
 357         unsigned int sfp_phy_avail;
 358         unsigned int sfp_cable_len;
 359         enum xgbe_sfp_base sfp_base;
 360         enum xgbe_sfp_cable sfp_cable;
 361         enum xgbe_sfp_speed sfp_speed;
 362         struct xgbe_sfp_eeprom sfp_eeprom;
 363 
 364         /* External PHY support */
 365         enum xgbe_mdio_mode phydev_mode;
 366         struct mii_bus *mii;
 367         struct phy_device *phydev;
 368         enum xgbe_mdio_reset mdio_reset;
 369         unsigned int mdio_reset_addr;
 370         unsigned int mdio_reset_gpio;
 371 
 372         /* Re-driver support */
 373         unsigned int redrv;
 374         unsigned int redrv_if;
 375         unsigned int redrv_addr;
 376         unsigned int redrv_lane;
 377         unsigned int redrv_model;
 378 
 379         /* KR AN support */
 380         unsigned int phy_cdr_notrack;
 381         unsigned int phy_cdr_delay;
 382 };
 383 
 384 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
 385 static DEFINE_MUTEX(xgbe_phy_comm_lock);
 386 
 387 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
 388 
 389 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
 390                              struct xgbe_i2c_op *i2c_op)
 391 {
 392         return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
 393 }
 394 
 395 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
 396                                 unsigned int val)
 397 {
 398         struct xgbe_phy_data *phy_data = pdata->phy_data;
 399         struct xgbe_i2c_op i2c_op;
 400         __be16 *redrv_val;
 401         u8 redrv_data[5], csum;
 402         unsigned int i, retry;
 403         int ret;
 404 
 405         /* High byte of register contains read/write indicator */
 406         redrv_data[0] = ((reg >> 8) & 0xff) << 1;
 407         redrv_data[1] = reg & 0xff;
 408         redrv_val = (__be16 *)&redrv_data[2];
 409         *redrv_val = cpu_to_be16(val);
 410 
 411         /* Calculate 1 byte checksum */
 412         csum = 0;
 413         for (i = 0; i < 4; i++) {
 414                 csum += redrv_data[i];
 415                 if (redrv_data[i] > csum)
 416                         csum++;
 417         }
 418         redrv_data[4] = ~csum;
 419 
 420         retry = 1;
 421 again1:
 422         i2c_op.cmd = XGBE_I2C_CMD_WRITE;
 423         i2c_op.target = phy_data->redrv_addr;
 424         i2c_op.len = sizeof(redrv_data);
 425         i2c_op.buf = redrv_data;
 426         ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
 427         if (ret) {
 428                 if ((ret == -EAGAIN) && retry--)
 429                         goto again1;
 430 
 431                 return ret;
 432         }
 433 
 434         retry = 1;
 435 again2:
 436         i2c_op.cmd = XGBE_I2C_CMD_READ;
 437         i2c_op.target = phy_data->redrv_addr;
 438         i2c_op.len = 1;
 439         i2c_op.buf = redrv_data;
 440         ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
 441         if (ret) {
 442                 if ((ret == -EAGAIN) && retry--)
 443                         goto again2;
 444 
 445                 return ret;
 446         }
 447 
 448         if (redrv_data[0] != 0xff) {
 449                 netif_dbg(pdata, drv, pdata->netdev,
 450                           "Redriver write checksum error\n");
 451                 ret = -EIO;
 452         }
 453 
 454         return ret;
 455 }
 456 
 457 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
 458                               void *val, unsigned int val_len)
 459 {
 460         struct xgbe_i2c_op i2c_op;
 461         int retry, ret;
 462 
 463         retry = 1;
 464 again:
 465         /* Write the specfied register */
 466         i2c_op.cmd = XGBE_I2C_CMD_WRITE;
 467         i2c_op.target = target;
 468         i2c_op.len = val_len;
 469         i2c_op.buf = val;
 470         ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
 471         if ((ret == -EAGAIN) && retry--)
 472                 goto again;
 473 
 474         return ret;
 475 }
 476 
 477 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
 478                              void *reg, unsigned int reg_len,
 479                              void *val, unsigned int val_len)
 480 {
 481         struct xgbe_i2c_op i2c_op;
 482         int retry, ret;
 483 
 484         retry = 1;
 485 again1:
 486         /* Set the specified register to read */
 487         i2c_op.cmd = XGBE_I2C_CMD_WRITE;
 488         i2c_op.target = target;
 489         i2c_op.len = reg_len;
 490         i2c_op.buf = reg;
 491         ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
 492         if (ret) {
 493                 if ((ret == -EAGAIN) && retry--)
 494                         goto again1;
 495 
 496                 return ret;
 497         }
 498 
 499         retry = 1;
 500 again2:
 501         /* Read the specfied register */
 502         i2c_op.cmd = XGBE_I2C_CMD_READ;
 503         i2c_op.target = target;
 504         i2c_op.len = val_len;
 505         i2c_op.buf = val;
 506         ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
 507         if ((ret == -EAGAIN) && retry--)
 508                 goto again2;
 509 
 510         return ret;
 511 }
 512 
 513 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
 514 {
 515         struct xgbe_phy_data *phy_data = pdata->phy_data;
 516         struct xgbe_i2c_op i2c_op;
 517         u8 mux_channel;
 518 
 519         if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
 520                 return 0;
 521 
 522         /* Select no mux channels */
 523         mux_channel = 0;
 524         i2c_op.cmd = XGBE_I2C_CMD_WRITE;
 525         i2c_op.target = phy_data->sfp_mux_address;
 526         i2c_op.len = sizeof(mux_channel);
 527         i2c_op.buf = &mux_channel;
 528 
 529         return xgbe_phy_i2c_xfer(pdata, &i2c_op);
 530 }
 531 
 532 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
 533 {
 534         struct xgbe_phy_data *phy_data = pdata->phy_data;
 535         struct xgbe_i2c_op i2c_op;
 536         u8 mux_channel;
 537 
 538         if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
 539                 return 0;
 540 
 541         /* Select desired mux channel */
 542         mux_channel = 1 << phy_data->sfp_mux_channel;
 543         i2c_op.cmd = XGBE_I2C_CMD_WRITE;
 544         i2c_op.target = phy_data->sfp_mux_address;
 545         i2c_op.len = sizeof(mux_channel);
 546         i2c_op.buf = &mux_channel;
 547 
 548         return xgbe_phy_i2c_xfer(pdata, &i2c_op);
 549 }
 550 
 551 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
 552 {
 553         mutex_unlock(&xgbe_phy_comm_lock);
 554 }
 555 
 556 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
 557 {
 558         struct xgbe_phy_data *phy_data = pdata->phy_data;
 559         unsigned long timeout;
 560         unsigned int mutex_id;
 561 
 562         /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
 563          * the driver needs to take the software mutex and then the hardware
 564          * mutexes before being able to use the busses.
 565          */
 566         mutex_lock(&xgbe_phy_comm_lock);
 567 
 568         /* Clear the mutexes */
 569         XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
 570         XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
 571 
 572         /* Mutex formats are the same for I2C and MDIO/GPIO */
 573         mutex_id = 0;
 574         XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
 575         XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
 576 
 577         timeout = jiffies + (5 * HZ);
 578         while (time_before(jiffies, timeout)) {
 579                 /* Must be all zeroes in order to obtain the mutex */
 580                 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
 581                     XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
 582                         usleep_range(100, 200);
 583                         continue;
 584                 }
 585 
 586                 /* Obtain the mutex */
 587                 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
 588                 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
 589 
 590                 return 0;
 591         }
 592 
 593         mutex_unlock(&xgbe_phy_comm_lock);
 594 
 595         netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
 596 
 597         return -ETIMEDOUT;
 598 }
 599 
 600 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
 601                                    int reg, u16 val)
 602 {
 603         struct xgbe_phy_data *phy_data = pdata->phy_data;
 604 
 605         if (reg & MII_ADDR_C45) {
 606                 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
 607                         return -ENOTSUPP;
 608         } else {
 609                 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
 610                         return -ENOTSUPP;
 611         }
 612 
 613         return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
 614 }
 615 
 616 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
 617 {
 618         __be16 *mii_val;
 619         u8 mii_data[3];
 620         int ret;
 621 
 622         ret = xgbe_phy_sfp_get_mux(pdata);
 623         if (ret)
 624                 return ret;
 625 
 626         mii_data[0] = reg & 0xff;
 627         mii_val = (__be16 *)&mii_data[1];
 628         *mii_val = cpu_to_be16(val);
 629 
 630         ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
 631                                  mii_data, sizeof(mii_data));
 632 
 633         xgbe_phy_sfp_put_mux(pdata);
 634 
 635         return ret;
 636 }
 637 
 638 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
 639 {
 640         struct xgbe_prv_data *pdata = mii->priv;
 641         struct xgbe_phy_data *phy_data = pdata->phy_data;
 642         int ret;
 643 
 644         ret = xgbe_phy_get_comm_ownership(pdata);
 645         if (ret)
 646                 return ret;
 647 
 648         if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
 649                 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
 650         else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
 651                 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
 652         else
 653                 ret = -ENOTSUPP;
 654 
 655         xgbe_phy_put_comm_ownership(pdata);
 656 
 657         return ret;
 658 }
 659 
 660 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
 661                                   int reg)
 662 {
 663         struct xgbe_phy_data *phy_data = pdata->phy_data;
 664 
 665         if (reg & MII_ADDR_C45) {
 666                 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
 667                         return -ENOTSUPP;
 668         } else {
 669                 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
 670                         return -ENOTSUPP;
 671         }
 672 
 673         return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
 674 }
 675 
 676 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
 677 {
 678         __be16 mii_val;
 679         u8 mii_reg;
 680         int ret;
 681 
 682         ret = xgbe_phy_sfp_get_mux(pdata);
 683         if (ret)
 684                 return ret;
 685 
 686         mii_reg = reg;
 687         ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
 688                                 &mii_reg, sizeof(mii_reg),
 689                                 &mii_val, sizeof(mii_val));
 690         if (!ret)
 691                 ret = be16_to_cpu(mii_val);
 692 
 693         xgbe_phy_sfp_put_mux(pdata);
 694 
 695         return ret;
 696 }
 697 
 698 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
 699 {
 700         struct xgbe_prv_data *pdata = mii->priv;
 701         struct xgbe_phy_data *phy_data = pdata->phy_data;
 702         int ret;
 703 
 704         ret = xgbe_phy_get_comm_ownership(pdata);
 705         if (ret)
 706                 return ret;
 707 
 708         if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
 709                 ret = xgbe_phy_i2c_mii_read(pdata, reg);
 710         else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
 711                 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
 712         else
 713                 ret = -ENOTSUPP;
 714 
 715         xgbe_phy_put_comm_ownership(pdata);
 716 
 717         return ret;
 718 }
 719 
 720 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
 721 {
 722         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
 723         struct xgbe_phy_data *phy_data = pdata->phy_data;
 724 
 725         if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
 726                 return;
 727 
 728         XGBE_ZERO_SUP(lks);
 729 
 730         if (phy_data->sfp_mod_absent) {
 731                 pdata->phy.speed = SPEED_UNKNOWN;
 732                 pdata->phy.duplex = DUPLEX_UNKNOWN;
 733                 pdata->phy.autoneg = AUTONEG_ENABLE;
 734                 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
 735 
 736                 XGBE_SET_SUP(lks, Autoneg);
 737                 XGBE_SET_SUP(lks, Pause);
 738                 XGBE_SET_SUP(lks, Asym_Pause);
 739                 XGBE_SET_SUP(lks, TP);
 740                 XGBE_SET_SUP(lks, FIBRE);
 741 
 742                 XGBE_LM_COPY(lks, advertising, lks, supported);
 743 
 744                 return;
 745         }
 746 
 747         switch (phy_data->sfp_base) {
 748         case XGBE_SFP_BASE_1000_T:
 749         case XGBE_SFP_BASE_1000_SX:
 750         case XGBE_SFP_BASE_1000_LX:
 751         case XGBE_SFP_BASE_1000_CX:
 752                 pdata->phy.speed = SPEED_UNKNOWN;
 753                 pdata->phy.duplex = DUPLEX_UNKNOWN;
 754                 pdata->phy.autoneg = AUTONEG_ENABLE;
 755                 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
 756                 XGBE_SET_SUP(lks, Autoneg);
 757                 XGBE_SET_SUP(lks, Pause);
 758                 XGBE_SET_SUP(lks, Asym_Pause);
 759                 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
 760                         if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
 761                                 XGBE_SET_SUP(lks, 100baseT_Full);
 762                         if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
 763                                 XGBE_SET_SUP(lks, 1000baseT_Full);
 764                 } else {
 765                         if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
 766                                 XGBE_SET_SUP(lks, 1000baseX_Full);
 767                 }
 768                 break;
 769         case XGBE_SFP_BASE_10000_SR:
 770         case XGBE_SFP_BASE_10000_LR:
 771         case XGBE_SFP_BASE_10000_LRM:
 772         case XGBE_SFP_BASE_10000_ER:
 773         case XGBE_SFP_BASE_10000_CR:
 774                 pdata->phy.speed = SPEED_10000;
 775                 pdata->phy.duplex = DUPLEX_FULL;
 776                 pdata->phy.autoneg = AUTONEG_DISABLE;
 777                 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
 778                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
 779                         switch (phy_data->sfp_base) {
 780                         case XGBE_SFP_BASE_10000_SR:
 781                                 XGBE_SET_SUP(lks, 10000baseSR_Full);
 782                                 break;
 783                         case XGBE_SFP_BASE_10000_LR:
 784                                 XGBE_SET_SUP(lks, 10000baseLR_Full);
 785                                 break;
 786                         case XGBE_SFP_BASE_10000_LRM:
 787                                 XGBE_SET_SUP(lks, 10000baseLRM_Full);
 788                                 break;
 789                         case XGBE_SFP_BASE_10000_ER:
 790                                 XGBE_SET_SUP(lks, 10000baseER_Full);
 791                                 break;
 792                         case XGBE_SFP_BASE_10000_CR:
 793                                 XGBE_SET_SUP(lks, 10000baseCR_Full);
 794                                 break;
 795                         default:
 796                                 break;
 797                         }
 798                 }
 799                 break;
 800         default:
 801                 pdata->phy.speed = SPEED_UNKNOWN;
 802                 pdata->phy.duplex = DUPLEX_UNKNOWN;
 803                 pdata->phy.autoneg = AUTONEG_DISABLE;
 804                 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
 805                 break;
 806         }
 807 
 808         switch (phy_data->sfp_base) {
 809         case XGBE_SFP_BASE_1000_T:
 810         case XGBE_SFP_BASE_1000_CX:
 811         case XGBE_SFP_BASE_10000_CR:
 812                 XGBE_SET_SUP(lks, TP);
 813                 break;
 814         default:
 815                 XGBE_SET_SUP(lks, FIBRE);
 816                 break;
 817         }
 818 
 819         XGBE_LM_COPY(lks, advertising, lks, supported);
 820 }
 821 
 822 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
 823                                   enum xgbe_sfp_speed sfp_speed)
 824 {
 825         u8 *sfp_base, min, max;
 826 
 827         sfp_base = sfp_eeprom->base;
 828 
 829         switch (sfp_speed) {
 830         case XGBE_SFP_SPEED_1000:
 831                 min = XGBE_SFP_BASE_BR_1GBE_MIN;
 832                 max = XGBE_SFP_BASE_BR_1GBE_MAX;
 833                 break;
 834         case XGBE_SFP_SPEED_10000:
 835                 min = XGBE_SFP_BASE_BR_10GBE_MIN;
 836                 max = XGBE_SFP_BASE_BR_10GBE_MAX;
 837                 break;
 838         default:
 839                 return false;
 840         }
 841 
 842         return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
 843                 (sfp_base[XGBE_SFP_BASE_BR] <= max));
 844 }
 845 
 846 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
 847 {
 848         struct xgbe_phy_data *phy_data = pdata->phy_data;
 849 
 850         if (phy_data->phydev) {
 851                 phy_detach(phy_data->phydev);
 852                 phy_device_remove(phy_data->phydev);
 853                 phy_device_free(phy_data->phydev);
 854                 phy_data->phydev = NULL;
 855         }
 856 }
 857 
 858 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
 859 {
 860         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
 861         struct xgbe_phy_data *phy_data = pdata->phy_data;
 862         unsigned int phy_id = phy_data->phydev->phy_id;
 863 
 864         if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
 865                 return false;
 866 
 867         if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
 868                 return false;
 869 
 870         /* Enable Base-T AN */
 871         phy_write(phy_data->phydev, 0x16, 0x0001);
 872         phy_write(phy_data->phydev, 0x00, 0x9140);
 873         phy_write(phy_data->phydev, 0x16, 0x0000);
 874 
 875         /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
 876         phy_write(phy_data->phydev, 0x1b, 0x9084);
 877         phy_write(phy_data->phydev, 0x09, 0x0e00);
 878         phy_write(phy_data->phydev, 0x00, 0x8140);
 879         phy_write(phy_data->phydev, 0x04, 0x0d01);
 880         phy_write(phy_data->phydev, 0x00, 0x9140);
 881 
 882         linkmode_set_bit_array(phy_10_100_features_array,
 883                                ARRAY_SIZE(phy_10_100_features_array),
 884                                supported);
 885         linkmode_set_bit_array(phy_gbit_features_array,
 886                                ARRAY_SIZE(phy_gbit_features_array),
 887                                supported);
 888 
 889         linkmode_copy(phy_data->phydev->supported, supported);
 890 
 891         phy_support_asym_pause(phy_data->phydev);
 892 
 893         netif_dbg(pdata, drv, pdata->netdev,
 894                   "Finisar PHY quirk in place\n");
 895 
 896         return true;
 897 }
 898 
 899 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
 900 {
 901         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
 902         struct xgbe_phy_data *phy_data = pdata->phy_data;
 903         struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
 904         unsigned int phy_id = phy_data->phydev->phy_id;
 905         int reg;
 906 
 907         if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
 908                 return false;
 909 
 910         if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
 911                    XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
 912                 return false;
 913 
 914         /* For Bel-Fuse, use the extra AN flag */
 915         pdata->an_again = 1;
 916 
 917         if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
 918                    XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
 919                 return false;
 920 
 921         if ((phy_id & 0xfffffff0) != 0x03625d10)
 922                 return false;
 923 
 924         /* Disable RGMII mode */
 925         phy_write(phy_data->phydev, 0x18, 0x7007);
 926         reg = phy_read(phy_data->phydev, 0x18);
 927         phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
 928 
 929         /* Enable fiber register bank */
 930         phy_write(phy_data->phydev, 0x1c, 0x7c00);
 931         reg = phy_read(phy_data->phydev, 0x1c);
 932         reg &= 0x03ff;
 933         reg &= ~0x0001;
 934         phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
 935 
 936         /* Power down SerDes */
 937         reg = phy_read(phy_data->phydev, 0x00);
 938         phy_write(phy_data->phydev, 0x00, reg | 0x00800);
 939 
 940         /* Configure SGMII-to-Copper mode */
 941         phy_write(phy_data->phydev, 0x1c, 0x7c00);
 942         reg = phy_read(phy_data->phydev, 0x1c);
 943         reg &= 0x03ff;
 944         reg &= ~0x0006;
 945         phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
 946 
 947         /* Power up SerDes */
 948         reg = phy_read(phy_data->phydev, 0x00);
 949         phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
 950 
 951         /* Enable copper register bank */
 952         phy_write(phy_data->phydev, 0x1c, 0x7c00);
 953         reg = phy_read(phy_data->phydev, 0x1c);
 954         reg &= 0x03ff;
 955         reg &= ~0x0001;
 956         phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
 957 
 958         /* Power up SerDes */
 959         reg = phy_read(phy_data->phydev, 0x00);
 960         phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
 961 
 962         linkmode_set_bit_array(phy_10_100_features_array,
 963                                ARRAY_SIZE(phy_10_100_features_array),
 964                                supported);
 965         linkmode_set_bit_array(phy_gbit_features_array,
 966                                ARRAY_SIZE(phy_gbit_features_array),
 967                                supported);
 968         linkmode_copy(phy_data->phydev->supported, supported);
 969         phy_support_asym_pause(phy_data->phydev);
 970 
 971         netif_dbg(pdata, drv, pdata->netdev,
 972                   "BelFuse PHY quirk in place\n");
 973 
 974         return true;
 975 }
 976 
 977 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
 978 {
 979         if (xgbe_phy_belfuse_phy_quirks(pdata))
 980                 return;
 981 
 982         if (xgbe_phy_finisar_phy_quirks(pdata))
 983                 return;
 984 }
 985 
 986 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
 987 {
 988         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
 989         struct xgbe_phy_data *phy_data = pdata->phy_data;
 990         struct phy_device *phydev;
 991         int ret;
 992 
 993         /* If we already have a PHY, just return */
 994         if (phy_data->phydev)
 995                 return 0;
 996 
 997         /* Clear the extra AN flag */
 998         pdata->an_again = 0;
 999 
1000         /* Check for the use of an external PHY */
1001         if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1002                 return 0;
1003 
1004         /* For SFP, only use an external PHY if available */
1005         if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1006             !phy_data->sfp_phy_avail)
1007                 return 0;
1008 
1009         /* Set the proper MDIO mode for the PHY */
1010         ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1011                                             phy_data->phydev_mode);
1012         if (ret) {
1013                 netdev_err(pdata->netdev,
1014                            "mdio port/clause not compatible (%u/%u)\n",
1015                            phy_data->mdio_addr, phy_data->phydev_mode);
1016                 return ret;
1017         }
1018 
1019         /* Create and connect to the PHY device */
1020         phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1021                                 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1022         if (IS_ERR(phydev)) {
1023                 netdev_err(pdata->netdev, "get_phy_device failed\n");
1024                 return -ENODEV;
1025         }
1026         netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1027                   phydev->phy_id);
1028 
1029         /*TODO: If c45, add request_module based on one of the MMD ids? */
1030 
1031         ret = phy_device_register(phydev);
1032         if (ret) {
1033                 netdev_err(pdata->netdev, "phy_device_register failed\n");
1034                 phy_device_free(phydev);
1035                 return ret;
1036         }
1037 
1038         ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1039                                 PHY_INTERFACE_MODE_SGMII);
1040         if (ret) {
1041                 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1042                 phy_device_remove(phydev);
1043                 phy_device_free(phydev);
1044                 return ret;
1045         }
1046         phy_data->phydev = phydev;
1047 
1048         xgbe_phy_external_phy_quirks(pdata);
1049 
1050         linkmode_and(phydev->advertising, phydev->advertising,
1051                      lks->link_modes.advertising);
1052 
1053         phy_start_aneg(phy_data->phydev);
1054 
1055         return 0;
1056 }
1057 
1058 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1059 {
1060         struct xgbe_phy_data *phy_data = pdata->phy_data;
1061         int ret;
1062 
1063         if (!phy_data->sfp_changed)
1064                 return;
1065 
1066         phy_data->sfp_phy_avail = 0;
1067 
1068         if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1069                 return;
1070 
1071         /* Check access to the PHY by reading CTRL1 */
1072         ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1073         if (ret < 0)
1074                 return;
1075 
1076         /* Successfully accessed the PHY */
1077         phy_data->sfp_phy_avail = 1;
1078 }
1079 
1080 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1081 {
1082         u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1083 
1084         if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1085                 return false;
1086 
1087         if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1088                 return false;
1089 
1090         if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1091                 return true;
1092 
1093         return false;
1094 }
1095 
1096 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1097 {
1098         u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1099 
1100         if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1101                 return false;
1102 
1103         if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1104                 return false;
1105 
1106         if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1107                 return true;
1108 
1109         return false;
1110 }
1111 
1112 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1113 {
1114         if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1115                 return false;
1116 
1117         if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1118                 return true;
1119 
1120         return false;
1121 }
1122 
1123 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1124 {
1125         struct xgbe_phy_data *phy_data = pdata->phy_data;
1126         struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1127         u8 *sfp_base;
1128 
1129         sfp_base = sfp_eeprom->base;
1130 
1131         if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1132                 return;
1133 
1134         if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1135                 return;
1136 
1137         /* Update transceiver signals (eeprom extd/options) */
1138         phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1139         phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1140 
1141         /* Assume ACTIVE cable unless told it is PASSIVE */
1142         if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1143                 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1144                 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1145         } else {
1146                 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1147         }
1148 
1149         /* Determine the type of SFP */
1150         if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1151                 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1152         else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1153                 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1154         else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1155                 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1156         else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1157                 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1158         else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1159                 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1160         else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1161                 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1162         else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1163                 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1164         else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1165                 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1166         else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1167                  xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1168                 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1169 
1170         switch (phy_data->sfp_base) {
1171         case XGBE_SFP_BASE_1000_T:
1172                 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1173                 break;
1174         case XGBE_SFP_BASE_1000_SX:
1175         case XGBE_SFP_BASE_1000_LX:
1176         case XGBE_SFP_BASE_1000_CX:
1177                 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1178                 break;
1179         case XGBE_SFP_BASE_10000_SR:
1180         case XGBE_SFP_BASE_10000_LR:
1181         case XGBE_SFP_BASE_10000_LRM:
1182         case XGBE_SFP_BASE_10000_ER:
1183         case XGBE_SFP_BASE_10000_CR:
1184                 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1185                 break;
1186         default:
1187                 break;
1188         }
1189 }
1190 
1191 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1192                                      struct xgbe_sfp_eeprom *sfp_eeprom)
1193 {
1194         struct xgbe_sfp_ascii sfp_ascii;
1195         char *sfp_data = (char *)&sfp_ascii;
1196 
1197         netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1198         memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1199                XGBE_SFP_BASE_VENDOR_NAME_LEN);
1200         sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1201         netif_dbg(pdata, drv, pdata->netdev, "  vendor:         %s\n",
1202                   sfp_data);
1203 
1204         memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1205                XGBE_SFP_BASE_VENDOR_PN_LEN);
1206         sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1207         netif_dbg(pdata, drv, pdata->netdev, "  part number:    %s\n",
1208                   sfp_data);
1209 
1210         memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1211                XGBE_SFP_BASE_VENDOR_REV_LEN);
1212         sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1213         netif_dbg(pdata, drv, pdata->netdev, "  revision level: %s\n",
1214                   sfp_data);
1215 
1216         memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1217                XGBE_SFP_BASE_VENDOR_SN_LEN);
1218         sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1219         netif_dbg(pdata, drv, pdata->netdev, "  serial number:  %s\n",
1220                   sfp_data);
1221 }
1222 
1223 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1224 {
1225         u8 cc;
1226 
1227         for (cc = 0; len; buf++, len--)
1228                 cc += *buf;
1229 
1230         return (cc == cc_in) ? true : false;
1231 }
1232 
1233 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1234 {
1235         struct xgbe_phy_data *phy_data = pdata->phy_data;
1236         struct xgbe_sfp_eeprom sfp_eeprom;
1237         u8 eeprom_addr;
1238         int ret;
1239 
1240         ret = xgbe_phy_sfp_get_mux(pdata);
1241         if (ret) {
1242                 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1243                              netdev_name(pdata->netdev));
1244                 return ret;
1245         }
1246 
1247         /* Read the SFP serial ID eeprom */
1248         eeprom_addr = 0;
1249         ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1250                                 &eeprom_addr, sizeof(eeprom_addr),
1251                                 &sfp_eeprom, sizeof(sfp_eeprom));
1252         if (ret) {
1253                 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1254                              netdev_name(pdata->netdev));
1255                 goto put;
1256         }
1257 
1258         /* Validate the contents read */
1259         if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1260                                         sfp_eeprom.base,
1261                                         sizeof(sfp_eeprom.base) - 1)) {
1262                 ret = -EINVAL;
1263                 goto put;
1264         }
1265 
1266         if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1267                                         sfp_eeprom.extd,
1268                                         sizeof(sfp_eeprom.extd) - 1)) {
1269                 ret = -EINVAL;
1270                 goto put;
1271         }
1272 
1273         /* Check for an added or changed SFP */
1274         if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1275                 phy_data->sfp_changed = 1;
1276 
1277                 if (netif_msg_drv(pdata))
1278                         xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1279 
1280                 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1281 
1282                 xgbe_phy_free_phy_device(pdata);
1283         } else {
1284                 phy_data->sfp_changed = 0;
1285         }
1286 
1287 put:
1288         xgbe_phy_sfp_put_mux(pdata);
1289 
1290         return ret;
1291 }
1292 
1293 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1294 {
1295         struct xgbe_phy_data *phy_data = pdata->phy_data;
1296         u8 gpio_reg, gpio_ports[2];
1297         int ret;
1298 
1299         /* Read the input port registers */
1300         gpio_reg = 0;
1301         ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1302                                 &gpio_reg, sizeof(gpio_reg),
1303                                 gpio_ports, sizeof(gpio_ports));
1304         if (ret) {
1305                 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1306                              netdev_name(pdata->netdev));
1307                 return;
1308         }
1309 
1310         phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1311 
1312         phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1313 }
1314 
1315 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1316 {
1317         struct xgbe_phy_data *phy_data = pdata->phy_data;
1318 
1319         xgbe_phy_free_phy_device(pdata);
1320 
1321         phy_data->sfp_mod_absent = 1;
1322         phy_data->sfp_phy_avail = 0;
1323         memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1324 }
1325 
1326 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1327 {
1328         phy_data->sfp_rx_los = 0;
1329         phy_data->sfp_tx_fault = 0;
1330         phy_data->sfp_mod_absent = 1;
1331         phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1332         phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1333         phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1334 }
1335 
1336 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1337 {
1338         struct xgbe_phy_data *phy_data = pdata->phy_data;
1339         int ret;
1340 
1341         /* Reset the SFP signals and info */
1342         xgbe_phy_sfp_reset(phy_data);
1343 
1344         ret = xgbe_phy_get_comm_ownership(pdata);
1345         if (ret)
1346                 return;
1347 
1348         /* Read the SFP signals and check for module presence */
1349         xgbe_phy_sfp_signals(pdata);
1350         if (phy_data->sfp_mod_absent) {
1351                 xgbe_phy_sfp_mod_absent(pdata);
1352                 goto put;
1353         }
1354 
1355         ret = xgbe_phy_sfp_read_eeprom(pdata);
1356         if (ret) {
1357                 /* Treat any error as if there isn't an SFP plugged in */
1358                 xgbe_phy_sfp_reset(phy_data);
1359                 xgbe_phy_sfp_mod_absent(pdata);
1360                 goto put;
1361         }
1362 
1363         xgbe_phy_sfp_parse_eeprom(pdata);
1364 
1365         xgbe_phy_sfp_external_phy(pdata);
1366 
1367 put:
1368         xgbe_phy_sfp_phy_settings(pdata);
1369 
1370         xgbe_phy_put_comm_ownership(pdata);
1371 }
1372 
1373 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1374                                   struct ethtool_eeprom *eeprom, u8 *data)
1375 {
1376         struct xgbe_phy_data *phy_data = pdata->phy_data;
1377         u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1378         struct xgbe_sfp_eeprom *sfp_eeprom;
1379         unsigned int i, j, rem;
1380         int ret;
1381 
1382         rem = eeprom->len;
1383 
1384         if (!eeprom->len) {
1385                 ret = -EINVAL;
1386                 goto done;
1387         }
1388 
1389         if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1390                 ret = -EINVAL;
1391                 goto done;
1392         }
1393 
1394         if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1395                 ret = -ENXIO;
1396                 goto done;
1397         }
1398 
1399         if (!netif_running(pdata->netdev)) {
1400                 ret = -EIO;
1401                 goto done;
1402         }
1403 
1404         if (phy_data->sfp_mod_absent) {
1405                 ret = -EIO;
1406                 goto done;
1407         }
1408 
1409         ret = xgbe_phy_get_comm_ownership(pdata);
1410         if (ret) {
1411                 ret = -EIO;
1412                 goto done;
1413         }
1414 
1415         ret = xgbe_phy_sfp_get_mux(pdata);
1416         if (ret) {
1417                 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1418                 ret = -EIO;
1419                 goto put_own;
1420         }
1421 
1422         /* Read the SFP serial ID eeprom */
1423         eeprom_addr = 0;
1424         ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1425                                 &eeprom_addr, sizeof(eeprom_addr),
1426                                 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1427         if (ret) {
1428                 netdev_err(pdata->netdev,
1429                            "I2C error reading SFP EEPROM\n");
1430                 ret = -EIO;
1431                 goto put_mux;
1432         }
1433 
1434         sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1435 
1436         if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1437                 /* Read the SFP diagnostic eeprom */
1438                 eeprom_addr = 0;
1439                 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1440                                         &eeprom_addr, sizeof(eeprom_addr),
1441                                         eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1442                                         XGBE_SFP_EEPROM_DIAG_LEN);
1443                 if (ret) {
1444                         netdev_err(pdata->netdev,
1445                                    "I2C error reading SFP DIAGS\n");
1446                         ret = -EIO;
1447                         goto put_mux;
1448                 }
1449         }
1450 
1451         for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1452                 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1453                     !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1454                         break;
1455 
1456                 data[i] = eeprom_data[j];
1457                 rem--;
1458         }
1459 
1460 put_mux:
1461         xgbe_phy_sfp_put_mux(pdata);
1462 
1463 put_own:
1464         xgbe_phy_put_comm_ownership(pdata);
1465 
1466 done:
1467         eeprom->len -= rem;
1468 
1469         return ret;
1470 }
1471 
1472 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1473                                 struct ethtool_modinfo *modinfo)
1474 {
1475         struct xgbe_phy_data *phy_data = pdata->phy_data;
1476 
1477         if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1478                 return -ENXIO;
1479 
1480         if (!netif_running(pdata->netdev))
1481                 return -EIO;
1482 
1483         if (phy_data->sfp_mod_absent)
1484                 return -EIO;
1485 
1486         if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1487                 modinfo->type = ETH_MODULE_SFF_8472;
1488                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1489         } else {
1490                 modinfo->type = ETH_MODULE_SFF_8079;
1491                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1492         }
1493 
1494         return 0;
1495 }
1496 
1497 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1498 {
1499         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1500         struct xgbe_phy_data *phy_data = pdata->phy_data;
1501         u16 lcl_adv = 0, rmt_adv = 0;
1502         u8 fc;
1503 
1504         pdata->phy.tx_pause = 0;
1505         pdata->phy.rx_pause = 0;
1506 
1507         if (!phy_data->phydev)
1508                 return;
1509 
1510         lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1511 
1512         if (phy_data->phydev->pause) {
1513                 XGBE_SET_LP_ADV(lks, Pause);
1514                 rmt_adv |= LPA_PAUSE_CAP;
1515         }
1516         if (phy_data->phydev->asym_pause) {
1517                 XGBE_SET_LP_ADV(lks, Asym_Pause);
1518                 rmt_adv |= LPA_PAUSE_ASYM;
1519         }
1520 
1521         fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1522         if (fc & FLOW_CTRL_TX)
1523                 pdata->phy.tx_pause = 1;
1524         if (fc & FLOW_CTRL_RX)
1525                 pdata->phy.rx_pause = 1;
1526 }
1527 
1528 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1529 {
1530         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1531         enum xgbe_mode mode;
1532 
1533         XGBE_SET_LP_ADV(lks, Autoneg);
1534         XGBE_SET_LP_ADV(lks, TP);
1535 
1536         /* Use external PHY to determine flow control */
1537         if (pdata->phy.pause_autoneg)
1538                 xgbe_phy_phydev_flowctrl(pdata);
1539 
1540         switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1541         case XGBE_SGMII_AN_LINK_SPEED_100:
1542                 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1543                         XGBE_SET_LP_ADV(lks, 100baseT_Full);
1544                         mode = XGBE_MODE_SGMII_100;
1545                 } else {
1546                         /* Half-duplex not supported */
1547                         XGBE_SET_LP_ADV(lks, 100baseT_Half);
1548                         mode = XGBE_MODE_UNKNOWN;
1549                 }
1550                 break;
1551         case XGBE_SGMII_AN_LINK_SPEED_1000:
1552                 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1553                         XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1554                         mode = XGBE_MODE_SGMII_1000;
1555                 } else {
1556                         /* Half-duplex not supported */
1557                         XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1558                         mode = XGBE_MODE_UNKNOWN;
1559                 }
1560                 break;
1561         default:
1562                 mode = XGBE_MODE_UNKNOWN;
1563         }
1564 
1565         return mode;
1566 }
1567 
1568 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1569 {
1570         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1571         enum xgbe_mode mode;
1572         unsigned int ad_reg, lp_reg;
1573 
1574         XGBE_SET_LP_ADV(lks, Autoneg);
1575         XGBE_SET_LP_ADV(lks, FIBRE);
1576 
1577         /* Compare Advertisement and Link Partner register */
1578         ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1579         lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1580         if (lp_reg & 0x100)
1581                 XGBE_SET_LP_ADV(lks, Pause);
1582         if (lp_reg & 0x80)
1583                 XGBE_SET_LP_ADV(lks, Asym_Pause);
1584 
1585         if (pdata->phy.pause_autoneg) {
1586                 /* Set flow control based on auto-negotiation result */
1587                 pdata->phy.tx_pause = 0;
1588                 pdata->phy.rx_pause = 0;
1589 
1590                 if (ad_reg & lp_reg & 0x100) {
1591                         pdata->phy.tx_pause = 1;
1592                         pdata->phy.rx_pause = 1;
1593                 } else if (ad_reg & lp_reg & 0x80) {
1594                         if (ad_reg & 0x100)
1595                                 pdata->phy.rx_pause = 1;
1596                         else if (lp_reg & 0x100)
1597                                 pdata->phy.tx_pause = 1;
1598                 }
1599         }
1600 
1601         if (lp_reg & 0x20)
1602                 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1603 
1604         /* Half duplex is not supported */
1605         ad_reg &= lp_reg;
1606         mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1607 
1608         return mode;
1609 }
1610 
1611 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1612 {
1613         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1614         struct xgbe_phy_data *phy_data = pdata->phy_data;
1615         enum xgbe_mode mode;
1616         unsigned int ad_reg, lp_reg;
1617 
1618         XGBE_SET_LP_ADV(lks, Autoneg);
1619         XGBE_SET_LP_ADV(lks, Backplane);
1620 
1621         /* Use external PHY to determine flow control */
1622         if (pdata->phy.pause_autoneg)
1623                 xgbe_phy_phydev_flowctrl(pdata);
1624 
1625         /* Compare Advertisement and Link Partner register 2 */
1626         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1627         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1628         if (lp_reg & 0x80)
1629                 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1630         if (lp_reg & 0x20)
1631                 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1632 
1633         ad_reg &= lp_reg;
1634         if (ad_reg & 0x80) {
1635                 switch (phy_data->port_mode) {
1636                 case XGBE_PORT_MODE_BACKPLANE:
1637                         mode = XGBE_MODE_KR;
1638                         break;
1639                 default:
1640                         mode = XGBE_MODE_SFI;
1641                         break;
1642                 }
1643         } else if (ad_reg & 0x20) {
1644                 switch (phy_data->port_mode) {
1645                 case XGBE_PORT_MODE_BACKPLANE:
1646                         mode = XGBE_MODE_KX_1000;
1647                         break;
1648                 case XGBE_PORT_MODE_1000BASE_X:
1649                         mode = XGBE_MODE_X;
1650                         break;
1651                 case XGBE_PORT_MODE_SFP:
1652                         switch (phy_data->sfp_base) {
1653                         case XGBE_SFP_BASE_1000_T:
1654                                 if (phy_data->phydev &&
1655                                     (phy_data->phydev->speed == SPEED_100))
1656                                         mode = XGBE_MODE_SGMII_100;
1657                                 else
1658                                         mode = XGBE_MODE_SGMII_1000;
1659                                 break;
1660                         case XGBE_SFP_BASE_1000_SX:
1661                         case XGBE_SFP_BASE_1000_LX:
1662                         case XGBE_SFP_BASE_1000_CX:
1663                         default:
1664                                 mode = XGBE_MODE_X;
1665                                 break;
1666                         }
1667                         break;
1668                 default:
1669                         if (phy_data->phydev &&
1670                             (phy_data->phydev->speed == SPEED_100))
1671                                 mode = XGBE_MODE_SGMII_100;
1672                         else
1673                                 mode = XGBE_MODE_SGMII_1000;
1674                         break;
1675                 }
1676         } else {
1677                 mode = XGBE_MODE_UNKNOWN;
1678         }
1679 
1680         /* Compare Advertisement and Link Partner register 3 */
1681         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1682         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1683         if (lp_reg & 0xc000)
1684                 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1685 
1686         return mode;
1687 }
1688 
1689 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1690 {
1691         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1692         enum xgbe_mode mode;
1693         unsigned int ad_reg, lp_reg;
1694 
1695         XGBE_SET_LP_ADV(lks, Autoneg);
1696         XGBE_SET_LP_ADV(lks, Backplane);
1697 
1698         /* Compare Advertisement and Link Partner register 1 */
1699         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1700         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1701         if (lp_reg & 0x400)
1702                 XGBE_SET_LP_ADV(lks, Pause);
1703         if (lp_reg & 0x800)
1704                 XGBE_SET_LP_ADV(lks, Asym_Pause);
1705 
1706         if (pdata->phy.pause_autoneg) {
1707                 /* Set flow control based on auto-negotiation result */
1708                 pdata->phy.tx_pause = 0;
1709                 pdata->phy.rx_pause = 0;
1710 
1711                 if (ad_reg & lp_reg & 0x400) {
1712                         pdata->phy.tx_pause = 1;
1713                         pdata->phy.rx_pause = 1;
1714                 } else if (ad_reg & lp_reg & 0x800) {
1715                         if (ad_reg & 0x400)
1716                                 pdata->phy.rx_pause = 1;
1717                         else if (lp_reg & 0x400)
1718                                 pdata->phy.tx_pause = 1;
1719                 }
1720         }
1721 
1722         /* Compare Advertisement and Link Partner register 2 */
1723         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1724         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1725         if (lp_reg & 0x80)
1726                 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1727         if (lp_reg & 0x20)
1728                 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1729 
1730         ad_reg &= lp_reg;
1731         if (ad_reg & 0x80)
1732                 mode = XGBE_MODE_KR;
1733         else if (ad_reg & 0x20)
1734                 mode = XGBE_MODE_KX_1000;
1735         else
1736                 mode = XGBE_MODE_UNKNOWN;
1737 
1738         /* Compare Advertisement and Link Partner register 3 */
1739         ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1740         lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1741         if (lp_reg & 0xc000)
1742                 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1743 
1744         return mode;
1745 }
1746 
1747 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1748 {
1749         switch (pdata->an_mode) {
1750         case XGBE_AN_MODE_CL73:
1751                 return xgbe_phy_an73_outcome(pdata);
1752         case XGBE_AN_MODE_CL73_REDRV:
1753                 return xgbe_phy_an73_redrv_outcome(pdata);
1754         case XGBE_AN_MODE_CL37:
1755                 return xgbe_phy_an37_outcome(pdata);
1756         case XGBE_AN_MODE_CL37_SGMII:
1757                 return xgbe_phy_an37_sgmii_outcome(pdata);
1758         default:
1759                 return XGBE_MODE_UNKNOWN;
1760         }
1761 }
1762 
1763 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1764                                     struct ethtool_link_ksettings *dlks)
1765 {
1766         struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1767         struct xgbe_phy_data *phy_data = pdata->phy_data;
1768 
1769         XGBE_LM_COPY(dlks, advertising, slks, advertising);
1770 
1771         /* Without a re-driver, just return current advertising */
1772         if (!phy_data->redrv)
1773                 return;
1774 
1775         /* With the KR re-driver we need to advertise a single speed */
1776         XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1777         XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1778 
1779         /* Advertise FEC support is present */
1780         if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1781                 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1782 
1783         switch (phy_data->port_mode) {
1784         case XGBE_PORT_MODE_BACKPLANE:
1785                 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1786                 break;
1787         case XGBE_PORT_MODE_BACKPLANE_2500:
1788                 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1789                 break;
1790         case XGBE_PORT_MODE_1000BASE_T:
1791         case XGBE_PORT_MODE_1000BASE_X:
1792         case XGBE_PORT_MODE_NBASE_T:
1793                 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1794                 break;
1795         case XGBE_PORT_MODE_10GBASE_T:
1796                 if (phy_data->phydev &&
1797                     (phy_data->phydev->speed == SPEED_10000))
1798                         XGBE_SET_ADV(dlks, 10000baseKR_Full);
1799                 else
1800                         XGBE_SET_ADV(dlks, 1000baseKX_Full);
1801                 break;
1802         case XGBE_PORT_MODE_10GBASE_R:
1803                 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1804                 break;
1805         case XGBE_PORT_MODE_SFP:
1806                 switch (phy_data->sfp_base) {
1807                 case XGBE_SFP_BASE_1000_T:
1808                 case XGBE_SFP_BASE_1000_SX:
1809                 case XGBE_SFP_BASE_1000_LX:
1810                 case XGBE_SFP_BASE_1000_CX:
1811                         XGBE_SET_ADV(dlks, 1000baseKX_Full);
1812                         break;
1813                 default:
1814                         XGBE_SET_ADV(dlks, 10000baseKR_Full);
1815                         break;
1816                 }
1817                 break;
1818         default:
1819                 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1820                 break;
1821         }
1822 }
1823 
1824 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1825 {
1826         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1827         struct xgbe_phy_data *phy_data = pdata->phy_data;
1828         int ret;
1829 
1830         ret = xgbe_phy_find_phy_device(pdata);
1831         if (ret)
1832                 return ret;
1833 
1834         if (!phy_data->phydev)
1835                 return 0;
1836 
1837         phy_data->phydev->autoneg = pdata->phy.autoneg;
1838         linkmode_and(phy_data->phydev->advertising,
1839                      phy_data->phydev->supported,
1840                      lks->link_modes.advertising);
1841 
1842         if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1843                 phy_data->phydev->speed = pdata->phy.speed;
1844                 phy_data->phydev->duplex = pdata->phy.duplex;
1845         }
1846 
1847         ret = phy_start_aneg(phy_data->phydev);
1848 
1849         return ret;
1850 }
1851 
1852 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1853 {
1854         switch (phy_data->sfp_base) {
1855         case XGBE_SFP_BASE_1000_T:
1856                 return XGBE_AN_MODE_CL37_SGMII;
1857         case XGBE_SFP_BASE_1000_SX:
1858         case XGBE_SFP_BASE_1000_LX:
1859         case XGBE_SFP_BASE_1000_CX:
1860                 return XGBE_AN_MODE_CL37;
1861         default:
1862                 return XGBE_AN_MODE_NONE;
1863         }
1864 }
1865 
1866 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1867 {
1868         struct xgbe_phy_data *phy_data = pdata->phy_data;
1869 
1870         /* A KR re-driver will always require CL73 AN */
1871         if (phy_data->redrv)
1872                 return XGBE_AN_MODE_CL73_REDRV;
1873 
1874         switch (phy_data->port_mode) {
1875         case XGBE_PORT_MODE_BACKPLANE:
1876                 return XGBE_AN_MODE_CL73;
1877         case XGBE_PORT_MODE_BACKPLANE_2500:
1878                 return XGBE_AN_MODE_NONE;
1879         case XGBE_PORT_MODE_1000BASE_T:
1880                 return XGBE_AN_MODE_CL37_SGMII;
1881         case XGBE_PORT_MODE_1000BASE_X:
1882                 return XGBE_AN_MODE_CL37;
1883         case XGBE_PORT_MODE_NBASE_T:
1884                 return XGBE_AN_MODE_CL37_SGMII;
1885         case XGBE_PORT_MODE_10GBASE_T:
1886                 return XGBE_AN_MODE_CL73;
1887         case XGBE_PORT_MODE_10GBASE_R:
1888                 return XGBE_AN_MODE_NONE;
1889         case XGBE_PORT_MODE_SFP:
1890                 return xgbe_phy_an_sfp_mode(phy_data);
1891         default:
1892                 return XGBE_AN_MODE_NONE;
1893         }
1894 }
1895 
1896 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1897                                         enum xgbe_phy_redrv_mode mode)
1898 {
1899         struct xgbe_phy_data *phy_data = pdata->phy_data;
1900         u16 redrv_reg, redrv_val;
1901 
1902         redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1903         redrv_val = (u16)mode;
1904 
1905         return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1906                                                redrv_reg, redrv_val);
1907 }
1908 
1909 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1910                                        enum xgbe_phy_redrv_mode mode)
1911 {
1912         struct xgbe_phy_data *phy_data = pdata->phy_data;
1913         unsigned int redrv_reg;
1914         int ret;
1915 
1916         /* Calculate the register to write */
1917         redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1918 
1919         ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1920 
1921         return ret;
1922 }
1923 
1924 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1925 {
1926         struct xgbe_phy_data *phy_data = pdata->phy_data;
1927         enum xgbe_phy_redrv_mode mode;
1928         int ret;
1929 
1930         if (!phy_data->redrv)
1931                 return;
1932 
1933         mode = XGBE_PHY_REDRV_MODE_CX;
1934         if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1935             (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1936             (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1937                 mode = XGBE_PHY_REDRV_MODE_SR;
1938 
1939         ret = xgbe_phy_get_comm_ownership(pdata);
1940         if (ret)
1941                 return;
1942 
1943         if (phy_data->redrv_if)
1944                 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1945         else
1946                 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1947 
1948         xgbe_phy_put_comm_ownership(pdata);
1949 }
1950 
1951 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1952                                         unsigned int cmd, unsigned int sub_cmd)
1953 {
1954         unsigned int s0 = 0;
1955         unsigned int wait;
1956 
1957         /* Log if a previous command did not complete */
1958         if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1959                 netif_dbg(pdata, link, pdata->netdev,
1960                           "firmware mailbox not ready for command\n");
1961 
1962         /* Construct the command */
1963         XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1964         XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1965 
1966         /* Issue the command */
1967         XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1968         XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1969         XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1970 
1971         /* Wait for command to complete */
1972         wait = XGBE_RATECHANGE_COUNT;
1973         while (wait--) {
1974                 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1975                         return;
1976 
1977                 usleep_range(1000, 2000);
1978         }
1979 
1980         netif_dbg(pdata, link, pdata->netdev,
1981                   "firmware mailbox command did not complete\n");
1982 }
1983 
1984 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1985 {
1986         /* Receiver Reset Cycle */
1987         xgbe_phy_perform_ratechange(pdata, 5, 0);
1988 
1989         netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1990 }
1991 
1992 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1993 {
1994         struct xgbe_phy_data *phy_data = pdata->phy_data;
1995 
1996         /* Power off */
1997         xgbe_phy_perform_ratechange(pdata, 0, 0);
1998 
1999         phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2000 
2001         netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2002 }
2003 
2004 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2005 {
2006         struct xgbe_phy_data *phy_data = pdata->phy_data;
2007 
2008         xgbe_phy_set_redrv_mode(pdata);
2009 
2010         /* 10G/SFI */
2011         if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2012                 xgbe_phy_perform_ratechange(pdata, 3, 0);
2013         } else {
2014                 if (phy_data->sfp_cable_len <= 1)
2015                         xgbe_phy_perform_ratechange(pdata, 3, 1);
2016                 else if (phy_data->sfp_cable_len <= 3)
2017                         xgbe_phy_perform_ratechange(pdata, 3, 2);
2018                 else
2019                         xgbe_phy_perform_ratechange(pdata, 3, 3);
2020         }
2021 
2022         phy_data->cur_mode = XGBE_MODE_SFI;
2023 
2024         netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2025 }
2026 
2027 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2028 {
2029         struct xgbe_phy_data *phy_data = pdata->phy_data;
2030 
2031         xgbe_phy_set_redrv_mode(pdata);
2032 
2033         /* 1G/X */
2034         xgbe_phy_perform_ratechange(pdata, 1, 3);
2035 
2036         phy_data->cur_mode = XGBE_MODE_X;
2037 
2038         netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2039 }
2040 
2041 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2042 {
2043         struct xgbe_phy_data *phy_data = pdata->phy_data;
2044 
2045         xgbe_phy_set_redrv_mode(pdata);
2046 
2047         /* 1G/SGMII */
2048         xgbe_phy_perform_ratechange(pdata, 1, 2);
2049 
2050         phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2051 
2052         netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2053 }
2054 
2055 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2056 {
2057         struct xgbe_phy_data *phy_data = pdata->phy_data;
2058 
2059         xgbe_phy_set_redrv_mode(pdata);
2060 
2061         /* 100M/SGMII */
2062         xgbe_phy_perform_ratechange(pdata, 1, 1);
2063 
2064         phy_data->cur_mode = XGBE_MODE_SGMII_100;
2065 
2066         netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2067 }
2068 
2069 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2070 {
2071         struct xgbe_phy_data *phy_data = pdata->phy_data;
2072 
2073         xgbe_phy_set_redrv_mode(pdata);
2074 
2075         /* 10G/KR */
2076         xgbe_phy_perform_ratechange(pdata, 4, 0);
2077 
2078         phy_data->cur_mode = XGBE_MODE_KR;
2079 
2080         netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2081 }
2082 
2083 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2084 {
2085         struct xgbe_phy_data *phy_data = pdata->phy_data;
2086 
2087         xgbe_phy_set_redrv_mode(pdata);
2088 
2089         /* 2.5G/KX */
2090         xgbe_phy_perform_ratechange(pdata, 2, 0);
2091 
2092         phy_data->cur_mode = XGBE_MODE_KX_2500;
2093 
2094         netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2095 }
2096 
2097 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2098 {
2099         struct xgbe_phy_data *phy_data = pdata->phy_data;
2100 
2101         xgbe_phy_set_redrv_mode(pdata);
2102 
2103         /* 1G/KX */
2104         xgbe_phy_perform_ratechange(pdata, 1, 3);
2105 
2106         phy_data->cur_mode = XGBE_MODE_KX_1000;
2107 
2108         netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2109 }
2110 
2111 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2112 {
2113         struct xgbe_phy_data *phy_data = pdata->phy_data;
2114 
2115         return phy_data->cur_mode;
2116 }
2117 
2118 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2119 {
2120         struct xgbe_phy_data *phy_data = pdata->phy_data;
2121 
2122         /* No switching if not 10GBase-T */
2123         if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2124                 return xgbe_phy_cur_mode(pdata);
2125 
2126         switch (xgbe_phy_cur_mode(pdata)) {
2127         case XGBE_MODE_SGMII_100:
2128         case XGBE_MODE_SGMII_1000:
2129                 return XGBE_MODE_KR;
2130         case XGBE_MODE_KR:
2131         default:
2132                 return XGBE_MODE_SGMII_1000;
2133         }
2134 }
2135 
2136 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2137 {
2138         return XGBE_MODE_KX_2500;
2139 }
2140 
2141 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2142 {
2143         /* If we are in KR switch to KX, and vice-versa */
2144         switch (xgbe_phy_cur_mode(pdata)) {
2145         case XGBE_MODE_KX_1000:
2146                 return XGBE_MODE_KR;
2147         case XGBE_MODE_KR:
2148         default:
2149                 return XGBE_MODE_KX_1000;
2150         }
2151 }
2152 
2153 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2154 {
2155         struct xgbe_phy_data *phy_data = pdata->phy_data;
2156 
2157         switch (phy_data->port_mode) {
2158         case XGBE_PORT_MODE_BACKPLANE:
2159                 return xgbe_phy_switch_bp_mode(pdata);
2160         case XGBE_PORT_MODE_BACKPLANE_2500:
2161                 return xgbe_phy_switch_bp_2500_mode(pdata);
2162         case XGBE_PORT_MODE_1000BASE_T:
2163         case XGBE_PORT_MODE_NBASE_T:
2164         case XGBE_PORT_MODE_10GBASE_T:
2165                 return xgbe_phy_switch_baset_mode(pdata);
2166         case XGBE_PORT_MODE_1000BASE_X:
2167         case XGBE_PORT_MODE_10GBASE_R:
2168         case XGBE_PORT_MODE_SFP:
2169                 /* No switching, so just return current mode */
2170                 return xgbe_phy_cur_mode(pdata);
2171         default:
2172                 return XGBE_MODE_UNKNOWN;
2173         }
2174 }
2175 
2176 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2177                                               int speed)
2178 {
2179         switch (speed) {
2180         case SPEED_1000:
2181                 return XGBE_MODE_X;
2182         case SPEED_10000:
2183                 return XGBE_MODE_KR;
2184         default:
2185                 return XGBE_MODE_UNKNOWN;
2186         }
2187 }
2188 
2189 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2190                                               int speed)
2191 {
2192         switch (speed) {
2193         case SPEED_100:
2194                 return XGBE_MODE_SGMII_100;
2195         case SPEED_1000:
2196                 return XGBE_MODE_SGMII_1000;
2197         case SPEED_2500:
2198                 return XGBE_MODE_KX_2500;
2199         case SPEED_10000:
2200                 return XGBE_MODE_KR;
2201         default:
2202                 return XGBE_MODE_UNKNOWN;
2203         }
2204 }
2205 
2206 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2207                                             int speed)
2208 {
2209         switch (speed) {
2210         case SPEED_100:
2211                 return XGBE_MODE_SGMII_100;
2212         case SPEED_1000:
2213                 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2214                         return XGBE_MODE_SGMII_1000;
2215                 else
2216                         return XGBE_MODE_X;
2217         case SPEED_10000:
2218         case SPEED_UNKNOWN:
2219                 return XGBE_MODE_SFI;
2220         default:
2221                 return XGBE_MODE_UNKNOWN;
2222         }
2223 }
2224 
2225 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2226 {
2227         switch (speed) {
2228         case SPEED_2500:
2229                 return XGBE_MODE_KX_2500;
2230         default:
2231                 return XGBE_MODE_UNKNOWN;
2232         }
2233 }
2234 
2235 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2236 {
2237         switch (speed) {
2238         case SPEED_1000:
2239                 return XGBE_MODE_KX_1000;
2240         case SPEED_10000:
2241                 return XGBE_MODE_KR;
2242         default:
2243                 return XGBE_MODE_UNKNOWN;
2244         }
2245 }
2246 
2247 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2248                                         int speed)
2249 {
2250         struct xgbe_phy_data *phy_data = pdata->phy_data;
2251 
2252         switch (phy_data->port_mode) {
2253         case XGBE_PORT_MODE_BACKPLANE:
2254                 return xgbe_phy_get_bp_mode(speed);
2255         case XGBE_PORT_MODE_BACKPLANE_2500:
2256                 return xgbe_phy_get_bp_2500_mode(speed);
2257         case XGBE_PORT_MODE_1000BASE_T:
2258         case XGBE_PORT_MODE_NBASE_T:
2259         case XGBE_PORT_MODE_10GBASE_T:
2260                 return xgbe_phy_get_baset_mode(phy_data, speed);
2261         case XGBE_PORT_MODE_1000BASE_X:
2262         case XGBE_PORT_MODE_10GBASE_R:
2263                 return xgbe_phy_get_basex_mode(phy_data, speed);
2264         case XGBE_PORT_MODE_SFP:
2265                 return xgbe_phy_get_sfp_mode(phy_data, speed);
2266         default:
2267                 return XGBE_MODE_UNKNOWN;
2268         }
2269 }
2270 
2271 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2272 {
2273         switch (mode) {
2274         case XGBE_MODE_KX_1000:
2275                 xgbe_phy_kx_1000_mode(pdata);
2276                 break;
2277         case XGBE_MODE_KX_2500:
2278                 xgbe_phy_kx_2500_mode(pdata);
2279                 break;
2280         case XGBE_MODE_KR:
2281                 xgbe_phy_kr_mode(pdata);
2282                 break;
2283         case XGBE_MODE_SGMII_100:
2284                 xgbe_phy_sgmii_100_mode(pdata);
2285                 break;
2286         case XGBE_MODE_SGMII_1000:
2287                 xgbe_phy_sgmii_1000_mode(pdata);
2288                 break;
2289         case XGBE_MODE_X:
2290                 xgbe_phy_x_mode(pdata);
2291                 break;
2292         case XGBE_MODE_SFI:
2293                 xgbe_phy_sfi_mode(pdata);
2294                 break;
2295         default:
2296                 break;
2297         }
2298 }
2299 
2300 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2301                                 enum xgbe_mode mode, bool advert)
2302 {
2303         if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2304                 return advert;
2305         } else {
2306                 enum xgbe_mode cur_mode;
2307 
2308                 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2309                 if (cur_mode == mode)
2310                         return true;
2311         }
2312 
2313         return false;
2314 }
2315 
2316 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2317                                     enum xgbe_mode mode)
2318 {
2319         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2320 
2321         switch (mode) {
2322         case XGBE_MODE_X:
2323                 return xgbe_phy_check_mode(pdata, mode,
2324                                            XGBE_ADV(lks, 1000baseX_Full));
2325         case XGBE_MODE_KR:
2326                 return xgbe_phy_check_mode(pdata, mode,
2327                                            XGBE_ADV(lks, 10000baseKR_Full));
2328         default:
2329                 return false;
2330         }
2331 }
2332 
2333 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2334                                     enum xgbe_mode mode)
2335 {
2336         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2337 
2338         switch (mode) {
2339         case XGBE_MODE_SGMII_100:
2340                 return xgbe_phy_check_mode(pdata, mode,
2341                                            XGBE_ADV(lks, 100baseT_Full));
2342         case XGBE_MODE_SGMII_1000:
2343                 return xgbe_phy_check_mode(pdata, mode,
2344                                            XGBE_ADV(lks, 1000baseT_Full));
2345         case XGBE_MODE_KX_2500:
2346                 return xgbe_phy_check_mode(pdata, mode,
2347                                            XGBE_ADV(lks, 2500baseT_Full));
2348         case XGBE_MODE_KR:
2349                 return xgbe_phy_check_mode(pdata, mode,
2350                                            XGBE_ADV(lks, 10000baseT_Full));
2351         default:
2352                 return false;
2353         }
2354 }
2355 
2356 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2357                                   enum xgbe_mode mode)
2358 {
2359         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2360         struct xgbe_phy_data *phy_data = pdata->phy_data;
2361 
2362         switch (mode) {
2363         case XGBE_MODE_X:
2364                 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2365                         return false;
2366                 return xgbe_phy_check_mode(pdata, mode,
2367                                            XGBE_ADV(lks, 1000baseX_Full));
2368         case XGBE_MODE_SGMII_100:
2369                 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2370                         return false;
2371                 return xgbe_phy_check_mode(pdata, mode,
2372                                            XGBE_ADV(lks, 100baseT_Full));
2373         case XGBE_MODE_SGMII_1000:
2374                 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2375                         return false;
2376                 return xgbe_phy_check_mode(pdata, mode,
2377                                            XGBE_ADV(lks, 1000baseT_Full));
2378         case XGBE_MODE_SFI:
2379                 if (phy_data->sfp_mod_absent)
2380                         return true;
2381                 return xgbe_phy_check_mode(pdata, mode,
2382                                            XGBE_ADV(lks, 10000baseSR_Full)  ||
2383                                            XGBE_ADV(lks, 10000baseLR_Full)  ||
2384                                            XGBE_ADV(lks, 10000baseLRM_Full) ||
2385                                            XGBE_ADV(lks, 10000baseER_Full)  ||
2386                                            XGBE_ADV(lks, 10000baseCR_Full));
2387         default:
2388                 return false;
2389         }
2390 }
2391 
2392 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2393                                       enum xgbe_mode mode)
2394 {
2395         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2396 
2397         switch (mode) {
2398         case XGBE_MODE_KX_2500:
2399                 return xgbe_phy_check_mode(pdata, mode,
2400                                            XGBE_ADV(lks, 2500baseX_Full));
2401         default:
2402                 return false;
2403         }
2404 }
2405 
2406 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2407                                  enum xgbe_mode mode)
2408 {
2409         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2410 
2411         switch (mode) {
2412         case XGBE_MODE_KX_1000:
2413                 return xgbe_phy_check_mode(pdata, mode,
2414                                            XGBE_ADV(lks, 1000baseKX_Full));
2415         case XGBE_MODE_KR:
2416                 return xgbe_phy_check_mode(pdata, mode,
2417                                            XGBE_ADV(lks, 10000baseKR_Full));
2418         default:
2419                 return false;
2420         }
2421 }
2422 
2423 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2424 {
2425         struct xgbe_phy_data *phy_data = pdata->phy_data;
2426 
2427         switch (phy_data->port_mode) {
2428         case XGBE_PORT_MODE_BACKPLANE:
2429                 return xgbe_phy_use_bp_mode(pdata, mode);
2430         case XGBE_PORT_MODE_BACKPLANE_2500:
2431                 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2432         case XGBE_PORT_MODE_1000BASE_T:
2433         case XGBE_PORT_MODE_NBASE_T:
2434         case XGBE_PORT_MODE_10GBASE_T:
2435                 return xgbe_phy_use_baset_mode(pdata, mode);
2436         case XGBE_PORT_MODE_1000BASE_X:
2437         case XGBE_PORT_MODE_10GBASE_R:
2438                 return xgbe_phy_use_basex_mode(pdata, mode);
2439         case XGBE_PORT_MODE_SFP:
2440                 return xgbe_phy_use_sfp_mode(pdata, mode);
2441         default:
2442                 return false;
2443         }
2444 }
2445 
2446 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2447                                             int speed)
2448 {
2449         switch (speed) {
2450         case SPEED_1000:
2451                 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2452         case SPEED_10000:
2453                 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2454         default:
2455                 return false;
2456         }
2457 }
2458 
2459 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2460                                             int speed)
2461 {
2462         switch (speed) {
2463         case SPEED_100:
2464         case SPEED_1000:
2465                 return true;
2466         case SPEED_2500:
2467                 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2468         case SPEED_10000:
2469                 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2470         default:
2471                 return false;
2472         }
2473 }
2474 
2475 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2476                                           int speed)
2477 {
2478         switch (speed) {
2479         case SPEED_100:
2480                 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2481         case SPEED_1000:
2482                 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2483                         (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2484         case SPEED_10000:
2485                 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2486         default:
2487                 return false;
2488         }
2489 }
2490 
2491 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2492 {
2493         switch (speed) {
2494         case SPEED_2500:
2495                 return true;
2496         default:
2497                 return false;
2498         }
2499 }
2500 
2501 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2502 {
2503         switch (speed) {
2504         case SPEED_1000:
2505         case SPEED_10000:
2506                 return true;
2507         default:
2508                 return false;
2509         }
2510 }
2511 
2512 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2513 {
2514         struct xgbe_phy_data *phy_data = pdata->phy_data;
2515 
2516         switch (phy_data->port_mode) {
2517         case XGBE_PORT_MODE_BACKPLANE:
2518                 return xgbe_phy_valid_speed_bp_mode(speed);
2519         case XGBE_PORT_MODE_BACKPLANE_2500:
2520                 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2521         case XGBE_PORT_MODE_1000BASE_T:
2522         case XGBE_PORT_MODE_NBASE_T:
2523         case XGBE_PORT_MODE_10GBASE_T:
2524                 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2525         case XGBE_PORT_MODE_1000BASE_X:
2526         case XGBE_PORT_MODE_10GBASE_R:
2527                 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2528         case XGBE_PORT_MODE_SFP:
2529                 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2530         default:
2531                 return false;
2532         }
2533 }
2534 
2535 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2536 {
2537         struct xgbe_phy_data *phy_data = pdata->phy_data;
2538         unsigned int reg;
2539         int ret;
2540 
2541         *an_restart = 0;
2542 
2543         if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2544                 /* Check SFP signals */
2545                 xgbe_phy_sfp_detect(pdata);
2546 
2547                 if (phy_data->sfp_changed) {
2548                         *an_restart = 1;
2549                         return 0;
2550                 }
2551 
2552                 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2553                         return 0;
2554         }
2555 
2556         if (phy_data->phydev) {
2557                 /* Check external PHY */
2558                 ret = phy_read_status(phy_data->phydev);
2559                 if (ret < 0)
2560                         return 0;
2561 
2562                 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2563                     !phy_aneg_done(phy_data->phydev))
2564                         return 0;
2565 
2566                 if (!phy_data->phydev->link)
2567                         return 0;
2568         }
2569 
2570         /* Link status is latched low, so read once to clear
2571          * and then read again to get current state
2572          */
2573         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2574         reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2575         if (reg & MDIO_STAT1_LSTATUS)
2576                 return 1;
2577 
2578         /* No link, attempt a receiver reset cycle */
2579         if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2580                 phy_data->rrc_count = 0;
2581                 xgbe_phy_rrc(pdata);
2582         }
2583 
2584         return 0;
2585 }
2586 
2587 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2588 {
2589         struct xgbe_phy_data *phy_data = pdata->phy_data;
2590 
2591         phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2592                                      XP_GET_BITS(pdata->pp3, XP_PROP_3,
2593                                                  GPIO_ADDR);
2594 
2595         phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2596                                               GPIO_MASK);
2597 
2598         phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2599                                                 GPIO_RX_LOS);
2600         phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2601                                                   GPIO_TX_FAULT);
2602         phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2603                                                     GPIO_MOD_ABS);
2604         phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2605                                                      GPIO_RATE_SELECT);
2606 
2607         if (netif_msg_probe(pdata)) {
2608                 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2609                         phy_data->sfp_gpio_address);
2610                 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2611                         phy_data->sfp_gpio_mask);
2612                 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2613                         phy_data->sfp_gpio_rx_los);
2614                 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2615                         phy_data->sfp_gpio_tx_fault);
2616                 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2617                         phy_data->sfp_gpio_mod_absent);
2618                 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2619                         phy_data->sfp_gpio_rate_select);
2620         }
2621 }
2622 
2623 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2624 {
2625         struct xgbe_phy_data *phy_data = pdata->phy_data;
2626         unsigned int mux_addr_hi, mux_addr_lo;
2627 
2628         mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2629         mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2630         if (mux_addr_lo == XGBE_SFP_DIRECT)
2631                 return;
2632 
2633         phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2634         phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2635         phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2636                                                 MUX_CHAN);
2637 
2638         if (netif_msg_probe(pdata)) {
2639                 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2640                         phy_data->sfp_mux_address);
2641                 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2642                         phy_data->sfp_mux_channel);
2643         }
2644 }
2645 
2646 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2647 {
2648         xgbe_phy_sfp_comm_setup(pdata);
2649         xgbe_phy_sfp_gpio_setup(pdata);
2650 }
2651 
2652 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2653 {
2654         struct xgbe_phy_data *phy_data = pdata->phy_data;
2655         unsigned int ret;
2656 
2657         ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2658         if (ret)
2659                 return ret;
2660 
2661         ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2662 
2663         return ret;
2664 }
2665 
2666 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2667 {
2668         struct xgbe_phy_data *phy_data = pdata->phy_data;
2669         u8 gpio_reg, gpio_ports[2], gpio_data[3];
2670         int ret;
2671 
2672         /* Read the output port registers */
2673         gpio_reg = 2;
2674         ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2675                                 &gpio_reg, sizeof(gpio_reg),
2676                                 gpio_ports, sizeof(gpio_ports));
2677         if (ret)
2678                 return ret;
2679 
2680         /* Prepare to write the GPIO data */
2681         gpio_data[0] = 2;
2682         gpio_data[1] = gpio_ports[0];
2683         gpio_data[2] = gpio_ports[1];
2684 
2685         /* Set the GPIO pin */
2686         if (phy_data->mdio_reset_gpio < 8)
2687                 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2688         else
2689                 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2690 
2691         /* Write the output port registers */
2692         ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2693                                  gpio_data, sizeof(gpio_data));
2694         if (ret)
2695                 return ret;
2696 
2697         /* Clear the GPIO pin */
2698         if (phy_data->mdio_reset_gpio < 8)
2699                 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2700         else
2701                 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2702 
2703         /* Write the output port registers */
2704         ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2705                                  gpio_data, sizeof(gpio_data));
2706 
2707         return ret;
2708 }
2709 
2710 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2711 {
2712         struct xgbe_phy_data *phy_data = pdata->phy_data;
2713         int ret;
2714 
2715         if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2716                 return 0;
2717 
2718         ret = xgbe_phy_get_comm_ownership(pdata);
2719         if (ret)
2720                 return ret;
2721 
2722         if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2723                 ret = xgbe_phy_i2c_mdio_reset(pdata);
2724         else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2725                 ret = xgbe_phy_int_mdio_reset(pdata);
2726 
2727         xgbe_phy_put_comm_ownership(pdata);
2728 
2729         return ret;
2730 }
2731 
2732 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2733 {
2734         if (!phy_data->redrv)
2735                 return false;
2736 
2737         if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2738                 return true;
2739 
2740         switch (phy_data->redrv_model) {
2741         case XGBE_PHY_REDRV_MODEL_4223:
2742                 if (phy_data->redrv_lane > 3)
2743                         return true;
2744                 break;
2745         case XGBE_PHY_REDRV_MODEL_4227:
2746                 if (phy_data->redrv_lane > 1)
2747                         return true;
2748                 break;
2749         default:
2750                 return true;
2751         }
2752 
2753         return false;
2754 }
2755 
2756 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2757 {
2758         struct xgbe_phy_data *phy_data = pdata->phy_data;
2759 
2760         if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2761                 return 0;
2762 
2763         phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2764         switch (phy_data->mdio_reset) {
2765         case XGBE_MDIO_RESET_NONE:
2766         case XGBE_MDIO_RESET_I2C_GPIO:
2767         case XGBE_MDIO_RESET_INT_GPIO:
2768                 break;
2769         default:
2770                 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2771                         phy_data->mdio_reset);
2772                 return -EINVAL;
2773         }
2774 
2775         if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2776                 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2777                                             XP_GET_BITS(pdata->pp3, XP_PROP_3,
2778                                                         MDIO_RESET_I2C_ADDR);
2779                 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2780                                                         MDIO_RESET_I2C_GPIO);
2781         } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2782                 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2783                                                         MDIO_RESET_INT_GPIO);
2784         }
2785 
2786         return 0;
2787 }
2788 
2789 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2790 {
2791         struct xgbe_phy_data *phy_data = pdata->phy_data;
2792 
2793         switch (phy_data->port_mode) {
2794         case XGBE_PORT_MODE_BACKPLANE:
2795                 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2796                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2797                         return false;
2798                 break;
2799         case XGBE_PORT_MODE_BACKPLANE_2500:
2800                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2801                         return false;
2802                 break;
2803         case XGBE_PORT_MODE_1000BASE_T:
2804                 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2805                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2806                         return false;
2807                 break;
2808         case XGBE_PORT_MODE_1000BASE_X:
2809                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2810                         return false;
2811                 break;
2812         case XGBE_PORT_MODE_NBASE_T:
2813                 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2814                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2815                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2816                         return false;
2817                 break;
2818         case XGBE_PORT_MODE_10GBASE_T:
2819                 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2820                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2821                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2822                         return false;
2823                 break;
2824         case XGBE_PORT_MODE_10GBASE_R:
2825                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2826                         return false;
2827                 break;
2828         case XGBE_PORT_MODE_SFP:
2829                 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2830                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2831                     (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2832                         return false;
2833                 break;
2834         default:
2835                 break;
2836         }
2837 
2838         return true;
2839 }
2840 
2841 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2842 {
2843         struct xgbe_phy_data *phy_data = pdata->phy_data;
2844 
2845         switch (phy_data->port_mode) {
2846         case XGBE_PORT_MODE_BACKPLANE:
2847         case XGBE_PORT_MODE_BACKPLANE_2500:
2848                 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2849                         return false;
2850                 break;
2851         case XGBE_PORT_MODE_1000BASE_T:
2852         case XGBE_PORT_MODE_1000BASE_X:
2853         case XGBE_PORT_MODE_NBASE_T:
2854         case XGBE_PORT_MODE_10GBASE_T:
2855         case XGBE_PORT_MODE_10GBASE_R:
2856                 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2857                         return false;
2858                 break;
2859         case XGBE_PORT_MODE_SFP:
2860                 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2861                         return false;
2862                 break;
2863         default:
2864                 break;
2865         }
2866 
2867         return true;
2868 }
2869 
2870 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2871 {
2872         if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2873                 return false;
2874         if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2875                 return false;
2876 
2877         return true;
2878 }
2879 
2880 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2881 {
2882         struct xgbe_phy_data *phy_data = pdata->phy_data;
2883 
2884         if (!pdata->debugfs_an_cdr_workaround)
2885                 return;
2886 
2887         if (!phy_data->phy_cdr_notrack)
2888                 return;
2889 
2890         usleep_range(phy_data->phy_cdr_delay,
2891                      phy_data->phy_cdr_delay + 500);
2892 
2893         XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2894                          XGBE_PMA_CDR_TRACK_EN_MASK,
2895                          XGBE_PMA_CDR_TRACK_EN_ON);
2896 
2897         phy_data->phy_cdr_notrack = 0;
2898 }
2899 
2900 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2901 {
2902         struct xgbe_phy_data *phy_data = pdata->phy_data;
2903 
2904         if (!pdata->debugfs_an_cdr_workaround)
2905                 return;
2906 
2907         if (phy_data->phy_cdr_notrack)
2908                 return;
2909 
2910         XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2911                          XGBE_PMA_CDR_TRACK_EN_MASK,
2912                          XGBE_PMA_CDR_TRACK_EN_OFF);
2913 
2914         xgbe_phy_rrc(pdata);
2915 
2916         phy_data->phy_cdr_notrack = 1;
2917 }
2918 
2919 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2920 {
2921         if (!pdata->debugfs_an_cdr_track_early)
2922                 xgbe_phy_cdr_track(pdata);
2923 }
2924 
2925 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2926 {
2927         if (pdata->debugfs_an_cdr_track_early)
2928                 xgbe_phy_cdr_track(pdata);
2929 }
2930 
2931 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2932 {
2933         struct xgbe_phy_data *phy_data = pdata->phy_data;
2934 
2935         switch (pdata->an_mode) {
2936         case XGBE_AN_MODE_CL73:
2937         case XGBE_AN_MODE_CL73_REDRV:
2938                 if (phy_data->cur_mode != XGBE_MODE_KR)
2939                         break;
2940 
2941                 xgbe_phy_cdr_track(pdata);
2942 
2943                 switch (pdata->an_result) {
2944                 case XGBE_AN_READY:
2945                 case XGBE_AN_COMPLETE:
2946                         break;
2947                 default:
2948                         if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2949                                 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2950                         else
2951                                 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2952                         break;
2953                 }
2954                 break;
2955         default:
2956                 break;
2957         }
2958 }
2959 
2960 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2961 {
2962         struct xgbe_phy_data *phy_data = pdata->phy_data;
2963 
2964         switch (pdata->an_mode) {
2965         case XGBE_AN_MODE_CL73:
2966         case XGBE_AN_MODE_CL73_REDRV:
2967                 if (phy_data->cur_mode != XGBE_MODE_KR)
2968                         break;
2969 
2970                 xgbe_phy_cdr_notrack(pdata);
2971                 break;
2972         default:
2973                 break;
2974         }
2975 }
2976 
2977 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2978 {
2979         struct xgbe_phy_data *phy_data = pdata->phy_data;
2980 
2981         /* If we have an external PHY, free it */
2982         xgbe_phy_free_phy_device(pdata);
2983 
2984         /* Reset SFP data */
2985         xgbe_phy_sfp_reset(phy_data);
2986         xgbe_phy_sfp_mod_absent(pdata);
2987 
2988         /* Reset CDR support */
2989         xgbe_phy_cdr_track(pdata);
2990 
2991         /* Power off the PHY */
2992         xgbe_phy_power_off(pdata);
2993 
2994         /* Stop the I2C controller */
2995         pdata->i2c_if.i2c_stop(pdata);
2996 }
2997 
2998 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2999 {
3000         struct xgbe_phy_data *phy_data = pdata->phy_data;
3001         int ret;
3002 
3003         /* Start the I2C controller */
3004         ret = pdata->i2c_if.i2c_start(pdata);
3005         if (ret)
3006                 return ret;
3007 
3008         /* Set the proper MDIO mode for the re-driver */
3009         if (phy_data->redrv && !phy_data->redrv_if) {
3010                 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3011                                                     XGBE_MDIO_MODE_CL22);
3012                 if (ret) {
3013                         netdev_err(pdata->netdev,
3014                                    "redriver mdio port not compatible (%u)\n",
3015                                    phy_data->redrv_addr);
3016                         return ret;
3017                 }
3018         }
3019 
3020         /* Start in highest supported mode */
3021         xgbe_phy_set_mode(pdata, phy_data->start_mode);
3022 
3023         /* Reset CDR support */
3024         xgbe_phy_cdr_track(pdata);
3025 
3026         /* After starting the I2C controller, we can check for an SFP */
3027         switch (phy_data->port_mode) {
3028         case XGBE_PORT_MODE_SFP:
3029                 xgbe_phy_sfp_detect(pdata);
3030                 break;
3031         default:
3032                 break;
3033         }
3034 
3035         /* If we have an external PHY, start it */
3036         ret = xgbe_phy_find_phy_device(pdata);
3037         if (ret)
3038                 goto err_i2c;
3039 
3040         return 0;
3041 
3042 err_i2c:
3043         pdata->i2c_if.i2c_stop(pdata);
3044 
3045         return ret;
3046 }
3047 
3048 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3049 {
3050         struct xgbe_phy_data *phy_data = pdata->phy_data;
3051         enum xgbe_mode cur_mode;
3052         int ret;
3053 
3054         /* Reset by power cycling the PHY */
3055         cur_mode = phy_data->cur_mode;
3056         xgbe_phy_power_off(pdata);
3057         xgbe_phy_set_mode(pdata, cur_mode);
3058 
3059         if (!phy_data->phydev)
3060                 return 0;
3061 
3062         /* Reset the external PHY */
3063         ret = xgbe_phy_mdio_reset(pdata);
3064         if (ret)
3065                 return ret;
3066 
3067         return phy_init_hw(phy_data->phydev);
3068 }
3069 
3070 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3071 {
3072         struct xgbe_phy_data *phy_data = pdata->phy_data;
3073 
3074         /* Unregister for driving external PHYs */
3075         mdiobus_unregister(phy_data->mii);
3076 }
3077 
3078 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3079 {
3080         struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3081         struct xgbe_phy_data *phy_data;
3082         struct mii_bus *mii;
3083         int ret;
3084 
3085         /* Check if enabled */
3086         if (!xgbe_phy_port_enabled(pdata)) {
3087                 dev_info(pdata->dev, "device is not enabled\n");
3088                 return -ENODEV;
3089         }
3090 
3091         /* Initialize the I2C controller */
3092         ret = pdata->i2c_if.i2c_init(pdata);
3093         if (ret)
3094                 return ret;
3095 
3096         phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3097         if (!phy_data)
3098                 return -ENOMEM;
3099         pdata->phy_data = phy_data;
3100 
3101         phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3102         phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3103         phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3104         phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3105         phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3106         if (netif_msg_probe(pdata)) {
3107                 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3108                 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3109                 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3110                 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3111                 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3112         }
3113 
3114         phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3115         phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3116         phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3117         phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3118         phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3119         if (phy_data->redrv && netif_msg_probe(pdata)) {
3120                 dev_dbg(pdata->dev, "redrv present\n");
3121                 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3122                 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3123                 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3124                 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3125         }
3126 
3127         /* Validate the connection requested */
3128         if (xgbe_phy_conn_type_mismatch(pdata)) {
3129                 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3130                         phy_data->port_mode, phy_data->conn_type);
3131                 return -EINVAL;
3132         }
3133 
3134         /* Validate the mode requested */
3135         if (xgbe_phy_port_mode_mismatch(pdata)) {
3136                 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3137                         phy_data->port_mode, phy_data->port_speeds);
3138                 return -EINVAL;
3139         }
3140 
3141         /* Check for and validate MDIO reset support */
3142         ret = xgbe_phy_mdio_reset_setup(pdata);
3143         if (ret)
3144                 return ret;
3145 
3146         /* Validate the re-driver information */
3147         if (xgbe_phy_redrv_error(phy_data)) {
3148                 dev_err(pdata->dev, "phy re-driver settings error\n");
3149                 return -EINVAL;
3150         }
3151         pdata->kr_redrv = phy_data->redrv;
3152 
3153         /* Indicate current mode is unknown */
3154         phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3155 
3156         /* Initialize supported features */
3157         XGBE_ZERO_SUP(lks);
3158 
3159         switch (phy_data->port_mode) {
3160         /* Backplane support */
3161         case XGBE_PORT_MODE_BACKPLANE:
3162                 XGBE_SET_SUP(lks, Autoneg);
3163                 XGBE_SET_SUP(lks, Pause);
3164                 XGBE_SET_SUP(lks, Asym_Pause);
3165                 XGBE_SET_SUP(lks, Backplane);
3166                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3167                         XGBE_SET_SUP(lks, 1000baseKX_Full);
3168                         phy_data->start_mode = XGBE_MODE_KX_1000;
3169                 }
3170                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3171                         XGBE_SET_SUP(lks, 10000baseKR_Full);
3172                         if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3173                                 XGBE_SET_SUP(lks, 10000baseR_FEC);
3174                         phy_data->start_mode = XGBE_MODE_KR;
3175                 }
3176 
3177                 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3178                 break;
3179         case XGBE_PORT_MODE_BACKPLANE_2500:
3180                 XGBE_SET_SUP(lks, Pause);
3181                 XGBE_SET_SUP(lks, Asym_Pause);
3182                 XGBE_SET_SUP(lks, Backplane);
3183                 XGBE_SET_SUP(lks, 2500baseX_Full);
3184                 phy_data->start_mode = XGBE_MODE_KX_2500;
3185 
3186                 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3187                 break;
3188 
3189         /* MDIO 1GBase-T support */
3190         case XGBE_PORT_MODE_1000BASE_T:
3191                 XGBE_SET_SUP(lks, Autoneg);
3192                 XGBE_SET_SUP(lks, Pause);
3193                 XGBE_SET_SUP(lks, Asym_Pause);
3194                 XGBE_SET_SUP(lks, TP);
3195                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3196                         XGBE_SET_SUP(lks, 100baseT_Full);
3197                         phy_data->start_mode = XGBE_MODE_SGMII_100;
3198                 }
3199                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3200                         XGBE_SET_SUP(lks, 1000baseT_Full);
3201                         phy_data->start_mode = XGBE_MODE_SGMII_1000;
3202                 }
3203 
3204                 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3205                 break;
3206 
3207         /* MDIO Base-X support */
3208         case XGBE_PORT_MODE_1000BASE_X:
3209                 XGBE_SET_SUP(lks, Autoneg);
3210                 XGBE_SET_SUP(lks, Pause);
3211                 XGBE_SET_SUP(lks, Asym_Pause);
3212                 XGBE_SET_SUP(lks, FIBRE);
3213                 XGBE_SET_SUP(lks, 1000baseX_Full);
3214                 phy_data->start_mode = XGBE_MODE_X;
3215 
3216                 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3217                 break;
3218 
3219         /* MDIO NBase-T support */
3220         case XGBE_PORT_MODE_NBASE_T:
3221                 XGBE_SET_SUP(lks, Autoneg);
3222                 XGBE_SET_SUP(lks, Pause);
3223                 XGBE_SET_SUP(lks, Asym_Pause);
3224                 XGBE_SET_SUP(lks, TP);
3225                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3226                         XGBE_SET_SUP(lks, 100baseT_Full);
3227                         phy_data->start_mode = XGBE_MODE_SGMII_100;
3228                 }
3229                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3230                         XGBE_SET_SUP(lks, 1000baseT_Full);
3231                         phy_data->start_mode = XGBE_MODE_SGMII_1000;
3232                 }
3233                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3234                         XGBE_SET_SUP(lks, 2500baseT_Full);
3235                         phy_data->start_mode = XGBE_MODE_KX_2500;
3236                 }
3237 
3238                 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3239                 break;
3240 
3241         /* 10GBase-T support */
3242         case XGBE_PORT_MODE_10GBASE_T:
3243                 XGBE_SET_SUP(lks, Autoneg);
3244                 XGBE_SET_SUP(lks, Pause);
3245                 XGBE_SET_SUP(lks, Asym_Pause);
3246                 XGBE_SET_SUP(lks, TP);
3247                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3248                         XGBE_SET_SUP(lks, 100baseT_Full);
3249                         phy_data->start_mode = XGBE_MODE_SGMII_100;
3250                 }
3251                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3252                         XGBE_SET_SUP(lks, 1000baseT_Full);
3253                         phy_data->start_mode = XGBE_MODE_SGMII_1000;
3254                 }
3255                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3256                         XGBE_SET_SUP(lks, 10000baseT_Full);
3257                         phy_data->start_mode = XGBE_MODE_KR;
3258                 }
3259 
3260                 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3261                 break;
3262 
3263         /* 10GBase-R support */
3264         case XGBE_PORT_MODE_10GBASE_R:
3265                 XGBE_SET_SUP(lks, Autoneg);
3266                 XGBE_SET_SUP(lks, Pause);
3267                 XGBE_SET_SUP(lks, Asym_Pause);
3268                 XGBE_SET_SUP(lks, FIBRE);
3269                 XGBE_SET_SUP(lks, 10000baseSR_Full);
3270                 XGBE_SET_SUP(lks, 10000baseLR_Full);
3271                 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3272                 XGBE_SET_SUP(lks, 10000baseER_Full);
3273                 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3274                         XGBE_SET_SUP(lks, 10000baseR_FEC);
3275                 phy_data->start_mode = XGBE_MODE_SFI;
3276 
3277                 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3278                 break;
3279 
3280         /* SFP support */
3281         case XGBE_PORT_MODE_SFP:
3282                 XGBE_SET_SUP(lks, Autoneg);
3283                 XGBE_SET_SUP(lks, Pause);
3284                 XGBE_SET_SUP(lks, Asym_Pause);
3285                 XGBE_SET_SUP(lks, TP);
3286                 XGBE_SET_SUP(lks, FIBRE);
3287                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3288                         phy_data->start_mode = XGBE_MODE_SGMII_100;
3289                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3290                         phy_data->start_mode = XGBE_MODE_SGMII_1000;
3291                 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3292                         phy_data->start_mode = XGBE_MODE_SFI;
3293 
3294                 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3295 
3296                 xgbe_phy_sfp_setup(pdata);
3297                 break;
3298         default:
3299                 return -EINVAL;
3300         }
3301 
3302         if (netif_msg_probe(pdata))
3303                 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3304                         __ETHTOOL_LINK_MODE_MASK_NBITS,
3305                         lks->link_modes.supported);
3306 
3307         if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3308             (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3309                 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3310                                                     phy_data->phydev_mode);
3311                 if (ret) {
3312                         dev_err(pdata->dev,
3313                                 "mdio port/clause not compatible (%d/%u)\n",
3314                                 phy_data->mdio_addr, phy_data->phydev_mode);
3315                         return -EINVAL;
3316                 }
3317         }
3318 
3319         if (phy_data->redrv && !phy_data->redrv_if) {
3320                 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3321                                                     XGBE_MDIO_MODE_CL22);
3322                 if (ret) {
3323                         dev_err(pdata->dev,
3324                                 "redriver mdio port not compatible (%u)\n",
3325                                 phy_data->redrv_addr);
3326                         return -EINVAL;
3327                 }
3328         }
3329 
3330         phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3331 
3332         /* Register for driving external PHYs */
3333         mii = devm_mdiobus_alloc(pdata->dev);
3334         if (!mii) {
3335                 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3336                 return -ENOMEM;
3337         }
3338 
3339         mii->priv = pdata;
3340         mii->name = "amd-xgbe-mii";
3341         mii->read = xgbe_phy_mii_read;
3342         mii->write = xgbe_phy_mii_write;
3343         mii->parent = pdata->dev;
3344         mii->phy_mask = ~0;
3345         snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3346         ret = mdiobus_register(mii);
3347         if (ret) {
3348                 dev_err(pdata->dev, "mdiobus_register failed\n");
3349                 return ret;
3350         }
3351         phy_data->mii = mii;
3352 
3353         return 0;
3354 }
3355 
3356 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3357 {
3358         struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3359 
3360         phy_impl->init                  = xgbe_phy_init;
3361         phy_impl->exit                  = xgbe_phy_exit;
3362 
3363         phy_impl->reset                 = xgbe_phy_reset;
3364         phy_impl->start                 = xgbe_phy_start;
3365         phy_impl->stop                  = xgbe_phy_stop;
3366 
3367         phy_impl->link_status           = xgbe_phy_link_status;
3368 
3369         phy_impl->valid_speed           = xgbe_phy_valid_speed;
3370 
3371         phy_impl->use_mode              = xgbe_phy_use_mode;
3372         phy_impl->set_mode              = xgbe_phy_set_mode;
3373         phy_impl->get_mode              = xgbe_phy_get_mode;
3374         phy_impl->switch_mode           = xgbe_phy_switch_mode;
3375         phy_impl->cur_mode              = xgbe_phy_cur_mode;
3376 
3377         phy_impl->an_mode               = xgbe_phy_an_mode;
3378 
3379         phy_impl->an_config             = xgbe_phy_an_config;
3380 
3381         phy_impl->an_advertising        = xgbe_phy_an_advertising;
3382 
3383         phy_impl->an_outcome            = xgbe_phy_an_outcome;
3384 
3385         phy_impl->an_pre                = xgbe_phy_an_pre;
3386         phy_impl->an_post               = xgbe_phy_an_post;
3387 
3388         phy_impl->kr_training_pre       = xgbe_phy_kr_training_pre;
3389         phy_impl->kr_training_post      = xgbe_phy_kr_training_post;
3390 
3391         phy_impl->module_info           = xgbe_phy_module_info;
3392         phy_impl->module_eeprom         = xgbe_phy_module_eeprom;
3393 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c

DEFINITIONS
