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6 #ifndef NIC_REG_H
7 #define NIC_REG_H
8
9 #define NIC_PF_REG_COUNT 29573
10 #define NIC_VF_REG_COUNT 249
11
12
13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
23 #define NIC_PF_CNM_STATUS (0x00B0)
24 #define NIC_PF_CQ_AVG_CFG (0x00C0)
25 #define NIC_PF_RRM_AVG_CFG (0x00C8)
26 #define NIC_PF_INTF_0_1_SEND_CFG (0x0200)
27 #define NIC_PF_INTF_0_1_BP_CFG (0x0208)
28 #define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210)
29 #define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220)
30 #define NIC_PF_RBDR_BP_STATE_0_3 (0x0240)
31 #define NIC_PF_MAILBOX_INT (0x0410)
32 #define NIC_PF_MAILBOX_INT_W1S (0x0430)
33 #define NIC_PF_MAILBOX_ENA_W1C (0x0450)
34 #define NIC_PF_MAILBOX_ENA_W1S (0x0470)
35 #define NIC_PF_RX_ETYPE_0_7 (0x0500)
36 #define NIC_PF_RX_GENEVE_DEF (0x0580)
37 #define UDP_GENEVE_PORT_NUM 0x17C1ULL
38 #define NIC_PF_RX_GENEVE_PROT_DEF (0x0588)
39 #define IPV6_PROT 0x86DDULL
40 #define IPV4_PROT 0x800ULL
41 #define ET_PROT 0x6558ULL
42 #define NIC_PF_RX_NVGRE_PROT_DEF (0x0598)
43 #define NIC_PF_RX_VXLAN_DEF_0_1 (0x05A0)
44 #define UDP_VXLAN_PORT_NUM 0x12B5
45 #define NIC_PF_RX_VXLAN_PROT_DEF (0x05B0)
46 #define IPV6_PROT_DEF 0x2ULL
47 #define IPV4_PROT_DEF 0x1ULL
48 #define ET_PROT_DEF 0x3ULL
49 #define NIC_PF_RX_CFG (0x05D0)
50 #define NIC_PF_PKIND_0_15_CFG (0x0600)
51 #define NIC_PF_ECC0_FLIP0 (0x1000)
52 #define NIC_PF_ECC1_FLIP0 (0x1008)
53 #define NIC_PF_ECC2_FLIP0 (0x1010)
54 #define NIC_PF_ECC3_FLIP0 (0x1018)
55 #define NIC_PF_ECC0_FLIP1 (0x1080)
56 #define NIC_PF_ECC1_FLIP1 (0x1088)
57 #define NIC_PF_ECC2_FLIP1 (0x1090)
58 #define NIC_PF_ECC3_FLIP1 (0x1098)
59 #define NIC_PF_ECC0_CDIS (0x1100)
60 #define NIC_PF_ECC1_CDIS (0x1108)
61 #define NIC_PF_ECC2_CDIS (0x1110)
62 #define NIC_PF_ECC3_CDIS (0x1118)
63 #define NIC_PF_BIST0_STATUS (0x1280)
64 #define NIC_PF_BIST1_STATUS (0x1288)
65 #define NIC_PF_BIST2_STATUS (0x1290)
66 #define NIC_PF_BIST3_STATUS (0x1298)
67 #define NIC_PF_ECC0_SBE_INT (0x2000)
68 #define NIC_PF_ECC0_SBE_INT_W1S (0x2008)
69 #define NIC_PF_ECC0_SBE_ENA_W1C (0x2010)
70 #define NIC_PF_ECC0_SBE_ENA_W1S (0x2018)
71 #define NIC_PF_ECC0_DBE_INT (0x2100)
72 #define NIC_PF_ECC0_DBE_INT_W1S (0x2108)
73 #define NIC_PF_ECC0_DBE_ENA_W1C (0x2110)
74 #define NIC_PF_ECC0_DBE_ENA_W1S (0x2118)
75 #define NIC_PF_ECC1_SBE_INT (0x2200)
76 #define NIC_PF_ECC1_SBE_INT_W1S (0x2208)
77 #define NIC_PF_ECC1_SBE_ENA_W1C (0x2210)
78 #define NIC_PF_ECC1_SBE_ENA_W1S (0x2218)
79 #define NIC_PF_ECC1_DBE_INT (0x2300)
80 #define NIC_PF_ECC1_DBE_INT_W1S (0x2308)
81 #define NIC_PF_ECC1_DBE_ENA_W1C (0x2310)
82 #define NIC_PF_ECC1_DBE_ENA_W1S (0x2318)
83 #define NIC_PF_ECC2_SBE_INT (0x2400)
84 #define NIC_PF_ECC2_SBE_INT_W1S (0x2408)
85 #define NIC_PF_ECC2_SBE_ENA_W1C (0x2410)
86 #define NIC_PF_ECC2_SBE_ENA_W1S (0x2418)
87 #define NIC_PF_ECC2_DBE_INT (0x2500)
88 #define NIC_PF_ECC2_DBE_INT_W1S (0x2508)
89 #define NIC_PF_ECC2_DBE_ENA_W1C (0x2510)
90 #define NIC_PF_ECC2_DBE_ENA_W1S (0x2518)
91 #define NIC_PF_ECC3_SBE_INT (0x2600)
92 #define NIC_PF_ECC3_SBE_INT_W1S (0x2608)
93 #define NIC_PF_ECC3_SBE_ENA_W1C (0x2610)
94 #define NIC_PF_ECC3_SBE_ENA_W1S (0x2618)
95 #define NIC_PF_ECC3_DBE_INT (0x2700)
96 #define NIC_PF_ECC3_DBE_INT_W1S (0x2708)
97 #define NIC_PF_ECC3_DBE_ENA_W1C (0x2710)
98 #define NIC_PF_ECC3_DBE_ENA_W1S (0x2718)
99 #define NIC_PF_INTFX_SEND_CFG (0x4000)
100 #define NIC_PF_MCAM_0_191_ENA (0x100000)
101 #define NIC_PF_MCAM_0_191_M_0_5_DATA (0x110000)
102 #define NIC_PF_MCAM_CTRL (0x120000)
103 #define NIC_PF_CPI_0_2047_CFG (0x200000)
104 #define NIC_PF_MPI_0_2047_CFG (0x210000)
105 #define NIC_PF_RSSI_0_4097_RQ (0x220000)
106 #define NIC_PF_LMAC_0_7_CFG (0x240000)
107 #define NIC_PF_LMAC_0_7_CFG2 (0x240100)
108 #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000)
109 #define NIC_PF_LMAC_0_7_CREDIT (0x244000)
110 #define NIC_PF_CHAN_0_255_TX_CFG (0x400000)
111 #define NIC_PF_CHAN_0_255_RX_CFG (0x420000)
112 #define NIC_PF_CHAN_0_255_SW_XOFF (0x440000)
113 #define NIC_PF_CHAN_0_255_CREDIT (0x460000)
114 #define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000)
115 #define NIC_PF_SW_SYNC_RX (0x490000)
116 #define NIC_PF_SW_SYNC_RX_DONE (0x490008)
117 #define NIC_PF_TL2_0_63_CFG (0x500000)
118 #define NIC_PF_TL2_0_63_PRI (0x520000)
119 #define NIC_PF_TL2_LMAC (0x540000)
120 #define NIC_PF_TL2_0_63_SH_STATUS (0x580000)
121 #define NIC_PF_TL3A_0_63_CFG (0x5F0000)
122 #define NIC_PF_TL3_0_255_CFG (0x600000)
123 #define NIC_PF_TL3_0_255_CHAN (0x620000)
124 #define NIC_PF_TL3_0_255_PIR (0x640000)
125 #define NIC_PF_TL3_0_255_SW_XOFF (0x660000)
126 #define NIC_PF_TL3_0_255_CNM_RATE (0x680000)
127 #define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000)
128 #define NIC_PF_TL4A_0_255_CFG (0x6F0000)
129 #define NIC_PF_TL4_0_1023_CFG (0x800000)
130 #define NIC_PF_TL4_0_1023_SW_XOFF (0x820000)
131 #define NIC_PF_TL4_0_1023_SH_STATUS (0x840000)
132 #define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000)
133 #define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000)
134 #define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030)
135 #define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000)
136 #define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100)
137 #define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000)
138 #define NIC_PF_QSET_0_127_CFG (0x20010000)
139 #define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400)
140 #define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420)
141 #define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500)
142 #define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600)
143 #define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00)
144 #define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08)
145 #define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00)
146
147 #define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000)
148 #define NIC_PF_MSIX_VEC_0_CTL (0x000008)
149 #define NIC_PF_MSIX_PBA_0 (0x0F0000)
150
151
152 #define NIC_VNIC_CFG (0x000020)
153 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
154 #define NIC_VF_INT (0x000200)
155 #define NIC_VF_INT_W1S (0x000220)
156 #define NIC_VF_ENA_W1C (0x000240)
157 #define NIC_VF_ENA_W1S (0x000260)
158
159 #define NIC_VNIC_RSS_CFG (0x0020E0)
160 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
161 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
162 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
163 #define NIC_QSET_RQ_GEN_CFG (0x010010)
164
165 #define NIC_QSET_CQ_0_7_CFG (0x010400)
166 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
167 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
168 #define NIC_QSET_CQ_0_7_BASE (0x010420)
169 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
170 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
171 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
172 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
173 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
174 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
175
176 #define NIC_QSET_RQ_0_7_CFG (0x010600)
177 #define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700)
178
179 #define NIC_QSET_SQ_0_7_CFG (0x010800)
180 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
181 #define NIC_QSET_SQ_0_7_BASE (0x010820)
182 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
183 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
184 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
185 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
186 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
187 #define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900)
188
189 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
190 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
191 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
192 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
193 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
194 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
195 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
196 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
197 #define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50)
198
199 #define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000)
200 #define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008)
201 #define NIC_VF_MSIX_PBA (0x0F0000)
202
203
204 #define NIC_MSIX_VEC_SHIFT 4
205 #define NIC_Q_NUM_SHIFT 18
206 #define NIC_QS_ID_SHIFT 21
207 #define NIC_VF_NUM_SHIFT 21
208
209
210 struct pkind_cfg {
211 #if defined(__BIG_ENDIAN_BITFIELD)
212 u64 reserved_42_63:22;
213 u64 hdr_sl:5;
214 u64 rx_hdr:3;
215 u64 lenerr_en:1;
216 u64 reserved_32_32:1;
217 u64 maxlen:16;
218 u64 minlen:16;
219 #elif defined(__LITTLE_ENDIAN_BITFIELD)
220 u64 minlen:16;
221 u64 maxlen:16;
222 u64 reserved_32_32:1;
223 u64 lenerr_en:1;
224 u64 rx_hdr:3;
225 u64 hdr_sl:5;
226 u64 reserved_42_63:22;
227 #endif
228 };
229
230 #endif