drivers/net/ethernet/cavium/thunder/nic

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This source file includes following definitions.
nic_reg_write
nic_reg_read
nic_enable_mbx_intr
nic_clear_mbx_intr
nic_get_mbx_addr
nic_send_msg_to_vf
nic_mbx_send_ready
nic_mbx_send_ack
nic_mbx_send_nack
nic_rcv_queue_sw_sync
nic_get_bgx_stats
nic_update_hw_frs
nic_set_tx_pkt_pad
nic_set_lmac_vf_mapping
nic_get_hw_info
nic_init_hw
nic_config_cpi
nic_send_rss_size
nic_config_rss
nic_tx_channel_cfg
nic_send_pnicvf
nic_send_snicvf
nic_nxt_avail_sqs
nic_alloc_sqs
nic_config_loopback
nic_reset_stat_counters
nic_enable_tunnel_parsing
nic_enable_vf
nic_pause_frame
nic_config_timestamp
nic_link_status_get
nic_handle_mbx_intr
nic_mbx_intr_handler
nic_free_all_interrupts
nic_register_interrupts
nic_unregister_interrupts
nic_num_sqs_en
nic_sriov_init
nic_probe
nic_remove
nic_init_module
nic_cleanup_module
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Cavium, Inc.
   4  */
   5 
   6 #include <linux/module.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/pci.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/of.h>
  11 #include <linux/if_vlan.h>
  12 
  13 #include "nic_reg.h"
  14 #include "nic.h"
  15 #include "q_struct.h"
  16 #include "thunder_bgx.h"
  17 
  18 #define DRV_NAME        "nicpf"
  19 #define DRV_VERSION     "1.0"
  20 
  21 #define NIC_VF_PER_MBX_REG      64
  22 
  23 struct hw_info {
  24         u8              bgx_cnt;
  25         u8              chans_per_lmac;
  26         u8              chans_per_bgx; /* Rx/Tx chans */
  27         u8              chans_per_rgx;
  28         u8              chans_per_lbk;
  29         u16             cpi_cnt;
  30         u16             rssi_cnt;
  31         u16             rss_ind_tbl_size;
  32         u16             tl4_cnt;
  33         u16             tl3_cnt;
  34         u8              tl2_cnt;
  35         u8              tl1_cnt;
  36         bool            tl1_per_bgx; /* TL1 per BGX or per LMAC */
  37 };
  38 
  39 struct nicpf {
  40         struct pci_dev          *pdev;
  41         struct hw_info          *hw;
  42         u8                      node;
  43         unsigned int            flags;
  44         u8                      num_vf_en;      /* No of VF enabled */
  45         bool                    vf_enabled[MAX_NUM_VFS_SUPPORTED];
  46         void __iomem            *reg_base;       /* Register start address */
  47         u8                      num_sqs_en;     /* Secondary qsets enabled */
  48         u64                     nicvf[MAX_NUM_VFS_SUPPORTED];
  49         u8                      vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
  50         u8                      pqs_vf[MAX_NUM_VFS_SUPPORTED];
  51         bool                    sqs_used[MAX_NUM_VFS_SUPPORTED];
  52         struct pkind_cfg        pkind;
  53 #define NIC_SET_VF_LMAC_MAP(bgx, lmac)  (((bgx & 0xF) << 4) | (lmac & 0xF))
  54 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map)       ((map >> 4) & 0xF)
  55 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map)      (map & 0xF)
  56         u8                      *vf_lmac_map;
  57         u16                     cpi_base[MAX_NUM_VFS_SUPPORTED];
  58         u16                     rssi_base[MAX_NUM_VFS_SUPPORTED];
  59 
  60         /* MSI-X */
  61         u8                      num_vec;
  62         bool                    irq_allocated[NIC_PF_MSIX_VECTORS];
  63         char                    irq_name[NIC_PF_MSIX_VECTORS][20];
  64 };
  65 
  66 /* Supported devices */
  67 static const struct pci_device_id nic_id_table[] = {
  68         { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
  69         { 0, }  /* end of table */
  70 };
  71 
  72 MODULE_AUTHOR("Sunil Goutham");
  73 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
  74 MODULE_LICENSE("GPL v2");
  75 MODULE_VERSION(DRV_VERSION);
  76 MODULE_DEVICE_TABLE(pci, nic_id_table);
  77 
  78 /* The Cavium ThunderX network controller can *only* be found in SoCs
  79  * containing the ThunderX ARM64 CPU implementation.  All accesses to the device
  80  * registers on this platform are implicitly strongly ordered with respect
  81  * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
  82  * with no memory barriers in this driver.  The readq()/writeq() functions add
  83  * explicit ordering operation which in this case are redundant, and only
  84  * add overhead.
  85  */
  86 
  87 /* Register read/write APIs */
  88 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
  89 {
  90         writeq_relaxed(val, nic->reg_base + offset);
  91 }
  92 
  93 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
  94 {
  95         return readq_relaxed(nic->reg_base + offset);
  96 }
  97 
  98 /* PF -> VF mailbox communication APIs */
  99 static void nic_enable_mbx_intr(struct nicpf *nic)
 100 {
 101         int vf_cnt = pci_sriov_get_totalvfs(nic->pdev);
 102 
 103 #define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull))
 104 
 105         /* Clear it, to avoid spurious interrupts (if any) */
 106         nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt));
 107 
 108         /* Enable mailbox interrupt for all VFs */
 109         nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt));
 110         /* One mailbox intr enable reg per 64 VFs */
 111         if (vf_cnt > 64) {
 112                 nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64),
 113                               INTR_MASK(vf_cnt - 64));
 114                 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64),
 115                               INTR_MASK(vf_cnt - 64));
 116         }
 117 }
 118 
 119 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
 120 {
 121         nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
 122 }
 123 
 124 static u64 nic_get_mbx_addr(int vf)
 125 {
 126         return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
 127 }
 128 
 129 /* Send a mailbox message to VF
 130  * @vf: vf to which this message to be sent
 131  * @mbx: Message to be sent
 132  */
 133 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
 134 {
 135         void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
 136         u64 *msg = (u64 *)mbx;
 137 
 138         /* In first revision HW, mbox interrupt is triggerred
 139          * when PF writes to MBOX(1), in next revisions when
 140          * PF writes to MBOX(0)
 141          */
 142         if (pass1_silicon(nic->pdev)) {
 143                 /* see the comment for nic_reg_write()/nic_reg_read()
 144                  * functions above
 145                  */
 146                 writeq_relaxed(msg[0], mbx_addr);
 147                 writeq_relaxed(msg[1], mbx_addr + 8);
 148         } else {
 149                 writeq_relaxed(msg[1], mbx_addr + 8);
 150                 writeq_relaxed(msg[0], mbx_addr);
 151         }
 152 }
 153 
 154 /* Responds to VF's READY message with VF's
 155  * ID, node, MAC address e.t.c
 156  * @vf: VF which sent READY message
 157  */
 158 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
 159 {
 160         union nic_mbx mbx = {};
 161         int bgx_idx, lmac;
 162         const char *mac;
 163 
 164         mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
 165         mbx.nic_cfg.vf_id = vf;
 166 
 167         mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
 168 
 169         if (vf < nic->num_vf_en) {
 170                 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 171                 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 172 
 173                 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
 174                 if (mac)
 175                         ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
 176         }
 177         mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
 178         mbx.nic_cfg.node_id = nic->node;
 179 
 180         mbx.nic_cfg.loopback_supported = vf < nic->num_vf_en;
 181 
 182         nic_send_msg_to_vf(nic, vf, &mbx);
 183 }
 184 
 185 /* ACKs VF's mailbox message
 186  * @vf: VF to which ACK to be sent
 187  */
 188 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
 189 {
 190         union nic_mbx mbx = {};
 191 
 192         mbx.msg.msg = NIC_MBOX_MSG_ACK;
 193         nic_send_msg_to_vf(nic, vf, &mbx);
 194 }
 195 
 196 /* NACKs VF's mailbox message that PF is not able to
 197  * complete the action
 198  * @vf: VF to which ACK to be sent
 199  */
 200 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
 201 {
 202         union nic_mbx mbx = {};
 203 
 204         mbx.msg.msg = NIC_MBOX_MSG_NACK;
 205         nic_send_msg_to_vf(nic, vf, &mbx);
 206 }
 207 
 208 /* Flush all in flight receive packets to memory and
 209  * bring down an active RQ
 210  */
 211 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
 212 {
 213         u16 timeout = ~0x00;
 214 
 215         nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
 216         /* Wait till sync cycle is finished */
 217         while (timeout) {
 218                 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
 219                         break;
 220                 timeout--;
 221         }
 222         nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
 223         if (!timeout) {
 224                 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
 225                 return 1;
 226         }
 227         return 0;
 228 }
 229 
 230 /* Get BGX Rx/Tx stats and respond to VF's request */
 231 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
 232 {
 233         int bgx_idx, lmac;
 234         union nic_mbx mbx = {};
 235 
 236         bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
 237         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
 238 
 239         mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
 240         mbx.bgx_stats.vf_id = bgx->vf_id;
 241         mbx.bgx_stats.rx = bgx->rx;
 242         mbx.bgx_stats.idx = bgx->idx;
 243         if (bgx->rx)
 244                 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
 245                                                             lmac, bgx->idx);
 246         else
 247                 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
 248                                                             lmac, bgx->idx);
 249         nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
 250 }
 251 
 252 /* Update hardware min/max frame size */
 253 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
 254 {
 255         int bgx, lmac, lmac_cnt;
 256         u64 lmac_credits;
 257 
 258         if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS))
 259                 return 1;
 260 
 261         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 262         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 263         lmac += bgx * MAX_LMAC_PER_BGX;
 264 
 265         new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
 266 
 267         /* Update corresponding LMAC credits */
 268         lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
 269         lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8));
 270         lmac_credits &= ~(0xFFFFFULL << 12);
 271         lmac_credits |= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12);
 272         nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits);
 273 
 274         /* Enforce MTU in HW
 275          * This config is supported only from 88xx pass 2.0 onwards.
 276          */
 277         if (!pass1_silicon(nic->pdev))
 278                 nic_reg_write(nic,
 279                               NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs);
 280         return 0;
 281 }
 282 
 283 /* Set minimum transmit packet size */
 284 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
 285 {
 286         int lmac, max_lmac;
 287         u16 sdevid;
 288         u64 lmac_cfg;
 289 
 290         /* There is a issue in HW where-in while sending GSO sized
 291          * pkts as part of TSO, if pkt len falls below this size
 292          * NIC will zero PAD packet and also updates IP total length.
 293          * Hence set this value to lessthan min pkt size of MAC+IP+TCP
 294          * headers, BGX will do the padding to transmit 64 byte pkt.
 295          */
 296         if (size > 52)
 297                 size = 52;
 298 
 299         pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
 300         /* 81xx's RGX has only one LMAC */
 301         if (sdevid == PCI_SUBSYS_DEVID_81XX_NIC_PF)
 302                 max_lmac = ((nic->hw->bgx_cnt - 1) * MAX_LMAC_PER_BGX) + 1;
 303         else
 304                 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX;
 305 
 306         for (lmac = 0; lmac < max_lmac; lmac++) {
 307                 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
 308                 lmac_cfg &= ~(0xF << 2);
 309                 lmac_cfg |= ((size / 4) << 2);
 310                 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
 311         }
 312 }
 313 
 314 /* Function to check number of LMACs present and set VF::LMAC mapping.
 315  * Mapping will be used while initializing channels.
 316  */
 317 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
 318 {
 319         unsigned bgx_map = bgx_get_map(nic->node);
 320         int bgx, next_bgx_lmac = 0;
 321         int lmac, lmac_cnt = 0;
 322         u64 lmac_credit;
 323 
 324         nic->num_vf_en = 0;
 325 
 326         for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) {
 327                 if (!(bgx_map & (1 << bgx)))
 328                         continue;
 329                 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
 330                 for (lmac = 0; lmac < lmac_cnt; lmac++)
 331                         nic->vf_lmac_map[next_bgx_lmac++] =
 332                                                 NIC_SET_VF_LMAC_MAP(bgx, lmac);
 333                 nic->num_vf_en += lmac_cnt;
 334 
 335                 /* Program LMAC credits */
 336                 lmac_credit = (1ull << 1); /* channel credit enable */
 337                 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
 338                 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
 339                 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
 340                                 NIC_HW_MAX_FRS) / 16) << 12);
 341                 lmac = bgx * MAX_LMAC_PER_BGX;
 342                 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
 343                         nic_reg_write(nic,
 344                                       NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
 345                                       lmac_credit);
 346 
 347                 /* On CN81XX there are only 8 VFs but max possible no of
 348                  * interfaces are 9.
 349                  */
 350                 if (nic->num_vf_en >= pci_sriov_get_totalvfs(nic->pdev)) {
 351                         nic->num_vf_en = pci_sriov_get_totalvfs(nic->pdev);
 352                         break;
 353                 }
 354         }
 355 }
 356 
 357 static void nic_get_hw_info(struct nicpf *nic)
 358 {
 359         u16 sdevid;
 360         struct hw_info *hw = nic->hw;
 361 
 362         pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
 363 
 364         switch (sdevid) {
 365         case PCI_SUBSYS_DEVID_88XX_NIC_PF:
 366                 hw->bgx_cnt = MAX_BGX_PER_CN88XX;
 367                 hw->chans_per_lmac = 16;
 368                 hw->chans_per_bgx = 128;
 369                 hw->cpi_cnt = 2048;
 370                 hw->rssi_cnt = 4096;
 371                 hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
 372                 hw->tl3_cnt = 256;
 373                 hw->tl2_cnt = 64;
 374                 hw->tl1_cnt = 2;
 375                 hw->tl1_per_bgx = true;
 376                 break;
 377         case PCI_SUBSYS_DEVID_81XX_NIC_PF:
 378                 hw->bgx_cnt = MAX_BGX_PER_CN81XX;
 379                 hw->chans_per_lmac = 8;
 380                 hw->chans_per_bgx = 32;
 381                 hw->chans_per_rgx = 8;
 382                 hw->chans_per_lbk = 24;
 383                 hw->cpi_cnt = 512;
 384                 hw->rssi_cnt = 256;
 385                 hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */
 386                 hw->tl3_cnt = 64;
 387                 hw->tl2_cnt = 16;
 388                 hw->tl1_cnt = 10;
 389                 hw->tl1_per_bgx = false;
 390                 break;
 391         case PCI_SUBSYS_DEVID_83XX_NIC_PF:
 392                 hw->bgx_cnt = MAX_BGX_PER_CN83XX;
 393                 hw->chans_per_lmac = 8;
 394                 hw->chans_per_bgx = 32;
 395                 hw->chans_per_lbk = 64;
 396                 hw->cpi_cnt = 2048;
 397                 hw->rssi_cnt = 1024;
 398                 hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */
 399                 hw->tl3_cnt = 256;
 400                 hw->tl2_cnt = 64;
 401                 hw->tl1_cnt = 18;
 402                 hw->tl1_per_bgx = false;
 403                 break;
 404         }
 405         hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
 406 }
 407 
 408 #define BGX0_BLOCK 8
 409 #define BGX1_BLOCK 9
 410 
 411 static void nic_init_hw(struct nicpf *nic)
 412 {
 413         int i;
 414         u64 cqm_cfg;
 415 
 416         /* Enable NIC HW block */
 417         nic_reg_write(nic, NIC_PF_CFG, 0x3);
 418 
 419         /* Enable backpressure */
 420         nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
 421 
 422         /* TNS and TNS bypass modes are present only on 88xx
 423          * Also offset of this CSR has changed in 81xx and 83xx.
 424          */
 425         if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) {
 426                 /* Disable TNS mode on both interfaces */
 427                 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
 428                               (NIC_TNS_BYPASS_MODE << 7) |
 429                               BGX0_BLOCK | (1ULL << 16));
 430                 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
 431                               (NIC_TNS_BYPASS_MODE << 7) |
 432                               BGX1_BLOCK | (1ULL << 16));
 433         } else {
 434                 /* Configure timestamp generation timeout to 10us */
 435                 for (i = 0; i < nic->hw->bgx_cnt; i++)
 436                         nic_reg_write(nic, NIC_PF_INTFX_SEND_CFG | (i << 3),
 437                                       (1ULL << 16));
 438         }
 439 
 440         nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
 441                       (1ULL << 63) | BGX0_BLOCK);
 442         nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
 443                       (1ULL << 63) | BGX1_BLOCK);
 444 
 445         /* PKIND configuration */
 446         nic->pkind.minlen = 0;
 447         nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
 448         nic->pkind.lenerr_en = 1;
 449         nic->pkind.rx_hdr = 0;
 450         nic->pkind.hdr_sl = 0;
 451 
 452         for (i = 0; i < NIC_MAX_PKIND; i++)
 453                 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
 454                               *(u64 *)&nic->pkind);
 455 
 456         nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
 457 
 458         /* Timer config */
 459         nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
 460 
 461         /* Enable VLAN ethertype matching and stripping */
 462         nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
 463                       (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
 464 
 465         /* Check if HW expected value is higher (could be in future chips) */
 466         cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG);
 467         if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL)
 468                 nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL);
 469 }
 470 
 471 /* Channel parse index configuration */
 472 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
 473 {
 474         struct hw_info *hw = nic->hw;
 475         u32 vnic, bgx, lmac, chan;
 476         u32 padd, cpi_count = 0;
 477         u64 cpi_base, cpi, rssi_base, rssi;
 478         u8  qset, rq_idx = 0;
 479 
 480         vnic = cfg->vf_id;
 481         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
 482         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
 483 
 484         chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
 485         cpi_base = vnic * NIC_MAX_CPI_PER_LMAC;
 486         rssi_base = vnic * hw->rss_ind_tbl_size;
 487 
 488         /* Rx channel configuration */
 489         nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
 490                       (1ull << 63) | (vnic << 0));
 491         nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
 492                       ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
 493 
 494         if (cfg->cpi_alg == CPI_ALG_NONE)
 495                 cpi_count = 1;
 496         else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
 497                 cpi_count = 8;
 498         else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
 499                 cpi_count = 16;
 500         else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
 501                 cpi_count = NIC_MAX_CPI_PER_LMAC;
 502 
 503         /* RSS Qset, Qidx mapping */
 504         qset = cfg->vf_id;
 505         rssi = rssi_base;
 506         for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
 507                 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
 508                               (qset << 3) | rq_idx);
 509                 rq_idx++;
 510         }
 511 
 512         rssi = 0;
 513         cpi = cpi_base;
 514         for (; cpi < (cpi_base + cpi_count); cpi++) {
 515                 /* Determine port to channel adder */
 516                 if (cfg->cpi_alg != CPI_ALG_DIFF)
 517                         padd = cpi % cpi_count;
 518                 else
 519                         padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
 520 
 521                 /* Leave RSS_SIZE as '0' to disable RSS */
 522                 if (pass1_silicon(nic->pdev)) {
 523                         nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
 524                                       (vnic << 24) | (padd << 16) |
 525                                       (rssi_base + rssi));
 526                 } else {
 527                         /* Set MPI_ALG to '0' to disable MCAM parsing */
 528                         nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
 529                                       (padd << 16));
 530                         /* MPI index is same as CPI if MPI_ALG is not enabled */
 531                         nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
 532                                       (vnic << 24) | (rssi_base + rssi));
 533                 }
 534 
 535                 if ((rssi + 1) >= cfg->rq_cnt)
 536                         continue;
 537 
 538                 if (cfg->cpi_alg == CPI_ALG_VLAN)
 539                         rssi++;
 540                 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
 541                         rssi = ((cpi - cpi_base) & 0xe) >> 1;
 542                 else if (cfg->cpi_alg == CPI_ALG_DIFF)
 543                         rssi = ((cpi - cpi_base) & 0x38) >> 3;
 544         }
 545         nic->cpi_base[cfg->vf_id] = cpi_base;
 546         nic->rssi_base[cfg->vf_id] = rssi_base;
 547 }
 548 
 549 /* Responsds to VF with its RSS indirection table size */
 550 static void nic_send_rss_size(struct nicpf *nic, int vf)
 551 {
 552         union nic_mbx mbx = {};
 553 
 554         mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
 555         mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size;
 556         nic_send_msg_to_vf(nic, vf, &mbx);
 557 }
 558 
 559 /* Receive side scaling configuration
 560  * configure:
 561  * - RSS index
 562  * - indir table i.e hash::RQ mapping
 563  * - no of hash bits to consider
 564  */
 565 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
 566 {
 567         u8  qset, idx = 0;
 568         u64 cpi_cfg, cpi_base, rssi_base, rssi;
 569         u64 idx_addr;
 570 
 571         rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
 572 
 573         rssi = rssi_base;
 574 
 575         for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
 576                 u8 svf = cfg->ind_tbl[idx] >> 3;
 577 
 578                 if (svf)
 579                         qset = nic->vf_sqs[cfg->vf_id][svf - 1];
 580                 else
 581                         qset = cfg->vf_id;
 582                 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
 583                               (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
 584                 idx++;
 585         }
 586 
 587         cpi_base = nic->cpi_base[cfg->vf_id];
 588         if (pass1_silicon(nic->pdev))
 589                 idx_addr = NIC_PF_CPI_0_2047_CFG;
 590         else
 591                 idx_addr = NIC_PF_MPI_0_2047_CFG;
 592         cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
 593         cpi_cfg &= ~(0xFULL << 20);
 594         cpi_cfg |= (cfg->hash_bits << 20);
 595         nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
 596 }
 597 
 598 /* 4 level transmit side scheduler configutation
 599  * for TNS bypass mode
 600  *
 601  * Sample configuration for SQ0 on 88xx
 602  * VNIC0-SQ0 -> TL4(0)   -> TL3[0]   -> TL2[0]  -> TL1[0] -> BGX0
 603  * VNIC1-SQ0 -> TL4(8)   -> TL3[2]   -> TL2[0]  -> TL1[0] -> BGX0
 604  * VNIC2-SQ0 -> TL4(16)  -> TL3[4]   -> TL2[1]  -> TL1[0] -> BGX0
 605  * VNIC3-SQ0 -> TL4(24)  -> TL3[6]   -> TL2[1]  -> TL1[0] -> BGX0
 606  * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
 607  * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
 608  * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
 609  * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
 610  */
 611 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
 612                                struct sq_cfg_msg *sq)
 613 {
 614         struct hw_info *hw = nic->hw;
 615         u32 bgx, lmac, chan;
 616         u32 tl2, tl3, tl4;
 617         u32 rr_quantum;
 618         u8 sq_idx = sq->sq_num;
 619         u8 pqs_vnic;
 620         int svf;
 621 
 622         if (sq->sqs_mode)
 623                 pqs_vnic = nic->pqs_vf[vnic];
 624         else
 625                 pqs_vnic = vnic;
 626 
 627         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
 628         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
 629 
 630         /* 24 bytes for FCS, IPG and preamble */
 631         rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
 632 
 633         /* For 88xx 0-511 TL4 transmits via BGX0 and
 634          * 512-1023 TL4s transmit via BGX1.
 635          */
 636         if (hw->tl1_per_bgx) {
 637                 tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
 638                 if (!sq->sqs_mode) {
 639                         tl4 += (lmac * MAX_QUEUES_PER_QSET);
 640                 } else {
 641                         for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
 642                                 if (nic->vf_sqs[pqs_vnic][svf] == vnic)
 643                                         break;
 644                         }
 645                         tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
 646                         tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
 647                         tl4 += (svf * MAX_QUEUES_PER_QSET);
 648                 }
 649         } else {
 650                 tl4 = (vnic * MAX_QUEUES_PER_QSET);
 651         }
 652         tl4 += sq_idx;
 653 
 654         tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt);
 655         nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
 656                       ((u64)vnic << NIC_QS_ID_SHIFT) |
 657                       ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
 658         nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
 659                       ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
 660 
 661         nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
 662 
 663         /* On 88xx 0-127 channels are for BGX0 and
 664          * 127-255 channels for BGX1.
 665          *
 666          * On 81xx/83xx TL3_CHAN reg should be configured with channel
 667          * within LMAC i.e 0-7 and not the actual channel number like on 88xx
 668          */
 669         chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
 670         if (hw->tl1_per_bgx)
 671                 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
 672         else
 673                 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0);
 674 
 675         /* Enable backpressure on the channel */
 676         nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
 677 
 678         tl2 = tl3 >> 2;
 679         nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
 680         nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
 681         /* No priorities as of now */
 682         nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
 683 
 684         /* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1'
 685          * on 81xx/83xx TL2 needs to be configured to transmit to one of the
 686          * possible LMACs.
 687          *
 688          * This register doesn't exist on 88xx.
 689          */
 690         if (!hw->tl1_per_bgx)
 691                 nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3),
 692                               lmac + (bgx * MAX_LMAC_PER_BGX));
 693 }
 694 
 695 /* Send primary nicvf pointer to secondary QS's VF */
 696 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
 697 {
 698         union nic_mbx mbx = {};
 699 
 700         mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
 701         mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
 702         nic_send_msg_to_vf(nic, sqs, &mbx);
 703 }
 704 
 705 /* Send SQS's nicvf pointer to primary QS's VF */
 706 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
 707 {
 708         union nic_mbx mbx = {};
 709         int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
 710 
 711         mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
 712         mbx.nicvf.sqs_id = nicvf->sqs_id;
 713         mbx.nicvf.nicvf = nic->nicvf[sqs_id];
 714         nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
 715 }
 716 
 717 /* Find next available Qset that can be assigned as a
 718  * secondary Qset to a VF.
 719  */
 720 static int nic_nxt_avail_sqs(struct nicpf *nic)
 721 {
 722         int sqs;
 723 
 724         for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
 725                 if (!nic->sqs_used[sqs])
 726                         nic->sqs_used[sqs] = true;
 727                 else
 728                         continue;
 729                 return sqs + nic->num_vf_en;
 730         }
 731         return -1;
 732 }
 733 
 734 /* Allocate additional Qsets for requested VF */
 735 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
 736 {
 737         union nic_mbx mbx = {};
 738         int idx, alloc_qs = 0;
 739         int sqs_id;
 740 
 741         if (!nic->num_sqs_en)
 742                 goto send_mbox;
 743 
 744         for (idx = 0; idx < sqs->qs_count; idx++) {
 745                 sqs_id = nic_nxt_avail_sqs(nic);
 746                 if (sqs_id < 0)
 747                         break;
 748                 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
 749                 nic->pqs_vf[sqs_id] = sqs->vf_id;
 750                 alloc_qs++;
 751         }
 752 
 753 send_mbox:
 754         mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
 755         mbx.sqs_alloc.vf_id = sqs->vf_id;
 756         mbx.sqs_alloc.qs_count = alloc_qs;
 757         nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
 758 }
 759 
 760 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
 761 {
 762         int bgx_idx, lmac_idx;
 763 
 764         if (lbk->vf_id >= nic->num_vf_en)
 765                 return -1;
 766 
 767         bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
 768         lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
 769 
 770         bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
 771 
 772         /* Enable moving average calculation.
 773          * Keep the LVL/AVG delay to HW enforced minimum so that, not too many
 774          * packets sneek in between average calculations.
 775          */
 776         nic_reg_write(nic, NIC_PF_CQ_AVG_CFG,
 777                       (BIT_ULL(20) | 0x2ull << 14 | 0x1));
 778         nic_reg_write(nic, NIC_PF_RRM_AVG_CFG,
 779                       (BIT_ULL(20) | 0x3ull << 14 | 0x1));
 780 
 781         return 0;
 782 }
 783 
 784 /* Reset statistics counters */
 785 static int nic_reset_stat_counters(struct nicpf *nic,
 786                                    int vf, struct reset_stat_cfg *cfg)
 787 {
 788         int i, stat, qnum;
 789         u64 reg_addr;
 790 
 791         for (i = 0; i < RX_STATS_ENUM_LAST; i++) {
 792                 if (cfg->rx_stat_mask & BIT(i)) {
 793                         reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 |
 794                                    (vf << NIC_QS_ID_SHIFT) |
 795                                    (i << 3);
 796                         nic_reg_write(nic, reg_addr, 0);
 797                 }
 798         }
 799 
 800         for (i = 0; i < TX_STATS_ENUM_LAST; i++) {
 801                 if (cfg->tx_stat_mask & BIT(i)) {
 802                         reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 |
 803                                    (vf << NIC_QS_ID_SHIFT) |
 804                                    (i << 3);
 805                         nic_reg_write(nic, reg_addr, 0);
 806                 }
 807         }
 808 
 809         for (i = 0; i <= 15; i++) {
 810                 qnum = i >> 1;
 811                 stat = i & 1 ? 1 : 0;
 812                 reg_addr = (vf << NIC_QS_ID_SHIFT) |
 813                            (qnum << NIC_Q_NUM_SHIFT) | (stat << 3);
 814                 if (cfg->rq_stat_mask & BIT(i)) {
 815                         reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1;
 816                         nic_reg_write(nic, reg_addr, 0);
 817                 }
 818                 if (cfg->sq_stat_mask & BIT(i)) {
 819                         reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1;
 820                         nic_reg_write(nic, reg_addr, 0);
 821                 }
 822         }
 823 
 824         return 0;
 825 }
 826 
 827 static void nic_enable_tunnel_parsing(struct nicpf *nic, int vf)
 828 {
 829         u64 prot_def = (IPV6_PROT << 32) | (IPV4_PROT << 16) | ET_PROT;
 830         u64 vxlan_prot_def = (IPV6_PROT_DEF << 32) |
 831                               (IPV4_PROT_DEF) << 16 | ET_PROT_DEF;
 832 
 833         /* Configure tunnel parsing parameters */
 834         nic_reg_write(nic, NIC_PF_RX_GENEVE_DEF,
 835                       (1ULL << 63 | UDP_GENEVE_PORT_NUM));
 836         nic_reg_write(nic, NIC_PF_RX_GENEVE_PROT_DEF,
 837                       ((7ULL << 61) | prot_def));
 838         nic_reg_write(nic, NIC_PF_RX_NVGRE_PROT_DEF,
 839                       ((7ULL << 61) | prot_def));
 840         nic_reg_write(nic, NIC_PF_RX_VXLAN_DEF_0_1,
 841                       ((1ULL << 63) | UDP_VXLAN_PORT_NUM));
 842         nic_reg_write(nic, NIC_PF_RX_VXLAN_PROT_DEF,
 843                       ((0xfULL << 60) | vxlan_prot_def));
 844 }
 845 
 846 static void nic_enable_vf(struct nicpf *nic, int vf, bool enable)
 847 {
 848         int bgx, lmac;
 849 
 850         nic->vf_enabled[vf] = enable;
 851 
 852         if (vf >= nic->num_vf_en)
 853                 return;
 854 
 855         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 856         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 857 
 858         bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable);
 859 }
 860 
 861 static void nic_pause_frame(struct nicpf *nic, int vf, struct pfc *cfg)
 862 {
 863         int bgx, lmac;
 864         struct pfc pfc;
 865         union nic_mbx mbx = {};
 866 
 867         if (vf >= nic->num_vf_en)
 868                 return;
 869         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 870         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 871 
 872         if (cfg->get) {
 873                 bgx_lmac_get_pfc(nic->node, bgx, lmac, &pfc);
 874                 mbx.pfc.msg = NIC_MBOX_MSG_PFC;
 875                 mbx.pfc.autoneg = pfc.autoneg;
 876                 mbx.pfc.fc_rx = pfc.fc_rx;
 877                 mbx.pfc.fc_tx = pfc.fc_tx;
 878                 nic_send_msg_to_vf(nic, vf, &mbx);
 879         } else {
 880                 bgx_lmac_set_pfc(nic->node, bgx, lmac, cfg);
 881                 nic_mbx_send_ack(nic, vf);
 882         }
 883 }
 884 
 885 /* Enable or disable HW timestamping by BGX for pkts received on a LMAC */
 886 static void nic_config_timestamp(struct nicpf *nic, int vf, struct set_ptp *ptp)
 887 {
 888         struct pkind_cfg *pkind;
 889         u8 lmac, bgx_idx;
 890         u64 pkind_val, pkind_idx;
 891 
 892         if (vf >= nic->num_vf_en)
 893                 return;
 894 
 895         bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 896         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 897 
 898         pkind_idx = lmac + bgx_idx * MAX_LMAC_PER_BGX;
 899         pkind_val = nic_reg_read(nic, NIC_PF_PKIND_0_15_CFG | (pkind_idx << 3));
 900         pkind = (struct pkind_cfg *)&pkind_val;
 901 
 902         if (ptp->enable && !pkind->hdr_sl) {
 903                 /* Skiplen to exclude 8byte timestamp while parsing pkt
 904                  * If not configured, will result in L2 errors.
 905                  */
 906                 pkind->hdr_sl = 4;
 907                 /* Adjust max packet length allowed */
 908                 pkind->maxlen += (pkind->hdr_sl * 2);
 909                 bgx_config_timestamping(nic->node, bgx_idx, lmac, true);
 910                 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7 | (1 << 3),
 911                               (ETYPE_ALG_ENDPARSE << 16) | ETH_P_1588);
 912         } else if (!ptp->enable && pkind->hdr_sl) {
 913                 pkind->maxlen -= (pkind->hdr_sl * 2);
 914                 pkind->hdr_sl = 0;
 915                 bgx_config_timestamping(nic->node, bgx_idx, lmac, false);
 916                 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7 | (1 << 3),
 917                               (ETYPE_ALG_SKIP << 16) | ETH_P_8021Q);
 918         }
 919 
 920         nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (pkind_idx << 3), pkind_val);
 921 }
 922 
 923 /* Get BGX LMAC link status and update corresponding VF
 924  * if there is a change, valid only if internal L2 switch
 925  * is not present otherwise VF link is always treated as up
 926  */
 927 static void nic_link_status_get(struct nicpf *nic, u8 vf)
 928 {
 929         union nic_mbx mbx = {};
 930         struct bgx_link_status link;
 931         u8 bgx, lmac;
 932 
 933         mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
 934 
 935         /* Get BGX, LMAC indices for the VF */
 936         bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 937         lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
 938 
 939         /* Get interface link status */
 940         bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
 941 
 942         /* Send a mbox message to VF with current link status */
 943         mbx.link_status.link_up = link.link_up;
 944         mbx.link_status.duplex = link.duplex;
 945         mbx.link_status.speed = link.speed;
 946         mbx.link_status.mac_type = link.mac_type;
 947 
 948         /* reply with link status */
 949         nic_send_msg_to_vf(nic, vf, &mbx);
 950 }
 951 
 952 /* Interrupt handler to handle mailbox messages from VFs */
 953 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
 954 {
 955         union nic_mbx mbx = {};
 956         u64 *mbx_data;
 957         u64 mbx_addr;
 958         u64 reg_addr;
 959         u64 cfg;
 960         int bgx, lmac;
 961         int i;
 962         int ret = 0;
 963 
 964         mbx_addr = nic_get_mbx_addr(vf);
 965         mbx_data = (u64 *)&mbx;
 966 
 967         for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
 968                 *mbx_data = nic_reg_read(nic, mbx_addr);
 969                 mbx_data++;
 970                 mbx_addr += sizeof(u64);
 971         }
 972 
 973         dev_dbg(&nic->pdev->dev, "%s: Mailbox msg 0x%02x from VF%d\n",
 974                 __func__, mbx.msg.msg, vf);
 975         switch (mbx.msg.msg) {
 976         case NIC_MBOX_MSG_READY:
 977                 nic_mbx_send_ready(nic, vf);
 978                 return;
 979         case NIC_MBOX_MSG_QS_CFG:
 980                 reg_addr = NIC_PF_QSET_0_127_CFG |
 981                            (mbx.qs.num << NIC_QS_ID_SHIFT);
 982                 cfg = mbx.qs.cfg;
 983                 /* Check if its a secondary Qset */
 984                 if (vf >= nic->num_vf_en) {
 985                         cfg = cfg & (~0x7FULL);
 986                         /* Assign this Qset to primary Qset's VF */
 987                         cfg |= nic->pqs_vf[vf];
 988                 }
 989                 nic_reg_write(nic, reg_addr, cfg);
 990                 break;
 991         case NIC_MBOX_MSG_RQ_CFG:
 992                 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
 993                            (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
 994                            (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
 995                 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
 996                 /* Enable CQE_RX2_S extension in CQE_RX descriptor.
 997                  * This gets appended by default on 81xx/83xx chips,
 998                  * for consistency enabling the same on 88xx pass2
 999                  * where this is introduced.
1000                  */
1001                 if (pass2_silicon(nic->pdev))
1002                         nic_reg_write(nic, NIC_PF_RX_CFG, 0x01);
1003                 if (!pass1_silicon(nic->pdev))
1004                         nic_enable_tunnel_parsing(nic, vf);
1005                 break;
1006         case NIC_MBOX_MSG_RQ_BP_CFG:
1007                 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
1008                            (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
1009                            (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
1010                 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
1011                 break;
1012         case NIC_MBOX_MSG_RQ_SW_SYNC:
1013                 ret = nic_rcv_queue_sw_sync(nic);
1014                 break;
1015         case NIC_MBOX_MSG_RQ_DROP_CFG:
1016                 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
1017                            (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
1018                            (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
1019                 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
1020                 break;
1021         case NIC_MBOX_MSG_SQ_CFG:
1022                 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
1023                            (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
1024                            (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
1025                 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
1026                 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
1027                 break;
1028         case NIC_MBOX_MSG_SET_MAC:
1029                 if (vf >= nic->num_vf_en) {
1030                         ret = -1; /* NACK */
1031                         break;
1032                 }
1033                 lmac = mbx.mac.vf_id;
1034                 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
1035                 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
1036                 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
1037                 break;
1038         case NIC_MBOX_MSG_SET_MAX_FRS:
1039                 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
1040                                         mbx.frs.vf_id);
1041                 break;
1042         case NIC_MBOX_MSG_CPI_CFG:
1043                 nic_config_cpi(nic, &mbx.cpi_cfg);
1044                 break;
1045         case NIC_MBOX_MSG_RSS_SIZE:
1046                 nic_send_rss_size(nic, vf);
1047                 return;
1048         case NIC_MBOX_MSG_RSS_CFG:
1049         case NIC_MBOX_MSG_RSS_CFG_CONT:
1050                 nic_config_rss(nic, &mbx.rss_cfg);
1051                 break;
1052         case NIC_MBOX_MSG_CFG_DONE:
1053                 /* Last message of VF config msg sequence */
1054                 nic_enable_vf(nic, vf, true);
1055                 break;
1056         case NIC_MBOX_MSG_SHUTDOWN:
1057                 /* First msg in VF teardown sequence */
1058                 if (vf >= nic->num_vf_en)
1059                         nic->sqs_used[vf - nic->num_vf_en] = false;
1060                 nic->pqs_vf[vf] = 0;
1061                 nic_enable_vf(nic, vf, false);
1062                 break;
1063         case NIC_MBOX_MSG_ALLOC_SQS:
1064                 nic_alloc_sqs(nic, &mbx.sqs_alloc);
1065                 return;
1066         case NIC_MBOX_MSG_NICVF_PTR:
1067                 nic->nicvf[vf] = mbx.nicvf.nicvf;
1068                 break;
1069         case NIC_MBOX_MSG_PNICVF_PTR:
1070                 nic_send_pnicvf(nic, vf);
1071                 return;
1072         case NIC_MBOX_MSG_SNICVF_PTR:
1073                 nic_send_snicvf(nic, &mbx.nicvf);
1074                 return;
1075         case NIC_MBOX_MSG_BGX_STATS:
1076                 nic_get_bgx_stats(nic, &mbx.bgx_stats);
1077                 return;
1078         case NIC_MBOX_MSG_LOOPBACK:
1079                 ret = nic_config_loopback(nic, &mbx.lbk);
1080                 break;
1081         case NIC_MBOX_MSG_RESET_STAT_COUNTER:
1082                 ret = nic_reset_stat_counters(nic, vf, &mbx.reset_stat);
1083                 break;
1084         case NIC_MBOX_MSG_PFC:
1085                 nic_pause_frame(nic, vf, &mbx.pfc);
1086                 return;
1087         case NIC_MBOX_MSG_PTP_CFG:
1088                 nic_config_timestamp(nic, vf, &mbx.ptp);
1089                 break;
1090         case NIC_MBOX_MSG_RESET_XCAST:
1091                 if (vf >= nic->num_vf_en) {
1092                         ret = -1; /* NACK */
1093                         break;
1094                 }
1095                 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1096                 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1097                 bgx_reset_xcast_mode(nic->node, bgx, lmac,
1098                                      vf < NIC_VF_PER_MBX_REG ? vf :
1099                                      vf - NIC_VF_PER_MBX_REG);
1100                 break;
1101 
1102         case NIC_MBOX_MSG_ADD_MCAST:
1103                 if (vf >= nic->num_vf_en) {
1104                         ret = -1; /* NACK */
1105                         break;
1106                 }
1107                 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1108                 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1109                 bgx_set_dmac_cam_filter(nic->node, bgx, lmac,
1110                                         mbx.xcast.mac,
1111                                         vf < NIC_VF_PER_MBX_REG ? vf :
1112                                         vf - NIC_VF_PER_MBX_REG);
1113                 break;
1114 
1115         case NIC_MBOX_MSG_SET_XCAST:
1116                 if (vf >= nic->num_vf_en) {
1117                         ret = -1; /* NACK */
1118                         break;
1119                 }
1120                 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1121                 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1122                 bgx_set_xcast_mode(nic->node, bgx, lmac, mbx.xcast.mode);
1123                 break;
1124         case NIC_MBOX_MSG_BGX_LINK_CHANGE:
1125                 if (vf >= nic->num_vf_en) {
1126                         ret = -1; /* NACK */
1127                         break;
1128                 }
1129                 nic_link_status_get(nic, vf);
1130                 return;
1131         default:
1132                 dev_err(&nic->pdev->dev,
1133                         "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
1134                 break;
1135         }
1136 
1137         if (!ret) {
1138                 nic_mbx_send_ack(nic, vf);
1139         } else if (mbx.msg.msg != NIC_MBOX_MSG_READY) {
1140                 dev_err(&nic->pdev->dev, "NACK for MBOX 0x%02x from VF %d\n",
1141                         mbx.msg.msg, vf);
1142                 nic_mbx_send_nack(nic, vf);
1143         }
1144 }
1145 
1146 static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq)
1147 {
1148         struct nicpf *nic = (struct nicpf *)nic_irq;
1149         int mbx;
1150         u64 intr;
1151         u8  vf;
1152 
1153         if (irq == pci_irq_vector(nic->pdev, NIC_PF_INTR_ID_MBOX0))
1154                 mbx = 0;
1155         else
1156                 mbx = 1;
1157 
1158         intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
1159         dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
1160         for (vf = 0; vf < NIC_VF_PER_MBX_REG; vf++) {
1161                 if (intr & (1ULL << vf)) {
1162                         dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
1163                                 vf + (mbx * NIC_VF_PER_MBX_REG));
1164 
1165                         nic_handle_mbx_intr(nic, vf +
1166                                             (mbx * NIC_VF_PER_MBX_REG));
1167                         nic_clear_mbx_intr(nic, vf, mbx);
1168                 }
1169         }
1170         return IRQ_HANDLED;
1171 }
1172 
1173 static void nic_free_all_interrupts(struct nicpf *nic)
1174 {
1175         int irq;
1176 
1177         for (irq = 0; irq < nic->num_vec; irq++) {
1178                 if (nic->irq_allocated[irq])
1179                         free_irq(pci_irq_vector(nic->pdev, irq), nic);
1180                 nic->irq_allocated[irq] = false;
1181         }
1182 }
1183 
1184 static int nic_register_interrupts(struct nicpf *nic)
1185 {
1186         int i, ret;
1187         nic->num_vec = pci_msix_vec_count(nic->pdev);
1188 
1189         /* Enable MSI-X */
1190         ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec,
1191                                     PCI_IRQ_MSIX);
1192         if (ret < 0) {
1193                 dev_err(&nic->pdev->dev,
1194                         "Request for #%d msix vectors failed, returned %d\n",
1195                            nic->num_vec, ret);
1196                 return 1;
1197         }
1198 
1199         /* Register mailbox interrupt handler */
1200         for (i = NIC_PF_INTR_ID_MBOX0; i < nic->num_vec; i++) {
1201                 sprintf(nic->irq_name[i],
1202                         "NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0));
1203 
1204                 ret = request_irq(pci_irq_vector(nic->pdev, i),
1205                                   nic_mbx_intr_handler, 0,
1206                                   nic->irq_name[i], nic);
1207                 if (ret)
1208                         goto fail;
1209 
1210                 nic->irq_allocated[i] = true;
1211         }
1212 
1213         /* Enable mailbox interrupt */
1214         nic_enable_mbx_intr(nic);
1215         return 0;
1216 
1217 fail:
1218         dev_err(&nic->pdev->dev, "Request irq failed\n");
1219         nic_free_all_interrupts(nic);
1220         pci_free_irq_vectors(nic->pdev);
1221         nic->num_vec = 0;
1222         return ret;
1223 }
1224 
1225 static void nic_unregister_interrupts(struct nicpf *nic)
1226 {
1227         nic_free_all_interrupts(nic);
1228         pci_free_irq_vectors(nic->pdev);
1229         nic->num_vec = 0;
1230 }
1231 
1232 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
1233 {
1234         int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
1235         u16 total_vf;
1236 
1237         /* Secondary Qsets are needed only if CPU count is
1238          * morethan MAX_QUEUES_PER_QSET.
1239          */
1240         if (num_online_cpus() <= MAX_QUEUES_PER_QSET)
1241                 return 0;
1242 
1243         /* Check if its a multi-node environment */
1244         if (nr_node_ids > 1)
1245                 sqs_per_vf = MAX_SQS_PER_VF;
1246 
1247         pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
1248         pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
1249         return min(total_vf - vf_en, vf_en * sqs_per_vf);
1250 }
1251 
1252 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
1253 {
1254         int pos = 0;
1255         int vf_en;
1256         int err;
1257         u16 total_vf_cnt;
1258 
1259         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1260         if (!pos) {
1261                 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
1262                 return -ENODEV;
1263         }
1264 
1265         pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
1266         if (total_vf_cnt < nic->num_vf_en)
1267                 nic->num_vf_en = total_vf_cnt;
1268 
1269         if (!total_vf_cnt)
1270                 return 0;
1271 
1272         vf_en = nic->num_vf_en;
1273         nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
1274         vf_en += nic->num_sqs_en;
1275 
1276         err = pci_enable_sriov(pdev, vf_en);
1277         if (err) {
1278                 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
1279                         vf_en);
1280                 nic->num_vf_en = 0;
1281                 return err;
1282         }
1283 
1284         dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
1285                  vf_en);
1286 
1287         nic->flags |= NIC_SRIOV_ENABLED;
1288         return 0;
1289 }
1290 
1291 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1292 {
1293         struct device *dev = &pdev->dev;
1294         struct nicpf *nic;
1295         u8     max_lmac;
1296         int    err;
1297 
1298         BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
1299 
1300         nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
1301         if (!nic)
1302                 return -ENOMEM;
1303 
1304         nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL);
1305         if (!nic->hw)
1306                 return -ENOMEM;
1307 
1308         pci_set_drvdata(pdev, nic);
1309 
1310         nic->pdev = pdev;
1311 
1312         err = pci_enable_device(pdev);
1313         if (err) {
1314                 dev_err(dev, "Failed to enable PCI device\n");
1315                 pci_set_drvdata(pdev, NULL);
1316                 return err;
1317         }
1318 
1319         err = pci_request_regions(pdev, DRV_NAME);
1320         if (err) {
1321                 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1322                 goto err_disable_device;
1323         }
1324 
1325         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1326         if (err) {
1327                 dev_err(dev, "Unable to get usable DMA configuration\n");
1328                 goto err_release_regions;
1329         }
1330 
1331         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1332         if (err) {
1333                 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1334                 goto err_release_regions;
1335         }
1336 
1337         /* MAP PF's configuration registers */
1338         nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1339         if (!nic->reg_base) {
1340                 dev_err(dev, "Cannot map config register space, aborting\n");
1341                 err = -ENOMEM;
1342                 goto err_release_regions;
1343         }
1344 
1345         nic->node = nic_get_node_id(pdev);
1346 
1347         /* Get HW capability info */
1348         nic_get_hw_info(nic);
1349 
1350         /* Allocate memory for LMAC tracking elements */
1351         err = -ENOMEM;
1352         max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX;
1353 
1354         nic->vf_lmac_map = devm_kmalloc_array(dev, max_lmac, sizeof(u8),
1355                                               GFP_KERNEL);
1356         if (!nic->vf_lmac_map)
1357                 goto err_release_regions;
1358 
1359         /* Initialize hardware */
1360         nic_init_hw(nic);
1361 
1362         nic_set_lmac_vf_mapping(nic);
1363 
1364         /* Register interrupts */
1365         err = nic_register_interrupts(nic);
1366         if (err)
1367                 goto err_release_regions;
1368 
1369         /* Configure SRIOV */
1370         err = nic_sriov_init(pdev, nic);
1371         if (err)
1372                 goto err_unregister_interrupts;
1373 
1374         return 0;
1375 
1376 err_unregister_interrupts:
1377         nic_unregister_interrupts(nic);
1378 err_release_regions:
1379         pci_release_regions(pdev);
1380 err_disable_device:
1381         pci_disable_device(pdev);
1382         pci_set_drvdata(pdev, NULL);
1383         return err;
1384 }
1385 
1386 static void nic_remove(struct pci_dev *pdev)
1387 {
1388         struct nicpf *nic = pci_get_drvdata(pdev);
1389 
1390         if (!nic)
1391                 return;
1392 
1393         if (nic->flags & NIC_SRIOV_ENABLED)
1394                 pci_disable_sriov(pdev);
1395 
1396         nic_unregister_interrupts(nic);
1397         pci_release_regions(pdev);
1398 
1399         pci_disable_device(pdev);
1400         pci_set_drvdata(pdev, NULL);
1401 }
1402 
1403 static struct pci_driver nic_driver = {
1404         .name = DRV_NAME,
1405         .id_table = nic_id_table,
1406         .probe = nic_probe,
1407         .remove = nic_remove,
1408 };
1409 
1410 static int __init nic_init_module(void)
1411 {
1412         pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1413 
1414         return pci_register_driver(&nic_driver);
1415 }
1416 
1417 static void __exit nic_cleanup_module(void)
1418 {
1419         pci_unregister_driver(&nic_driver);
1420 }
1421 
1422 module_init(nic_init_module);
1423 module_exit(nic_cleanup_module);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/cavium/thunder/nic_main.c

DEFINITIONS
