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23 #ifndef __CN23XX_VF_REGS_H__
24 #define __CN23XX_VF_REGS_H__
25
26 #define CN23XX_CONFIG_XPANSION_BAR 0x38
27
28 #define CN23XX_CONFIG_PCIE_CAP 0x70
29 #define CN23XX_CONFIG_PCIE_DEVCAP 0x74
30 #define CN23XX_CONFIG_PCIE_DEVCTL 0x78
31 #define CN23XX_CONFIG_PCIE_LINKCAP 0x7C
32 #define CN23XX_CONFIG_PCIE_LINKCTL 0x80
33 #define CN23XX_CONFIG_PCIE_SLOTCAP 0x84
34 #define CN23XX_CONFIG_PCIE_SLOTCTL 0x88
35
36 #define CN23XX_CONFIG_PCIE_FLTMSK 0x720
37
38
39
40
41
42
43 #define CN23XX_DEFAULT_INPUT_JABBER 0xEA60
44
45
46
47
48 #define CN23XX_VF_IQ_OFFSET 0x20000
49
50
51
52
53 #define CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 0x10040
54
55
56 #define CN23XX_VF_SLI_IQ_BASE_ADDR_START64 0x10010
57
58
59 #define CN23XX_VF_SLI_IQ_DOORBELL_START 0x10020
60
61
62 #define CN23XX_VF_SLI_IQ_SIZE_START 0x10030
63
64
65
66
67 #define CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 0x10000
68
69
70 #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \
71 (CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
72
73 #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \
74 (CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
75
76 #define CN23XX_VF_SLI_IQ_SIZE(iq) \
77 (CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET))
78
79 #define CN23XX_VF_SLI_IQ_DOORBELL(iq) \
80 (CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET))
81
82 #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \
83 (CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
84
85
86 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
87 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
88
89
90
91 #define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25)
92 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
93 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
94 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
95 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
96 #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8)
97 #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
98 #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5)
99 #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4)
100 #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3)
101 #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2)
102 #define CN23XX_PKT_INPUT_CTL_GATHER_RO (1)
103
104
105 #define CN23XX_PKT_INPUT_CTL_RPVF_MASK (0x3F)
106 #define CN23XX_PKT_INPUT_CTL_RPVF_POS (48)
107
108 #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK (0x7)
109 #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45)
110
111 #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK (0x1FFF)
112 #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS (32)
113 #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK (0x3)
114 #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29)
115 #define CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL)
116 #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32)
117 #define CN23XX_PKT_IN_DONE_CNT_MASK (0x00000000FFFFFFFFULL)
118
119 #ifdef __LITTLE_ENDIAN_BITFIELD
120 #define CN23XX_PKT_INPUT_CTL_MASK \
121 (CN23XX_PKT_INPUT_CTL_RDSIZE \
122 | CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \
123 | CN23XX_PKT_INPUT_CTL_USE_CSR)
124 #else
125 #define CN23XX_PKT_INPUT_CTL_MASK \
126 (CN23XX_PKT_INPUT_CTL_RDSIZE \
127 | CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \
128 | CN23XX_PKT_INPUT_CTL_USE_CSR \
129 | CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP)
130 #endif
131
132
133 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
134 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
135
136
137
138
139 #define CN23XX_VF_SLI_OQ_PKT_CONTROL_START 0x10050
140
141
142 #define CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE 0x10060
143
144
145 #define CN23XX_VF_SLI_OQ_BASE_ADDR_START64 0x10070
146
147
148 #define CN23XX_VF_SLI_OQ_PKT_CREDITS_START 0x10080
149
150
151 #define CN23XX_VF_SLI_OQ_SIZE_START 0x10090
152
153
154 #define CN23XX_VF_SLI_OQ_PKT_SENT_START 0x100B0
155
156
157 #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 0x100A0
158
159
160 #define CN23XX_VF_OQ_OFFSET 0x20000
161
162
163
164 #define CN23XX_VF_SLI_OQ_PKT_CONTROL(oq) \
165 (CN23XX_VF_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_VF_OQ_OFFSET))
166
167 #define CN23XX_VF_SLI_OQ_BASE_ADDR64(oq) \
168 (CN23XX_VF_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
169
170 #define CN23XX_VF_SLI_OQ_SIZE(oq) \
171 (CN23XX_VF_SLI_OQ_SIZE_START + ((oq) * CN23XX_VF_OQ_OFFSET))
172
173 #define CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq) \
174 (CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_VF_OQ_OFFSET))
175
176 #define CN23XX_VF_SLI_OQ_PKTS_SENT(oq) \
177 (CN23XX_VF_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_VF_OQ_OFFSET))
178
179 #define CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq) \
180 (CN23XX_VF_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_VF_OQ_OFFSET))
181
182 #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(oq) \
183 (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
184
185
186 #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_CNT(oq) \
187 (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
188
189 #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_TIME(oq) \
190 (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + \
191 ((oq) * CN23XX_VF_OQ_OFFSET) + 4)
192
193
194 #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13)
195 #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12)
196 #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11)
197 #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9)
198 #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8)
199 #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7)
200 #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6)
201 #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5)
202 #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3)
203 #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2)
204 #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1)
205 #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0)
206
207
208 #define CN23XX_VF_SLI_PKT_MBOX_INT_START 0x10210
209 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200
210
211 #define CN23XX_SLI_MBOX_OFFSET 0x20000
212 #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8
213
214 #define CN23XX_VF_SLI_PKT_MBOX_INT(q) \
215 (CN23XX_VF_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET))
216
217 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \
218 (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \
219 ((q) * CN23XX_SLI_MBOX_OFFSET + \
220 (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET))
221
222
223
224 #define CN23XX_VF_SLI_INT_SUM_START 0x100D0
225
226 #define CN23XX_VF_SLI_INT_SUM(q) \
227 (CN23XX_VF_SLI_INT_SUM_START + ((q) * CN23XX_VF_IQ_OFFSET))
228
229
230
231 #define CN23XX_INTR_PO_INT BIT_ULL(63)
232 #define CN23XX_INTR_PI_INT BIT_ULL(62)
233 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
234 #define CN23XX_INTR_RESEND BIT_ULL(60)
235
236 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
237 #define CN23XX_INTR_MBOX_ENB BIT(0)
238
239
240 #define CN23XX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL
241 #define CN23XX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL
242 #define CN23XX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL
243 #define CN23XX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL
244 #define CN23XX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL
245 #define CN23XX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL
246 #define CN23XX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL
247 #define CN23XX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL
248 #define CN23XX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL
249 #define CN23XX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL
250 #define CN23XX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL
251 #define CN23XX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL
252 #define CN23XX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL
253 #define CN23XX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL
254
255
256 #define CN23XX_RST_BOOT 0x0001180006001600ULL
257
258
259
260 #define CN23XX_MSIX_TABLE_ADDR_START 0x0
261 #define CN23XX_MSIX_TABLE_DATA_START 0x8
262
263 #define CN23XX_MSIX_TABLE_SIZE 0x10
264 #define CN23XX_MSIX_TABLE_ENTRIES 0x41
265
266 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
267
268 #define CN23XX_MSIX_TABLE_ADDR(idx) \
269 (CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
270
271 #define CN23XX_MSIX_TABLE_DATA(idx) \
272 (CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
273
274 #endif