drivers/net/ethernet/sun/sungem.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
__sungem_phy_read
_sungem_phy_read
sungem_phy_read
__sungem_phy_write
_sungem_phy_write
sungem_phy_write
gem_enable_ints
gem_disable_ints
gem_get_cell
gem_put_cell
gem_netif_stop
gem_netif_start
gem_schedule_reset
gem_handle_mif_event
gem_pcs_interrupt
gem_txmac_interrupt
gem_rxmac_reset
gem_rxmac_interrupt
gem_mac_interrupt
gem_mif_interrupt
gem_pci_interrupt
gem_abnormal_irq
gem_tx
gem_post_rxds
gem_alloc_skb
gem_rx
gem_poll
gem_interrupt
gem_poll_controller
gem_tx_timeout
gem_intme
gem_start_xmit
gem_pcs_reset
gem_pcs_reinit_adv
gem_reset
gem_start_dma
gem_stop_dma
gem_begin_auto_negotiation
gem_set_link_modes
gem_mdio_link_not_up
gem_link_timer
gem_clean_rings
gem_init_rings
gem_init_phy
gem_init_dma
gem_setup_multicast
gem_init_mac
gem_init_pause_thresholds
gem_check_invariants
gem_reinit_chip
gem_stop_phy
gem_do_start
gem_do_stop
gem_reset_task
gem_open
gem_close
gem_suspend
gem_resume
gem_get_stats
gem_set_mac_address
gem_set_multicast
gem_change_mtu
gem_get_drvinfo
gem_get_link_ksettings
gem_set_link_ksettings
gem_nway_reset
gem_get_msglevel
gem_set_msglevel
gem_get_wol
gem_set_wol
gem_ioctl
find_eth_addr_in_vpd
get_gem_mac_nonobp
gem_get_device_address
gem_remove_one
gem_init_one
   1 // SPDX-License-Identifier: GPL-2.0
   2 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
   3  * sungem.c: Sun GEM ethernet driver.
   4  *
   5  * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
   6  *
   7  * Support for Apple GMAC and assorted PHYs, WOL, Power Management
   8  * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
   9  * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
  10  *
  11  * NAPI and NETPOLL support
  12  * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
  13  *
  14  */
  15 
  16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17 
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/fcntl.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/ioport.h>
  24 #include <linux/in.h>
  25 #include <linux/sched.h>
  26 #include <linux/string.h>
  27 #include <linux/delay.h>
  28 #include <linux/errno.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/mii.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/crc32.h>
  37 #include <linux/random.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/bitops.h>
  41 #include <linux/mm.h>
  42 #include <linux/gfp.h>
  43 
  44 #include <asm/io.h>
  45 #include <asm/byteorder.h>
  46 #include <linux/uaccess.h>
  47 #include <asm/irq.h>
  48 
  49 #ifdef CONFIG_SPARC
  50 #include <asm/idprom.h>
  51 #include <asm/prom.h>
  52 #endif
  53 
  54 #ifdef CONFIG_PPC_PMAC
  55 #include <asm/prom.h>
  56 #include <asm/machdep.h>
  57 #include <asm/pmac_feature.h>
  58 #endif
  59 
  60 #include <linux/sungem_phy.h>
  61 #include "sungem.h"
  62 
  63 #define STRIP_FCS
  64 
  65 #define DEFAULT_MSG     (NETIF_MSG_DRV          | \
  66                          NETIF_MSG_PROBE        | \
  67                          NETIF_MSG_LINK)
  68 
  69 #define ADVERTISE_MASK  (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  70                          SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  71                          SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
  72                          SUPPORTED_Pause | SUPPORTED_Autoneg)
  73 
  74 #define DRV_NAME        "sungem"
  75 #define DRV_VERSION     "1.0"
  76 #define DRV_AUTHOR      "David S. Miller <davem@redhat.com>"
  77 
  78 static char version[] =
  79         DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
  80 
  81 MODULE_AUTHOR(DRV_AUTHOR);
  82 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
  83 MODULE_LICENSE("GPL");
  84 
  85 #define GEM_MODULE_NAME "gem"
  86 
  87 static const struct pci_device_id gem_pci_tbl[] = {
  88         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
  89           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  90 
  91         /* These models only differ from the original GEM in
  92          * that their tx/rx fifos are of a different size and
  93          * they only support 10/100 speeds. -DaveM
  94          *
  95          * Apple's GMAC does support gigabit on machines with
  96          * the BCM54xx PHYs. -BenH
  97          */
  98         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
  99           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 100         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
 101           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 102         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
 103           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 104         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
 105           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 106         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
 107           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 108         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
 109           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 110         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
 111           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 112         {0, }
 113 };
 114 
 115 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
 116 
 117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
 118 {
 119         u32 cmd;
 120         int limit = 10000;
 121 
 122         cmd  = (1 << 30);
 123         cmd |= (2 << 28);
 124         cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 125         cmd |= (reg << 18) & MIF_FRAME_REGAD;
 126         cmd |= (MIF_FRAME_TAMSB);
 127         writel(cmd, gp->regs + MIF_FRAME);
 128 
 129         while (--limit) {
 130                 cmd = readl(gp->regs + MIF_FRAME);
 131                 if (cmd & MIF_FRAME_TALSB)
 132                         break;
 133 
 134                 udelay(10);
 135         }
 136 
 137         if (!limit)
 138                 cmd = 0xffff;
 139 
 140         return cmd & MIF_FRAME_DATA;
 141 }
 142 
 143 static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
 144 {
 145         struct gem *gp = netdev_priv(dev);
 146         return __sungem_phy_read(gp, mii_id, reg);
 147 }
 148 
 149 static inline u16 sungem_phy_read(struct gem *gp, int reg)
 150 {
 151         return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
 152 }
 153 
 154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
 155 {
 156         u32 cmd;
 157         int limit = 10000;
 158 
 159         cmd  = (1 << 30);
 160         cmd |= (1 << 28);
 161         cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 162         cmd |= (reg << 18) & MIF_FRAME_REGAD;
 163         cmd |= (MIF_FRAME_TAMSB);
 164         cmd |= (val & MIF_FRAME_DATA);
 165         writel(cmd, gp->regs + MIF_FRAME);
 166 
 167         while (limit--) {
 168                 cmd = readl(gp->regs + MIF_FRAME);
 169                 if (cmd & MIF_FRAME_TALSB)
 170                         break;
 171 
 172                 udelay(10);
 173         }
 174 }
 175 
 176 static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
 177 {
 178         struct gem *gp = netdev_priv(dev);
 179         __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
 180 }
 181 
 182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
 183 {
 184         __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
 185 }
 186 
 187 static inline void gem_enable_ints(struct gem *gp)
 188 {
 189         /* Enable all interrupts but TXDONE */
 190         writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 191 }
 192 
 193 static inline void gem_disable_ints(struct gem *gp)
 194 {
 195         /* Disable all interrupts, including TXDONE */
 196         writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 197         (void)readl(gp->regs + GREG_IMASK); /* write posting */
 198 }
 199 
 200 static void gem_get_cell(struct gem *gp)
 201 {
 202         BUG_ON(gp->cell_enabled < 0);
 203         gp->cell_enabled++;
 204 #ifdef CONFIG_PPC_PMAC
 205         if (gp->cell_enabled == 1) {
 206                 mb();
 207                 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
 208                 udelay(10);
 209         }
 210 #endif /* CONFIG_PPC_PMAC */
 211 }
 212 
 213 /* Turn off the chip's clock */
 214 static void gem_put_cell(struct gem *gp)
 215 {
 216         BUG_ON(gp->cell_enabled <= 0);
 217         gp->cell_enabled--;
 218 #ifdef CONFIG_PPC_PMAC
 219         if (gp->cell_enabled == 0) {
 220                 mb();
 221                 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
 222                 udelay(10);
 223         }
 224 #endif /* CONFIG_PPC_PMAC */
 225 }
 226 
 227 static inline void gem_netif_stop(struct gem *gp)
 228 {
 229         netif_trans_update(gp->dev);    /* prevent tx timeout */
 230         napi_disable(&gp->napi);
 231         netif_tx_disable(gp->dev);
 232 }
 233 
 234 static inline void gem_netif_start(struct gem *gp)
 235 {
 236         /* NOTE: unconditional netif_wake_queue is only
 237          * appropriate so long as all callers are assured to
 238          * have free tx slots.
 239          */
 240         netif_wake_queue(gp->dev);
 241         napi_enable(&gp->napi);
 242 }
 243 
 244 static void gem_schedule_reset(struct gem *gp)
 245 {
 246         gp->reset_task_pending = 1;
 247         schedule_work(&gp->reset_task);
 248 }
 249 
 250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
 251 {
 252         if (netif_msg_intr(gp))
 253                 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
 254 }
 255 
 256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 257 {
 258         u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
 259         u32 pcs_miistat;
 260 
 261         if (netif_msg_intr(gp))
 262                 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
 263                         gp->dev->name, pcs_istat);
 264 
 265         if (!(pcs_istat & PCS_ISTAT_LSC)) {
 266                 netdev_err(dev, "PCS irq but no link status change???\n");
 267                 return 0;
 268         }
 269 
 270         /* The link status bit latches on zero, so you must
 271          * read it twice in such a case to see a transition
 272          * to the link being up.
 273          */
 274         pcs_miistat = readl(gp->regs + PCS_MIISTAT);
 275         if (!(pcs_miistat & PCS_MIISTAT_LS))
 276                 pcs_miistat |=
 277                         (readl(gp->regs + PCS_MIISTAT) &
 278                          PCS_MIISTAT_LS);
 279 
 280         if (pcs_miistat & PCS_MIISTAT_ANC) {
 281                 /* The remote-fault indication is only valid
 282                  * when autoneg has completed.
 283                  */
 284                 if (pcs_miistat & PCS_MIISTAT_RF)
 285                         netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
 286                 else
 287                         netdev_info(dev, "PCS AutoNEG complete\n");
 288         }
 289 
 290         if (pcs_miistat & PCS_MIISTAT_LS) {
 291                 netdev_info(dev, "PCS link is now up\n");
 292                 netif_carrier_on(gp->dev);
 293         } else {
 294                 netdev_info(dev, "PCS link is now down\n");
 295                 netif_carrier_off(gp->dev);
 296                 /* If this happens and the link timer is not running,
 297                  * reset so we re-negotiate.
 298                  */
 299                 if (!timer_pending(&gp->link_timer))
 300                         return 1;
 301         }
 302 
 303         return 0;
 304 }
 305 
 306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 307 {
 308         u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
 309 
 310         if (netif_msg_intr(gp))
 311                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
 312                         gp->dev->name, txmac_stat);
 313 
 314         /* Defer timer expiration is quite normal,
 315          * don't even log the event.
 316          */
 317         if ((txmac_stat & MAC_TXSTAT_DTE) &&
 318             !(txmac_stat & ~MAC_TXSTAT_DTE))
 319                 return 0;
 320 
 321         if (txmac_stat & MAC_TXSTAT_URUN) {
 322                 netdev_err(dev, "TX MAC xmit underrun\n");
 323                 dev->stats.tx_fifo_errors++;
 324         }
 325 
 326         if (txmac_stat & MAC_TXSTAT_MPE) {
 327                 netdev_err(dev, "TX MAC max packet size error\n");
 328                 dev->stats.tx_errors++;
 329         }
 330 
 331         /* The rest are all cases of one of the 16-bit TX
 332          * counters expiring.
 333          */
 334         if (txmac_stat & MAC_TXSTAT_NCE)
 335                 dev->stats.collisions += 0x10000;
 336 
 337         if (txmac_stat & MAC_TXSTAT_ECE) {
 338                 dev->stats.tx_aborted_errors += 0x10000;
 339                 dev->stats.collisions += 0x10000;
 340         }
 341 
 342         if (txmac_stat & MAC_TXSTAT_LCE) {
 343                 dev->stats.tx_aborted_errors += 0x10000;
 344                 dev->stats.collisions += 0x10000;
 345         }
 346 
 347         /* We do not keep track of MAC_TXSTAT_FCE and
 348          * MAC_TXSTAT_PCE events.
 349          */
 350         return 0;
 351 }
 352 
 353 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
 354  * so we do the following.
 355  *
 356  * If any part of the reset goes wrong, we return 1 and that causes the
 357  * whole chip to be reset.
 358  */
 359 static int gem_rxmac_reset(struct gem *gp)
 360 {
 361         struct net_device *dev = gp->dev;
 362         int limit, i;
 363         u64 desc_dma;
 364         u32 val;
 365 
 366         /* First, reset & disable MAC RX. */
 367         writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
 368         for (limit = 0; limit < 5000; limit++) {
 369                 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
 370                         break;
 371                 udelay(10);
 372         }
 373         if (limit == 5000) {
 374                 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
 375                 return 1;
 376         }
 377 
 378         writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
 379                gp->regs + MAC_RXCFG);
 380         for (limit = 0; limit < 5000; limit++) {
 381                 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
 382                         break;
 383                 udelay(10);
 384         }
 385         if (limit == 5000) {
 386                 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
 387                 return 1;
 388         }
 389 
 390         /* Second, disable RX DMA. */
 391         writel(0, gp->regs + RXDMA_CFG);
 392         for (limit = 0; limit < 5000; limit++) {
 393                 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
 394                         break;
 395                 udelay(10);
 396         }
 397         if (limit == 5000) {
 398                 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
 399                 return 1;
 400         }
 401 
 402         mdelay(5);
 403 
 404         /* Execute RX reset command. */
 405         writel(gp->swrst_base | GREG_SWRST_RXRST,
 406                gp->regs + GREG_SWRST);
 407         for (limit = 0; limit < 5000; limit++) {
 408                 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
 409                         break;
 410                 udelay(10);
 411         }
 412         if (limit == 5000) {
 413                 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
 414                 return 1;
 415         }
 416 
 417         /* Refresh the RX ring. */
 418         for (i = 0; i < RX_RING_SIZE; i++) {
 419                 struct gem_rxd *rxd = &gp->init_block->rxd[i];
 420 
 421                 if (gp->rx_skbs[i] == NULL) {
 422                         netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
 423                         return 1;
 424                 }
 425 
 426                 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 427         }
 428         gp->rx_new = gp->rx_old = 0;
 429 
 430         /* Now we must reprogram the rest of RX unit. */
 431         desc_dma = (u64) gp->gblock_dvma;
 432         desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
 433         writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
 434         writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
 435         writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 436         val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
 437                (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
 438         writel(val, gp->regs + RXDMA_CFG);
 439         if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
 440                 writel(((5 & RXDMA_BLANK_IPKTS) |
 441                         ((8 << 12) & RXDMA_BLANK_ITIME)),
 442                        gp->regs + RXDMA_BLANK);
 443         else
 444                 writel(((5 & RXDMA_BLANK_IPKTS) |
 445                         ((4 << 12) & RXDMA_BLANK_ITIME)),
 446                        gp->regs + RXDMA_BLANK);
 447         val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
 448         val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
 449         writel(val, gp->regs + RXDMA_PTHRESH);
 450         val = readl(gp->regs + RXDMA_CFG);
 451         writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 452         writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
 453         val = readl(gp->regs + MAC_RXCFG);
 454         writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 455 
 456         return 0;
 457 }
 458 
 459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 460 {
 461         u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
 462         int ret = 0;
 463 
 464         if (netif_msg_intr(gp))
 465                 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
 466                         gp->dev->name, rxmac_stat);
 467 
 468         if (rxmac_stat & MAC_RXSTAT_OFLW) {
 469                 u32 smac = readl(gp->regs + MAC_SMACHINE);
 470 
 471                 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
 472                 dev->stats.rx_over_errors++;
 473                 dev->stats.rx_fifo_errors++;
 474 
 475                 ret = gem_rxmac_reset(gp);
 476         }
 477 
 478         if (rxmac_stat & MAC_RXSTAT_ACE)
 479                 dev->stats.rx_frame_errors += 0x10000;
 480 
 481         if (rxmac_stat & MAC_RXSTAT_CCE)
 482                 dev->stats.rx_crc_errors += 0x10000;
 483 
 484         if (rxmac_stat & MAC_RXSTAT_LCE)
 485                 dev->stats.rx_length_errors += 0x10000;
 486 
 487         /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
 488          * events.
 489          */
 490         return ret;
 491 }
 492 
 493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 494 {
 495         u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
 496 
 497         if (netif_msg_intr(gp))
 498                 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
 499                         gp->dev->name, mac_cstat);
 500 
 501         /* This interrupt is just for pause frame and pause
 502          * tracking.  It is useful for diagnostics and debug
 503          * but probably by default we will mask these events.
 504          */
 505         if (mac_cstat & MAC_CSTAT_PS)
 506                 gp->pause_entered++;
 507 
 508         if (mac_cstat & MAC_CSTAT_PRCV)
 509                 gp->pause_last_time_recvd = (mac_cstat >> 16);
 510 
 511         return 0;
 512 }
 513 
 514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 515 {
 516         u32 mif_status = readl(gp->regs + MIF_STATUS);
 517         u32 reg_val, changed_bits;
 518 
 519         reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
 520         changed_bits = (mif_status & MIF_STATUS_STAT);
 521 
 522         gem_handle_mif_event(gp, reg_val, changed_bits);
 523 
 524         return 0;
 525 }
 526 
 527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 528 {
 529         u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
 530 
 531         if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
 532             gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 533                 netdev_err(dev, "PCI error [%04x]", pci_estat);
 534 
 535                 if (pci_estat & GREG_PCIESTAT_BADACK)
 536                         pr_cont(" <No ACK64# during ABS64 cycle>");
 537                 if (pci_estat & GREG_PCIESTAT_DTRTO)
 538                         pr_cont(" <Delayed transaction timeout>");
 539                 if (pci_estat & GREG_PCIESTAT_OTHER)
 540                         pr_cont(" <other>");
 541                 pr_cont("\n");
 542         } else {
 543                 pci_estat |= GREG_PCIESTAT_OTHER;
 544                 netdev_err(dev, "PCI error\n");
 545         }
 546 
 547         if (pci_estat & GREG_PCIESTAT_OTHER) {
 548                 u16 pci_cfg_stat;
 549 
 550                 /* Interrogate PCI config space for the
 551                  * true cause.
 552                  */
 553                 pci_read_config_word(gp->pdev, PCI_STATUS,
 554                                      &pci_cfg_stat);
 555                 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
 556                            pci_cfg_stat);
 557                 if (pci_cfg_stat & PCI_STATUS_PARITY)
 558                         netdev_err(dev, "PCI parity error detected\n");
 559                 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
 560                         netdev_err(dev, "PCI target abort\n");
 561                 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
 562                         netdev_err(dev, "PCI master acks target abort\n");
 563                 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
 564                         netdev_err(dev, "PCI master abort\n");
 565                 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
 566                         netdev_err(dev, "PCI system error SERR#\n");
 567                 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
 568                         netdev_err(dev, "PCI parity error\n");
 569 
 570                 /* Write the error bits back to clear them. */
 571                 pci_cfg_stat &= (PCI_STATUS_PARITY |
 572                                  PCI_STATUS_SIG_TARGET_ABORT |
 573                                  PCI_STATUS_REC_TARGET_ABORT |
 574                                  PCI_STATUS_REC_MASTER_ABORT |
 575                                  PCI_STATUS_SIG_SYSTEM_ERROR |
 576                                  PCI_STATUS_DETECTED_PARITY);
 577                 pci_write_config_word(gp->pdev,
 578                                       PCI_STATUS, pci_cfg_stat);
 579         }
 580 
 581         /* For all PCI errors, we should reset the chip. */
 582         return 1;
 583 }
 584 
 585 /* All non-normal interrupt conditions get serviced here.
 586  * Returns non-zero if we should just exit the interrupt
 587  * handler right now (ie. if we reset the card which invalidates
 588  * all of the other original irq status bits).
 589  */
 590 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
 591 {
 592         if (gem_status & GREG_STAT_RXNOBUF) {
 593                 /* Frame arrived, no free RX buffers available. */
 594                 if (netif_msg_rx_err(gp))
 595                         printk(KERN_DEBUG "%s: no buffer for rx frame\n",
 596                                 gp->dev->name);
 597                 dev->stats.rx_dropped++;
 598         }
 599 
 600         if (gem_status & GREG_STAT_RXTAGERR) {
 601                 /* corrupt RX tag framing */
 602                 if (netif_msg_rx_err(gp))
 603                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
 604                                 gp->dev->name);
 605                 dev->stats.rx_errors++;
 606 
 607                 return 1;
 608         }
 609 
 610         if (gem_status & GREG_STAT_PCS) {
 611                 if (gem_pcs_interrupt(dev, gp, gem_status))
 612                         return 1;
 613         }
 614 
 615         if (gem_status & GREG_STAT_TXMAC) {
 616                 if (gem_txmac_interrupt(dev, gp, gem_status))
 617                         return 1;
 618         }
 619 
 620         if (gem_status & GREG_STAT_RXMAC) {
 621                 if (gem_rxmac_interrupt(dev, gp, gem_status))
 622                         return 1;
 623         }
 624 
 625         if (gem_status & GREG_STAT_MAC) {
 626                 if (gem_mac_interrupt(dev, gp, gem_status))
 627                         return 1;
 628         }
 629 
 630         if (gem_status & GREG_STAT_MIF) {
 631                 if (gem_mif_interrupt(dev, gp, gem_status))
 632                         return 1;
 633         }
 634 
 635         if (gem_status & GREG_STAT_PCIERR) {
 636                 if (gem_pci_interrupt(dev, gp, gem_status))
 637                         return 1;
 638         }
 639 
 640         return 0;
 641 }
 642 
 643 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
 644 {
 645         int entry, limit;
 646 
 647         entry = gp->tx_old;
 648         limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
 649         while (entry != limit) {
 650                 struct sk_buff *skb;
 651                 struct gem_txd *txd;
 652                 dma_addr_t dma_addr;
 653                 u32 dma_len;
 654                 int frag;
 655 
 656                 if (netif_msg_tx_done(gp))
 657                         printk(KERN_DEBUG "%s: tx done, slot %d\n",
 658                                 gp->dev->name, entry);
 659                 skb = gp->tx_skbs[entry];
 660                 if (skb_shinfo(skb)->nr_frags) {
 661                         int last = entry + skb_shinfo(skb)->nr_frags;
 662                         int walk = entry;
 663                         int incomplete = 0;
 664 
 665                         last &= (TX_RING_SIZE - 1);
 666                         for (;;) {
 667                                 walk = NEXT_TX(walk);
 668                                 if (walk == limit)
 669                                         incomplete = 1;
 670                                 if (walk == last)
 671                                         break;
 672                         }
 673                         if (incomplete)
 674                                 break;
 675                 }
 676                 gp->tx_skbs[entry] = NULL;
 677                 dev->stats.tx_bytes += skb->len;
 678 
 679                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
 680                         txd = &gp->init_block->txd[entry];
 681 
 682                         dma_addr = le64_to_cpu(txd->buffer);
 683                         dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
 684 
 685                         pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 686                         entry = NEXT_TX(entry);
 687                 }
 688 
 689                 dev->stats.tx_packets++;
 690                 dev_consume_skb_any(skb);
 691         }
 692         gp->tx_old = entry;
 693 
 694         /* Need to make the tx_old update visible to gem_start_xmit()
 695          * before checking for netif_queue_stopped().  Without the
 696          * memory barrier, there is a small possibility that gem_start_xmit()
 697          * will miss it and cause the queue to be stopped forever.
 698          */
 699         smp_mb();
 700 
 701         if (unlikely(netif_queue_stopped(dev) &&
 702                      TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
 703                 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 704 
 705                 __netif_tx_lock(txq, smp_processor_id());
 706                 if (netif_queue_stopped(dev) &&
 707                     TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
 708                         netif_wake_queue(dev);
 709                 __netif_tx_unlock(txq);
 710         }
 711 }
 712 
 713 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
 714 {
 715         int cluster_start, curr, count, kick;
 716 
 717         cluster_start = curr = (gp->rx_new & ~(4 - 1));
 718         count = 0;
 719         kick = -1;
 720         dma_wmb();
 721         while (curr != limit) {
 722                 curr = NEXT_RX(curr);
 723                 if (++count == 4) {
 724                         struct gem_rxd *rxd =
 725                                 &gp->init_block->rxd[cluster_start];
 726                         for (;;) {
 727                                 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 728                                 rxd++;
 729                                 cluster_start = NEXT_RX(cluster_start);
 730                                 if (cluster_start == curr)
 731                                         break;
 732                         }
 733                         kick = curr;
 734                         count = 0;
 735                 }
 736         }
 737         if (kick >= 0) {
 738                 mb();
 739                 writel(kick, gp->regs + RXDMA_KICK);
 740         }
 741 }
 742 
 743 #define ALIGNED_RX_SKB_ADDR(addr) \
 744         ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
 745 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
 746                                                 gfp_t gfp_flags)
 747 {
 748         struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
 749 
 750         if (likely(skb)) {
 751                 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
 752                 skb_reserve(skb, offset);
 753         }
 754         return skb;
 755 }
 756 
 757 static int gem_rx(struct gem *gp, int work_to_do)
 758 {
 759         struct net_device *dev = gp->dev;
 760         int entry, drops, work_done = 0;
 761         u32 done;
 762 
 763         if (netif_msg_rx_status(gp))
 764                 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
 765                         gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
 766 
 767         entry = gp->rx_new;
 768         drops = 0;
 769         done = readl(gp->regs + RXDMA_DONE);
 770         for (;;) {
 771                 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
 772                 struct sk_buff *skb;
 773                 u64 status = le64_to_cpu(rxd->status_word);
 774                 dma_addr_t dma_addr;
 775                 int len;
 776 
 777                 if ((status & RXDCTRL_OWN) != 0)
 778                         break;
 779 
 780                 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
 781                         break;
 782 
 783                 /* When writing back RX descriptor, GEM writes status
 784                  * then buffer address, possibly in separate transactions.
 785                  * If we don't wait for the chip to write both, we could
 786                  * post a new buffer to this descriptor then have GEM spam
 787                  * on the buffer address.  We sync on the RX completion
 788                  * register to prevent this from happening.
 789                  */
 790                 if (entry == done) {
 791                         done = readl(gp->regs + RXDMA_DONE);
 792                         if (entry == done)
 793                                 break;
 794                 }
 795 
 796                 /* We can now account for the work we're about to do */
 797                 work_done++;
 798 
 799                 skb = gp->rx_skbs[entry];
 800 
 801                 len = (status & RXDCTRL_BUFSZ) >> 16;
 802                 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
 803                         dev->stats.rx_errors++;
 804                         if (len < ETH_ZLEN)
 805                                 dev->stats.rx_length_errors++;
 806                         if (len & RXDCTRL_BAD)
 807                                 dev->stats.rx_crc_errors++;
 808 
 809                         /* We'll just return it to GEM. */
 810                 drop_it:
 811                         dev->stats.rx_dropped++;
 812                         goto next;
 813                 }
 814 
 815                 dma_addr = le64_to_cpu(rxd->buffer);
 816                 if (len > RX_COPY_THRESHOLD) {
 817                         struct sk_buff *new_skb;
 818 
 819                         new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
 820                         if (new_skb == NULL) {
 821                                 drops++;
 822                                 goto drop_it;
 823                         }
 824                         pci_unmap_page(gp->pdev, dma_addr,
 825                                        RX_BUF_ALLOC_SIZE(gp),
 826                                        PCI_DMA_FROMDEVICE);
 827                         gp->rx_skbs[entry] = new_skb;
 828                         skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
 829                         rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
 830                                                                virt_to_page(new_skb->data),
 831                                                                offset_in_page(new_skb->data),
 832                                                                RX_BUF_ALLOC_SIZE(gp),
 833                                                                PCI_DMA_FROMDEVICE));
 834                         skb_reserve(new_skb, RX_OFFSET);
 835 
 836                         /* Trim the original skb for the netif. */
 837                         skb_trim(skb, len);
 838                 } else {
 839                         struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
 840 
 841                         if (copy_skb == NULL) {
 842                                 drops++;
 843                                 goto drop_it;
 844                         }
 845 
 846                         skb_reserve(copy_skb, 2);
 847                         skb_put(copy_skb, len);
 848                         pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
 849                         skb_copy_from_linear_data(skb, copy_skb->data, len);
 850                         pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
 851 
 852                         /* We'll reuse the original ring buffer. */
 853                         skb = copy_skb;
 854                 }
 855 
 856                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 857                         __sum16 csum;
 858 
 859                         csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
 860                         skb->csum = csum_unfold(csum);
 861                         skb->ip_summed = CHECKSUM_COMPLETE;
 862                 }
 863                 skb->protocol = eth_type_trans(skb, gp->dev);
 864 
 865                 napi_gro_receive(&gp->napi, skb);
 866 
 867                 dev->stats.rx_packets++;
 868                 dev->stats.rx_bytes += len;
 869 
 870         next:
 871                 entry = NEXT_RX(entry);
 872         }
 873 
 874         gem_post_rxds(gp, entry);
 875 
 876         gp->rx_new = entry;
 877 
 878         if (drops)
 879                 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
 880 
 881         return work_done;
 882 }
 883 
 884 static int gem_poll(struct napi_struct *napi, int budget)
 885 {
 886         struct gem *gp = container_of(napi, struct gem, napi);
 887         struct net_device *dev = gp->dev;
 888         int work_done;
 889 
 890         work_done = 0;
 891         do {
 892                 /* Handle anomalies */
 893                 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
 894                         struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 895                         int reset;
 896 
 897                         /* We run the abnormal interrupt handling code with
 898                          * the Tx lock. It only resets the Rx portion of the
 899                          * chip, but we need to guard it against DMA being
 900                          * restarted by the link poll timer
 901                          */
 902                         __netif_tx_lock(txq, smp_processor_id());
 903                         reset = gem_abnormal_irq(dev, gp, gp->status);
 904                         __netif_tx_unlock(txq);
 905                         if (reset) {
 906                                 gem_schedule_reset(gp);
 907                                 napi_complete(napi);
 908                                 return work_done;
 909                         }
 910                 }
 911 
 912                 /* Run TX completion thread */
 913                 gem_tx(dev, gp, gp->status);
 914 
 915                 /* Run RX thread. We don't use any locking here,
 916                  * code willing to do bad things - like cleaning the
 917                  * rx ring - must call napi_disable(), which
 918                  * schedule_timeout()'s if polling is already disabled.
 919                  */
 920                 work_done += gem_rx(gp, budget - work_done);
 921 
 922                 if (work_done >= budget)
 923                         return work_done;
 924 
 925                 gp->status = readl(gp->regs + GREG_STAT);
 926         } while (gp->status & GREG_STAT_NAPI);
 927 
 928         napi_complete_done(napi, work_done);
 929         gem_enable_ints(gp);
 930 
 931         return work_done;
 932 }
 933 
 934 static irqreturn_t gem_interrupt(int irq, void *dev_id)
 935 {
 936         struct net_device *dev = dev_id;
 937         struct gem *gp = netdev_priv(dev);
 938 
 939         if (napi_schedule_prep(&gp->napi)) {
 940                 u32 gem_status = readl(gp->regs + GREG_STAT);
 941 
 942                 if (unlikely(gem_status == 0)) {
 943                         napi_enable(&gp->napi);
 944                         return IRQ_NONE;
 945                 }
 946                 if (netif_msg_intr(gp))
 947                         printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
 948                                gp->dev->name, gem_status);
 949 
 950                 gp->status = gem_status;
 951                 gem_disable_ints(gp);
 952                 __napi_schedule(&gp->napi);
 953         }
 954 
 955         /* If polling was disabled at the time we received that
 956          * interrupt, we may return IRQ_HANDLED here while we
 957          * should return IRQ_NONE. No big deal...
 958          */
 959         return IRQ_HANDLED;
 960 }
 961 
 962 #ifdef CONFIG_NET_POLL_CONTROLLER
 963 static void gem_poll_controller(struct net_device *dev)
 964 {
 965         struct gem *gp = netdev_priv(dev);
 966 
 967         disable_irq(gp->pdev->irq);
 968         gem_interrupt(gp->pdev->irq, dev);
 969         enable_irq(gp->pdev->irq);
 970 }
 971 #endif
 972 
 973 static void gem_tx_timeout(struct net_device *dev)
 974 {
 975         struct gem *gp = netdev_priv(dev);
 976 
 977         netdev_err(dev, "transmit timed out, resetting\n");
 978 
 979         netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
 980                    readl(gp->regs + TXDMA_CFG),
 981                    readl(gp->regs + MAC_TXSTAT),
 982                    readl(gp->regs + MAC_TXCFG));
 983         netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
 984                    readl(gp->regs + RXDMA_CFG),
 985                    readl(gp->regs + MAC_RXSTAT),
 986                    readl(gp->regs + MAC_RXCFG));
 987 
 988         gem_schedule_reset(gp);
 989 }
 990 
 991 static __inline__ int gem_intme(int entry)
 992 {
 993         /* Algorithm: IRQ every 1/2 of descriptors. */
 994         if (!(entry & ((TX_RING_SIZE>>1)-1)))
 995                 return 1;
 996 
 997         return 0;
 998 }
 999 
1000 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
1001                                   struct net_device *dev)
1002 {
1003         struct gem *gp = netdev_priv(dev);
1004         int entry;
1005         u64 ctrl;
1006 
1007         ctrl = 0;
1008         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1009                 const u64 csum_start_off = skb_checksum_start_offset(skb);
1010                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1011 
1012                 ctrl = (TXDCTRL_CENAB |
1013                         (csum_start_off << 15) |
1014                         (csum_stuff_off << 21));
1015         }
1016 
1017         if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1018                 /* This is a hard error, log it. */
1019                 if (!netif_queue_stopped(dev)) {
1020                         netif_stop_queue(dev);
1021                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1022                 }
1023                 return NETDEV_TX_BUSY;
1024         }
1025 
1026         entry = gp->tx_new;
1027         gp->tx_skbs[entry] = skb;
1028 
1029         if (skb_shinfo(skb)->nr_frags == 0) {
1030                 struct gem_txd *txd = &gp->init_block->txd[entry];
1031                 dma_addr_t mapping;
1032                 u32 len;
1033 
1034                 len = skb->len;
1035                 mapping = pci_map_page(gp->pdev,
1036                                        virt_to_page(skb->data),
1037                                        offset_in_page(skb->data),
1038                                        len, PCI_DMA_TODEVICE);
1039                 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1040                 if (gem_intme(entry))
1041                         ctrl |= TXDCTRL_INTME;
1042                 txd->buffer = cpu_to_le64(mapping);
1043                 dma_wmb();
1044                 txd->control_word = cpu_to_le64(ctrl);
1045                 entry = NEXT_TX(entry);
1046         } else {
1047                 struct gem_txd *txd;
1048                 u32 first_len;
1049                 u64 intme;
1050                 dma_addr_t first_mapping;
1051                 int frag, first_entry = entry;
1052 
1053                 intme = 0;
1054                 if (gem_intme(entry))
1055                         intme |= TXDCTRL_INTME;
1056 
1057                 /* We must give this initial chunk to the device last.
1058                  * Otherwise we could race with the device.
1059                  */
1060                 first_len = skb_headlen(skb);
1061                 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1062                                              offset_in_page(skb->data),
1063                                              first_len, PCI_DMA_TODEVICE);
1064                 entry = NEXT_TX(entry);
1065 
1066                 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1067                         const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1068                         u32 len;
1069                         dma_addr_t mapping;
1070                         u64 this_ctrl;
1071 
1072                         len = skb_frag_size(this_frag);
1073                         mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1074                                                    0, len, DMA_TO_DEVICE);
1075                         this_ctrl = ctrl;
1076                         if (frag == skb_shinfo(skb)->nr_frags - 1)
1077                                 this_ctrl |= TXDCTRL_EOF;
1078 
1079                         txd = &gp->init_block->txd[entry];
1080                         txd->buffer = cpu_to_le64(mapping);
1081                         dma_wmb();
1082                         txd->control_word = cpu_to_le64(this_ctrl | len);
1083 
1084                         if (gem_intme(entry))
1085                                 intme |= TXDCTRL_INTME;
1086 
1087                         entry = NEXT_TX(entry);
1088                 }
1089                 txd = &gp->init_block->txd[first_entry];
1090                 txd->buffer = cpu_to_le64(first_mapping);
1091                 dma_wmb();
1092                 txd->control_word =
1093                         cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1094         }
1095 
1096         gp->tx_new = entry;
1097         if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1098                 netif_stop_queue(dev);
1099 
1100                 /* netif_stop_queue() must be done before checking
1101                  * checking tx index in TX_BUFFS_AVAIL() below, because
1102                  * in gem_tx(), we update tx_old before checking for
1103                  * netif_queue_stopped().
1104                  */
1105                 smp_mb();
1106                 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1107                         netif_wake_queue(dev);
1108         }
1109         if (netif_msg_tx_queued(gp))
1110                 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1111                        dev->name, entry, skb->len);
1112         mb();
1113         writel(gp->tx_new, gp->regs + TXDMA_KICK);
1114 
1115         return NETDEV_TX_OK;
1116 }
1117 
1118 static void gem_pcs_reset(struct gem *gp)
1119 {
1120         int limit;
1121         u32 val;
1122 
1123         /* Reset PCS unit. */
1124         val = readl(gp->regs + PCS_MIICTRL);
1125         val |= PCS_MIICTRL_RST;
1126         writel(val, gp->regs + PCS_MIICTRL);
1127 
1128         limit = 32;
1129         while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1130                 udelay(100);
1131                 if (limit-- <= 0)
1132                         break;
1133         }
1134         if (limit < 0)
1135                 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1136 }
1137 
1138 static void gem_pcs_reinit_adv(struct gem *gp)
1139 {
1140         u32 val;
1141 
1142         /* Make sure PCS is disabled while changing advertisement
1143          * configuration.
1144          */
1145         val = readl(gp->regs + PCS_CFG);
1146         val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1147         writel(val, gp->regs + PCS_CFG);
1148 
1149         /* Advertise all capabilities except asymmetric
1150          * pause.
1151          */
1152         val = readl(gp->regs + PCS_MIIADV);
1153         val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1154                 PCS_MIIADV_SP | PCS_MIIADV_AP);
1155         writel(val, gp->regs + PCS_MIIADV);
1156 
1157         /* Enable and restart auto-negotiation, disable wrapback/loopback,
1158          * and re-enable PCS.
1159          */
1160         val = readl(gp->regs + PCS_MIICTRL);
1161         val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1162         val &= ~PCS_MIICTRL_WB;
1163         writel(val, gp->regs + PCS_MIICTRL);
1164 
1165         val = readl(gp->regs + PCS_CFG);
1166         val |= PCS_CFG_ENABLE;
1167         writel(val, gp->regs + PCS_CFG);
1168 
1169         /* Make sure serialink loopback is off.  The meaning
1170          * of this bit is logically inverted based upon whether
1171          * you are in Serialink or SERDES mode.
1172          */
1173         val = readl(gp->regs + PCS_SCTRL);
1174         if (gp->phy_type == phy_serialink)
1175                 val &= ~PCS_SCTRL_LOOP;
1176         else
1177                 val |= PCS_SCTRL_LOOP;
1178         writel(val, gp->regs + PCS_SCTRL);
1179 }
1180 
1181 #define STOP_TRIES 32
1182 
1183 static void gem_reset(struct gem *gp)
1184 {
1185         int limit;
1186         u32 val;
1187 
1188         /* Make sure we won't get any more interrupts */
1189         writel(0xffffffff, gp->regs + GREG_IMASK);
1190 
1191         /* Reset the chip */
1192         writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1193                gp->regs + GREG_SWRST);
1194 
1195         limit = STOP_TRIES;
1196 
1197         do {
1198                 udelay(20);
1199                 val = readl(gp->regs + GREG_SWRST);
1200                 if (limit-- <= 0)
1201                         break;
1202         } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1203 
1204         if (limit < 0)
1205                 netdev_err(gp->dev, "SW reset is ghetto\n");
1206 
1207         if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1208                 gem_pcs_reinit_adv(gp);
1209 }
1210 
1211 static void gem_start_dma(struct gem *gp)
1212 {
1213         u32 val;
1214 
1215         /* We are ready to rock, turn everything on. */
1216         val = readl(gp->regs + TXDMA_CFG);
1217         writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1218         val = readl(gp->regs + RXDMA_CFG);
1219         writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1220         val = readl(gp->regs + MAC_TXCFG);
1221         writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1222         val = readl(gp->regs + MAC_RXCFG);
1223         writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1224 
1225         (void) readl(gp->regs + MAC_RXCFG);
1226         udelay(100);
1227 
1228         gem_enable_ints(gp);
1229 
1230         writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1231 }
1232 
1233 /* DMA won't be actually stopped before about 4ms tho ...
1234  */
1235 static void gem_stop_dma(struct gem *gp)
1236 {
1237         u32 val;
1238 
1239         /* We are done rocking, turn everything off. */
1240         val = readl(gp->regs + TXDMA_CFG);
1241         writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1242         val = readl(gp->regs + RXDMA_CFG);
1243         writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1244         val = readl(gp->regs + MAC_TXCFG);
1245         writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1246         val = readl(gp->regs + MAC_RXCFG);
1247         writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1248 
1249         (void) readl(gp->regs + MAC_RXCFG);
1250 
1251         /* Need to wait a bit ... done by the caller */
1252 }
1253 
1254 
1255 // XXX dbl check what that function should do when called on PCS PHY
1256 static void gem_begin_auto_negotiation(struct gem *gp,
1257                                        const struct ethtool_link_ksettings *ep)
1258 {
1259         u32 advertise, features;
1260         int autoneg;
1261         int speed;
1262         int duplex;
1263         u32 advertising;
1264 
1265         if (ep)
1266                 ethtool_convert_link_mode_to_legacy_u32(
1267                         &advertising, ep->link_modes.advertising);
1268 
1269         if (gp->phy_type != phy_mii_mdio0 &&
1270             gp->phy_type != phy_mii_mdio1)
1271                 goto non_mii;
1272 
1273         /* Setup advertise */
1274         if (found_mii_phy(gp))
1275                 features = gp->phy_mii.def->features;
1276         else
1277                 features = 0;
1278 
1279         advertise = features & ADVERTISE_MASK;
1280         if (gp->phy_mii.advertising != 0)
1281                 advertise &= gp->phy_mii.advertising;
1282 
1283         autoneg = gp->want_autoneg;
1284         speed = gp->phy_mii.speed;
1285         duplex = gp->phy_mii.duplex;
1286 
1287         /* Setup link parameters */
1288         if (!ep)
1289                 goto start_aneg;
1290         if (ep->base.autoneg == AUTONEG_ENABLE) {
1291                 advertise = advertising;
1292                 autoneg = 1;
1293         } else {
1294                 autoneg = 0;
1295                 speed = ep->base.speed;
1296                 duplex = ep->base.duplex;
1297         }
1298 
1299 start_aneg:
1300         /* Sanitize settings based on PHY capabilities */
1301         if ((features & SUPPORTED_Autoneg) == 0)
1302                 autoneg = 0;
1303         if (speed == SPEED_1000 &&
1304             !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1305                 speed = SPEED_100;
1306         if (speed == SPEED_100 &&
1307             !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1308                 speed = SPEED_10;
1309         if (duplex == DUPLEX_FULL &&
1310             !(features & (SUPPORTED_1000baseT_Full |
1311                           SUPPORTED_100baseT_Full |
1312                           SUPPORTED_10baseT_Full)))
1313                 duplex = DUPLEX_HALF;
1314         if (speed == 0)
1315                 speed = SPEED_10;
1316 
1317         /* If we are asleep, we don't try to actually setup the PHY, we
1318          * just store the settings
1319          */
1320         if (!netif_device_present(gp->dev)) {
1321                 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1322                 gp->phy_mii.speed = speed;
1323                 gp->phy_mii.duplex = duplex;
1324                 return;
1325         }
1326 
1327         /* Configure PHY & start aneg */
1328         gp->want_autoneg = autoneg;
1329         if (autoneg) {
1330                 if (found_mii_phy(gp))
1331                         gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1332                 gp->lstate = link_aneg;
1333         } else {
1334                 if (found_mii_phy(gp))
1335                         gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1336                 gp->lstate = link_force_ok;
1337         }
1338 
1339 non_mii:
1340         gp->timer_ticks = 0;
1341         mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1342 }
1343 
1344 /* A link-up condition has occurred, initialize and enable the
1345  * rest of the chip.
1346  */
1347 static int gem_set_link_modes(struct gem *gp)
1348 {
1349         struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1350         int full_duplex, speed, pause;
1351         u32 val;
1352 
1353         full_duplex = 0;
1354         speed = SPEED_10;
1355         pause = 0;
1356 
1357         if (found_mii_phy(gp)) {
1358                 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1359                         return 1;
1360                 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1361                 speed = gp->phy_mii.speed;
1362                 pause = gp->phy_mii.pause;
1363         } else if (gp->phy_type == phy_serialink ||
1364                    gp->phy_type == phy_serdes) {
1365                 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1366 
1367                 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1368                         full_duplex = 1;
1369                 speed = SPEED_1000;
1370         }
1371 
1372         netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1373                    speed, (full_duplex ? "full" : "half"));
1374 
1375 
1376         /* We take the tx queue lock to avoid collisions between
1377          * this code, the tx path and the NAPI-driven error path
1378          */
1379         __netif_tx_lock(txq, smp_processor_id());
1380 
1381         val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1382         if (full_duplex) {
1383                 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1384         } else {
1385                 /* MAC_TXCFG_NBO must be zero. */
1386         }
1387         writel(val, gp->regs + MAC_TXCFG);
1388 
1389         val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1390         if (!full_duplex &&
1391             (gp->phy_type == phy_mii_mdio0 ||
1392              gp->phy_type == phy_mii_mdio1)) {
1393                 val |= MAC_XIFCFG_DISE;
1394         } else if (full_duplex) {
1395                 val |= MAC_XIFCFG_FLED;
1396         }
1397 
1398         if (speed == SPEED_1000)
1399                 val |= (MAC_XIFCFG_GMII);
1400 
1401         writel(val, gp->regs + MAC_XIFCFG);
1402 
1403         /* If gigabit and half-duplex, enable carrier extension
1404          * mode.  Else, disable it.
1405          */
1406         if (speed == SPEED_1000 && !full_duplex) {
1407                 val = readl(gp->regs + MAC_TXCFG);
1408                 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1409 
1410                 val = readl(gp->regs + MAC_RXCFG);
1411                 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1412         } else {
1413                 val = readl(gp->regs + MAC_TXCFG);
1414                 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1415 
1416                 val = readl(gp->regs + MAC_RXCFG);
1417                 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1418         }
1419 
1420         if (gp->phy_type == phy_serialink ||
1421             gp->phy_type == phy_serdes) {
1422                 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1423 
1424                 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1425                         pause = 1;
1426         }
1427 
1428         if (!full_duplex)
1429                 writel(512, gp->regs + MAC_STIME);
1430         else
1431                 writel(64, gp->regs + MAC_STIME);
1432         val = readl(gp->regs + MAC_MCCFG);
1433         if (pause)
1434                 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1435         else
1436                 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1437         writel(val, gp->regs + MAC_MCCFG);
1438 
1439         gem_start_dma(gp);
1440 
1441         __netif_tx_unlock(txq);
1442 
1443         if (netif_msg_link(gp)) {
1444                 if (pause) {
1445                         netdev_info(gp->dev,
1446                                     "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1447                                     gp->rx_fifo_sz,
1448                                     gp->rx_pause_off,
1449                                     gp->rx_pause_on);
1450                 } else {
1451                         netdev_info(gp->dev, "Pause is disabled\n");
1452                 }
1453         }
1454 
1455         return 0;
1456 }
1457 
1458 static int gem_mdio_link_not_up(struct gem *gp)
1459 {
1460         switch (gp->lstate) {
1461         case link_force_ret:
1462                 netif_info(gp, link, gp->dev,
1463                            "Autoneg failed again, keeping forced mode\n");
1464                 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1465                         gp->last_forced_speed, DUPLEX_HALF);
1466                 gp->timer_ticks = 5;
1467                 gp->lstate = link_force_ok;
1468                 return 0;
1469         case link_aneg:
1470                 /* We try forced modes after a failed aneg only on PHYs that don't
1471                  * have "magic_aneg" bit set, which means they internally do the
1472                  * while forced-mode thingy. On these, we just restart aneg
1473                  */
1474                 if (gp->phy_mii.def->magic_aneg)
1475                         return 1;
1476                 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1477                 /* Try forced modes. */
1478                 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1479                         DUPLEX_HALF);
1480                 gp->timer_ticks = 5;
1481                 gp->lstate = link_force_try;
1482                 return 0;
1483         case link_force_try:
1484                 /* Downgrade from 100 to 10 Mbps if necessary.
1485                  * If already at 10Mbps, warn user about the
1486                  * situation every 10 ticks.
1487                  */
1488                 if (gp->phy_mii.speed == SPEED_100) {
1489                         gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1490                                 DUPLEX_HALF);
1491                         gp->timer_ticks = 5;
1492                         netif_info(gp, link, gp->dev,
1493                                    "switching to forced 10bt\n");
1494                         return 0;
1495                 } else
1496                         return 1;
1497         default:
1498                 return 0;
1499         }
1500 }
1501 
1502 static void gem_link_timer(struct timer_list *t)
1503 {
1504         struct gem *gp = from_timer(gp, t, link_timer);
1505         struct net_device *dev = gp->dev;
1506         int restart_aneg = 0;
1507 
1508         /* There's no point doing anything if we're going to be reset */
1509         if (gp->reset_task_pending)
1510                 return;
1511 
1512         if (gp->phy_type == phy_serialink ||
1513             gp->phy_type == phy_serdes) {
1514                 u32 val = readl(gp->regs + PCS_MIISTAT);
1515 
1516                 if (!(val & PCS_MIISTAT_LS))
1517                         val = readl(gp->regs + PCS_MIISTAT);
1518 
1519                 if ((val & PCS_MIISTAT_LS) != 0) {
1520                         if (gp->lstate == link_up)
1521                                 goto restart;
1522 
1523                         gp->lstate = link_up;
1524                         netif_carrier_on(dev);
1525                         (void)gem_set_link_modes(gp);
1526                 }
1527                 goto restart;
1528         }
1529         if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1530                 /* Ok, here we got a link. If we had it due to a forced
1531                  * fallback, and we were configured for autoneg, we do
1532                  * retry a short autoneg pass. If you know your hub is
1533                  * broken, use ethtool ;)
1534                  */
1535                 if (gp->lstate == link_force_try && gp->want_autoneg) {
1536                         gp->lstate = link_force_ret;
1537                         gp->last_forced_speed = gp->phy_mii.speed;
1538                         gp->timer_ticks = 5;
1539                         if (netif_msg_link(gp))
1540                                 netdev_info(dev,
1541                                             "Got link after fallback, retrying autoneg once...\n");
1542                         gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1543                 } else if (gp->lstate != link_up) {
1544                         gp->lstate = link_up;
1545                         netif_carrier_on(dev);
1546                         if (gem_set_link_modes(gp))
1547                                 restart_aneg = 1;
1548                 }
1549         } else {
1550                 /* If the link was previously up, we restart the
1551                  * whole process
1552                  */
1553                 if (gp->lstate == link_up) {
1554                         gp->lstate = link_down;
1555                         netif_info(gp, link, dev, "Link down\n");
1556                         netif_carrier_off(dev);
1557                         gem_schedule_reset(gp);
1558                         /* The reset task will restart the timer */
1559                         return;
1560                 } else if (++gp->timer_ticks > 10) {
1561                         if (found_mii_phy(gp))
1562                                 restart_aneg = gem_mdio_link_not_up(gp);
1563                         else
1564                                 restart_aneg = 1;
1565                 }
1566         }
1567         if (restart_aneg) {
1568                 gem_begin_auto_negotiation(gp, NULL);
1569                 return;
1570         }
1571 restart:
1572         mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1573 }
1574 
1575 static void gem_clean_rings(struct gem *gp)
1576 {
1577         struct gem_init_block *gb = gp->init_block;
1578         struct sk_buff *skb;
1579         int i;
1580         dma_addr_t dma_addr;
1581 
1582         for (i = 0; i < RX_RING_SIZE; i++) {
1583                 struct gem_rxd *rxd;
1584 
1585                 rxd = &gb->rxd[i];
1586                 if (gp->rx_skbs[i] != NULL) {
1587                         skb = gp->rx_skbs[i];
1588                         dma_addr = le64_to_cpu(rxd->buffer);
1589                         pci_unmap_page(gp->pdev, dma_addr,
1590                                        RX_BUF_ALLOC_SIZE(gp),
1591                                        PCI_DMA_FROMDEVICE);
1592                         dev_kfree_skb_any(skb);
1593                         gp->rx_skbs[i] = NULL;
1594                 }
1595                 rxd->status_word = 0;
1596                 dma_wmb();
1597                 rxd->buffer = 0;
1598         }
1599 
1600         for (i = 0; i < TX_RING_SIZE; i++) {
1601                 if (gp->tx_skbs[i] != NULL) {
1602                         struct gem_txd *txd;
1603                         int frag;
1604 
1605                         skb = gp->tx_skbs[i];
1606                         gp->tx_skbs[i] = NULL;
1607 
1608                         for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1609                                 int ent = i & (TX_RING_SIZE - 1);
1610 
1611                                 txd = &gb->txd[ent];
1612                                 dma_addr = le64_to_cpu(txd->buffer);
1613                                 pci_unmap_page(gp->pdev, dma_addr,
1614                                                le64_to_cpu(txd->control_word) &
1615                                                TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1616 
1617                                 if (frag != skb_shinfo(skb)->nr_frags)
1618                                         i++;
1619                         }
1620                         dev_kfree_skb_any(skb);
1621                 }
1622         }
1623 }
1624 
1625 static void gem_init_rings(struct gem *gp)
1626 {
1627         struct gem_init_block *gb = gp->init_block;
1628         struct net_device *dev = gp->dev;
1629         int i;
1630         dma_addr_t dma_addr;
1631 
1632         gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1633 
1634         gem_clean_rings(gp);
1635 
1636         gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1637                             (unsigned)VLAN_ETH_FRAME_LEN);
1638 
1639         for (i = 0; i < RX_RING_SIZE; i++) {
1640                 struct sk_buff *skb;
1641                 struct gem_rxd *rxd = &gb->rxd[i];
1642 
1643                 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1644                 if (!skb) {
1645                         rxd->buffer = 0;
1646                         rxd->status_word = 0;
1647                         continue;
1648                 }
1649 
1650                 gp->rx_skbs[i] = skb;
1651                 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1652                 dma_addr = pci_map_page(gp->pdev,
1653                                         virt_to_page(skb->data),
1654                                         offset_in_page(skb->data),
1655                                         RX_BUF_ALLOC_SIZE(gp),
1656                                         PCI_DMA_FROMDEVICE);
1657                 rxd->buffer = cpu_to_le64(dma_addr);
1658                 dma_wmb();
1659                 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1660                 skb_reserve(skb, RX_OFFSET);
1661         }
1662 
1663         for (i = 0; i < TX_RING_SIZE; i++) {
1664                 struct gem_txd *txd = &gb->txd[i];
1665 
1666                 txd->control_word = 0;
1667                 dma_wmb();
1668                 txd->buffer = 0;
1669         }
1670         wmb();
1671 }
1672 
1673 /* Init PHY interface and start link poll state machine */
1674 static void gem_init_phy(struct gem *gp)
1675 {
1676         u32 mifcfg;
1677 
1678         /* Revert MIF CFG setting done on stop_phy */
1679         mifcfg = readl(gp->regs + MIF_CFG);
1680         mifcfg &= ~MIF_CFG_BBMODE;
1681         writel(mifcfg, gp->regs + MIF_CFG);
1682 
1683         if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1684                 int i;
1685 
1686                 /* Those delay sucks, the HW seem to love them though, I'll
1687                  * serisouly consider breaking some locks here to be able
1688                  * to schedule instead
1689                  */
1690                 for (i = 0; i < 3; i++) {
1691 #ifdef CONFIG_PPC_PMAC
1692                         pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1693                         msleep(20);
1694 #endif
1695                         /* Some PHYs used by apple have problem getting back to us,
1696                          * we do an additional reset here
1697                          */
1698                         sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1699                         msleep(20);
1700                         if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1701                                 break;
1702                         if (i == 2)
1703                                 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1704                 }
1705         }
1706 
1707         if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1708             gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1709                 u32 val;
1710 
1711                 /* Init datapath mode register. */
1712                 if (gp->phy_type == phy_mii_mdio0 ||
1713                     gp->phy_type == phy_mii_mdio1) {
1714                         val = PCS_DMODE_MGM;
1715                 } else if (gp->phy_type == phy_serialink) {
1716                         val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1717                 } else {
1718                         val = PCS_DMODE_ESM;
1719                 }
1720 
1721                 writel(val, gp->regs + PCS_DMODE);
1722         }
1723 
1724         if (gp->phy_type == phy_mii_mdio0 ||
1725             gp->phy_type == phy_mii_mdio1) {
1726                 /* Reset and detect MII PHY */
1727                 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1728 
1729                 /* Init PHY */
1730                 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1731                         gp->phy_mii.def->ops->init(&gp->phy_mii);
1732         } else {
1733                 gem_pcs_reset(gp);
1734                 gem_pcs_reinit_adv(gp);
1735         }
1736 
1737         /* Default aneg parameters */
1738         gp->timer_ticks = 0;
1739         gp->lstate = link_down;
1740         netif_carrier_off(gp->dev);
1741 
1742         /* Print things out */
1743         if (gp->phy_type == phy_mii_mdio0 ||
1744             gp->phy_type == phy_mii_mdio1)
1745                 netdev_info(gp->dev, "Found %s PHY\n",
1746                             gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1747 
1748         gem_begin_auto_negotiation(gp, NULL);
1749 }
1750 
1751 static void gem_init_dma(struct gem *gp)
1752 {
1753         u64 desc_dma = (u64) gp->gblock_dvma;
1754         u32 val;
1755 
1756         val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1757         writel(val, gp->regs + TXDMA_CFG);
1758 
1759         writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1760         writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1761         desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1762 
1763         writel(0, gp->regs + TXDMA_KICK);
1764 
1765         val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1766                (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
1767         writel(val, gp->regs + RXDMA_CFG);
1768 
1769         writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1770         writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1771 
1772         writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1773 
1774         val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1775         val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1776         writel(val, gp->regs + RXDMA_PTHRESH);
1777 
1778         if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1779                 writel(((5 & RXDMA_BLANK_IPKTS) |
1780                         ((8 << 12) & RXDMA_BLANK_ITIME)),
1781                        gp->regs + RXDMA_BLANK);
1782         else
1783                 writel(((5 & RXDMA_BLANK_IPKTS) |
1784                         ((4 << 12) & RXDMA_BLANK_ITIME)),
1785                        gp->regs + RXDMA_BLANK);
1786 }
1787 
1788 static u32 gem_setup_multicast(struct gem *gp)
1789 {
1790         u32 rxcfg = 0;
1791         int i;
1792 
1793         if ((gp->dev->flags & IFF_ALLMULTI) ||
1794             (netdev_mc_count(gp->dev) > 256)) {
1795                 for (i=0; i<16; i++)
1796                         writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1797                 rxcfg |= MAC_RXCFG_HFE;
1798         } else if (gp->dev->flags & IFF_PROMISC) {
1799                 rxcfg |= MAC_RXCFG_PROM;
1800         } else {
1801                 u16 hash_table[16];
1802                 u32 crc;
1803                 struct netdev_hw_addr *ha;
1804                 int i;
1805 
1806                 memset(hash_table, 0, sizeof(hash_table));
1807                 netdev_for_each_mc_addr(ha, gp->dev) {
1808                         crc = ether_crc_le(6, ha->addr);
1809                         crc >>= 24;
1810                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1811                 }
1812                 for (i=0; i<16; i++)
1813                         writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1814                 rxcfg |= MAC_RXCFG_HFE;
1815         }
1816 
1817         return rxcfg;
1818 }
1819 
1820 static void gem_init_mac(struct gem *gp)
1821 {
1822         unsigned char *e = &gp->dev->dev_addr[0];
1823 
1824         writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1825 
1826         writel(0x00, gp->regs + MAC_IPG0);
1827         writel(0x08, gp->regs + MAC_IPG1);
1828         writel(0x04, gp->regs + MAC_IPG2);
1829         writel(0x40, gp->regs + MAC_STIME);
1830         writel(0x40, gp->regs + MAC_MINFSZ);
1831 
1832         /* Ethernet payload + header + FCS + optional VLAN tag. */
1833         writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1834 
1835         writel(0x07, gp->regs + MAC_PASIZE);
1836         writel(0x04, gp->regs + MAC_JAMSIZE);
1837         writel(0x10, gp->regs + MAC_ATTLIM);
1838         writel(0x8808, gp->regs + MAC_MCTYPE);
1839 
1840         writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1841 
1842         writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1843         writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1844         writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1845 
1846         writel(0, gp->regs + MAC_ADDR3);
1847         writel(0, gp->regs + MAC_ADDR4);
1848         writel(0, gp->regs + MAC_ADDR5);
1849 
1850         writel(0x0001, gp->regs + MAC_ADDR6);
1851         writel(0xc200, gp->regs + MAC_ADDR7);
1852         writel(0x0180, gp->regs + MAC_ADDR8);
1853 
1854         writel(0, gp->regs + MAC_AFILT0);
1855         writel(0, gp->regs + MAC_AFILT1);
1856         writel(0, gp->regs + MAC_AFILT2);
1857         writel(0, gp->regs + MAC_AF21MSK);
1858         writel(0, gp->regs + MAC_AF0MSK);
1859 
1860         gp->mac_rx_cfg = gem_setup_multicast(gp);
1861 #ifdef STRIP_FCS
1862         gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1863 #endif
1864         writel(0, gp->regs + MAC_NCOLL);
1865         writel(0, gp->regs + MAC_FASUCC);
1866         writel(0, gp->regs + MAC_ECOLL);
1867         writel(0, gp->regs + MAC_LCOLL);
1868         writel(0, gp->regs + MAC_DTIMER);
1869         writel(0, gp->regs + MAC_PATMPS);
1870         writel(0, gp->regs + MAC_RFCTR);
1871         writel(0, gp->regs + MAC_LERR);
1872         writel(0, gp->regs + MAC_AERR);
1873         writel(0, gp->regs + MAC_FCSERR);
1874         writel(0, gp->regs + MAC_RXCVERR);
1875 
1876         /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1877          * them once a link is established.
1878          */
1879         writel(0, gp->regs + MAC_TXCFG);
1880         writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1881         writel(0, gp->regs + MAC_MCCFG);
1882         writel(0, gp->regs + MAC_XIFCFG);
1883 
1884         /* Setup MAC interrupts.  We want to get all of the interesting
1885          * counter expiration events, but we do not want to hear about
1886          * normal rx/tx as the DMA engine tells us that.
1887          */
1888         writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1889         writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1890 
1891         /* Don't enable even the PAUSE interrupts for now, we
1892          * make no use of those events other than to record them.
1893          */
1894         writel(0xffffffff, gp->regs + MAC_MCMASK);
1895 
1896         /* Don't enable GEM's WOL in normal operations
1897          */
1898         if (gp->has_wol)
1899                 writel(0, gp->regs + WOL_WAKECSR);
1900 }
1901 
1902 static void gem_init_pause_thresholds(struct gem *gp)
1903 {
1904         u32 cfg;
1905 
1906         /* Calculate pause thresholds.  Setting the OFF threshold to the
1907          * full RX fifo size effectively disables PAUSE generation which
1908          * is what we do for 10/100 only GEMs which have FIFOs too small
1909          * to make real gains from PAUSE.
1910          */
1911         if (gp->rx_fifo_sz <= (2 * 1024)) {
1912                 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1913         } else {
1914                 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1915                 int off = (gp->rx_fifo_sz - (max_frame * 2));
1916                 int on = off - max_frame;
1917 
1918                 gp->rx_pause_off = off;
1919                 gp->rx_pause_on = on;
1920         }
1921 
1922 
1923         /* Configure the chip "burst" DMA mode & enable some
1924          * HW bug fixes on Apple version
1925          */
1926         cfg  = 0;
1927         if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1928                 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1929 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1930         cfg |= GREG_CFG_IBURST;
1931 #endif
1932         cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1933         cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1934         writel(cfg, gp->regs + GREG_CFG);
1935 
1936         /* If Infinite Burst didn't stick, then use different
1937          * thresholds (and Apple bug fixes don't exist)
1938          */
1939         if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1940                 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1941                 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1942                 writel(cfg, gp->regs + GREG_CFG);
1943         }
1944 }
1945 
1946 static int gem_check_invariants(struct gem *gp)
1947 {
1948         struct pci_dev *pdev = gp->pdev;
1949         u32 mif_cfg;
1950 
1951         /* On Apple's sungem, we can't rely on registers as the chip
1952          * was been powered down by the firmware. The PHY is looked
1953          * up later on.
1954          */
1955         if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1956                 gp->phy_type = phy_mii_mdio0;
1957                 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1958                 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1959                 gp->swrst_base = 0;
1960 
1961                 mif_cfg = readl(gp->regs + MIF_CFG);
1962                 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1963                 mif_cfg |= MIF_CFG_MDI0;
1964                 writel(mif_cfg, gp->regs + MIF_CFG);
1965                 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1966                 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1967 
1968                 /* We hard-code the PHY address so we can properly bring it out of
1969                  * reset later on, we can't really probe it at this point, though
1970                  * that isn't an issue.
1971                  */
1972                 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1973                         gp->mii_phy_addr = 1;
1974                 else
1975                         gp->mii_phy_addr = 0;
1976 
1977                 return 0;
1978         }
1979 
1980         mif_cfg = readl(gp->regs + MIF_CFG);
1981 
1982         if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1983             pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1984                 /* One of the MII PHYs _must_ be present
1985                  * as this chip has no gigabit PHY.
1986                  */
1987                 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1988                         pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1989                                mif_cfg);
1990                         return -1;
1991                 }
1992         }
1993 
1994         /* Determine initial PHY interface type guess.  MDIO1 is the
1995          * external PHY and thus takes precedence over MDIO0.
1996          */
1997 
1998         if (mif_cfg & MIF_CFG_MDI1) {
1999                 gp->phy_type = phy_mii_mdio1;
2000                 mif_cfg |= MIF_CFG_PSELECT;
2001                 writel(mif_cfg, gp->regs + MIF_CFG);
2002         } else if (mif_cfg & MIF_CFG_MDI0) {
2003                 gp->phy_type = phy_mii_mdio0;
2004                 mif_cfg &= ~MIF_CFG_PSELECT;
2005                 writel(mif_cfg, gp->regs + MIF_CFG);
2006         } else {
2007 #ifdef CONFIG_SPARC
2008                 const char *p;
2009 
2010                 p = of_get_property(gp->of_node, "shared-pins", NULL);
2011                 if (p && !strcmp(p, "serdes"))
2012                         gp->phy_type = phy_serdes;
2013                 else
2014 #endif
2015                         gp->phy_type = phy_serialink;
2016         }
2017         if (gp->phy_type == phy_mii_mdio1 ||
2018             gp->phy_type == phy_mii_mdio0) {
2019                 int i;
2020 
2021                 for (i = 0; i < 32; i++) {
2022                         gp->mii_phy_addr = i;
2023                         if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2024                                 break;
2025                 }
2026                 if (i == 32) {
2027                         if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2028                                 pr_err("RIO MII phy will not respond\n");
2029                                 return -1;
2030                         }
2031                         gp->phy_type = phy_serdes;
2032                 }
2033         }
2034 
2035         /* Fetch the FIFO configurations now too. */
2036         gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2037         gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2038 
2039         if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2040                 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2041                         if (gp->tx_fifo_sz != (9 * 1024) ||
2042                             gp->rx_fifo_sz != (20 * 1024)) {
2043                                 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2044                                        gp->tx_fifo_sz, gp->rx_fifo_sz);
2045                                 return -1;
2046                         }
2047                         gp->swrst_base = 0;
2048                 } else {
2049                         if (gp->tx_fifo_sz != (2 * 1024) ||
2050                             gp->rx_fifo_sz != (2 * 1024)) {
2051                                 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2052                                        gp->tx_fifo_sz, gp->rx_fifo_sz);
2053                                 return -1;
2054                         }
2055                         gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2056                 }
2057         }
2058 
2059         return 0;
2060 }
2061 
2062 static void gem_reinit_chip(struct gem *gp)
2063 {
2064         /* Reset the chip */
2065         gem_reset(gp);
2066 
2067         /* Make sure ints are disabled */
2068         gem_disable_ints(gp);
2069 
2070         /* Allocate & setup ring buffers */
2071         gem_init_rings(gp);
2072 
2073         /* Configure pause thresholds */
2074         gem_init_pause_thresholds(gp);
2075 
2076         /* Init DMA & MAC engines */
2077         gem_init_dma(gp);
2078         gem_init_mac(gp);
2079 }
2080 
2081 
2082 static void gem_stop_phy(struct gem *gp, int wol)
2083 {
2084         u32 mifcfg;
2085 
2086         /* Let the chip settle down a bit, it seems that helps
2087          * for sleep mode on some models
2088          */
2089         msleep(10);
2090 
2091         /* Make sure we aren't polling PHY status change. We
2092          * don't currently use that feature though
2093          */
2094         mifcfg = readl(gp->regs + MIF_CFG);
2095         mifcfg &= ~MIF_CFG_POLL;
2096         writel(mifcfg, gp->regs + MIF_CFG);
2097 
2098         if (wol && gp->has_wol) {
2099                 unsigned char *e = &gp->dev->dev_addr[0];
2100                 u32 csr;
2101 
2102                 /* Setup wake-on-lan for MAGIC packet */
2103                 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2104                        gp->regs + MAC_RXCFG);
2105                 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2106                 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2107                 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2108 
2109                 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2110                 csr = WOL_WAKECSR_ENABLE;
2111                 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2112                         csr |= WOL_WAKECSR_MII;
2113                 writel(csr, gp->regs + WOL_WAKECSR);
2114         } else {
2115                 writel(0, gp->regs + MAC_RXCFG);
2116                 (void)readl(gp->regs + MAC_RXCFG);
2117                 /* Machine sleep will die in strange ways if we
2118                  * dont wait a bit here, looks like the chip takes
2119                  * some time to really shut down
2120                  */
2121                 msleep(10);
2122         }
2123 
2124         writel(0, gp->regs + MAC_TXCFG);
2125         writel(0, gp->regs + MAC_XIFCFG);
2126         writel(0, gp->regs + TXDMA_CFG);
2127         writel(0, gp->regs + RXDMA_CFG);
2128 
2129         if (!wol) {
2130                 gem_reset(gp);
2131                 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2132                 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2133 
2134                 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2135                         gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2136 
2137                 /* According to Apple, we must set the MDIO pins to this begnign
2138                  * state or we may 1) eat more current, 2) damage some PHYs
2139                  */
2140                 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2141                 writel(0, gp->regs + MIF_BBCLK);
2142                 writel(0, gp->regs + MIF_BBDATA);
2143                 writel(0, gp->regs + MIF_BBOENAB);
2144                 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2145                 (void) readl(gp->regs + MAC_XIFCFG);
2146         }
2147 }
2148 
2149 static int gem_do_start(struct net_device *dev)
2150 {
2151         struct gem *gp = netdev_priv(dev);
2152         int rc;
2153 
2154         /* Enable the cell */
2155         gem_get_cell(gp);
2156 
2157         /* Make sure PCI access and bus master are enabled */
2158         rc = pci_enable_device(gp->pdev);
2159         if (rc) {
2160                 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2161 
2162                 /* Put cell and forget it for now, it will be considered as
2163                  * still asleep, a new sleep cycle may bring it back
2164                  */
2165                 gem_put_cell(gp);
2166                 return -ENXIO;
2167         }
2168         pci_set_master(gp->pdev);
2169 
2170         /* Init & setup chip hardware */
2171         gem_reinit_chip(gp);
2172 
2173         /* An interrupt might come in handy */
2174         rc = request_irq(gp->pdev->irq, gem_interrupt,
2175                          IRQF_SHARED, dev->name, (void *)dev);
2176         if (rc) {
2177                 netdev_err(dev, "failed to request irq !\n");
2178 
2179                 gem_reset(gp);
2180                 gem_clean_rings(gp);
2181                 gem_put_cell(gp);
2182                 return rc;
2183         }
2184 
2185         /* Mark us as attached again if we come from resume(), this has
2186          * no effect if we weren't detached and needs to be done now.
2187          */
2188         netif_device_attach(dev);
2189 
2190         /* Restart NAPI & queues */
2191         gem_netif_start(gp);
2192 
2193         /* Detect & init PHY, start autoneg etc... this will
2194          * eventually result in starting DMA operations when
2195          * the link is up
2196          */
2197         gem_init_phy(gp);
2198 
2199         return 0;
2200 }
2201 
2202 static void gem_do_stop(struct net_device *dev, int wol)
2203 {
2204         struct gem *gp = netdev_priv(dev);
2205 
2206         /* Stop NAPI and stop tx queue */
2207         gem_netif_stop(gp);
2208 
2209         /* Make sure ints are disabled. We don't care about
2210          * synchronizing as NAPI is disabled, thus a stray
2211          * interrupt will do nothing bad (our irq handler
2212          * just schedules NAPI)
2213          */
2214         gem_disable_ints(gp);
2215 
2216         /* Stop the link timer */
2217         del_timer_sync(&gp->link_timer);
2218 
2219         /* We cannot cancel the reset task while holding the
2220          * rtnl lock, we'd get an A->B / B->A deadlock stituation
2221          * if we did. This is not an issue however as the reset
2222          * task is synchronized vs. us (rtnl_lock) and will do
2223          * nothing if the device is down or suspended. We do
2224          * still clear reset_task_pending to avoid a spurrious
2225          * reset later on in case we do resume before it gets
2226          * scheduled.
2227          */
2228         gp->reset_task_pending = 0;
2229 
2230         /* If we are going to sleep with WOL */
2231         gem_stop_dma(gp);
2232         msleep(10);
2233         if (!wol)
2234                 gem_reset(gp);
2235         msleep(10);
2236 
2237         /* Get rid of rings */
2238         gem_clean_rings(gp);
2239 
2240         /* No irq needed anymore */
2241         free_irq(gp->pdev->irq, (void *) dev);
2242 
2243         /* Shut the PHY down eventually and setup WOL */
2244         gem_stop_phy(gp, wol);
2245 
2246         /* Make sure bus master is disabled */
2247         pci_disable_device(gp->pdev);
2248 
2249         /* Cell not needed neither if no WOL */
2250         if (!wol)
2251                 gem_put_cell(gp);
2252 }
2253 
2254 static void gem_reset_task(struct work_struct *work)
2255 {
2256         struct gem *gp = container_of(work, struct gem, reset_task);
2257 
2258         /* Lock out the network stack (essentially shield ourselves
2259          * against a racing open, close, control call, or suspend
2260          */
2261         rtnl_lock();
2262 
2263         /* Skip the reset task if suspended or closed, or if it's
2264          * been cancelled by gem_do_stop (see comment there)
2265          */
2266         if (!netif_device_present(gp->dev) ||
2267             !netif_running(gp->dev) ||
2268             !gp->reset_task_pending) {
2269                 rtnl_unlock();
2270                 return;
2271         }
2272 
2273         /* Stop the link timer */
2274         del_timer_sync(&gp->link_timer);
2275 
2276         /* Stop NAPI and tx */
2277         gem_netif_stop(gp);
2278 
2279         /* Reset the chip & rings */
2280         gem_reinit_chip(gp);
2281         if (gp->lstate == link_up)
2282                 gem_set_link_modes(gp);
2283 
2284         /* Restart NAPI and Tx */
2285         gem_netif_start(gp);
2286 
2287         /* We are back ! */
2288         gp->reset_task_pending = 0;
2289 
2290         /* If the link is not up, restart autoneg, else restart the
2291          * polling timer
2292          */
2293         if (gp->lstate != link_up)
2294                 gem_begin_auto_negotiation(gp, NULL);
2295         else
2296                 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2297 
2298         rtnl_unlock();
2299 }
2300 
2301 static int gem_open(struct net_device *dev)
2302 {
2303         /* We allow open while suspended, we just do nothing,
2304          * the chip will be initialized in resume()
2305          */
2306         if (netif_device_present(dev))
2307                 return gem_do_start(dev);
2308         return 0;
2309 }
2310 
2311 static int gem_close(struct net_device *dev)
2312 {
2313         if (netif_device_present(dev))
2314                 gem_do_stop(dev, 0);
2315 
2316         return 0;
2317 }
2318 
2319 #ifdef CONFIG_PM
2320 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2321 {
2322         struct net_device *dev = pci_get_drvdata(pdev);
2323         struct gem *gp = netdev_priv(dev);
2324 
2325         /* Lock the network stack first to avoid racing with open/close,
2326          * reset task and setting calls
2327          */
2328         rtnl_lock();
2329 
2330         /* Not running, mark ourselves non-present, no need for
2331          * a lock here
2332          */
2333         if (!netif_running(dev)) {
2334                 netif_device_detach(dev);
2335                 rtnl_unlock();
2336                 return 0;
2337         }
2338         netdev_info(dev, "suspending, WakeOnLan %s\n",
2339                     (gp->wake_on_lan && netif_running(dev)) ?
2340                     "enabled" : "disabled");
2341 
2342         /* Tell the network stack we're gone. gem_do_stop() below will
2343          * synchronize with TX, stop NAPI etc...
2344          */
2345         netif_device_detach(dev);
2346 
2347         /* Switch off chip, remember WOL setting */
2348         gp->asleep_wol = !!gp->wake_on_lan;
2349         gem_do_stop(dev, gp->asleep_wol);
2350 
2351         /* Unlock the network stack */
2352         rtnl_unlock();
2353 
2354         return 0;
2355 }
2356 
2357 static int gem_resume(struct pci_dev *pdev)
2358 {
2359         struct net_device *dev = pci_get_drvdata(pdev);
2360         struct gem *gp = netdev_priv(dev);
2361 
2362         /* See locking comment in gem_suspend */
2363         rtnl_lock();
2364 
2365         /* Not running, mark ourselves present, no need for
2366          * a lock here
2367          */
2368         if (!netif_running(dev)) {
2369                 netif_device_attach(dev);
2370                 rtnl_unlock();
2371                 return 0;
2372         }
2373 
2374         /* Restart chip. If that fails there isn't much we can do, we
2375          * leave things stopped.
2376          */
2377         gem_do_start(dev);
2378 
2379         /* If we had WOL enabled, the cell clock was never turned off during
2380          * sleep, so we end up beeing unbalanced. Fix that here
2381          */
2382         if (gp->asleep_wol)
2383                 gem_put_cell(gp);
2384 
2385         /* Unlock the network stack */
2386         rtnl_unlock();
2387 
2388         return 0;
2389 }
2390 #endif /* CONFIG_PM */
2391 
2392 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2393 {
2394         struct gem *gp = netdev_priv(dev);
2395 
2396         /* I have seen this being called while the PM was in progress,
2397          * so we shield against this. Let's also not poke at registers
2398          * while the reset task is going on.
2399          *
2400          * TODO: Move stats collection elsewhere (link timer ?) and
2401          * make this a nop to avoid all those synchro issues
2402          */
2403         if (!netif_device_present(dev) || !netif_running(dev))
2404                 goto bail;
2405 
2406         /* Better safe than sorry... */
2407         if (WARN_ON(!gp->cell_enabled))
2408                 goto bail;
2409 
2410         dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2411         writel(0, gp->regs + MAC_FCSERR);
2412 
2413         dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2414         writel(0, gp->regs + MAC_AERR);
2415 
2416         dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2417         writel(0, gp->regs + MAC_LERR);
2418 
2419         dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2420         dev->stats.collisions +=
2421                 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2422         writel(0, gp->regs + MAC_ECOLL);
2423         writel(0, gp->regs + MAC_LCOLL);
2424  bail:
2425         return &dev->stats;
2426 }
2427 
2428 static int gem_set_mac_address(struct net_device *dev, void *addr)
2429 {
2430         struct sockaddr *macaddr = (struct sockaddr *) addr;
2431         struct gem *gp = netdev_priv(dev);
2432         unsigned char *e = &dev->dev_addr[0];
2433 
2434         if (!is_valid_ether_addr(macaddr->sa_data))
2435                 return -EADDRNOTAVAIL;
2436 
2437         memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2438 
2439         /* We'll just catch it later when the device is up'd or resumed */
2440         if (!netif_running(dev) || !netif_device_present(dev))
2441                 return 0;
2442 
2443         /* Better safe than sorry... */
2444         if (WARN_ON(!gp->cell_enabled))
2445                 return 0;
2446 
2447         writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2448         writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2449         writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2450 
2451         return 0;
2452 }
2453 
2454 static void gem_set_multicast(struct net_device *dev)
2455 {
2456         struct gem *gp = netdev_priv(dev);
2457         u32 rxcfg, rxcfg_new;
2458         int limit = 10000;
2459 
2460         if (!netif_running(dev) || !netif_device_present(dev))
2461                 return;
2462 
2463         /* Better safe than sorry... */
2464         if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2465                 return;
2466 
2467         rxcfg = readl(gp->regs + MAC_RXCFG);
2468         rxcfg_new = gem_setup_multicast(gp);
2469 #ifdef STRIP_FCS
2470         rxcfg_new |= MAC_RXCFG_SFCS;
2471 #endif
2472         gp->mac_rx_cfg = rxcfg_new;
2473 
2474         writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2475         while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2476                 if (!limit--)
2477                         break;
2478                 udelay(10);
2479         }
2480 
2481         rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2482         rxcfg |= rxcfg_new;
2483 
2484         writel(rxcfg, gp->regs + MAC_RXCFG);
2485 }
2486 
2487 /* Jumbo-grams don't seem to work :-( */
2488 #define GEM_MIN_MTU     ETH_MIN_MTU
2489 #if 1
2490 #define GEM_MAX_MTU     ETH_DATA_LEN
2491 #else
2492 #define GEM_MAX_MTU     9000
2493 #endif
2494 
2495 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2496 {
2497         struct gem *gp = netdev_priv(dev);
2498 
2499         dev->mtu = new_mtu;
2500 
2501         /* We'll just catch it later when the device is up'd or resumed */
2502         if (!netif_running(dev) || !netif_device_present(dev))
2503                 return 0;
2504 
2505         /* Better safe than sorry... */
2506         if (WARN_ON(!gp->cell_enabled))
2507                 return 0;
2508 
2509         gem_netif_stop(gp);
2510         gem_reinit_chip(gp);
2511         if (gp->lstate == link_up)
2512                 gem_set_link_modes(gp);
2513         gem_netif_start(gp);
2514 
2515         return 0;
2516 }
2517 
2518 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2519 {
2520         struct gem *gp = netdev_priv(dev);
2521 
2522         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2523         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2524         strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2525 }
2526 
2527 static int gem_get_link_ksettings(struct net_device *dev,
2528                                   struct ethtool_link_ksettings *cmd)
2529 {
2530         struct gem *gp = netdev_priv(dev);
2531         u32 supported, advertising;
2532 
2533         if (gp->phy_type == phy_mii_mdio0 ||
2534             gp->phy_type == phy_mii_mdio1) {
2535                 if (gp->phy_mii.def)
2536                         supported = gp->phy_mii.def->features;
2537                 else
2538                         supported = (SUPPORTED_10baseT_Half |
2539                                           SUPPORTED_10baseT_Full);
2540 
2541                 /* XXX hardcoded stuff for now */
2542                 cmd->base.port = PORT_MII;
2543                 cmd->base.phy_address = 0; /* XXX fixed PHYAD */
2544 
2545                 /* Return current PHY settings */
2546                 cmd->base.autoneg = gp->want_autoneg;
2547                 cmd->base.speed = gp->phy_mii.speed;
2548                 cmd->base.duplex = gp->phy_mii.duplex;
2549                 advertising = gp->phy_mii.advertising;
2550 
2551                 /* If we started with a forced mode, we don't have a default
2552                  * advertise set, we need to return something sensible so
2553                  * userland can re-enable autoneg properly.
2554                  */
2555                 if (advertising == 0)
2556                         advertising = supported;
2557         } else { // XXX PCS ?
2558                 supported =
2559                         (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2560                          SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2561                          SUPPORTED_Autoneg);
2562                 advertising = supported;
2563                 cmd->base.speed = 0;
2564                 cmd->base.duplex = 0;
2565                 cmd->base.port = 0;
2566                 cmd->base.phy_address = 0;
2567                 cmd->base.autoneg = 0;
2568 
2569                 /* serdes means usually a Fibre connector, with most fixed */
2570                 if (gp->phy_type == phy_serdes) {
2571                         cmd->base.port = PORT_FIBRE;
2572                         supported = (SUPPORTED_1000baseT_Half |
2573                                 SUPPORTED_1000baseT_Full |
2574                                 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2575                                 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2576                         advertising = supported;
2577                         if (gp->lstate == link_up)
2578                                 cmd->base.speed = SPEED_1000;
2579                         cmd->base.duplex = DUPLEX_FULL;
2580                         cmd->base.autoneg = 1;
2581                 }
2582         }
2583 
2584         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2585                                                 supported);
2586         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2587                                                 advertising);
2588 
2589         return 0;
2590 }
2591 
2592 static int gem_set_link_ksettings(struct net_device *dev,
2593                                   const struct ethtool_link_ksettings *cmd)
2594 {
2595         struct gem *gp = netdev_priv(dev);
2596         u32 speed = cmd->base.speed;
2597         u32 advertising;
2598 
2599         ethtool_convert_link_mode_to_legacy_u32(&advertising,
2600                                                 cmd->link_modes.advertising);
2601 
2602         /* Verify the settings we care about. */
2603         if (cmd->base.autoneg != AUTONEG_ENABLE &&
2604             cmd->base.autoneg != AUTONEG_DISABLE)
2605                 return -EINVAL;
2606 
2607         if (cmd->base.autoneg == AUTONEG_ENABLE &&
2608             advertising == 0)
2609                 return -EINVAL;
2610 
2611         if (cmd->base.autoneg == AUTONEG_DISABLE &&
2612             ((speed != SPEED_1000 &&
2613               speed != SPEED_100 &&
2614               speed != SPEED_10) ||
2615              (cmd->base.duplex != DUPLEX_HALF &&
2616               cmd->base.duplex != DUPLEX_FULL)))
2617                 return -EINVAL;
2618 
2619         /* Apply settings and restart link process. */
2620         if (netif_device_present(gp->dev)) {
2621                 del_timer_sync(&gp->link_timer);
2622                 gem_begin_auto_negotiation(gp, cmd);
2623         }
2624 
2625         return 0;
2626 }
2627 
2628 static int gem_nway_reset(struct net_device *dev)
2629 {
2630         struct gem *gp = netdev_priv(dev);
2631 
2632         if (!gp->want_autoneg)
2633                 return -EINVAL;
2634 
2635         /* Restart link process  */
2636         if (netif_device_present(gp->dev)) {
2637                 del_timer_sync(&gp->link_timer);
2638                 gem_begin_auto_negotiation(gp, NULL);
2639         }
2640 
2641         return 0;
2642 }
2643 
2644 static u32 gem_get_msglevel(struct net_device *dev)
2645 {
2646         struct gem *gp = netdev_priv(dev);
2647         return gp->msg_enable;
2648 }
2649 
2650 static void gem_set_msglevel(struct net_device *dev, u32 value)
2651 {
2652         struct gem *gp = netdev_priv(dev);
2653         gp->msg_enable = value;
2654 }
2655 
2656 
2657 /* Add more when I understand how to program the chip */
2658 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2659 
2660 #define WOL_SUPPORTED_MASK      (WAKE_MAGIC)
2661 
2662 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2663 {
2664         struct gem *gp = netdev_priv(dev);
2665 
2666         /* Add more when I understand how to program the chip */
2667         if (gp->has_wol) {
2668                 wol->supported = WOL_SUPPORTED_MASK;
2669                 wol->wolopts = gp->wake_on_lan;
2670         } else {
2671                 wol->supported = 0;
2672                 wol->wolopts = 0;
2673         }
2674 }
2675 
2676 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2677 {
2678         struct gem *gp = netdev_priv(dev);
2679 
2680         if (!gp->has_wol)
2681                 return -EOPNOTSUPP;
2682         gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2683         return 0;
2684 }
2685 
2686 static const struct ethtool_ops gem_ethtool_ops = {
2687         .get_drvinfo            = gem_get_drvinfo,
2688         .get_link               = ethtool_op_get_link,
2689         .nway_reset             = gem_nway_reset,
2690         .get_msglevel           = gem_get_msglevel,
2691         .set_msglevel           = gem_set_msglevel,
2692         .get_wol                = gem_get_wol,
2693         .set_wol                = gem_set_wol,
2694         .get_link_ksettings     = gem_get_link_ksettings,
2695         .set_link_ksettings     = gem_set_link_ksettings,
2696 };
2697 
2698 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2699 {
2700         struct gem *gp = netdev_priv(dev);
2701         struct mii_ioctl_data *data = if_mii(ifr);
2702         int rc = -EOPNOTSUPP;
2703 
2704         /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2705          * netif_device_present() is true and holds rtnl_lock for us
2706          * so we have nothing to worry about
2707          */
2708 
2709         switch (cmd) {
2710         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
2711                 data->phy_id = gp->mii_phy_addr;
2712                 /* Fallthrough... */
2713 
2714         case SIOCGMIIREG:               /* Read MII PHY register. */
2715                 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2716                                            data->reg_num & 0x1f);
2717                 rc = 0;
2718                 break;
2719 
2720         case SIOCSMIIREG:               /* Write MII PHY register. */
2721                 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2722                             data->val_in);
2723                 rc = 0;
2724                 break;
2725         }
2726         return rc;
2727 }
2728 
2729 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2730 /* Fetch MAC address from vital product data of PCI ROM. */
2731 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2732 {
2733         int this_offset;
2734 
2735         for (this_offset = 0x20; this_offset < len; this_offset++) {
2736                 void __iomem *p = rom_base + this_offset;
2737                 int i;
2738 
2739                 if (readb(p + 0) != 0x90 ||
2740                     readb(p + 1) != 0x00 ||
2741                     readb(p + 2) != 0x09 ||
2742                     readb(p + 3) != 0x4e ||
2743                     readb(p + 4) != 0x41 ||
2744                     readb(p + 5) != 0x06)
2745                         continue;
2746 
2747                 this_offset += 6;
2748                 p += 6;
2749 
2750                 for (i = 0; i < 6; i++)
2751                         dev_addr[i] = readb(p + i);
2752                 return 1;
2753         }
2754         return 0;
2755 }
2756 
2757 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2758 {
2759         size_t size;
2760         void __iomem *p = pci_map_rom(pdev, &size);
2761 
2762         if (p) {
2763                 int found;
2764 
2765                 found = readb(p) == 0x55 &&
2766                         readb(p + 1) == 0xaa &&
2767                         find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2768                 pci_unmap_rom(pdev, p);
2769                 if (found)
2770                         return;
2771         }
2772 
2773         /* Sun MAC prefix then 3 random bytes. */
2774         dev_addr[0] = 0x08;
2775         dev_addr[1] = 0x00;
2776         dev_addr[2] = 0x20;
2777         get_random_bytes(dev_addr + 3, 3);
2778 }
2779 #endif /* not Sparc and not PPC */
2780 
2781 static int gem_get_device_address(struct gem *gp)
2782 {
2783 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2784         struct net_device *dev = gp->dev;
2785         const unsigned char *addr;
2786 
2787         addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2788         if (addr == NULL) {
2789 #ifdef CONFIG_SPARC
2790                 addr = idprom->id_ethaddr;
2791 #else
2792                 printk("\n");
2793                 pr_err("%s: can't get mac-address\n", dev->name);
2794                 return -1;
2795 #endif
2796         }
2797         memcpy(dev->dev_addr, addr, ETH_ALEN);
2798 #else
2799         get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2800 #endif
2801         return 0;
2802 }
2803 
2804 static void gem_remove_one(struct pci_dev *pdev)
2805 {
2806         struct net_device *dev = pci_get_drvdata(pdev);
2807 
2808         if (dev) {
2809                 struct gem *gp = netdev_priv(dev);
2810 
2811                 unregister_netdev(dev);
2812 
2813                 /* Ensure reset task is truly gone */
2814                 cancel_work_sync(&gp->reset_task);
2815 
2816                 /* Free resources */
2817                 pci_free_consistent(pdev,
2818                                     sizeof(struct gem_init_block),
2819                                     gp->init_block,
2820                                     gp->gblock_dvma);
2821                 iounmap(gp->regs);
2822                 pci_release_regions(pdev);
2823                 free_netdev(dev);
2824         }
2825 }
2826 
2827 static const struct net_device_ops gem_netdev_ops = {
2828         .ndo_open               = gem_open,
2829         .ndo_stop               = gem_close,
2830         .ndo_start_xmit         = gem_start_xmit,
2831         .ndo_get_stats          = gem_get_stats,
2832         .ndo_set_rx_mode        = gem_set_multicast,
2833         .ndo_do_ioctl           = gem_ioctl,
2834         .ndo_tx_timeout         = gem_tx_timeout,
2835         .ndo_change_mtu         = gem_change_mtu,
2836         .ndo_validate_addr      = eth_validate_addr,
2837         .ndo_set_mac_address    = gem_set_mac_address,
2838 #ifdef CONFIG_NET_POLL_CONTROLLER
2839         .ndo_poll_controller    = gem_poll_controller,
2840 #endif
2841 };
2842 
2843 static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2844 {
2845         unsigned long gemreg_base, gemreg_len;
2846         struct net_device *dev;
2847         struct gem *gp;
2848         int err, pci_using_dac;
2849 
2850         printk_once(KERN_INFO "%s", version);
2851 
2852         /* Apple gmac note: during probe, the chip is powered up by
2853          * the arch code to allow the code below to work (and to let
2854          * the chip be probed on the config space. It won't stay powered
2855          * up until the interface is brought up however, so we can't rely
2856          * on register configuration done at this point.
2857          */
2858         err = pci_enable_device(pdev);
2859         if (err) {
2860                 pr_err("Cannot enable MMIO operation, aborting\n");
2861                 return err;
2862         }
2863         pci_set_master(pdev);
2864 
2865         /* Configure DMA attributes. */
2866 
2867         /* All of the GEM documentation states that 64-bit DMA addressing
2868          * is fully supported and should work just fine.  However the
2869          * front end for RIO based GEMs is different and only supports
2870          * 32-bit addressing.
2871          *
2872          * For now we assume the various PPC GEMs are 32-bit only as well.
2873          */
2874         if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2875             pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2876             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2877                 pci_using_dac = 1;
2878         } else {
2879                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2880                 if (err) {
2881                         pr_err("No usable DMA configuration, aborting\n");
2882                         goto err_disable_device;
2883                 }
2884                 pci_using_dac = 0;
2885         }
2886 
2887         gemreg_base = pci_resource_start(pdev, 0);
2888         gemreg_len = pci_resource_len(pdev, 0);
2889 
2890         if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2891                 pr_err("Cannot find proper PCI device base address, aborting\n");
2892                 err = -ENODEV;
2893                 goto err_disable_device;
2894         }
2895 
2896         dev = alloc_etherdev(sizeof(*gp));
2897         if (!dev) {
2898                 err = -ENOMEM;
2899                 goto err_disable_device;
2900         }
2901         SET_NETDEV_DEV(dev, &pdev->dev);
2902 
2903         gp = netdev_priv(dev);
2904 
2905         err = pci_request_regions(pdev, DRV_NAME);
2906         if (err) {
2907                 pr_err("Cannot obtain PCI resources, aborting\n");
2908                 goto err_out_free_netdev;
2909         }
2910 
2911         gp->pdev = pdev;
2912         gp->dev = dev;
2913 
2914         gp->msg_enable = DEFAULT_MSG;
2915 
2916         timer_setup(&gp->link_timer, gem_link_timer, 0);
2917 
2918         INIT_WORK(&gp->reset_task, gem_reset_task);
2919 
2920         gp->lstate = link_down;
2921         gp->timer_ticks = 0;
2922         netif_carrier_off(dev);
2923 
2924         gp->regs = ioremap(gemreg_base, gemreg_len);
2925         if (!gp->regs) {
2926                 pr_err("Cannot map device registers, aborting\n");
2927                 err = -EIO;
2928                 goto err_out_free_res;
2929         }
2930 
2931         /* On Apple, we want a reference to the Open Firmware device-tree
2932          * node. We use it for clock control.
2933          */
2934 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2935         gp->of_node = pci_device_to_OF_node(pdev);
2936 #endif
2937 
2938         /* Only Apple version supports WOL afaik */
2939         if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2940                 gp->has_wol = 1;
2941 
2942         /* Make sure cell is enabled */
2943         gem_get_cell(gp);
2944 
2945         /* Make sure everything is stopped and in init state */
2946         gem_reset(gp);
2947 
2948         /* Fill up the mii_phy structure (even if we won't use it) */
2949         gp->phy_mii.dev = dev;
2950         gp->phy_mii.mdio_read = _sungem_phy_read;
2951         gp->phy_mii.mdio_write = _sungem_phy_write;
2952 #ifdef CONFIG_PPC_PMAC
2953         gp->phy_mii.platform_data = gp->of_node;
2954 #endif
2955         /* By default, we start with autoneg */
2956         gp->want_autoneg = 1;
2957 
2958         /* Check fifo sizes, PHY type, etc... */
2959         if (gem_check_invariants(gp)) {
2960                 err = -ENODEV;
2961                 goto err_out_iounmap;
2962         }
2963 
2964         /* It is guaranteed that the returned buffer will be at least
2965          * PAGE_SIZE aligned.
2966          */
2967         gp->init_block = (struct gem_init_block *)
2968                 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2969                                      &gp->gblock_dvma);
2970         if (!gp->init_block) {
2971                 pr_err("Cannot allocate init block, aborting\n");
2972                 err = -ENOMEM;
2973                 goto err_out_iounmap;
2974         }
2975 
2976         err = gem_get_device_address(gp);
2977         if (err)
2978                 goto err_out_free_consistent;
2979 
2980         dev->netdev_ops = &gem_netdev_ops;
2981         netif_napi_add(dev, &gp->napi, gem_poll, 64);
2982         dev->ethtool_ops = &gem_ethtool_ops;
2983         dev->watchdog_timeo = 5 * HZ;
2984         dev->dma = 0;
2985 
2986         /* Set that now, in case PM kicks in now */
2987         pci_set_drvdata(pdev, dev);
2988 
2989         /* We can do scatter/gather and HW checksum */
2990         dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2991         dev->features = dev->hw_features;
2992         if (pci_using_dac)
2993                 dev->features |= NETIF_F_HIGHDMA;
2994 
2995         /* MTU range: 68 - 1500 (Jumbo mode is broken) */
2996         dev->min_mtu = GEM_MIN_MTU;
2997         dev->max_mtu = GEM_MAX_MTU;
2998 
2999         /* Register with kernel */
3000         if (register_netdev(dev)) {
3001                 pr_err("Cannot register net device, aborting\n");
3002                 err = -ENOMEM;
3003                 goto err_out_free_consistent;
3004         }
3005 
3006         /* Undo the get_cell with appropriate locking (we could use
3007          * ndo_init/uninit but that would be even more clumsy imho)
3008          */
3009         rtnl_lock();
3010         gem_put_cell(gp);
3011         rtnl_unlock();
3012 
3013         netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3014                     dev->dev_addr);
3015         return 0;
3016 
3017 err_out_free_consistent:
3018         gem_remove_one(pdev);
3019 err_out_iounmap:
3020         gem_put_cell(gp);
3021         iounmap(gp->regs);
3022 
3023 err_out_free_res:
3024         pci_release_regions(pdev);
3025 
3026 err_out_free_netdev:
3027         free_netdev(dev);
3028 err_disable_device:
3029         pci_disable_device(pdev);
3030         return err;
3031 
3032 }
3033 
3034 
3035 static struct pci_driver gem_driver = {
3036         .name           = GEM_MODULE_NAME,
3037         .id_table       = gem_pci_tbl,
3038         .probe          = gem_init_one,
3039         .remove         = gem_remove_one,
3040 #ifdef CONFIG_PM
3041         .suspend        = gem_suspend,
3042         .resume         = gem_resume,
3043 #endif /* CONFIG_PM */
3044 };
3045 
3046 module_pci_driver(gem_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/sun/sungem.c

DEFINITIONS
