drivers/net/ethernet/sun/cassini.c

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This source file includes following definitions.
cas_lock_tx
cas_lock_all
cas_unlock_tx
cas_unlock_all
cas_disable_irq
cas_mask_intr
cas_enable_irq
cas_unmask_intr
cas_entropy_gather
cas_entropy_reset
cas_phy_read
cas_phy_write
cas_phy_powerup
cas_phy_powerdown
cas_page_free
cas_page_alloc
cas_spare_init
cas_spare_free
cas_spare_recover
cas_page_dequeue
cas_mif_poll
cas_begin_auto_negotiation
cas_reset_mii_phy
cas_saturn_firmware_init
cas_saturn_firmware_load
cas_phy_init
cas_pcs_link_check
cas_pcs_interrupt
cas_txmac_interrupt
cas_load_firmware
cas_init_rx_dma
cas_rxc_init
cas_page_spare
cas_page_swap
cas_clean_rxds
cas_clean_rxcs
cas_rxmac_reset
cas_rxmac_interrupt
cas_mac_interrupt
cas_mdio_link_not_up
cas_mii_link_check
cas_mif_interrupt
cas_pci_interrupt
cas_abnormal_irq
cas_calc_tabort
cas_tx_ringN
cas_tx
cas_rx_process_pkt
cas_rx_flow_pkt
cas_post_page
cas_post_rxds_ringN
cas_rx_ringN
cas_post_rxcs_ringN
cas_handle_irqN
cas_interruptN
cas_handle_irq1
cas_interrupt1
cas_handle_irq
cas_interrupt
cas_poll
cas_netpoll
cas_tx_timeout
cas_intme
cas_write_txd
tx_tiny_buf
tx_tiny_map
cas_xmit_tx_ringN
cas_start_xmit
cas_init_tx_dma
cas_init_dma
cas_process_mc_list
cas_setup_multicast
cas_clear_mac_err
cas_mac_reset
cas_init_mac
cas_init_pause_thresholds
cas_vpd_match
cas_get_vpd_info
cas_check_pci_invariants
cas_check_invariants
cas_start_dma
cas_read_pcs_link_mode
cas_read_mii_link_mode
cas_set_link_modes
cas_init_hw
cas_hard_reset
cas_global_reset
cas_reset
cas_shutdown
cas_change_mtu
cas_clean_txd
cas_free_rx_desc
cas_free_rxds
cas_clean_rings
cas_alloc_rx_desc
cas_alloc_rxds
cas_reset_task
cas_link_timer
cas_tx_tiny_free
cas_tx_tiny_alloc
cas_open
cas_close
cas_read_regs
cas_get_stats
cas_set_multicast
cas_get_drvinfo
cas_get_link_ksettings
cas_set_link_ksettings
cas_nway_reset
cas_get_link
cas_get_msglevel
cas_set_msglevel
cas_get_regs_len
cas_get_regs
cas_get_sset_count
cas_get_strings
cas_get_ethtool_stats
cas_ioctl
cas_program_bridge
cas_init_one
cas_remove_one
cas_suspend
cas_resume
cas_init
cas_cleanup
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
   3  *
   4  * Copyright (C) 2004 Sun Microsystems Inc.
   5  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
   6  *
   7  * This driver uses the sungem driver (c) David Miller
   8  * (davem@redhat.com) as its basis.
   9  *
  10  * The cassini chip has a number of features that distinguish it from
  11  * the gem chip:
  12  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
  13  *      load balancing (non-VLAN mode)
  14  *  batching of multiple packets
  15  *  multiple CPU dispatching
  16  *  page-based RX descriptor engine with separate completion rings
  17  *  Gigabit support (GMII and PCS interface)
  18  *  MIF link up/down detection works
  19  *
  20  * RX is handled by page sized buffers that are attached as fragments to
  21  * the skb. here's what's done:
  22  *  -- driver allocates pages at a time and keeps reference counts
  23  *     on them.
  24  *  -- the upper protocol layers assume that the header is in the skb
  25  *     itself. as a result, cassini will copy a small amount (64 bytes)
  26  *     to make them happy.
  27  *  -- driver appends the rest of the data pages as frags to skbuffs
  28  *     and increments the reference count
  29  *  -- on page reclamation, the driver swaps the page with a spare page.
  30  *     if that page is still in use, it frees its reference to that page,
  31  *     and allocates a new page for use. otherwise, it just recycles the
  32  *     the page.
  33  *
  34  * NOTE: cassini can parse the header. however, it's not worth it
  35  *       as long as the network stack requires a header copy.
  36  *
  37  * TX has 4 queues. currently these queues are used in a round-robin
  38  * fashion for load balancing. They can also be used for QoS. for that
  39  * to work, however, QoS information needs to be exposed down to the driver
  40  * level so that subqueues get targeted to particular transmit rings.
  41  * alternatively, the queues can be configured via use of the all-purpose
  42  * ioctl.
  43  *
  44  * RX DATA: the rx completion ring has all the info, but the rx desc
  45  * ring has all of the data. RX can conceivably come in under multiple
  46  * interrupts, but the INT# assignment needs to be set up properly by
  47  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
  48  * that. also, the two descriptor rings are designed to distinguish between
  49  * encrypted and non-encrypted packets, but we use them for buffering
  50  * instead.
  51  *
  52  * by default, the selective clear mask is set up to process rx packets.
  53  */
  54 
  55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  56 
  57 #include <linux/module.h>
  58 #include <linux/kernel.h>
  59 #include <linux/types.h>
  60 #include <linux/compiler.h>
  61 #include <linux/slab.h>
  62 #include <linux/delay.h>
  63 #include <linux/init.h>
  64 #include <linux/interrupt.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/ioport.h>
  67 #include <linux/pci.h>
  68 #include <linux/mm.h>
  69 #include <linux/highmem.h>
  70 #include <linux/list.h>
  71 #include <linux/dma-mapping.h>
  72 
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/ethtool.h>
  77 #include <linux/crc32.h>
  78 #include <linux/random.h>
  79 #include <linux/mii.h>
  80 #include <linux/ip.h>
  81 #include <linux/tcp.h>
  82 #include <linux/mutex.h>
  83 #include <linux/firmware.h>
  84 
  85 #include <net/checksum.h>
  86 
  87 #include <linux/atomic.h>
  88 #include <asm/io.h>
  89 #include <asm/byteorder.h>
  90 #include <linux/uaccess.h>
  91 
  92 #define cas_page_map(x)      kmap_atomic((x))
  93 #define cas_page_unmap(x)    kunmap_atomic((x))
  94 #define CAS_NCPUS            num_online_cpus()
  95 
  96 #define cas_skb_release(x)  netif_rx(x)
  97 
  98 /* select which firmware to use */
  99 #define USE_HP_WORKAROUND
 100 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
 101 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
 102 
 103 #include "cassini.h"
 104 
 105 #define USE_TX_COMPWB      /* use completion writeback registers */
 106 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
 107 #define USE_RX_BLANK       /* hw interrupt mitigation */
 108 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
 109 
 110 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
 111  * also, we need to make cp->lock finer-grained.
 112  */
 113 #undef  USE_PCI_INTB
 114 #undef  USE_PCI_INTC
 115 #undef  USE_PCI_INTD
 116 #undef  USE_QOS
 117 
 118 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
 119 
 120 /* rx processing options */
 121 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
 122 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
 123 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
 124 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
 125 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
 126 
 127 #define DRV_MODULE_NAME         "cassini"
 128 #define DRV_MODULE_VERSION      "1.6"
 129 #define DRV_MODULE_RELDATE      "21 May 2008"
 130 
 131 #define CAS_DEF_MSG_ENABLE        \
 132         (NETIF_MSG_DRV          | \
 133          NETIF_MSG_PROBE        | \
 134          NETIF_MSG_LINK         | \
 135          NETIF_MSG_TIMER        | \
 136          NETIF_MSG_IFDOWN       | \
 137          NETIF_MSG_IFUP         | \
 138          NETIF_MSG_RX_ERR       | \
 139          NETIF_MSG_TX_ERR)
 140 
 141 /* length of time before we decide the hardware is borked,
 142  * and dev->tx_timeout() should be called to fix the problem
 143  */
 144 #define CAS_TX_TIMEOUT                  (HZ)
 145 #define CAS_LINK_TIMEOUT                (22*HZ/10)
 146 #define CAS_LINK_FAST_TIMEOUT           (1)
 147 
 148 /* timeout values for state changing. these specify the number
 149  * of 10us delays to be used before giving up.
 150  */
 151 #define STOP_TRIES_PHY 1000
 152 #define STOP_TRIES     5000
 153 
 154 /* specify a minimum frame size to deal with some fifo issues
 155  * max mtu == 2 * page size - ethernet header - 64 - swivel =
 156  *            2 * page_size - 0x50
 157  */
 158 #define CAS_MIN_FRAME                   97
 159 #define CAS_1000MB_MIN_FRAME            255
 160 #define CAS_MIN_MTU                     60
 161 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
 162 
 163 #if 1
 164 /*
 165  * Eliminate these and use separate atomic counters for each, to
 166  * avoid a race condition.
 167  */
 168 #else
 169 #define CAS_RESET_MTU                   1
 170 #define CAS_RESET_ALL                   2
 171 #define CAS_RESET_SPARE                 3
 172 #endif
 173 
 174 static char version[] =
 175         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 176 
 177 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
 178 static int link_mode;
 179 
 180 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
 181 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
 182 MODULE_LICENSE("GPL");
 183 MODULE_FIRMWARE("sun/cassini.bin");
 184 module_param(cassini_debug, int, 0);
 185 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
 186 module_param(link_mode, int, 0);
 187 MODULE_PARM_DESC(link_mode, "default link mode");
 188 
 189 /*
 190  * Work around for a PCS bug in which the link goes down due to the chip
 191  * being confused and never showing a link status of "up."
 192  */
 193 #define DEFAULT_LINKDOWN_TIMEOUT 5
 194 /*
 195  * Value in seconds, for user input.
 196  */
 197 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
 198 module_param(linkdown_timeout, int, 0);
 199 MODULE_PARM_DESC(linkdown_timeout,
 200 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
 201 
 202 /*
 203  * value in 'ticks' (units used by jiffies). Set when we init the
 204  * module because 'HZ' in actually a function call on some flavors of
 205  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
 206  */
 207 static int link_transition_timeout;
 208 
 209 
 210 
 211 static u16 link_modes[] = {
 212         BMCR_ANENABLE,                   /* 0 : autoneg */
 213         0,                               /* 1 : 10bt half duplex */
 214         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
 215         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
 216         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
 217         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
 218 };
 219 
 220 static const struct pci_device_id cas_pci_tbl[] = {
 221         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 223         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 225         { 0, }
 226 };
 227 
 228 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
 229 
 230 static void cas_set_link_modes(struct cas *cp);
 231 
 232 static inline void cas_lock_tx(struct cas *cp)
 233 {
 234         int i;
 235 
 236         for (i = 0; i < N_TX_RINGS; i++)
 237                 spin_lock_nested(&cp->tx_lock[i], i);
 238 }
 239 
 240 static inline void cas_lock_all(struct cas *cp)
 241 {
 242         spin_lock_irq(&cp->lock);
 243         cas_lock_tx(cp);
 244 }
 245 
 246 /* WTZ: QA was finding deadlock problems with the previous
 247  * versions after long test runs with multiple cards per machine.
 248  * See if replacing cas_lock_all with safer versions helps. The
 249  * symptoms QA is reporting match those we'd expect if interrupts
 250  * aren't being properly restored, and we fixed a previous deadlock
 251  * with similar symptoms by using save/restore versions in other
 252  * places.
 253  */
 254 #define cas_lock_all_save(cp, flags) \
 255 do { \
 256         struct cas *xxxcp = (cp); \
 257         spin_lock_irqsave(&xxxcp->lock, flags); \
 258         cas_lock_tx(xxxcp); \
 259 } while (0)
 260 
 261 static inline void cas_unlock_tx(struct cas *cp)
 262 {
 263         int i;
 264 
 265         for (i = N_TX_RINGS; i > 0; i--)
 266                 spin_unlock(&cp->tx_lock[i - 1]);
 267 }
 268 
 269 static inline void cas_unlock_all(struct cas *cp)
 270 {
 271         cas_unlock_tx(cp);
 272         spin_unlock_irq(&cp->lock);
 273 }
 274 
 275 #define cas_unlock_all_restore(cp, flags) \
 276 do { \
 277         struct cas *xxxcp = (cp); \
 278         cas_unlock_tx(xxxcp); \
 279         spin_unlock_irqrestore(&xxxcp->lock, flags); \
 280 } while (0)
 281 
 282 static void cas_disable_irq(struct cas *cp, const int ring)
 283 {
 284         /* Make sure we won't get any more interrupts */
 285         if (ring == 0) {
 286                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
 287                 return;
 288         }
 289 
 290         /* disable completion interrupts and selectively mask */
 291         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
 292                 switch (ring) {
 293 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
 294 #ifdef USE_PCI_INTB
 295                 case 1:
 296 #endif
 297 #ifdef USE_PCI_INTC
 298                 case 2:
 299 #endif
 300 #ifdef USE_PCI_INTD
 301                 case 3:
 302 #endif
 303                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
 304                                cp->regs + REG_PLUS_INTRN_MASK(ring));
 305                         break;
 306 #endif
 307                 default:
 308                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
 309                                REG_PLUS_INTRN_MASK(ring));
 310                         break;
 311                 }
 312         }
 313 }
 314 
 315 static inline void cas_mask_intr(struct cas *cp)
 316 {
 317         int i;
 318 
 319         for (i = 0; i < N_RX_COMP_RINGS; i++)
 320                 cas_disable_irq(cp, i);
 321 }
 322 
 323 static void cas_enable_irq(struct cas *cp, const int ring)
 324 {
 325         if (ring == 0) { /* all but TX_DONE */
 326                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
 327                 return;
 328         }
 329 
 330         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
 331                 switch (ring) {
 332 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
 333 #ifdef USE_PCI_INTB
 334                 case 1:
 335 #endif
 336 #ifdef USE_PCI_INTC
 337                 case 2:
 338 #endif
 339 #ifdef USE_PCI_INTD
 340                 case 3:
 341 #endif
 342                         writel(INTRN_MASK_RX_EN, cp->regs +
 343                                REG_PLUS_INTRN_MASK(ring));
 344                         break;
 345 #endif
 346                 default:
 347                         break;
 348                 }
 349         }
 350 }
 351 
 352 static inline void cas_unmask_intr(struct cas *cp)
 353 {
 354         int i;
 355 
 356         for (i = 0; i < N_RX_COMP_RINGS; i++)
 357                 cas_enable_irq(cp, i);
 358 }
 359 
 360 static inline void cas_entropy_gather(struct cas *cp)
 361 {
 362 #ifdef USE_ENTROPY_DEV
 363         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
 364                 return;
 365 
 366         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
 367                             readl(cp->regs + REG_ENTROPY_IV),
 368                             sizeof(uint64_t)*8);
 369 #endif
 370 }
 371 
 372 static inline void cas_entropy_reset(struct cas *cp)
 373 {
 374 #ifdef USE_ENTROPY_DEV
 375         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
 376                 return;
 377 
 378         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
 379                cp->regs + REG_BIM_LOCAL_DEV_EN);
 380         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
 381         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
 382 
 383         /* if we read back 0x0, we don't have an entropy device */
 384         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
 385                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
 386 #endif
 387 }
 388 
 389 /* access to the phy. the following assumes that we've initialized the MIF to
 390  * be in frame rather than bit-bang mode
 391  */
 392 static u16 cas_phy_read(struct cas *cp, int reg)
 393 {
 394         u32 cmd;
 395         int limit = STOP_TRIES_PHY;
 396 
 397         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
 398         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
 399         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
 400         cmd |= MIF_FRAME_TURN_AROUND_MSB;
 401         writel(cmd, cp->regs + REG_MIF_FRAME);
 402 
 403         /* poll for completion */
 404         while (limit-- > 0) {
 405                 udelay(10);
 406                 cmd = readl(cp->regs + REG_MIF_FRAME);
 407                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
 408                         return cmd & MIF_FRAME_DATA_MASK;
 409         }
 410         return 0xFFFF; /* -1 */
 411 }
 412 
 413 static int cas_phy_write(struct cas *cp, int reg, u16 val)
 414 {
 415         int limit = STOP_TRIES_PHY;
 416         u32 cmd;
 417 
 418         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
 419         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
 420         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
 421         cmd |= MIF_FRAME_TURN_AROUND_MSB;
 422         cmd |= val & MIF_FRAME_DATA_MASK;
 423         writel(cmd, cp->regs + REG_MIF_FRAME);
 424 
 425         /* poll for completion */
 426         while (limit-- > 0) {
 427                 udelay(10);
 428                 cmd = readl(cp->regs + REG_MIF_FRAME);
 429                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
 430                         return 0;
 431         }
 432         return -1;
 433 }
 434 
 435 static void cas_phy_powerup(struct cas *cp)
 436 {
 437         u16 ctl = cas_phy_read(cp, MII_BMCR);
 438 
 439         if ((ctl & BMCR_PDOWN) == 0)
 440                 return;
 441         ctl &= ~BMCR_PDOWN;
 442         cas_phy_write(cp, MII_BMCR, ctl);
 443 }
 444 
 445 static void cas_phy_powerdown(struct cas *cp)
 446 {
 447         u16 ctl = cas_phy_read(cp, MII_BMCR);
 448 
 449         if (ctl & BMCR_PDOWN)
 450                 return;
 451         ctl |= BMCR_PDOWN;
 452         cas_phy_write(cp, MII_BMCR, ctl);
 453 }
 454 
 455 /* cp->lock held. note: the last put_page will free the buffer */
 456 static int cas_page_free(struct cas *cp, cas_page_t *page)
 457 {
 458         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
 459                        PCI_DMA_FROMDEVICE);
 460         __free_pages(page->buffer, cp->page_order);
 461         kfree(page);
 462         return 0;
 463 }
 464 
 465 #ifdef RX_COUNT_BUFFERS
 466 #define RX_USED_ADD(x, y)       ((x)->used += (y))
 467 #define RX_USED_SET(x, y)       ((x)->used  = (y))
 468 #else
 469 #define RX_USED_ADD(x, y)
 470 #define RX_USED_SET(x, y)
 471 #endif
 472 
 473 /* local page allocation routines for the receive buffers. jumbo pages
 474  * require at least 8K contiguous and 8K aligned buffers.
 475  */
 476 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
 477 {
 478         cas_page_t *page;
 479 
 480         page = kmalloc(sizeof(cas_page_t), flags);
 481         if (!page)
 482                 return NULL;
 483 
 484         INIT_LIST_HEAD(&page->list);
 485         RX_USED_SET(page, 0);
 486         page->buffer = alloc_pages(flags, cp->page_order);
 487         if (!page->buffer)
 488                 goto page_err;
 489         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
 490                                       cp->page_size, PCI_DMA_FROMDEVICE);
 491         return page;
 492 
 493 page_err:
 494         kfree(page);
 495         return NULL;
 496 }
 497 
 498 /* initialize spare pool of rx buffers, but allocate during the open */
 499 static void cas_spare_init(struct cas *cp)
 500 {
 501         spin_lock(&cp->rx_inuse_lock);
 502         INIT_LIST_HEAD(&cp->rx_inuse_list);
 503         spin_unlock(&cp->rx_inuse_lock);
 504 
 505         spin_lock(&cp->rx_spare_lock);
 506         INIT_LIST_HEAD(&cp->rx_spare_list);
 507         cp->rx_spares_needed = RX_SPARE_COUNT;
 508         spin_unlock(&cp->rx_spare_lock);
 509 }
 510 
 511 /* used on close. free all the spare buffers. */
 512 static void cas_spare_free(struct cas *cp)
 513 {
 514         struct list_head list, *elem, *tmp;
 515 
 516         /* free spare buffers */
 517         INIT_LIST_HEAD(&list);
 518         spin_lock(&cp->rx_spare_lock);
 519         list_splice_init(&cp->rx_spare_list, &list);
 520         spin_unlock(&cp->rx_spare_lock);
 521         list_for_each_safe(elem, tmp, &list) {
 522                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
 523         }
 524 
 525         INIT_LIST_HEAD(&list);
 526 #if 1
 527         /*
 528          * Looks like Adrian had protected this with a different
 529          * lock than used everywhere else to manipulate this list.
 530          */
 531         spin_lock(&cp->rx_inuse_lock);
 532         list_splice_init(&cp->rx_inuse_list, &list);
 533         spin_unlock(&cp->rx_inuse_lock);
 534 #else
 535         spin_lock(&cp->rx_spare_lock);
 536         list_splice_init(&cp->rx_inuse_list, &list);
 537         spin_unlock(&cp->rx_spare_lock);
 538 #endif
 539         list_for_each_safe(elem, tmp, &list) {
 540                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
 541         }
 542 }
 543 
 544 /* replenish spares if needed */
 545 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
 546 {
 547         struct list_head list, *elem, *tmp;
 548         int needed, i;
 549 
 550         /* check inuse list. if we don't need any more free buffers,
 551          * just free it
 552          */
 553 
 554         /* make a local copy of the list */
 555         INIT_LIST_HEAD(&list);
 556         spin_lock(&cp->rx_inuse_lock);
 557         list_splice_init(&cp->rx_inuse_list, &list);
 558         spin_unlock(&cp->rx_inuse_lock);
 559 
 560         list_for_each_safe(elem, tmp, &list) {
 561                 cas_page_t *page = list_entry(elem, cas_page_t, list);
 562 
 563                 /*
 564                  * With the lockless pagecache, cassini buffering scheme gets
 565                  * slightly less accurate: we might find that a page has an
 566                  * elevated reference count here, due to a speculative ref,
 567                  * and skip it as in-use. Ideally we would be able to reclaim
 568                  * it. However this would be such a rare case, it doesn't
 569                  * matter too much as we should pick it up the next time round.
 570                  *
 571                  * Importantly, if we find that the page has a refcount of 1
 572                  * here (our refcount), then we know it is definitely not inuse
 573                  * so we can reuse it.
 574                  */
 575                 if (page_count(page->buffer) > 1)
 576                         continue;
 577 
 578                 list_del(elem);
 579                 spin_lock(&cp->rx_spare_lock);
 580                 if (cp->rx_spares_needed > 0) {
 581                         list_add(elem, &cp->rx_spare_list);
 582                         cp->rx_spares_needed--;
 583                         spin_unlock(&cp->rx_spare_lock);
 584                 } else {
 585                         spin_unlock(&cp->rx_spare_lock);
 586                         cas_page_free(cp, page);
 587                 }
 588         }
 589 
 590         /* put any inuse buffers back on the list */
 591         if (!list_empty(&list)) {
 592                 spin_lock(&cp->rx_inuse_lock);
 593                 list_splice(&list, &cp->rx_inuse_list);
 594                 spin_unlock(&cp->rx_inuse_lock);
 595         }
 596 
 597         spin_lock(&cp->rx_spare_lock);
 598         needed = cp->rx_spares_needed;
 599         spin_unlock(&cp->rx_spare_lock);
 600         if (!needed)
 601                 return;
 602 
 603         /* we still need spares, so try to allocate some */
 604         INIT_LIST_HEAD(&list);
 605         i = 0;
 606         while (i < needed) {
 607                 cas_page_t *spare = cas_page_alloc(cp, flags);
 608                 if (!spare)
 609                         break;
 610                 list_add(&spare->list, &list);
 611                 i++;
 612         }
 613 
 614         spin_lock(&cp->rx_spare_lock);
 615         list_splice(&list, &cp->rx_spare_list);
 616         cp->rx_spares_needed -= i;
 617         spin_unlock(&cp->rx_spare_lock);
 618 }
 619 
 620 /* pull a page from the list. */
 621 static cas_page_t *cas_page_dequeue(struct cas *cp)
 622 {
 623         struct list_head *entry;
 624         int recover;
 625 
 626         spin_lock(&cp->rx_spare_lock);
 627         if (list_empty(&cp->rx_spare_list)) {
 628                 /* try to do a quick recovery */
 629                 spin_unlock(&cp->rx_spare_lock);
 630                 cas_spare_recover(cp, GFP_ATOMIC);
 631                 spin_lock(&cp->rx_spare_lock);
 632                 if (list_empty(&cp->rx_spare_list)) {
 633                         netif_err(cp, rx_err, cp->dev,
 634                                   "no spare buffers available\n");
 635                         spin_unlock(&cp->rx_spare_lock);
 636                         return NULL;
 637                 }
 638         }
 639 
 640         entry = cp->rx_spare_list.next;
 641         list_del(entry);
 642         recover = ++cp->rx_spares_needed;
 643         spin_unlock(&cp->rx_spare_lock);
 644 
 645         /* trigger the timer to do the recovery */
 646         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
 647 #if 1
 648                 atomic_inc(&cp->reset_task_pending);
 649                 atomic_inc(&cp->reset_task_pending_spare);
 650                 schedule_work(&cp->reset_task);
 651 #else
 652                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
 653                 schedule_work(&cp->reset_task);
 654 #endif
 655         }
 656         return list_entry(entry, cas_page_t, list);
 657 }
 658 
 659 
 660 static void cas_mif_poll(struct cas *cp, const int enable)
 661 {
 662         u32 cfg;
 663 
 664         cfg  = readl(cp->regs + REG_MIF_CFG);
 665         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
 666 
 667         if (cp->phy_type & CAS_PHY_MII_MDIO1)
 668                 cfg |= MIF_CFG_PHY_SELECT;
 669 
 670         /* poll and interrupt on link status change. */
 671         if (enable) {
 672                 cfg |= MIF_CFG_POLL_EN;
 673                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
 674                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
 675         }
 676         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
 677                cp->regs + REG_MIF_MASK);
 678         writel(cfg, cp->regs + REG_MIF_CFG);
 679 }
 680 
 681 /* Must be invoked under cp->lock */
 682 static void cas_begin_auto_negotiation(struct cas *cp,
 683                                        const struct ethtool_link_ksettings *ep)
 684 {
 685         u16 ctl;
 686 #if 1
 687         int lcntl;
 688         int changed = 0;
 689         int oldstate = cp->lstate;
 690         int link_was_not_down = !(oldstate == link_down);
 691 #endif
 692         /* Setup link parameters */
 693         if (!ep)
 694                 goto start_aneg;
 695         lcntl = cp->link_cntl;
 696         if (ep->base.autoneg == AUTONEG_ENABLE) {
 697                 cp->link_cntl = BMCR_ANENABLE;
 698         } else {
 699                 u32 speed = ep->base.speed;
 700                 cp->link_cntl = 0;
 701                 if (speed == SPEED_100)
 702                         cp->link_cntl |= BMCR_SPEED100;
 703                 else if (speed == SPEED_1000)
 704                         cp->link_cntl |= CAS_BMCR_SPEED1000;
 705                 if (ep->base.duplex == DUPLEX_FULL)
 706                         cp->link_cntl |= BMCR_FULLDPLX;
 707         }
 708 #if 1
 709         changed = (lcntl != cp->link_cntl);
 710 #endif
 711 start_aneg:
 712         if (cp->lstate == link_up) {
 713                 netdev_info(cp->dev, "PCS link down\n");
 714         } else {
 715                 if (changed) {
 716                         netdev_info(cp->dev, "link configuration changed\n");
 717                 }
 718         }
 719         cp->lstate = link_down;
 720         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
 721         if (!cp->hw_running)
 722                 return;
 723 #if 1
 724         /*
 725          * WTZ: If the old state was link_up, we turn off the carrier
 726          * to replicate everything we do elsewhere on a link-down
 727          * event when we were already in a link-up state..
 728          */
 729         if (oldstate == link_up)
 730                 netif_carrier_off(cp->dev);
 731         if (changed  && link_was_not_down) {
 732                 /*
 733                  * WTZ: This branch will simply schedule a full reset after
 734                  * we explicitly changed link modes in an ioctl. See if this
 735                  * fixes the link-problems we were having for forced mode.
 736                  */
 737                 atomic_inc(&cp->reset_task_pending);
 738                 atomic_inc(&cp->reset_task_pending_all);
 739                 schedule_work(&cp->reset_task);
 740                 cp->timer_ticks = 0;
 741                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
 742                 return;
 743         }
 744 #endif
 745         if (cp->phy_type & CAS_PHY_SERDES) {
 746                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
 747 
 748                 if (cp->link_cntl & BMCR_ANENABLE) {
 749                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
 750                         cp->lstate = link_aneg;
 751                 } else {
 752                         if (cp->link_cntl & BMCR_FULLDPLX)
 753                                 val |= PCS_MII_CTRL_DUPLEX;
 754                         val &= ~PCS_MII_AUTONEG_EN;
 755                         cp->lstate = link_force_ok;
 756                 }
 757                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
 758                 writel(val, cp->regs + REG_PCS_MII_CTRL);
 759 
 760         } else {
 761                 cas_mif_poll(cp, 0);
 762                 ctl = cas_phy_read(cp, MII_BMCR);
 763                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
 764                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
 765                 ctl |= cp->link_cntl;
 766                 if (ctl & BMCR_ANENABLE) {
 767                         ctl |= BMCR_ANRESTART;
 768                         cp->lstate = link_aneg;
 769                 } else {
 770                         cp->lstate = link_force_ok;
 771                 }
 772                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
 773                 cas_phy_write(cp, MII_BMCR, ctl);
 774                 cas_mif_poll(cp, 1);
 775         }
 776 
 777         cp->timer_ticks = 0;
 778         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
 779 }
 780 
 781 /* Must be invoked under cp->lock. */
 782 static int cas_reset_mii_phy(struct cas *cp)
 783 {
 784         int limit = STOP_TRIES_PHY;
 785         u16 val;
 786 
 787         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
 788         udelay(100);
 789         while (--limit) {
 790                 val = cas_phy_read(cp, MII_BMCR);
 791                 if ((val & BMCR_RESET) == 0)
 792                         break;
 793                 udelay(10);
 794         }
 795         return limit <= 0;
 796 }
 797 
 798 static void cas_saturn_firmware_init(struct cas *cp)
 799 {
 800         const struct firmware *fw;
 801         const char fw_name[] = "sun/cassini.bin";
 802         int err;
 803 
 804         if (PHY_NS_DP83065 != cp->phy_id)
 805                 return;
 806 
 807         err = request_firmware(&fw, fw_name, &cp->pdev->dev);
 808         if (err) {
 809                 pr_err("Failed to load firmware \"%s\"\n",
 810                        fw_name);
 811                 return;
 812         }
 813         if (fw->size < 2) {
 814                 pr_err("bogus length %zu in \"%s\"\n",
 815                        fw->size, fw_name);
 816                 goto out;
 817         }
 818         cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
 819         cp->fw_size = fw->size - 2;
 820         cp->fw_data = vmalloc(cp->fw_size);
 821         if (!cp->fw_data)
 822                 goto out;
 823         memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
 824 out:
 825         release_firmware(fw);
 826 }
 827 
 828 static void cas_saturn_firmware_load(struct cas *cp)
 829 {
 830         int i;
 831 
 832         if (!cp->fw_data)
 833                 return;
 834 
 835         cas_phy_powerdown(cp);
 836 
 837         /* expanded memory access mode */
 838         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
 839 
 840         /* pointer configuration for new firmware */
 841         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
 842         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
 843         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
 844         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
 845         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
 846         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
 847         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
 848         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
 849 
 850         /* download new firmware */
 851         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
 852         cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
 853         for (i = 0; i < cp->fw_size; i++)
 854                 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
 855 
 856         /* enable firmware */
 857         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
 858         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
 859 }
 860 
 861 
 862 /* phy initialization */
 863 static void cas_phy_init(struct cas *cp)
 864 {
 865         u16 val;
 866 
 867         /* if we're in MII/GMII mode, set up phy */
 868         if (CAS_PHY_MII(cp->phy_type)) {
 869                 writel(PCS_DATAPATH_MODE_MII,
 870                        cp->regs + REG_PCS_DATAPATH_MODE);
 871 
 872                 cas_mif_poll(cp, 0);
 873                 cas_reset_mii_phy(cp); /* take out of isolate mode */
 874 
 875                 if (PHY_LUCENT_B0 == cp->phy_id) {
 876                         /* workaround link up/down issue with lucent */
 877                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
 878                         cas_phy_write(cp, MII_BMCR, 0x00f1);
 879                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
 880 
 881                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
 882                         /* workarounds for broadcom phy */
 883                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
 884                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
 885                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
 886                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
 887                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
 888                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
 889                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
 890                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
 891                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
 892                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
 893                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
 894 
 895                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
 896                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
 897                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
 898                         if (val & 0x0080) {
 899                                 /* link workaround */
 900                                 cas_phy_write(cp, BROADCOM_MII_REG4,
 901                                               val & ~0x0080);
 902                         }
 903 
 904                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
 905                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
 906                                SATURN_PCFG_FSI : 0x0,
 907                                cp->regs + REG_SATURN_PCFG);
 908 
 909                         /* load firmware to address 10Mbps auto-negotiation
 910                          * issue. NOTE: this will need to be changed if the
 911                          * default firmware gets fixed.
 912                          */
 913                         if (PHY_NS_DP83065 == cp->phy_id) {
 914                                 cas_saturn_firmware_load(cp);
 915                         }
 916                         cas_phy_powerup(cp);
 917                 }
 918 
 919                 /* advertise capabilities */
 920                 val = cas_phy_read(cp, MII_BMCR);
 921                 val &= ~BMCR_ANENABLE;
 922                 cas_phy_write(cp, MII_BMCR, val);
 923                 udelay(10);
 924 
 925                 cas_phy_write(cp, MII_ADVERTISE,
 926                               cas_phy_read(cp, MII_ADVERTISE) |
 927                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
 928                                ADVERTISE_100HALF | ADVERTISE_100FULL |
 929                                CAS_ADVERTISE_PAUSE |
 930                                CAS_ADVERTISE_ASYM_PAUSE));
 931 
 932                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
 933                         /* make sure that we don't advertise half
 934                          * duplex to avoid a chip issue
 935                          */
 936                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
 937                         val &= ~CAS_ADVERTISE_1000HALF;
 938                         val |= CAS_ADVERTISE_1000FULL;
 939                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
 940                 }
 941 
 942         } else {
 943                 /* reset pcs for serdes */
 944                 u32 val;
 945                 int limit;
 946 
 947                 writel(PCS_DATAPATH_MODE_SERDES,
 948                        cp->regs + REG_PCS_DATAPATH_MODE);
 949 
 950                 /* enable serdes pins on saturn */
 951                 if (cp->cas_flags & CAS_FLAG_SATURN)
 952                         writel(0, cp->regs + REG_SATURN_PCFG);
 953 
 954                 /* Reset PCS unit. */
 955                 val = readl(cp->regs + REG_PCS_MII_CTRL);
 956                 val |= PCS_MII_RESET;
 957                 writel(val, cp->regs + REG_PCS_MII_CTRL);
 958 
 959                 limit = STOP_TRIES;
 960                 while (--limit > 0) {
 961                         udelay(10);
 962                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
 963                              PCS_MII_RESET) == 0)
 964                                 break;
 965                 }
 966                 if (limit <= 0)
 967                         netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
 968                                     readl(cp->regs + REG_PCS_STATE_MACHINE));
 969 
 970                 /* Make sure PCS is disabled while changing advertisement
 971                  * configuration.
 972                  */
 973                 writel(0x0, cp->regs + REG_PCS_CFG);
 974 
 975                 /* Advertise all capabilities except half-duplex. */
 976                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
 977                 val &= ~PCS_MII_ADVERT_HD;
 978                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
 979                         PCS_MII_ADVERT_ASYM_PAUSE);
 980                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
 981 
 982                 /* enable PCS */
 983                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
 984 
 985                 /* pcs workaround: enable sync detect */
 986                 writel(PCS_SERDES_CTRL_SYNCD_EN,
 987                        cp->regs + REG_PCS_SERDES_CTRL);
 988         }
 989 }
 990 
 991 
 992 static int cas_pcs_link_check(struct cas *cp)
 993 {
 994         u32 stat, state_machine;
 995         int retval = 0;
 996 
 997         /* The link status bit latches on zero, so you must
 998          * read it twice in such a case to see a transition
 999          * to the link being up.
1000          */
1001         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1002         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1003                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1004 
1005         /* The remote-fault indication is only valid
1006          * when autoneg has completed.
1007          */
1008         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1009                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1010             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1011                 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1012 
1013         /* work around link detection issue by querying the PCS state
1014          * machine directly.
1015          */
1016         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1017         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1018                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1019         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1020                 stat |= PCS_MII_STATUS_LINK_STATUS;
1021         }
1022 
1023         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1024                 if (cp->lstate != link_up) {
1025                         if (cp->opened) {
1026                                 cp->lstate = link_up;
1027                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1028 
1029                                 cas_set_link_modes(cp);
1030                                 netif_carrier_on(cp->dev);
1031                         }
1032                 }
1033         } else if (cp->lstate == link_up) {
1034                 cp->lstate = link_down;
1035                 if (link_transition_timeout != 0 &&
1036                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1037                     !cp->link_transition_jiffies_valid) {
1038                         /*
1039                          * force a reset, as a workaround for the
1040                          * link-failure problem. May want to move this to a
1041                          * point a bit earlier in the sequence. If we had
1042                          * generated a reset a short time ago, we'll wait for
1043                          * the link timer to check the status until a
1044                          * timer expires (link_transistion_jiffies_valid is
1045                          * true when the timer is running.)  Instead of using
1046                          * a system timer, we just do a check whenever the
1047                          * link timer is running - this clears the flag after
1048                          * a suitable delay.
1049                          */
1050                         retval = 1;
1051                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1052                         cp->link_transition_jiffies = jiffies;
1053                         cp->link_transition_jiffies_valid = 1;
1054                 } else {
1055                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1056                 }
1057                 netif_carrier_off(cp->dev);
1058                 if (cp->opened)
1059                         netif_info(cp, link, cp->dev, "PCS link down\n");
1060 
1061                 /* Cassini only: if you force a mode, there can be
1062                  * sync problems on link down. to fix that, the following
1063                  * things need to be checked:
1064                  * 1) read serialink state register
1065                  * 2) read pcs status register to verify link down.
1066                  * 3) if link down and serial link == 0x03, then you need
1067                  *    to global reset the chip.
1068                  */
1069                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1070                         /* should check to see if we're in a forced mode */
1071                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1072                         if (stat == 0x03)
1073                                 return 1;
1074                 }
1075         } else if (cp->lstate == link_down) {
1076                 if (link_transition_timeout != 0 &&
1077                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1078                     !cp->link_transition_jiffies_valid) {
1079                         /* force a reset, as a workaround for the
1080                          * link-failure problem.  May want to move
1081                          * this to a point a bit earlier in the
1082                          * sequence.
1083                          */
1084                         retval = 1;
1085                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1086                         cp->link_transition_jiffies = jiffies;
1087                         cp->link_transition_jiffies_valid = 1;
1088                 } else {
1089                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1090                 }
1091         }
1092 
1093         return retval;
1094 }
1095 
1096 static int cas_pcs_interrupt(struct net_device *dev,
1097                              struct cas *cp, u32 status)
1098 {
1099         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1100 
1101         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1102                 return 0;
1103         return cas_pcs_link_check(cp);
1104 }
1105 
1106 static int cas_txmac_interrupt(struct net_device *dev,
1107                                struct cas *cp, u32 status)
1108 {
1109         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1110 
1111         if (!txmac_stat)
1112                 return 0;
1113 
1114         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1115                      "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1116 
1117         /* Defer timer expiration is quite normal,
1118          * don't even log the event.
1119          */
1120         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1121             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1122                 return 0;
1123 
1124         spin_lock(&cp->stat_lock[0]);
1125         if (txmac_stat & MAC_TX_UNDERRUN) {
1126                 netdev_err(dev, "TX MAC xmit underrun\n");
1127                 cp->net_stats[0].tx_fifo_errors++;
1128         }
1129 
1130         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1131                 netdev_err(dev, "TX MAC max packet size error\n");
1132                 cp->net_stats[0].tx_errors++;
1133         }
1134 
1135         /* The rest are all cases of one of the 16-bit TX
1136          * counters expiring.
1137          */
1138         if (txmac_stat & MAC_TX_COLL_NORMAL)
1139                 cp->net_stats[0].collisions += 0x10000;
1140 
1141         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1142                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1143                 cp->net_stats[0].collisions += 0x10000;
1144         }
1145 
1146         if (txmac_stat & MAC_TX_COLL_LATE) {
1147                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1148                 cp->net_stats[0].collisions += 0x10000;
1149         }
1150         spin_unlock(&cp->stat_lock[0]);
1151 
1152         /* We do not keep track of MAC_TX_COLL_FIRST and
1153          * MAC_TX_PEAK_ATTEMPTS events.
1154          */
1155         return 0;
1156 }
1157 
1158 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1159 {
1160         cas_hp_inst_t *inst;
1161         u32 val;
1162         int i;
1163 
1164         i = 0;
1165         while ((inst = firmware) && inst->note) {
1166                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1167 
1168                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1169                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1170                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1171 
1172                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1173                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1174                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1175                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1176                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1177                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1178                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1179                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1180 
1181                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1182                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1183                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1184                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1185                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1186                 ++firmware;
1187                 ++i;
1188         }
1189 }
1190 
1191 static void cas_init_rx_dma(struct cas *cp)
1192 {
1193         u64 desc_dma = cp->block_dvma;
1194         u32 val;
1195         int i, size;
1196 
1197         /* rx free descriptors */
1198         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1199         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1200         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1201         if ((N_RX_DESC_RINGS > 1) &&
1202             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1203                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1204         writel(val, cp->regs + REG_RX_CFG);
1205 
1206         val = (unsigned long) cp->init_rxds[0] -
1207                 (unsigned long) cp->init_block;
1208         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1209         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1210         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1211 
1212         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1213                 /* rx desc 2 is for IPSEC packets. however,
1214                  * we don't it that for that purpose.
1215                  */
1216                 val = (unsigned long) cp->init_rxds[1] -
1217                         (unsigned long) cp->init_block;
1218                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1219                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1220                        REG_PLUS_RX_DB1_LOW);
1221                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1222                        REG_PLUS_RX_KICK1);
1223         }
1224 
1225         /* rx completion registers */
1226         val = (unsigned long) cp->init_rxcs[0] -
1227                 (unsigned long) cp->init_block;
1228         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1229         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1230 
1231         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1232                 /* rx comp 2-4 */
1233                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1234                         val = (unsigned long) cp->init_rxcs[i] -
1235                                 (unsigned long) cp->init_block;
1236                         writel((desc_dma + val) >> 32, cp->regs +
1237                                REG_PLUS_RX_CBN_HI(i));
1238                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1239                                REG_PLUS_RX_CBN_LOW(i));
1240                 }
1241         }
1242 
1243         /* read selective clear regs to prevent spurious interrupts
1244          * on reset because complete == kick.
1245          * selective clear set up to prevent interrupts on resets
1246          */
1247         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1248         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1249         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1250                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1251                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1252 
1253                 /* 2 is different from 3 and 4 */
1254                 if (N_RX_COMP_RINGS > 1)
1255                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1256                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1257 
1258                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1259                         writel(INTR_RX_DONE_ALT,
1260                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1261         }
1262 
1263         /* set up pause thresholds */
1264         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1265                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1266         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1267                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1268         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1269 
1270         /* zero out dma reassembly buffers */
1271         for (i = 0; i < 64; i++) {
1272                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1273                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1274                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1275                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1276         }
1277 
1278         /* make sure address register is 0 for normal operation */
1279         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1280         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1281 
1282         /* interrupt mitigation */
1283 #ifdef USE_RX_BLANK
1284         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1285         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1286         writel(val, cp->regs + REG_RX_BLANK);
1287 #else
1288         writel(0x0, cp->regs + REG_RX_BLANK);
1289 #endif
1290 
1291         /* interrupt generation as a function of low water marks for
1292          * free desc and completion entries. these are used to trigger
1293          * housekeeping for rx descs. we don't use the free interrupt
1294          * as it's not very useful
1295          */
1296         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1297         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1298         writel(val, cp->regs + REG_RX_AE_THRESH);
1299         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1300                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1301                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1302         }
1303 
1304         /* Random early detect registers. useful for congestion avoidance.
1305          * this should be tunable.
1306          */
1307         writel(0x0, cp->regs + REG_RX_RED);
1308 
1309         /* receive page sizes. default == 2K (0x800) */
1310         val = 0;
1311         if (cp->page_size == 0x1000)
1312                 val = 0x1;
1313         else if (cp->page_size == 0x2000)
1314                 val = 0x2;
1315         else if (cp->page_size == 0x4000)
1316                 val = 0x3;
1317 
1318         /* round mtu + offset. constrain to page size. */
1319         size = cp->dev->mtu + 64;
1320         if (size > cp->page_size)
1321                 size = cp->page_size;
1322 
1323         if (size <= 0x400)
1324                 i = 0x0;
1325         else if (size <= 0x800)
1326                 i = 0x1;
1327         else if (size <= 0x1000)
1328                 i = 0x2;
1329         else
1330                 i = 0x3;
1331 
1332         cp->mtu_stride = 1 << (i + 10);
1333         val  = CAS_BASE(RX_PAGE_SIZE, val);
1334         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1335         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1336         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1337         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1338 
1339         /* enable the header parser if desired */
1340         if (CAS_HP_FIRMWARE == cas_prog_null)
1341                 return;
1342 
1343         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1344         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1345         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1346         writel(val, cp->regs + REG_HP_CFG);
1347 }
1348 
1349 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1350 {
1351         memset(rxc, 0, sizeof(*rxc));
1352         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1353 }
1354 
1355 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1356  * flipping is protected by the fact that the chip will not
1357  * hand back the same page index while it's being processed.
1358  */
1359 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1360 {
1361         cas_page_t *page = cp->rx_pages[1][index];
1362         cas_page_t *new;
1363 
1364         if (page_count(page->buffer) == 1)
1365                 return page;
1366 
1367         new = cas_page_dequeue(cp);
1368         if (new) {
1369                 spin_lock(&cp->rx_inuse_lock);
1370                 list_add(&page->list, &cp->rx_inuse_list);
1371                 spin_unlock(&cp->rx_inuse_lock);
1372         }
1373         return new;
1374 }
1375 
1376 /* this needs to be changed if we actually use the ENC RX DESC ring */
1377 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1378                                  const int index)
1379 {
1380         cas_page_t **page0 = cp->rx_pages[0];
1381         cas_page_t **page1 = cp->rx_pages[1];
1382 
1383         /* swap if buffer is in use */
1384         if (page_count(page0[index]->buffer) > 1) {
1385                 cas_page_t *new = cas_page_spare(cp, index);
1386                 if (new) {
1387                         page1[index] = page0[index];
1388                         page0[index] = new;
1389                 }
1390         }
1391         RX_USED_SET(page0[index], 0);
1392         return page0[index];
1393 }
1394 
1395 static void cas_clean_rxds(struct cas *cp)
1396 {
1397         /* only clean ring 0 as ring 1 is used for spare buffers */
1398         struct cas_rx_desc *rxd = cp->init_rxds[0];
1399         int i, size;
1400 
1401         /* release all rx flows */
1402         for (i = 0; i < N_RX_FLOWS; i++) {
1403                 struct sk_buff *skb;
1404                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1405                         cas_skb_release(skb);
1406                 }
1407         }
1408 
1409         /* initialize descriptors */
1410         size = RX_DESC_RINGN_SIZE(0);
1411         for (i = 0; i < size; i++) {
1412                 cas_page_t *page = cas_page_swap(cp, 0, i);
1413                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1414                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1415                                             CAS_BASE(RX_INDEX_RING, 0));
1416         }
1417 
1418         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1419         cp->rx_last[0] = 0;
1420         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1421 }
1422 
1423 static void cas_clean_rxcs(struct cas *cp)
1424 {
1425         int i, j;
1426 
1427         /* take ownership of rx comp descriptors */
1428         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1429         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1430         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1431                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1432                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1433                         cas_rxc_init(rxc + j);
1434                 }
1435         }
1436 }
1437 
1438 #if 0
1439 /* When we get a RX fifo overflow, the RX unit is probably hung
1440  * so we do the following.
1441  *
1442  * If any part of the reset goes wrong, we return 1 and that causes the
1443  * whole chip to be reset.
1444  */
1445 static int cas_rxmac_reset(struct cas *cp)
1446 {
1447         struct net_device *dev = cp->dev;
1448         int limit;
1449         u32 val;
1450 
1451         /* First, reset MAC RX. */
1452         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1453         for (limit = 0; limit < STOP_TRIES; limit++) {
1454                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1455                         break;
1456                 udelay(10);
1457         }
1458         if (limit == STOP_TRIES) {
1459                 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1460                 return 1;
1461         }
1462 
1463         /* Second, disable RX DMA. */
1464         writel(0, cp->regs + REG_RX_CFG);
1465         for (limit = 0; limit < STOP_TRIES; limit++) {
1466                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1467                         break;
1468                 udelay(10);
1469         }
1470         if (limit == STOP_TRIES) {
1471                 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1472                 return 1;
1473         }
1474 
1475         mdelay(5);
1476 
1477         /* Execute RX reset command. */
1478         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1479         for (limit = 0; limit < STOP_TRIES; limit++) {
1480                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1481                         break;
1482                 udelay(10);
1483         }
1484         if (limit == STOP_TRIES) {
1485                 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1486                 return 1;
1487         }
1488 
1489         /* reset driver rx state */
1490         cas_clean_rxds(cp);
1491         cas_clean_rxcs(cp);
1492 
1493         /* Now, reprogram the rest of RX unit. */
1494         cas_init_rx_dma(cp);
1495 
1496         /* re-enable */
1497         val = readl(cp->regs + REG_RX_CFG);
1498         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1499         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1500         val = readl(cp->regs + REG_MAC_RX_CFG);
1501         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1502         return 0;
1503 }
1504 #endif
1505 
1506 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1507                                u32 status)
1508 {
1509         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1510 
1511         if (!stat)
1512                 return 0;
1513 
1514         netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1515 
1516         /* these are all rollovers */
1517         spin_lock(&cp->stat_lock[0]);
1518         if (stat & MAC_RX_ALIGN_ERR)
1519                 cp->net_stats[0].rx_frame_errors += 0x10000;
1520 
1521         if (stat & MAC_RX_CRC_ERR)
1522                 cp->net_stats[0].rx_crc_errors += 0x10000;
1523 
1524         if (stat & MAC_RX_LEN_ERR)
1525                 cp->net_stats[0].rx_length_errors += 0x10000;
1526 
1527         if (stat & MAC_RX_OVERFLOW) {
1528                 cp->net_stats[0].rx_over_errors++;
1529                 cp->net_stats[0].rx_fifo_errors++;
1530         }
1531 
1532         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1533          * events.
1534          */
1535         spin_unlock(&cp->stat_lock[0]);
1536         return 0;
1537 }
1538 
1539 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1540                              u32 status)
1541 {
1542         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1543 
1544         if (!stat)
1545                 return 0;
1546 
1547         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1548                      "mac interrupt, stat: 0x%x\n", stat);
1549 
1550         /* This interrupt is just for pause frame and pause
1551          * tracking.  It is useful for diagnostics and debug
1552          * but probably by default we will mask these events.
1553          */
1554         if (stat & MAC_CTRL_PAUSE_STATE)
1555                 cp->pause_entered++;
1556 
1557         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1558                 cp->pause_last_time_recvd = (stat >> 16);
1559 
1560         return 0;
1561 }
1562 
1563 
1564 /* Must be invoked under cp->lock. */
1565 static inline int cas_mdio_link_not_up(struct cas *cp)
1566 {
1567         u16 val;
1568 
1569         switch (cp->lstate) {
1570         case link_force_ret:
1571                 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1572                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1573                 cp->timer_ticks = 5;
1574                 cp->lstate = link_force_ok;
1575                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1576                 break;
1577 
1578         case link_aneg:
1579                 val = cas_phy_read(cp, MII_BMCR);
1580 
1581                 /* Try forced modes. we try things in the following order:
1582                  * 1000 full -> 100 full/half -> 10 half
1583                  */
1584                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1585                 val |= BMCR_FULLDPLX;
1586                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1587                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1588                 cas_phy_write(cp, MII_BMCR, val);
1589                 cp->timer_ticks = 5;
1590                 cp->lstate = link_force_try;
1591                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1592                 break;
1593 
1594         case link_force_try:
1595                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1596                 val = cas_phy_read(cp, MII_BMCR);
1597                 cp->timer_ticks = 5;
1598                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1599                         val &= ~CAS_BMCR_SPEED1000;
1600                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1601                         cas_phy_write(cp, MII_BMCR, val);
1602                         break;
1603                 }
1604 
1605                 if (val & BMCR_SPEED100) {
1606                         if (val & BMCR_FULLDPLX) /* fd failed */
1607                                 val &= ~BMCR_FULLDPLX;
1608                         else { /* 100Mbps failed */
1609                                 val &= ~BMCR_SPEED100;
1610                         }
1611                         cas_phy_write(cp, MII_BMCR, val);
1612                         break;
1613                 }
1614         default:
1615                 break;
1616         }
1617         return 0;
1618 }
1619 
1620 
1621 /* must be invoked with cp->lock held */
1622 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1623 {
1624         int restart;
1625 
1626         if (bmsr & BMSR_LSTATUS) {
1627                 /* Ok, here we got a link. If we had it due to a forced
1628                  * fallback, and we were configured for autoneg, we
1629                  * retry a short autoneg pass. If you know your hub is
1630                  * broken, use ethtool ;)
1631                  */
1632                 if ((cp->lstate == link_force_try) &&
1633                     (cp->link_cntl & BMCR_ANENABLE)) {
1634                         cp->lstate = link_force_ret;
1635                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1636                         cas_mif_poll(cp, 0);
1637                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1638                         cp->timer_ticks = 5;
1639                         if (cp->opened)
1640                                 netif_info(cp, link, cp->dev,
1641                                            "Got link after fallback, retrying autoneg once...\n");
1642                         cas_phy_write(cp, MII_BMCR,
1643                                       cp->link_fcntl | BMCR_ANENABLE |
1644                                       BMCR_ANRESTART);
1645                         cas_mif_poll(cp, 1);
1646 
1647                 } else if (cp->lstate != link_up) {
1648                         cp->lstate = link_up;
1649                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1650 
1651                         if (cp->opened) {
1652                                 cas_set_link_modes(cp);
1653                                 netif_carrier_on(cp->dev);
1654                         }
1655                 }
1656                 return 0;
1657         }
1658 
1659         /* link not up. if the link was previously up, we restart the
1660          * whole process
1661          */
1662         restart = 0;
1663         if (cp->lstate == link_up) {
1664                 cp->lstate = link_down;
1665                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1666 
1667                 netif_carrier_off(cp->dev);
1668                 if (cp->opened)
1669                         netif_info(cp, link, cp->dev, "Link down\n");
1670                 restart = 1;
1671 
1672         } else if (++cp->timer_ticks > 10)
1673                 cas_mdio_link_not_up(cp);
1674 
1675         return restart;
1676 }
1677 
1678 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1679                              u32 status)
1680 {
1681         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1682         u16 bmsr;
1683 
1684         /* check for a link change */
1685         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1686                 return 0;
1687 
1688         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1689         return cas_mii_link_check(cp, bmsr);
1690 }
1691 
1692 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1693                              u32 status)
1694 {
1695         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1696 
1697         if (!stat)
1698                 return 0;
1699 
1700         netdev_err(dev, "PCI error [%04x:%04x]",
1701                    stat, readl(cp->regs + REG_BIM_DIAG));
1702 
1703         /* cassini+ has this reserved */
1704         if ((stat & PCI_ERR_BADACK) &&
1705             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1706                 pr_cont(" <No ACK64# during ABS64 cycle>");
1707 
1708         if (stat & PCI_ERR_DTRTO)
1709                 pr_cont(" <Delayed transaction timeout>");
1710         if (stat & PCI_ERR_OTHER)
1711                 pr_cont(" <other>");
1712         if (stat & PCI_ERR_BIM_DMA_WRITE)
1713                 pr_cont(" <BIM DMA 0 write req>");
1714         if (stat & PCI_ERR_BIM_DMA_READ)
1715                 pr_cont(" <BIM DMA 0 read req>");
1716         pr_cont("\n");
1717 
1718         if (stat & PCI_ERR_OTHER) {
1719                 u16 cfg;
1720 
1721                 /* Interrogate PCI config space for the
1722                  * true cause.
1723                  */
1724                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1725                 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1726                 if (cfg & PCI_STATUS_PARITY)
1727                         netdev_err(dev, "PCI parity error detected\n");
1728                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1729                         netdev_err(dev, "PCI target abort\n");
1730                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1731                         netdev_err(dev, "PCI master acks target abort\n");
1732                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1733                         netdev_err(dev, "PCI master abort\n");
1734                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1735                         netdev_err(dev, "PCI system error SERR#\n");
1736                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1737                         netdev_err(dev, "PCI parity error\n");
1738 
1739                 /* Write the error bits back to clear them. */
1740                 cfg &= (PCI_STATUS_PARITY |
1741                         PCI_STATUS_SIG_TARGET_ABORT |
1742                         PCI_STATUS_REC_TARGET_ABORT |
1743                         PCI_STATUS_REC_MASTER_ABORT |
1744                         PCI_STATUS_SIG_SYSTEM_ERROR |
1745                         PCI_STATUS_DETECTED_PARITY);
1746                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1747         }
1748 
1749         /* For all PCI errors, we should reset the chip. */
1750         return 1;
1751 }
1752 
1753 /* All non-normal interrupt conditions get serviced here.
1754  * Returns non-zero if we should just exit the interrupt
1755  * handler right now (ie. if we reset the card which invalidates
1756  * all of the other original irq status bits).
1757  */
1758 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1759                             u32 status)
1760 {
1761         if (status & INTR_RX_TAG_ERROR) {
1762                 /* corrupt RX tag framing */
1763                 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1764                              "corrupt rx tag framing\n");
1765                 spin_lock(&cp->stat_lock[0]);
1766                 cp->net_stats[0].rx_errors++;
1767                 spin_unlock(&cp->stat_lock[0]);
1768                 goto do_reset;
1769         }
1770 
1771         if (status & INTR_RX_LEN_MISMATCH) {
1772                 /* length mismatch. */
1773                 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1774                              "length mismatch for rx frame\n");
1775                 spin_lock(&cp->stat_lock[0]);
1776                 cp->net_stats[0].rx_errors++;
1777                 spin_unlock(&cp->stat_lock[0]);
1778                 goto do_reset;
1779         }
1780 
1781         if (status & INTR_PCS_STATUS) {
1782                 if (cas_pcs_interrupt(dev, cp, status))
1783                         goto do_reset;
1784         }
1785 
1786         if (status & INTR_TX_MAC_STATUS) {
1787                 if (cas_txmac_interrupt(dev, cp, status))
1788                         goto do_reset;
1789         }
1790 
1791         if (status & INTR_RX_MAC_STATUS) {
1792                 if (cas_rxmac_interrupt(dev, cp, status))
1793                         goto do_reset;
1794         }
1795 
1796         if (status & INTR_MAC_CTRL_STATUS) {
1797                 if (cas_mac_interrupt(dev, cp, status))
1798                         goto do_reset;
1799         }
1800 
1801         if (status & INTR_MIF_STATUS) {
1802                 if (cas_mif_interrupt(dev, cp, status))
1803                         goto do_reset;
1804         }
1805 
1806         if (status & INTR_PCI_ERROR_STATUS) {
1807                 if (cas_pci_interrupt(dev, cp, status))
1808                         goto do_reset;
1809         }
1810         return 0;
1811 
1812 do_reset:
1813 #if 1
1814         atomic_inc(&cp->reset_task_pending);
1815         atomic_inc(&cp->reset_task_pending_all);
1816         netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1817         schedule_work(&cp->reset_task);
1818 #else
1819         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1820         netdev_err(dev, "reset called in cas_abnormal_irq\n");
1821         schedule_work(&cp->reset_task);
1822 #endif
1823         return 1;
1824 }
1825 
1826 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1827  *       determining whether to do a netif_stop/wakeup
1828  */
1829 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1830 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1831 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1832                                   const int len)
1833 {
1834         unsigned long off = addr + len;
1835 
1836         if (CAS_TABORT(cp) == 1)
1837                 return 0;
1838         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1839                 return 0;
1840         return TX_TARGET_ABORT_LEN;
1841 }
1842 
1843 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1844 {
1845         struct cas_tx_desc *txds;
1846         struct sk_buff **skbs;
1847         struct net_device *dev = cp->dev;
1848         int entry, count;
1849 
1850         spin_lock(&cp->tx_lock[ring]);
1851         txds = cp->init_txds[ring];
1852         skbs = cp->tx_skbs[ring];
1853         entry = cp->tx_old[ring];
1854 
1855         count = TX_BUFF_COUNT(ring, entry, limit);
1856         while (entry != limit) {
1857                 struct sk_buff *skb = skbs[entry];
1858                 dma_addr_t daddr;
1859                 u32 dlen;
1860                 int frag;
1861 
1862                 if (!skb) {
1863                         /* this should never occur */
1864                         entry = TX_DESC_NEXT(ring, entry);
1865                         continue;
1866                 }
1867 
1868                 /* however, we might get only a partial skb release. */
1869                 count -= skb_shinfo(skb)->nr_frags +
1870                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1871                 if (count < 0)
1872                         break;
1873 
1874                 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1875                              "tx[%d] done, slot %d\n", ring, entry);
1876 
1877                 skbs[entry] = NULL;
1878                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1879 
1880                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1881                         struct cas_tx_desc *txd = txds + entry;
1882 
1883                         daddr = le64_to_cpu(txd->buffer);
1884                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1885                                        le64_to_cpu(txd->control));
1886                         pci_unmap_page(cp->pdev, daddr, dlen,
1887                                        PCI_DMA_TODEVICE);
1888                         entry = TX_DESC_NEXT(ring, entry);
1889 
1890                         /* tiny buffer may follow */
1891                         if (cp->tx_tiny_use[ring][entry].used) {
1892                                 cp->tx_tiny_use[ring][entry].used = 0;
1893                                 entry = TX_DESC_NEXT(ring, entry);
1894                         }
1895                 }
1896 
1897                 spin_lock(&cp->stat_lock[ring]);
1898                 cp->net_stats[ring].tx_packets++;
1899                 cp->net_stats[ring].tx_bytes += skb->len;
1900                 spin_unlock(&cp->stat_lock[ring]);
1901                 dev_consume_skb_irq(skb);
1902         }
1903         cp->tx_old[ring] = entry;
1904 
1905         /* this is wrong for multiple tx rings. the net device needs
1906          * multiple queues for this to do the right thing.  we wait
1907          * for 2*packets to be available when using tiny buffers
1908          */
1909         if (netif_queue_stopped(dev) &&
1910             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1911                 netif_wake_queue(dev);
1912         spin_unlock(&cp->tx_lock[ring]);
1913 }
1914 
1915 static void cas_tx(struct net_device *dev, struct cas *cp,
1916                    u32 status)
1917 {
1918         int limit, ring;
1919 #ifdef USE_TX_COMPWB
1920         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1921 #endif
1922         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1923                      "tx interrupt, status: 0x%x, %llx\n",
1924                      status, (unsigned long long)compwb);
1925         /* process all the rings */
1926         for (ring = 0; ring < N_TX_RINGS; ring++) {
1927 #ifdef USE_TX_COMPWB
1928                 /* use the completion writeback registers */
1929                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1930                         CAS_VAL(TX_COMPWB_LSB, compwb);
1931                 compwb = TX_COMPWB_NEXT(compwb);
1932 #else
1933                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1934 #endif
1935                 if (cp->tx_old[ring] != limit)
1936                         cas_tx_ringN(cp, ring, limit);
1937         }
1938 }
1939 
1940 
1941 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1942                               int entry, const u64 *words,
1943                               struct sk_buff **skbref)
1944 {
1945         int dlen, hlen, len, i, alloclen;
1946         int off, swivel = RX_SWIVEL_OFF_VAL;
1947         struct cas_page *page;
1948         struct sk_buff *skb;
1949         void *addr, *crcaddr;
1950         __sum16 csum;
1951         char *p;
1952 
1953         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1954         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1955         len  = hlen + dlen;
1956 
1957         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1958                 alloclen = len;
1959         else
1960                 alloclen = max(hlen, RX_COPY_MIN);
1961 
1962         skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1963         if (skb == NULL)
1964                 return -1;
1965 
1966         *skbref = skb;
1967         skb_reserve(skb, swivel);
1968 
1969         p = skb->data;
1970         addr = crcaddr = NULL;
1971         if (hlen) { /* always copy header pages */
1972                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1973                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1974                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1975                         swivel;
1976 
1977                 i = hlen;
1978                 if (!dlen) /* attach FCS */
1979                         i += cp->crc_size;
1980                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1981                                     PCI_DMA_FROMDEVICE);
1982                 addr = cas_page_map(page->buffer);
1983                 memcpy(p, addr + off, i);
1984                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1985                                     PCI_DMA_FROMDEVICE);
1986                 cas_page_unmap(addr);
1987                 RX_USED_ADD(page, 0x100);
1988                 p += hlen;
1989                 swivel = 0;
1990         }
1991 
1992 
1993         if (alloclen < (hlen + dlen)) {
1994                 skb_frag_t *frag = skb_shinfo(skb)->frags;
1995 
1996                 /* normal or jumbo packets. we use frags */
1997                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
1998                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1999                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2000 
2001                 hlen = min(cp->page_size - off, dlen);
2002                 if (hlen < 0) {
2003                         netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2004                                      "rx page overflow: %d\n", hlen);
2005                         dev_kfree_skb_irq(skb);
2006                         return -1;
2007                 }
2008                 i = hlen;
2009                 if (i == dlen)  /* attach FCS */
2010                         i += cp->crc_size;
2011                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2012                                     PCI_DMA_FROMDEVICE);
2013 
2014                 /* make sure we always copy a header */
2015                 swivel = 0;
2016                 if (p == (char *) skb->data) { /* not split */
2017                         addr = cas_page_map(page->buffer);
2018                         memcpy(p, addr + off, RX_COPY_MIN);
2019                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2020                                         PCI_DMA_FROMDEVICE);
2021                         cas_page_unmap(addr);
2022                         off += RX_COPY_MIN;
2023                         swivel = RX_COPY_MIN;
2024                         RX_USED_ADD(page, cp->mtu_stride);
2025                 } else {
2026                         RX_USED_ADD(page, hlen);
2027                 }
2028                 skb_put(skb, alloclen);
2029 
2030                 skb_shinfo(skb)->nr_frags++;
2031                 skb->data_len += hlen - swivel;
2032                 skb->truesize += hlen - swivel;
2033                 skb->len      += hlen - swivel;
2034 
2035                 __skb_frag_set_page(frag, page->buffer);
2036                 __skb_frag_ref(frag);
2037                 skb_frag_off_set(frag, off);
2038                 skb_frag_size_set(frag, hlen - swivel);
2039 
2040                 /* any more data? */
2041                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2042                         hlen = dlen;
2043                         off = 0;
2044 
2045                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2046                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2047                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2048                                             hlen + cp->crc_size,
2049                                             PCI_DMA_FROMDEVICE);
2050                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2051                                             hlen + cp->crc_size,
2052                                             PCI_DMA_FROMDEVICE);
2053 
2054                         skb_shinfo(skb)->nr_frags++;
2055                         skb->data_len += hlen;
2056                         skb->len      += hlen;
2057                         frag++;
2058 
2059                         __skb_frag_set_page(frag, page->buffer);
2060                         __skb_frag_ref(frag);
2061                         skb_frag_off_set(frag, 0);
2062                         skb_frag_size_set(frag, hlen);
2063                         RX_USED_ADD(page, hlen + cp->crc_size);
2064                 }
2065 
2066                 if (cp->crc_size) {
2067                         addr = cas_page_map(page->buffer);
2068                         crcaddr  = addr + off + hlen;
2069                 }
2070 
2071         } else {
2072                 /* copying packet */
2073                 if (!dlen)
2074                         goto end_copy_pkt;
2075 
2076                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2077                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2078                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2079                 hlen = min(cp->page_size - off, dlen);
2080                 if (hlen < 0) {
2081                         netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2082                                      "rx page overflow: %d\n", hlen);
2083                         dev_kfree_skb_irq(skb);
2084                         return -1;
2085                 }
2086                 i = hlen;
2087                 if (i == dlen) /* attach FCS */
2088                         i += cp->crc_size;
2089                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2090                                     PCI_DMA_FROMDEVICE);
2091                 addr = cas_page_map(page->buffer);
2092                 memcpy(p, addr + off, i);
2093                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2094                                     PCI_DMA_FROMDEVICE);
2095                 cas_page_unmap(addr);
2096                 if (p == (char *) skb->data) /* not split */
2097                         RX_USED_ADD(page, cp->mtu_stride);
2098                 else
2099                         RX_USED_ADD(page, i);
2100 
2101                 /* any more data? */
2102                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2103                         p += hlen;
2104                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2105                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2106                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2107                                             dlen + cp->crc_size,
2108                                             PCI_DMA_FROMDEVICE);
2109                         addr = cas_page_map(page->buffer);
2110                         memcpy(p, addr, dlen + cp->crc_size);
2111                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2112                                             dlen + cp->crc_size,
2113                                             PCI_DMA_FROMDEVICE);
2114                         cas_page_unmap(addr);
2115                         RX_USED_ADD(page, dlen + cp->crc_size);
2116                 }
2117 end_copy_pkt:
2118                 if (cp->crc_size) {
2119                         addr    = NULL;
2120                         crcaddr = skb->data + alloclen;
2121                 }
2122                 skb_put(skb, alloclen);
2123         }
2124 
2125         csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2126         if (cp->crc_size) {
2127                 /* checksum includes FCS. strip it out. */
2128                 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2129                                               csum_unfold(csum)));
2130                 if (addr)
2131                         cas_page_unmap(addr);
2132         }
2133         skb->protocol = eth_type_trans(skb, cp->dev);
2134         if (skb->protocol == htons(ETH_P_IP)) {
2135                 skb->csum = csum_unfold(~csum);
2136                 skb->ip_summed = CHECKSUM_COMPLETE;
2137         } else
2138                 skb_checksum_none_assert(skb);
2139         return len;
2140 }
2141 
2142 
2143 /* we can handle up to 64 rx flows at a time. we do the same thing
2144  * as nonreassm except that we batch up the buffers.
2145  * NOTE: we currently just treat each flow as a bunch of packets that
2146  *       we pass up. a better way would be to coalesce the packets
2147  *       into a jumbo packet. to do that, we need to do the following:
2148  *       1) the first packet will have a clean split between header and
2149  *          data. save both.
2150  *       2) each time the next flow packet comes in, extend the
2151  *          data length and merge the checksums.
2152  *       3) on flow release, fix up the header.
2153  *       4) make sure the higher layer doesn't care.
2154  * because packets get coalesced, we shouldn't run into fragment count
2155  * issues.
2156  */
2157 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2158                                    struct sk_buff *skb)
2159 {
2160         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2161         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2162 
2163         /* this is protected at a higher layer, so no need to
2164          * do any additional locking here. stick the buffer
2165          * at the end.
2166          */
2167         __skb_queue_tail(flow, skb);
2168         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2169                 while ((skb = __skb_dequeue(flow))) {
2170                         cas_skb_release(skb);
2171                 }
2172         }
2173 }
2174 
2175 /* put rx descriptor back on ring. if a buffer is in use by a higher
2176  * layer, this will need to put in a replacement.
2177  */
2178 static void cas_post_page(struct cas *cp, const int ring, const int index)
2179 {
2180         cas_page_t *new;
2181         int entry;
2182 
2183         entry = cp->rx_old[ring];
2184 
2185         new = cas_page_swap(cp, ring, index);
2186         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2187         cp->init_rxds[ring][entry].index  =
2188                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2189                             CAS_BASE(RX_INDEX_RING, ring));
2190 
2191         entry = RX_DESC_ENTRY(ring, entry + 1);
2192         cp->rx_old[ring] = entry;
2193 
2194         if (entry % 4)
2195                 return;
2196 
2197         if (ring == 0)
2198                 writel(entry, cp->regs + REG_RX_KICK);
2199         else if ((N_RX_DESC_RINGS > 1) &&
2200                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2201                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2202 }
2203 
2204 
2205 /* only when things are bad */
2206 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2207 {
2208         unsigned int entry, last, count, released;
2209         int cluster;
2210         cas_page_t **page = cp->rx_pages[ring];
2211 
2212         entry = cp->rx_old[ring];
2213 
2214         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2215                      "rxd[%d] interrupt, done: %d\n", ring, entry);
2216 
2217         cluster = -1;
2218         count = entry & 0x3;
2219         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2220         released = 0;
2221         while (entry != last) {
2222                 /* make a new buffer if it's still in use */
2223                 if (page_count(page[entry]->buffer) > 1) {
2224                         cas_page_t *new = cas_page_dequeue(cp);
2225                         if (!new) {
2226                                 /* let the timer know that we need to
2227                                  * do this again
2228                                  */
2229                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2230                                 if (!timer_pending(&cp->link_timer))
2231                                         mod_timer(&cp->link_timer, jiffies +
2232                                                   CAS_LINK_FAST_TIMEOUT);
2233                                 cp->rx_old[ring]  = entry;
2234                                 cp->rx_last[ring] = num ? num - released : 0;
2235                                 return -ENOMEM;
2236                         }
2237                         spin_lock(&cp->rx_inuse_lock);
2238                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2239                         spin_unlock(&cp->rx_inuse_lock);
2240                         cp->init_rxds[ring][entry].buffer =
2241                                 cpu_to_le64(new->dma_addr);
2242                         page[entry] = new;
2243 
2244                 }
2245 
2246                 if (++count == 4) {
2247                         cluster = entry;
2248                         count = 0;
2249                 }
2250                 released++;
2251                 entry = RX_DESC_ENTRY(ring, entry + 1);
2252         }
2253         cp->rx_old[ring] = entry;
2254 
2255         if (cluster < 0)
2256                 return 0;
2257 
2258         if (ring == 0)
2259                 writel(cluster, cp->regs + REG_RX_KICK);
2260         else if ((N_RX_DESC_RINGS > 1) &&
2261                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2262                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2263         return 0;
2264 }
2265 
2266 
2267 /* process a completion ring. packets are set up in three basic ways:
2268  * small packets: should be copied header + data in single buffer.
2269  * large packets: header and data in a single buffer.
2270  * split packets: header in a separate buffer from data.
2271  *                data may be in multiple pages. data may be > 256
2272  *                bytes but in a single page.
2273  *
2274  * NOTE: RX page posting is done in this routine as well. while there's
2275  *       the capability of using multiple RX completion rings, it isn't
2276  *       really worthwhile due to the fact that the page posting will
2277  *       force serialization on the single descriptor ring.
2278  */
2279 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2280 {
2281         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2282         int entry, drops;
2283         int npackets = 0;
2284 
2285         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2286                      "rx[%d] interrupt, done: %d/%d\n",
2287                      ring,
2288                      readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2289 
2290         entry = cp->rx_new[ring];
2291         drops = 0;
2292         while (1) {
2293                 struct cas_rx_comp *rxc = rxcs + entry;
2294                 struct sk_buff *uninitialized_var(skb);
2295                 int type, len;
2296                 u64 words[4];
2297                 int i, dring;
2298 
2299                 words[0] = le64_to_cpu(rxc->word1);
2300                 words[1] = le64_to_cpu(rxc->word2);
2301                 words[2] = le64_to_cpu(rxc->word3);
2302                 words[3] = le64_to_cpu(rxc->word4);
2303 
2304                 /* don't touch if still owned by hw */
2305                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2306                 if (type == 0)
2307                         break;
2308 
2309                 /* hw hasn't cleared the zero bit yet */
2310                 if (words[3] & RX_COMP4_ZERO) {
2311                         break;
2312                 }
2313 
2314                 /* get info on the packet */
2315                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2316                         spin_lock(&cp->stat_lock[ring]);
2317                         cp->net_stats[ring].rx_errors++;
2318                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2319                                 cp->net_stats[ring].rx_length_errors++;
2320                         if (words[3] & RX_COMP4_BAD)
2321                                 cp->net_stats[ring].rx_crc_errors++;
2322                         spin_unlock(&cp->stat_lock[ring]);
2323 
2324                         /* We'll just return it to Cassini. */
2325                 drop_it:
2326                         spin_lock(&cp->stat_lock[ring]);
2327                         ++cp->net_stats[ring].rx_dropped;
2328                         spin_unlock(&cp->stat_lock[ring]);
2329                         goto next;
2330                 }
2331 
2332                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2333                 if (len < 0) {
2334                         ++drops;
2335                         goto drop_it;
2336                 }
2337 
2338                 /* see if it's a flow re-assembly or not. the driver
2339                  * itself handles release back up.
2340                  */
2341                 if (RX_DONT_BATCH || (type == 0x2)) {
2342                         /* non-reassm: these always get released */
2343                         cas_skb_release(skb);
2344                 } else {
2345                         cas_rx_flow_pkt(cp, words, skb);
2346                 }
2347 
2348                 spin_lock(&cp->stat_lock[ring]);
2349                 cp->net_stats[ring].rx_packets++;
2350                 cp->net_stats[ring].rx_bytes += len;
2351                 spin_unlock(&cp->stat_lock[ring]);
2352 
2353         next:
2354                 npackets++;
2355 
2356                 /* should it be released? */
2357                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2358                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2359                         dring = CAS_VAL(RX_INDEX_RING, i);
2360                         i = CAS_VAL(RX_INDEX_NUM, i);
2361                         cas_post_page(cp, dring, i);
2362                 }
2363 
2364                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2365                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2366                         dring = CAS_VAL(RX_INDEX_RING, i);
2367                         i = CAS_VAL(RX_INDEX_NUM, i);
2368                         cas_post_page(cp, dring, i);
2369                 }
2370 
2371                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2372                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2373                         dring = CAS_VAL(RX_INDEX_RING, i);
2374                         i = CAS_VAL(RX_INDEX_NUM, i);
2375                         cas_post_page(cp, dring, i);
2376                 }
2377 
2378                 /* skip to the next entry */
2379                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2380                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2381 #ifdef USE_NAPI
2382                 if (budget && (npackets >= budget))
2383                         break;
2384 #endif
2385         }
2386         cp->rx_new[ring] = entry;
2387 
2388         if (drops)
2389                 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2390         return npackets;
2391 }
2392 
2393 
2394 /* put completion entries back on the ring */
2395 static void cas_post_rxcs_ringN(struct net_device *dev,
2396                                 struct cas *cp, int ring)
2397 {
2398         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2399         int last, entry;
2400 
2401         last = cp->rx_cur[ring];
2402         entry = cp->rx_new[ring];
2403         netif_printk(cp, intr, KERN_DEBUG, dev,
2404                      "rxc[%d] interrupt, done: %d/%d\n",
2405                      ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2406 
2407         /* zero and re-mark descriptors */
2408         while (last != entry) {
2409                 cas_rxc_init(rxc + last);
2410                 last = RX_COMP_ENTRY(ring, last + 1);
2411         }
2412         cp->rx_cur[ring] = last;
2413 
2414         if (ring == 0)
2415                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2416         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2417                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2418 }
2419 
2420 
2421 
2422 /* cassini can use all four PCI interrupts for the completion ring.
2423  * rings 3 and 4 are identical
2424  */
2425 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2426 static inline void cas_handle_irqN(struct net_device *dev,
2427                                    struct cas *cp, const u32 status,
2428                                    const int ring)
2429 {
2430         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2431                 cas_post_rxcs_ringN(dev, cp, ring);
2432 }
2433 
2434 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2435 {
2436         struct net_device *dev = dev_id;
2437         struct cas *cp = netdev_priv(dev);
2438         unsigned long flags;
2439         int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2440         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2441 
2442         /* check for shared irq */
2443         if (status == 0)
2444                 return IRQ_NONE;
2445 
2446         spin_lock_irqsave(&cp->lock, flags);
2447         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2448 #ifdef USE_NAPI
2449                 cas_mask_intr(cp);
2450                 napi_schedule(&cp->napi);
2451 #else
2452                 cas_rx_ringN(cp, ring, 0);
2453 #endif
2454                 status &= ~INTR_RX_DONE_ALT;
2455         }
2456 
2457         if (status)
2458                 cas_handle_irqN(dev, cp, status, ring);
2459         spin_unlock_irqrestore(&cp->lock, flags);
2460         return IRQ_HANDLED;
2461 }
2462 #endif
2463 
2464 #ifdef USE_PCI_INTB
2465 /* everything but rx packets */
2466 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2467 {
2468         if (status & INTR_RX_BUF_UNAVAIL_1) {
2469                 /* Frame arrived, no free RX buffers available.
2470                  * NOTE: we can get this on a link transition. */
2471                 cas_post_rxds_ringN(cp, 1, 0);
2472                 spin_lock(&cp->stat_lock[1]);
2473                 cp->net_stats[1].rx_dropped++;
2474                 spin_unlock(&cp->stat_lock[1]);
2475         }
2476 
2477         if (status & INTR_RX_BUF_AE_1)
2478                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2479                                     RX_AE_FREEN_VAL(1));
2480 
2481         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2482                 cas_post_rxcs_ringN(cp, 1);
2483 }
2484 
2485 /* ring 2 handles a few more events than 3 and 4 */
2486 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2487 {
2488         struct net_device *dev = dev_id;
2489         struct cas *cp = netdev_priv(dev);
2490         unsigned long flags;
2491         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2492 
2493         /* check for shared interrupt */
2494         if (status == 0)
2495                 return IRQ_NONE;
2496 
2497         spin_lock_irqsave(&cp->lock, flags);
2498         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2499 #ifdef USE_NAPI
2500                 cas_mask_intr(cp);
2501                 napi_schedule(&cp->napi);
2502 #else
2503                 cas_rx_ringN(cp, 1, 0);
2504 #endif
2505                 status &= ~INTR_RX_DONE_ALT;
2506         }
2507         if (status)
2508                 cas_handle_irq1(cp, status);
2509         spin_unlock_irqrestore(&cp->lock, flags);
2510         return IRQ_HANDLED;
2511 }
2512 #endif
2513 
2514 static inline void cas_handle_irq(struct net_device *dev,
2515                                   struct cas *cp, const u32 status)
2516 {
2517         /* housekeeping interrupts */
2518         if (status & INTR_ERROR_MASK)
2519                 cas_abnormal_irq(dev, cp, status);
2520 
2521         if (status & INTR_RX_BUF_UNAVAIL) {
2522                 /* Frame arrived, no free RX buffers available.
2523                  * NOTE: we can get this on a link transition.
2524                  */
2525                 cas_post_rxds_ringN(cp, 0, 0);
2526                 spin_lock(&cp->stat_lock[0]);
2527                 cp->net_stats[0].rx_dropped++;
2528                 spin_unlock(&cp->stat_lock[0]);
2529         } else if (status & INTR_RX_BUF_AE) {
2530                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2531                                     RX_AE_FREEN_VAL(0));
2532         }
2533 
2534         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2535                 cas_post_rxcs_ringN(dev, cp, 0);
2536 }
2537 
2538 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2539 {
2540         struct net_device *dev = dev_id;
2541         struct cas *cp = netdev_priv(dev);
2542         unsigned long flags;
2543         u32 status = readl(cp->regs + REG_INTR_STATUS);
2544 
2545         if (status == 0)
2546                 return IRQ_NONE;
2547 
2548         spin_lock_irqsave(&cp->lock, flags);
2549         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2550                 cas_tx(dev, cp, status);
2551                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2552         }
2553 
2554         if (status & INTR_RX_DONE) {
2555 #ifdef USE_NAPI
2556                 cas_mask_intr(cp);
2557                 napi_schedule(&cp->napi);
2558 #else
2559                 cas_rx_ringN(cp, 0, 0);
2560 #endif
2561                 status &= ~INTR_RX_DONE;
2562         }
2563 
2564         if (status)
2565                 cas_handle_irq(dev, cp, status);
2566         spin_unlock_irqrestore(&cp->lock, flags);
2567         return IRQ_HANDLED;
2568 }
2569 
2570 
2571 #ifdef USE_NAPI
2572 static int cas_poll(struct napi_struct *napi, int budget)
2573 {
2574         struct cas *cp = container_of(napi, struct cas, napi);
2575         struct net_device *dev = cp->dev;
2576         int i, enable_intr, credits;
2577         u32 status = readl(cp->regs + REG_INTR_STATUS);
2578         unsigned long flags;
2579 
2580         spin_lock_irqsave(&cp->lock, flags);
2581         cas_tx(dev, cp, status);
2582         spin_unlock_irqrestore(&cp->lock, flags);
2583 
2584         /* NAPI rx packets. we spread the credits across all of the
2585          * rxc rings
2586          *
2587          * to make sure we're fair with the work we loop through each
2588          * ring N_RX_COMP_RING times with a request of
2589          * budget / N_RX_COMP_RINGS
2590          */
2591         enable_intr = 1;
2592         credits = 0;
2593         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2594                 int j;
2595                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2596                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2597                         if (credits >= budget) {
2598                                 enable_intr = 0;
2599                                 goto rx_comp;
2600                         }
2601                 }
2602         }
2603 
2604 rx_comp:
2605         /* final rx completion */
2606         spin_lock_irqsave(&cp->lock, flags);
2607         if (status)
2608                 cas_handle_irq(dev, cp, status);
2609 
2610 #ifdef USE_PCI_INTB
2611         if (N_RX_COMP_RINGS > 1) {
2612                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2613                 if (status)
2614                         cas_handle_irq1(dev, cp, status);
2615         }
2616 #endif
2617 
2618 #ifdef USE_PCI_INTC
2619         if (N_RX_COMP_RINGS > 2) {
2620                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2621                 if (status)
2622                         cas_handle_irqN(dev, cp, status, 2);
2623         }
2624 #endif
2625 
2626 #ifdef USE_PCI_INTD
2627         if (N_RX_COMP_RINGS > 3) {
2628                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2629                 if (status)
2630                         cas_handle_irqN(dev, cp, status, 3);
2631         }
2632 #endif
2633         spin_unlock_irqrestore(&cp->lock, flags);
2634         if (enable_intr) {
2635                 napi_complete(napi);
2636                 cas_unmask_intr(cp);
2637         }
2638         return credits;
2639 }
2640 #endif
2641 
2642 #ifdef CONFIG_NET_POLL_CONTROLLER
2643 static void cas_netpoll(struct net_device *dev)
2644 {
2645         struct cas *cp = netdev_priv(dev);
2646 
2647         cas_disable_irq(cp, 0);
2648         cas_interrupt(cp->pdev->irq, dev);
2649         cas_enable_irq(cp, 0);
2650 
2651 #ifdef USE_PCI_INTB
2652         if (N_RX_COMP_RINGS > 1) {
2653                 /* cas_interrupt1(); */
2654         }
2655 #endif
2656 #ifdef USE_PCI_INTC
2657         if (N_RX_COMP_RINGS > 2) {
2658                 /* cas_interruptN(); */
2659         }
2660 #endif
2661 #ifdef USE_PCI_INTD
2662         if (N_RX_COMP_RINGS > 3) {
2663                 /* cas_interruptN(); */
2664         }
2665 #endif
2666 }
2667 #endif
2668 
2669 static void cas_tx_timeout(struct net_device *dev)
2670 {
2671         struct cas *cp = netdev_priv(dev);
2672 
2673         netdev_err(dev, "transmit timed out, resetting\n");
2674         if (!cp->hw_running) {
2675                 netdev_err(dev, "hrm.. hw not running!\n");
2676                 return;
2677         }
2678 
2679         netdev_err(dev, "MIF_STATE[%08x]\n",
2680                    readl(cp->regs + REG_MIF_STATE_MACHINE));
2681 
2682         netdev_err(dev, "MAC_STATE[%08x]\n",
2683                    readl(cp->regs + REG_MAC_STATE_MACHINE));
2684 
2685         netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2686                    readl(cp->regs + REG_TX_CFG),
2687                    readl(cp->regs + REG_MAC_TX_STATUS),
2688                    readl(cp->regs + REG_MAC_TX_CFG),
2689                    readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2690                    readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2691                    readl(cp->regs + REG_TX_FIFO_READ_PTR),
2692                    readl(cp->regs + REG_TX_SM_1),
2693                    readl(cp->regs + REG_TX_SM_2));
2694 
2695         netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2696                    readl(cp->regs + REG_RX_CFG),
2697                    readl(cp->regs + REG_MAC_RX_STATUS),
2698                    readl(cp->regs + REG_MAC_RX_CFG));
2699 
2700         netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2701                    readl(cp->regs + REG_HP_STATE_MACHINE),
2702                    readl(cp->regs + REG_HP_STATUS0),
2703                    readl(cp->regs + REG_HP_STATUS1),
2704                    readl(cp->regs + REG_HP_STATUS2));
2705 
2706 #if 1
2707         atomic_inc(&cp->reset_task_pending);
2708         atomic_inc(&cp->reset_task_pending_all);
2709         schedule_work(&cp->reset_task);
2710 #else
2711         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2712         schedule_work(&cp->reset_task);
2713 #endif
2714 }
2715 
2716 static inline int cas_intme(int ring, int entry)
2717 {
2718         /* Algorithm: IRQ every 1/2 of descriptors. */
2719         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2720                 return 1;
2721         return 0;
2722 }
2723 
2724 
2725 static void cas_write_txd(struct cas *cp, int ring, int entry,
2726                           dma_addr_t mapping, int len, u64 ctrl, int last)
2727 {
2728         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2729 
2730         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2731         if (cas_intme(ring, entry))
2732                 ctrl |= TX_DESC_INTME;
2733         if (last)
2734                 ctrl |= TX_DESC_EOF;
2735         txd->control = cpu_to_le64(ctrl);
2736         txd->buffer = cpu_to_le64(mapping);
2737 }
2738 
2739 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2740                                 const int entry)
2741 {
2742         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2743 }
2744 
2745 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2746                                      const int entry, const int tentry)
2747 {
2748         cp->tx_tiny_use[ring][tentry].nbufs++;
2749         cp->tx_tiny_use[ring][entry].used = 1;
2750         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2751 }
2752 
2753 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2754                                     struct sk_buff *skb)
2755 {
2756         struct net_device *dev = cp->dev;
2757         int entry, nr_frags, frag, tabort, tentry;
2758         dma_addr_t mapping;
2759         unsigned long flags;
2760         u64 ctrl;
2761         u32 len;
2762 
2763         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2764 
2765         /* This is a hard error, log it. */
2766         if (TX_BUFFS_AVAIL(cp, ring) <=
2767             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2768                 netif_stop_queue(dev);
2769                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2770                 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2771                 return 1;
2772         }
2773 
2774         ctrl = 0;
2775         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2776                 const u64 csum_start_off = skb_checksum_start_offset(skb);
2777                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2778 
2779                 ctrl =  TX_DESC_CSUM_EN |
2780                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2781                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2782         }
2783 
2784         entry = cp->tx_new[ring];
2785         cp->tx_skbs[ring][entry] = skb;
2786 
2787         nr_frags = skb_shinfo(skb)->nr_frags;
2788         len = skb_headlen(skb);
2789         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2790                                offset_in_page(skb->data), len,
2791                                PCI_DMA_TODEVICE);
2792 
2793         tentry = entry;
2794         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2795         if (unlikely(tabort)) {
2796                 /* NOTE: len is always >  tabort */
2797                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2798                               ctrl | TX_DESC_SOF, 0);
2799                 entry = TX_DESC_NEXT(ring, entry);
2800 
2801                 skb_copy_from_linear_data_offset(skb, len - tabort,
2802                               tx_tiny_buf(cp, ring, entry), tabort);
2803                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2804                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2805                               (nr_frags == 0));
2806         } else {
2807                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2808                               TX_DESC_SOF, (nr_frags == 0));
2809         }
2810         entry = TX_DESC_NEXT(ring, entry);
2811 
2812         for (frag = 0; frag < nr_frags; frag++) {
2813                 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2814 
2815                 len = skb_frag_size(fragp);
2816                 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2817                                            DMA_TO_DEVICE);
2818 
2819                 tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len);
2820                 if (unlikely(tabort)) {
2821                         void *addr;
2822 
2823                         /* NOTE: len is always > tabort */
2824                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2825                                       ctrl, 0);
2826                         entry = TX_DESC_NEXT(ring, entry);
2827 
2828                         addr = cas_page_map(skb_frag_page(fragp));
2829                         memcpy(tx_tiny_buf(cp, ring, entry),
2830                                addr + skb_frag_off(fragp) + len - tabort,
2831                                tabort);
2832                         cas_page_unmap(addr);
2833                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2834                         len     = tabort;
2835                 }
2836 
2837                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2838                               (frag + 1 == nr_frags));
2839                 entry = TX_DESC_NEXT(ring, entry);
2840         }
2841 
2842         cp->tx_new[ring] = entry;
2843         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2844                 netif_stop_queue(dev);
2845 
2846         netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2847                      "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2848                      ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2849         writel(entry, cp->regs + REG_TX_KICKN(ring));
2850         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2851         return 0;
2852 }
2853 
2854 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2855 {
2856         struct cas *cp = netdev_priv(dev);
2857 
2858         /* this is only used as a load-balancing hint, so it doesn't
2859          * need to be SMP safe
2860          */
2861         static int ring;
2862 
2863         if (skb_padto(skb, cp->min_frame_size))
2864                 return NETDEV_TX_OK;
2865 
2866         /* XXX: we need some higher-level QoS hooks to steer packets to
2867          *      individual queues.
2868          */
2869         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2870                 return NETDEV_TX_BUSY;
2871         return NETDEV_TX_OK;
2872 }
2873 
2874 static void cas_init_tx_dma(struct cas *cp)
2875 {
2876         u64 desc_dma = cp->block_dvma;
2877         unsigned long off;
2878         u32 val;
2879         int i;
2880 
2881         /* set up tx completion writeback registers. must be 8-byte aligned */
2882 #ifdef USE_TX_COMPWB
2883         off = offsetof(struct cas_init_block, tx_compwb);
2884         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2885         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2886 #endif
2887 
2888         /* enable completion writebacks, enable paced mode,
2889          * disable read pipe, and disable pre-interrupt compwbs
2890          */
2891         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2892                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2893                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2894                 TX_CFG_INTR_COMPWB_DIS;
2895 
2896         /* write out tx ring info and tx desc bases */
2897         for (i = 0; i < MAX_TX_RINGS; i++) {
2898                 off = (unsigned long) cp->init_txds[i] -
2899                         (unsigned long) cp->init_block;
2900 
2901                 val |= CAS_TX_RINGN_BASE(i);
2902                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2903                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2904                        REG_TX_DBN_LOW(i));
2905                 /* don't zero out the kick register here as the system
2906                  * will wedge
2907                  */
2908         }
2909         writel(val, cp->regs + REG_TX_CFG);
2910 
2911         /* program max burst sizes. these numbers should be different
2912          * if doing QoS.
2913          */
2914 #ifdef USE_QOS
2915         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2916         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2917         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2918         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2919 #else
2920         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2921         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2922         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2923         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2924 #endif
2925 }
2926 
2927 /* Must be invoked under cp->lock. */
2928 static inline void cas_init_dma(struct cas *cp)
2929 {
2930         cas_init_tx_dma(cp);
2931         cas_init_rx_dma(cp);
2932 }
2933 
2934 static void cas_process_mc_list(struct cas *cp)
2935 {
2936         u16 hash_table[16];
2937         u32 crc;
2938         struct netdev_hw_addr *ha;
2939         int i = 1;
2940 
2941         memset(hash_table, 0, sizeof(hash_table));
2942         netdev_for_each_mc_addr(ha, cp->dev) {
2943                 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2944                         /* use the alternate mac address registers for the
2945                          * first 15 multicast addresses
2946                          */
2947                         writel((ha->addr[4] << 8) | ha->addr[5],
2948                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
2949                         writel((ha->addr[2] << 8) | ha->addr[3],
2950                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
2951                         writel((ha->addr[0] << 8) | ha->addr[1],
2952                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
2953                         i++;
2954                 }
2955                 else {
2956                         /* use hw hash table for the next series of
2957                          * multicast addresses
2958                          */
2959                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2960                         crc >>= 24;
2961                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2962                 }
2963         }
2964         for (i = 0; i < 16; i++)
2965                 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2966 }
2967 
2968 /* Must be invoked under cp->lock. */
2969 static u32 cas_setup_multicast(struct cas *cp)
2970 {
2971         u32 rxcfg = 0;
2972         int i;
2973 
2974         if (cp->dev->flags & IFF_PROMISC) {
2975                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2976 
2977         } else if (cp->dev->flags & IFF_ALLMULTI) {
2978                 for (i=0; i < 16; i++)
2979                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2980                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2981 
2982         } else {
2983                 cas_process_mc_list(cp);
2984                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2985         }
2986 
2987         return rxcfg;
2988 }
2989 
2990 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
2991 static void cas_clear_mac_err(struct cas *cp)
2992 {
2993         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
2994         writel(0, cp->regs + REG_MAC_COLL_FIRST);
2995         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
2996         writel(0, cp->regs + REG_MAC_COLL_LATE);
2997         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
2998         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
2999         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3000         writel(0, cp->regs + REG_MAC_LEN_ERR);
3001         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3002         writel(0, cp->regs + REG_MAC_FCS_ERR);
3003         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3004 }
3005 
3006 
3007 static void cas_mac_reset(struct cas *cp)
3008 {
3009         int i;
3010 
3011         /* do both TX and RX reset */
3012         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3013         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3014 
3015         /* wait for TX */
3016         i = STOP_TRIES;
3017         while (i-- > 0) {
3018                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3019                         break;
3020                 udelay(10);
3021         }
3022 
3023         /* wait for RX */
3024         i = STOP_TRIES;
3025         while (i-- > 0) {
3026                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3027                         break;
3028                 udelay(10);
3029         }
3030 
3031         if (readl(cp->regs + REG_MAC_TX_RESET) |
3032             readl(cp->regs + REG_MAC_RX_RESET))
3033                 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3034                            readl(cp->regs + REG_MAC_TX_RESET),
3035                            readl(cp->regs + REG_MAC_RX_RESET),
3036                            readl(cp->regs + REG_MAC_STATE_MACHINE));
3037 }
3038 
3039 
3040 /* Must be invoked under cp->lock. */
3041 static void cas_init_mac(struct cas *cp)
3042 {
3043         unsigned char *e = &cp->dev->dev_addr[0];
3044         int i;
3045         cas_mac_reset(cp);
3046 
3047         /* setup core arbitration weight register */
3048         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3049 
3050 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3051         /* set the infinite burst register for chips that don't have
3052          * pci issues.
3053          */
3054         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3055                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3056 #endif
3057 
3058         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3059 
3060         writel(0x00, cp->regs + REG_MAC_IPG0);
3061         writel(0x08, cp->regs + REG_MAC_IPG1);
3062         writel(0x04, cp->regs + REG_MAC_IPG2);
3063 
3064         /* change later for 802.3z */
3065         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3066 
3067         /* min frame + FCS */
3068         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3069 
3070         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3071          * specify the maximum frame size to prevent RX tag errors on
3072          * oversized frames.
3073          */
3074         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3075                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3076                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3077                cp->regs + REG_MAC_FRAMESIZE_MAX);
3078 
3079         /* NOTE: crc_size is used as a surrogate for half-duplex.
3080          * workaround saturn half-duplex issue by increasing preamble
3081          * size to 65 bytes.
3082          */
3083         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3084                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3085         else
3086                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3087         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3088         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3089         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3090 
3091         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3092 
3093         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3094         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3095         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3096         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3097         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3098 
3099         /* setup mac address in perfect filter array */
3100         for (i = 0; i < 45; i++)
3101                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3102 
3103         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3104         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3105         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3106 
3107         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3108         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3109         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3110 
3111         cp->mac_rx_cfg = cas_setup_multicast(cp);
3112 
3113         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3114         cas_clear_mac_err(cp);
3115         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3116 
3117         /* Setup MAC interrupts.  We want to get all of the interesting
3118          * counter expiration events, but we do not want to hear about
3119          * normal rx/tx as the DMA engine tells us that.
3120          */
3121         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3122         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3123 
3124         /* Don't enable even the PAUSE interrupts for now, we
3125          * make no use of those events other than to record them.
3126          */
3127         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3128 }
3129 
3130 /* Must be invoked under cp->lock. */
3131 static void cas_init_pause_thresholds(struct cas *cp)
3132 {
3133         /* Calculate pause thresholds.  Setting the OFF threshold to the
3134          * full RX fifo size effectively disables PAUSE generation
3135          */
3136         if (cp->rx_fifo_size <= (2 * 1024)) {
3137                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3138         } else {
3139                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3140                 if (max_frame * 3 > cp->rx_fifo_size) {
3141                         cp->rx_pause_off = 7104;
3142                         cp->rx_pause_on  = 960;
3143                 } else {
3144                         int off = (cp->rx_fifo_size - (max_frame * 2));
3145                         int on = off - max_frame;
3146                         cp->rx_pause_off = off;
3147                         cp->rx_pause_on = on;
3148                 }
3149         }
3150 }
3151 
3152 static int cas_vpd_match(const void __iomem *p, const char *str)
3153 {
3154         int len = strlen(str) + 1;
3155         int i;
3156 
3157         for (i = 0; i < len; i++) {
3158                 if (readb(p + i) != str[i])
3159                         return 0;
3160         }
3161         return 1;
3162 }
3163 
3164 
3165 /* get the mac address by reading the vpd information in the rom.
3166  * also get the phy type and determine if there's an entropy generator.
3167  * NOTE: this is a bit convoluted for the following reasons:
3168  *  1) vpd info has order-dependent mac addresses for multinic cards
3169  *  2) the only way to determine the nic order is to use the slot
3170  *     number.
3171  *  3) fiber cards don't have bridges, so their slot numbers don't
3172  *     mean anything.
3173  *  4) we don't actually know we have a fiber card until after
3174  *     the mac addresses are parsed.
3175  */
3176 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3177                             const int offset)
3178 {
3179         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3180         void __iomem *base, *kstart;
3181         int i, len;
3182         int found = 0;
3183 #define VPD_FOUND_MAC        0x01
3184 #define VPD_FOUND_PHY        0x02
3185 
3186         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3187         int mac_off  = 0;
3188 
3189 #if defined(CONFIG_SPARC)
3190         const unsigned char *addr;
3191 #endif
3192 
3193         /* give us access to the PROM */
3194         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3195                cp->regs + REG_BIM_LOCAL_DEV_EN);
3196 
3197         /* check for an expansion rom */
3198         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3199                 goto use_random_mac_addr;
3200 
3201         /* search for beginning of vpd */
3202         base = NULL;
3203         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3204                 /* check for PCIR */
3205                 if ((readb(p + i + 0) == 0x50) &&
3206                     (readb(p + i + 1) == 0x43) &&
3207                     (readb(p + i + 2) == 0x49) &&
3208                     (readb(p + i + 3) == 0x52)) {
3209                         base = p + (readb(p + i + 8) |
3210                                     (readb(p + i + 9) << 8));
3211                         break;
3212                 }
3213         }
3214 
3215         if (!base || (readb(base) != 0x82))
3216                 goto use_random_mac_addr;
3217 
3218         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3219         while (i < EXPANSION_ROM_SIZE) {
3220                 if (readb(base + i) != 0x90) /* no vpd found */
3221                         goto use_random_mac_addr;
3222 
3223                 /* found a vpd field */
3224                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3225 
3226                 /* extract keywords */
3227                 kstart = base + i + 3;
3228                 p = kstart;
3229                 while ((p - kstart) < len) {
3230                         int klen = readb(p + 2);
3231                         int j;
3232                         char type;
3233 
3234                         p += 3;
3235 
3236                         /* look for the following things:
3237                          * -- correct length == 29
3238                          * 3 (type) + 2 (size) +
3239                          * 18 (strlen("local-mac-address") + 1) +
3240                          * 6 (mac addr)
3241                          * -- VPD Instance 'I'
3242                          * -- VPD Type Bytes 'B'
3243                          * -- VPD data length == 6
3244                          * -- property string == local-mac-address
3245                          *
3246                          * -- correct length == 24
3247                          * 3 (type) + 2 (size) +
3248                          * 12 (strlen("entropy-dev") + 1) +
3249                          * 7 (strlen("vms110") + 1)
3250                          * -- VPD Instance 'I'
3251                          * -- VPD Type String 'B'
3252                          * -- VPD data length == 7
3253                          * -- property string == entropy-dev
3254                          *
3255                          * -- correct length == 18
3256                          * 3 (type) + 2 (size) +
3257                          * 9 (strlen("phy-type") + 1) +
3258                          * 4 (strlen("pcs") + 1)
3259                          * -- VPD Instance 'I'
3260                          * -- VPD Type String 'S'
3261                          * -- VPD data length == 4
3262                          * -- property string == phy-type
3263                          *
3264                          * -- correct length == 23
3265                          * 3 (type) + 2 (size) +
3266                          * 14 (strlen("phy-interface") + 1) +
3267                          * 4 (strlen("pcs") + 1)
3268                          * -- VPD Instance 'I'
3269                          * -- VPD Type String 'S'
3270                          * -- VPD data length == 4
3271                          * -- property string == phy-interface
3272                          */
3273                         if (readb(p) != 'I')
3274                                 goto next;
3275 
3276                         /* finally, check string and length */
3277                         type = readb(p + 3);
3278                         if (type == 'B') {
3279                                 if ((klen == 29) && readb(p + 4) == 6 &&
3280                                     cas_vpd_match(p + 5,
3281                                                   "local-mac-address")) {
3282                                         if (mac_off++ > offset)
3283                                                 goto next;
3284 
3285                                         /* set mac address */
3286                                         for (j = 0; j < 6; j++)
3287                                                 dev_addr[j] =
3288                                                         readb(p + 23 + j);
3289                                         goto found_mac;
3290                                 }
3291                         }
3292 
3293                         if (type != 'S')
3294                                 goto next;
3295 
3296 #ifdef USE_ENTROPY_DEV
3297                         if ((klen == 24) &&
3298                             cas_vpd_match(p + 5, "entropy-dev") &&
3299                             cas_vpd_match(p + 17, "vms110")) {
3300                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3301                                 goto next;
3302                         }
3303 #endif
3304 
3305                         if (found & VPD_FOUND_PHY)
3306                                 goto next;
3307 
3308                         if ((klen == 18) && readb(p + 4) == 4 &&
3309                             cas_vpd_match(p + 5, "phy-type")) {
3310                                 if (cas_vpd_match(p + 14, "pcs")) {
3311                                         phy_type = CAS_PHY_SERDES;
3312                                         goto found_phy;
3313                                 }
3314                         }
3315 
3316                         if ((klen == 23) && readb(p + 4) == 4 &&
3317                             cas_vpd_match(p + 5, "phy-interface")) {
3318                                 if (cas_vpd_match(p + 19, "pcs")) {
3319                                         phy_type = CAS_PHY_SERDES;
3320                                         goto found_phy;
3321                                 }
3322                         }
3323 found_mac:
3324                         found |= VPD_FOUND_MAC;
3325                         goto next;
3326 
3327 found_phy:
3328                         found |= VPD_FOUND_PHY;
3329 
3330 next:
3331                         p += klen;
3332                 }
3333                 i += len + 3;
3334         }
3335 
3336 use_random_mac_addr:
3337         if (found & VPD_FOUND_MAC)
3338                 goto done;
3339 
3340 #if defined(CONFIG_SPARC)
3341         addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3342         if (addr != NULL) {
3343                 memcpy(dev_addr, addr, ETH_ALEN);
3344                 goto done;
3345         }
3346 #endif
3347 
3348         /* Sun MAC prefix then 3 random bytes. */
3349         pr_info("MAC address not found in ROM VPD\n");
3350         dev_addr[0] = 0x08;
3351         dev_addr[1] = 0x00;
3352         dev_addr[2] = 0x20;
3353         get_random_bytes(dev_addr + 3, 3);
3354 
3355 done:
3356         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3357         return phy_type;
3358 }
3359 
3360 /* check pci invariants */
3361 static void cas_check_pci_invariants(struct cas *cp)
3362 {
3363         struct pci_dev *pdev = cp->pdev;
3364 
3365         cp->cas_flags = 0;
3366         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3367             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3368                 if (pdev->revision >= CAS_ID_REVPLUS)
3369                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3370                 if (pdev->revision < CAS_ID_REVPLUS02u)
3371                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3372 
3373                 /* Original Cassini supports HW CSUM, but it's not
3374                  * enabled by default as it can trigger TX hangs.
3375                  */
3376                 if (pdev->revision < CAS_ID_REV2)
3377                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3378         } else {
3379                 /* Only sun has original cassini chips.  */
3380                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3381 
3382                 /* We use a flag because the same phy might be externally
3383                  * connected.
3384                  */
3385                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3386                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3387                         cp->cas_flags |= CAS_FLAG_SATURN;
3388         }
3389 }
3390 
3391 
3392 static int cas_check_invariants(struct cas *cp)
3393 {
3394         struct pci_dev *pdev = cp->pdev;
3395         u32 cfg;
3396         int i;
3397 
3398         /* get page size for rx buffers. */
3399         cp->page_order = 0;
3400 #ifdef USE_PAGE_ORDER
3401         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3402                 /* see if we can allocate larger pages */
3403                 struct page *page = alloc_pages(GFP_ATOMIC,
3404                                                 CAS_JUMBO_PAGE_SHIFT -
3405                                                 PAGE_SHIFT);
3406                 if (page) {
3407                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3408                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3409                 } else {
3410                         printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3411                 }
3412         }
3413 #endif
3414         cp->page_size = (PAGE_SIZE << cp->page_order);
3415 
3416         /* Fetch the FIFO configurations. */
3417         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3418         cp->rx_fifo_size = RX_FIFO_SIZE;
3419 
3420         /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3421          * they're both connected.
3422          */
3423         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3424                                         PCI_SLOT(pdev->devfn));
3425         if (cp->phy_type & CAS_PHY_SERDES) {
3426                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3427                 return 0; /* no more checking needed */
3428         }
3429 
3430         /* MII */
3431         cfg = readl(cp->regs + REG_MIF_CFG);
3432         if (cfg & MIF_CFG_MDIO_1) {
3433                 cp->phy_type = CAS_PHY_MII_MDIO1;
3434         } else if (cfg & MIF_CFG_MDIO_0) {
3435                 cp->phy_type = CAS_PHY_MII_MDIO0;
3436         }
3437 
3438         cas_mif_poll(cp, 0);
3439         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3440 
3441         for (i = 0; i < 32; i++) {
3442                 u32 phy_id;
3443                 int j;
3444 
3445                 for (j = 0; j < 3; j++) {
3446                         cp->phy_addr = i;
3447                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3448                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3449                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3450                                 cp->phy_id = phy_id;
3451                                 goto done;
3452                         }
3453                 }
3454         }
3455         pr_err("MII phy did not respond [%08x]\n",
3456                readl(cp->regs + REG_MIF_STATE_MACHINE));
3457         return -1;
3458 
3459 done:
3460         /* see if we can do gigabit */
3461         cfg = cas_phy_read(cp, MII_BMSR);
3462         if ((cfg & CAS_BMSR_1000_EXTEND) &&
3463             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3464                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3465         return 0;
3466 }
3467 
3468 /* Must be invoked under cp->lock. */
3469 static inline void cas_start_dma(struct cas *cp)
3470 {
3471         int i;
3472         u32 val;
3473         int txfailed = 0;
3474 
3475         /* enable dma */
3476         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3477         writel(val, cp->regs + REG_TX_CFG);
3478         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3479         writel(val, cp->regs + REG_RX_CFG);
3480 
3481         /* enable the mac */
3482         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3483         writel(val, cp->regs + REG_MAC_TX_CFG);
3484         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3485         writel(val, cp->regs + REG_MAC_RX_CFG);
3486 
3487         i = STOP_TRIES;
3488         while (i-- > 0) {
3489                 val = readl(cp->regs + REG_MAC_TX_CFG);
3490                 if ((val & MAC_TX_CFG_EN))
3491                         break;
3492                 udelay(10);
3493         }
3494         if (i < 0) txfailed = 1;
3495         i = STOP_TRIES;
3496         while (i-- > 0) {
3497                 val = readl(cp->regs + REG_MAC_RX_CFG);
3498                 if ((val & MAC_RX_CFG_EN)) {
3499                         if (txfailed) {
3500                                 netdev_err(cp->dev,
3501                                            "enabling mac failed [tx:%08x:%08x]\n",
3502                                            readl(cp->regs + REG_MIF_STATE_MACHINE),
3503                                            readl(cp->regs + REG_MAC_STATE_MACHINE));
3504                         }
3505                         goto enable_rx_done;
3506                 }
3507                 udelay(10);
3508         }
3509         netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3510                    (txfailed ? "tx,rx" : "rx"),
3511                    readl(cp->regs + REG_MIF_STATE_MACHINE),
3512                    readl(cp->regs + REG_MAC_STATE_MACHINE));
3513 
3514 enable_rx_done:
3515         cas_unmask_intr(cp); /* enable interrupts */
3516         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3517         writel(0, cp->regs + REG_RX_COMP_TAIL);
3518 
3519         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3520                 if (N_RX_DESC_RINGS > 1)
3521                         writel(RX_DESC_RINGN_SIZE(1) - 4,
3522                                cp->regs + REG_PLUS_RX_KICK1);
3523 
3524                 for (i = 1; i < N_RX_COMP_RINGS; i++)
3525                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3526         }
3527 }
3528 
3529 /* Must be invoked under cp->lock. */
3530 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3531                                    int *pause)
3532 {
3533         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3534         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3535         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3536         if (val & PCS_MII_LPA_ASYM_PAUSE)
3537                 *pause |= 0x10;
3538         *spd = 1000;
3539 }
3540 
3541 /* Must be invoked under cp->lock. */
3542 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3543                                    int *pause)
3544 {
3545         u32 val;
3546 
3547         *fd = 0;
3548         *spd = 10;
3549         *pause = 0;
3550 
3551         /* use GMII registers */
3552         val = cas_phy_read(cp, MII_LPA);
3553         if (val & CAS_LPA_PAUSE)
3554                 *pause = 0x01;
3555 
3556         if (val & CAS_LPA_ASYM_PAUSE)
3557                 *pause |= 0x10;
3558 
3559         if (val & LPA_DUPLEX)
3560                 *fd = 1;
3561         if (val & LPA_100)
3562                 *spd = 100;
3563 
3564         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3565                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3566                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3567                         *spd = 1000;
3568                 if (val & CAS_LPA_1000FULL)
3569                         *fd = 1;
3570         }
3571 }
3572 
3573 /* A link-up condition has occurred, initialize and enable the
3574  * rest of the chip.
3575  *
3576  * Must be invoked under cp->lock.
3577  */
3578 static void cas_set_link_modes(struct cas *cp)
3579 {
3580         u32 val;
3581         int full_duplex, speed, pause;
3582 
3583         full_duplex = 0;
3584         speed = 10;
3585         pause = 0;
3586 
3587         if (CAS_PHY_MII(cp->phy_type)) {
3588                 cas_mif_poll(cp, 0);
3589                 val = cas_phy_read(cp, MII_BMCR);
3590                 if (val & BMCR_ANENABLE) {
3591                         cas_read_mii_link_mode(cp, &full_duplex, &speed,
3592                                                &pause);
3593                 } else {
3594                         if (val & BMCR_FULLDPLX)
3595                                 full_duplex = 1;
3596 
3597                         if (val & BMCR_SPEED100)
3598                                 speed = 100;
3599                         else if (val & CAS_BMCR_SPEED1000)
3600                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3601                                         1000 : 100;
3602                 }
3603                 cas_mif_poll(cp, 1);
3604 
3605         } else {
3606                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3607                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3608                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3609                         if (val & PCS_MII_CTRL_DUPLEX)
3610                                 full_duplex = 1;
3611                 }
3612         }
3613 
3614         netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3615                    speed, full_duplex ? "full" : "half");
3616 
3617         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3618         if (CAS_PHY_MII(cp->phy_type)) {
3619                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3620                 if (!full_duplex)
3621                         val |= MAC_XIF_DISABLE_ECHO;
3622         }
3623         if (full_duplex)
3624                 val |= MAC_XIF_FDPLX_LED;
3625         if (speed == 1000)
3626                 val |= MAC_XIF_GMII_MODE;
3627         writel(val, cp->regs + REG_MAC_XIF_CFG);
3628 
3629         /* deal with carrier and collision detect. */
3630         val = MAC_TX_CFG_IPG_EN;
3631         if (full_duplex) {
3632                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3633                 val |= MAC_TX_CFG_IGNORE_COLL;
3634         } else {
3635 #ifndef USE_CSMA_CD_PROTO
3636                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3637                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3638 #endif
3639         }
3640         /* val now set up for REG_MAC_TX_CFG */
3641 
3642         /* If gigabit and half-duplex, enable carrier extension
3643          * mode.  increase slot time to 512 bytes as well.
3644          * else, disable it and make sure slot time is 64 bytes.
3645          * also activate checksum bug workaround
3646          */
3647         if ((speed == 1000) && !full_duplex) {
3648                 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3649                        cp->regs + REG_MAC_TX_CFG);
3650 
3651                 val = readl(cp->regs + REG_MAC_RX_CFG);
3652                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3653                 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3654                        cp->regs + REG_MAC_RX_CFG);
3655 
3656                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3657 
3658                 cp->crc_size = 4;
3659                 /* minimum size gigabit frame at half duplex */
3660                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3661 
3662         } else {
3663                 writel(val, cp->regs + REG_MAC_TX_CFG);
3664 
3665                 /* checksum bug workaround. don't strip FCS when in
3666                  * half-duplex mode
3667                  */
3668                 val = readl(cp->regs + REG_MAC_RX_CFG);
3669                 if (full_duplex) {
3670                         val |= MAC_RX_CFG_STRIP_FCS;
3671                         cp->crc_size = 0;
3672                         cp->min_frame_size = CAS_MIN_MTU;
3673                 } else {
3674                         val &= ~MAC_RX_CFG_STRIP_FCS;
3675                         cp->crc_size = 4;
3676                         cp->min_frame_size = CAS_MIN_FRAME;
3677                 }
3678                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3679                        cp->regs + REG_MAC_RX_CFG);
3680                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3681         }
3682 
3683         if (netif_msg_link(cp)) {
3684                 if (pause & 0x01) {
3685                         netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3686                                     cp->rx_fifo_size,
3687                                     cp->rx_pause_off,
3688                                     cp->rx_pause_on);
3689                 } else if (pause & 0x10) {
3690                         netdev_info(cp->dev, "TX pause enabled\n");
3691                 } else {
3692                         netdev_info(cp->dev, "Pause is disabled\n");
3693                 }
3694         }
3695 
3696         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3697         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3698         if (pause) { /* symmetric or asymmetric pause */
3699                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3700                 if (pause & 0x01) { /* symmetric pause */
3701                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3702                 }
3703         }
3704         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3705         cas_start_dma(cp);
3706 }
3707 
3708 /* Must be invoked under cp->lock. */
3709 static void cas_init_hw(struct cas *cp, int restart_link)
3710 {
3711         if (restart_link)
3712                 cas_phy_init(cp);
3713 
3714         cas_init_pause_thresholds(cp);
3715         cas_init_mac(cp);
3716         cas_init_dma(cp);
3717 
3718         if (restart_link) {
3719                 /* Default aneg parameters */
3720                 cp->timer_ticks = 0;
3721                 cas_begin_auto_negotiation(cp, NULL);
3722         } else if (cp->lstate == link_up) {
3723                 cas_set_link_modes(cp);
3724                 netif_carrier_on(cp->dev);
3725         }
3726 }
3727 
3728 /* Must be invoked under cp->lock. on earlier cassini boards,
3729  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3730  * let it settle out, and then restore pci state.
3731  */
3732 static void cas_hard_reset(struct cas *cp)
3733 {
3734         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3735         udelay(20);
3736         pci_restore_state(cp->pdev);
3737 }
3738 
3739 
3740 static void cas_global_reset(struct cas *cp, int blkflag)
3741 {
3742         int limit;
3743 
3744         /* issue a global reset. don't use RSTOUT. */
3745         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3746                 /* For PCS, when the blkflag is set, we should set the
3747                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3748                  * the last autonegotiation from being cleared.  We'll
3749                  * need some special handling if the chip is set into a
3750                  * loopback mode.
3751                  */
3752                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3753                        cp->regs + REG_SW_RESET);
3754         } else {
3755                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3756         }
3757 
3758         /* need to wait at least 3ms before polling register */
3759         mdelay(3);
3760 
3761         limit = STOP_TRIES;
3762         while (limit-- > 0) {
3763                 u32 val = readl(cp->regs + REG_SW_RESET);
3764                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3765                         goto done;
3766                 udelay(10);
3767         }
3768         netdev_err(cp->dev, "sw reset failed\n");
3769 
3770 done:
3771         /* enable various BIM interrupts */
3772         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3773                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3774 
3775         /* clear out pci error status mask for handled errors.
3776          * we don't deal with DMA counter overflows as they happen
3777          * all the time.
3778          */
3779         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3780                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3781                                PCI_ERR_BIM_DMA_READ), cp->regs +
3782                REG_PCI_ERR_STATUS_MASK);
3783 
3784         /* set up for MII by default to address mac rx reset timeout
3785          * issue
3786          */
3787         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3788 }
3789 
3790 static void cas_reset(struct cas *cp, int blkflag)
3791 {
3792         u32 val;
3793 
3794         cas_mask_intr(cp);
3795         cas_global_reset(cp, blkflag);
3796         cas_mac_reset(cp);
3797         cas_entropy_reset(cp);
3798 
3799         /* disable dma engines. */
3800         val = readl(cp->regs + REG_TX_CFG);
3801         val &= ~TX_CFG_DMA_EN;
3802         writel(val, cp->regs + REG_TX_CFG);
3803 
3804         val = readl(cp->regs + REG_RX_CFG);
3805         val &= ~RX_CFG_DMA_EN;
3806         writel(val, cp->regs + REG_RX_CFG);
3807 
3808         /* program header parser */
3809         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3810             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3811                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3812         } else {
3813                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3814         }
3815 
3816         /* clear out error registers */
3817         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3818         cas_clear_mac_err(cp);
3819         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3820 }
3821 
3822 /* Shut down the chip, must be called with pm_mutex held.  */
3823 static void cas_shutdown(struct cas *cp)
3824 {
3825         unsigned long flags;
3826 
3827         /* Make us not-running to avoid timers respawning */
3828         cp->hw_running = 0;
3829 
3830         del_timer_sync(&cp->link_timer);
3831 
3832         /* Stop the reset task */
3833 #if 0
3834         while (atomic_read(&cp->reset_task_pending_mtu) ||
3835                atomic_read(&cp->reset_task_pending_spare) ||
3836                atomic_read(&cp->reset_task_pending_all))
3837                 schedule();
3838 
3839 #else
3840         while (atomic_read(&cp->reset_task_pending))
3841                 schedule();
3842 #endif
3843         /* Actually stop the chip */
3844         cas_lock_all_save(cp, flags);
3845         cas_reset(cp, 0);
3846         if (cp->cas_flags & CAS_FLAG_SATURN)
3847                 cas_phy_powerdown(cp);
3848         cas_unlock_all_restore(cp, flags);
3849 }
3850 
3851 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3852 {
3853         struct cas *cp = netdev_priv(dev);
3854 
3855         dev->mtu = new_mtu;
3856         if (!netif_running(dev) || !netif_device_present(dev))
3857                 return 0;
3858 
3859         /* let the reset task handle it */
3860 #if 1
3861         atomic_inc(&cp->reset_task_pending);
3862         if ((cp->phy_type & CAS_PHY_SERDES)) {
3863                 atomic_inc(&cp->reset_task_pending_all);
3864         } else {
3865                 atomic_inc(&cp->reset_task_pending_mtu);
3866         }
3867         schedule_work(&cp->reset_task);
3868 #else
3869         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3870                    CAS_RESET_ALL : CAS_RESET_MTU);
3871         pr_err("reset called in cas_change_mtu\n");
3872         schedule_work(&cp->reset_task);
3873 #endif
3874 
3875         flush_work(&cp->reset_task);
3876         return 0;
3877 }
3878 
3879 static void cas_clean_txd(struct cas *cp, int ring)
3880 {
3881         struct cas_tx_desc *txd = cp->init_txds[ring];
3882         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3883         u64 daddr, dlen;
3884         int i, size;
3885 
3886         size = TX_DESC_RINGN_SIZE(ring);
3887         for (i = 0; i < size; i++) {
3888                 int frag;
3889 
3890                 if (skbs[i] == NULL)
3891                         continue;
3892 
3893                 skb = skbs[i];
3894                 skbs[i] = NULL;
3895 
3896                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3897                         int ent = i & (size - 1);
3898 
3899                         /* first buffer is never a tiny buffer and so
3900                          * needs to be unmapped.
3901                          */
3902                         daddr = le64_to_cpu(txd[ent].buffer);
3903                         dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3904                                          le64_to_cpu(txd[ent].control));
3905                         pci_unmap_page(cp->pdev, daddr, dlen,
3906                                        PCI_DMA_TODEVICE);
3907 
3908                         if (frag != skb_shinfo(skb)->nr_frags) {
3909                                 i++;
3910 
3911                                 /* next buffer might by a tiny buffer.
3912                                  * skip past it.
3913                                  */
3914                                 ent = i & (size - 1);
3915                                 if (cp->tx_tiny_use[ring][ent].used)
3916                                         i++;
3917                         }
3918                 }
3919                 dev_kfree_skb_any(skb);
3920         }
3921 
3922         /* zero out tiny buf usage */
3923         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3924 }
3925 
3926 /* freed on close */
3927 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3928 {
3929         cas_page_t **page = cp->rx_pages[ring];
3930         int i, size;
3931 
3932         size = RX_DESC_RINGN_SIZE(ring);
3933         for (i = 0; i < size; i++) {
3934                 if (page[i]) {
3935                         cas_page_free(cp, page[i]);
3936                         page[i] = NULL;
3937                 }
3938         }
3939 }
3940 
3941 static void cas_free_rxds(struct cas *cp)
3942 {
3943         int i;
3944 
3945         for (i = 0; i < N_RX_DESC_RINGS; i++)
3946                 cas_free_rx_desc(cp, i);
3947 }
3948 
3949 /* Must be invoked under cp->lock. */
3950 static void cas_clean_rings(struct cas *cp)
3951 {
3952         int i;
3953 
3954         /* need to clean all tx rings */
3955         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3956         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3957         for (i = 0; i < N_TX_RINGS; i++)
3958                 cas_clean_txd(cp, i);
3959 
3960         /* zero out init block */
3961         memset(cp->init_block, 0, sizeof(struct cas_init_block));
3962         cas_clean_rxds(cp);
3963         cas_clean_rxcs(cp);
3964 }
3965 
3966 /* allocated on open */
3967 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3968 {
3969         cas_page_t **page = cp->rx_pages[ring];
3970         int size, i = 0;
3971 
3972         size = RX_DESC_RINGN_SIZE(ring);
3973         for (i = 0; i < size; i++) {
3974                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3975                         return -1;
3976         }
3977         return 0;
3978 }
3979 
3980 static int cas_alloc_rxds(struct cas *cp)
3981 {
3982         int i;
3983 
3984         for (i = 0; i < N_RX_DESC_RINGS; i++) {
3985                 if (cas_alloc_rx_desc(cp, i) < 0) {
3986                         cas_free_rxds(cp);
3987                         return -1;
3988                 }
3989         }
3990         return 0;
3991 }
3992 
3993 static void cas_reset_task(struct work_struct *work)
3994 {
3995         struct cas *cp = container_of(work, struct cas, reset_task);
3996 #if 0
3997         int pending = atomic_read(&cp->reset_task_pending);
3998 #else
3999         int pending_all = atomic_read(&cp->reset_task_pending_all);
4000         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4001         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4002 
4003         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4004                 /* We can have more tasks scheduled than actually
4005                  * needed.
4006                  */
4007                 atomic_dec(&cp->reset_task_pending);
4008                 return;
4009         }
4010 #endif
4011         /* The link went down, we reset the ring, but keep
4012          * DMA stopped. Use this function for reset
4013          * on error as well.
4014          */
4015         if (cp->hw_running) {
4016                 unsigned long flags;
4017 
4018                 /* Make sure we don't get interrupts or tx packets */
4019                 netif_device_detach(cp->dev);
4020                 cas_lock_all_save(cp, flags);
4021 
4022                 if (cp->opened) {
4023                         /* We call cas_spare_recover when we call cas_open.
4024                          * but we do not initialize the lists cas_spare_recover
4025                          * uses until cas_open is called.
4026                          */
4027                         cas_spare_recover(cp, GFP_ATOMIC);
4028                 }
4029 #if 1
4030                 /* test => only pending_spare set */
4031                 if (!pending_all && !pending_mtu)
4032                         goto done;
4033 #else
4034                 if (pending == CAS_RESET_SPARE)
4035                         goto done;
4036 #endif
4037                 /* when pending == CAS_RESET_ALL, the following
4038                  * call to cas_init_hw will restart auto negotiation.
4039                  * Setting the second argument of cas_reset to
4040                  * !(pending == CAS_RESET_ALL) will set this argument
4041                  * to 1 (avoiding reinitializing the PHY for the normal
4042                  * PCS case) when auto negotiation is not restarted.
4043                  */
4044 #if 1
4045                 cas_reset(cp, !(pending_all > 0));
4046                 if (cp->opened)
4047                         cas_clean_rings(cp);
4048                 cas_init_hw(cp, (pending_all > 0));
4049 #else
4050                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4051                 if (cp->opened)
4052                         cas_clean_rings(cp);
4053                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4054 #endif
4055 
4056 done:
4057                 cas_unlock_all_restore(cp, flags);
4058                 netif_device_attach(cp->dev);
4059         }
4060 #if 1
4061         atomic_sub(pending_all, &cp->reset_task_pending_all);
4062         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4063         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4064         atomic_dec(&cp->reset_task_pending);
4065 #else
4066         atomic_set(&cp->reset_task_pending, 0);
4067 #endif
4068 }
4069 
4070 static void cas_link_timer(struct timer_list *t)
4071 {
4072         struct cas *cp = from_timer(cp, t, link_timer);
4073         int mask, pending = 0, reset = 0;
4074         unsigned long flags;
4075 
4076         if (link_transition_timeout != 0 &&
4077             cp->link_transition_jiffies_valid &&
4078             ((jiffies - cp->link_transition_jiffies) >
4079               (link_transition_timeout))) {
4080                 /* One-second counter so link-down workaround doesn't
4081                  * cause resets to occur so fast as to fool the switch
4082                  * into thinking the link is down.
4083                  */
4084                 cp->link_transition_jiffies_valid = 0;
4085         }
4086 
4087         if (!cp->hw_running)
4088                 return;
4089 
4090         spin_lock_irqsave(&cp->lock, flags);
4091         cas_lock_tx(cp);
4092         cas_entropy_gather(cp);
4093 
4094         /* If the link task is still pending, we just
4095          * reschedule the link timer
4096          */
4097 #if 1
4098         if (atomic_read(&cp->reset_task_pending_all) ||
4099             atomic_read(&cp->reset_task_pending_spare) ||
4100             atomic_read(&cp->reset_task_pending_mtu))
4101                 goto done;
4102 #else
4103         if (atomic_read(&cp->reset_task_pending))
4104                 goto done;
4105 #endif
4106 
4107         /* check for rx cleaning */
4108         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4109                 int i, rmask;
4110 
4111                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4112                         rmask = CAS_FLAG_RXD_POST(i);
4113                         if ((mask & rmask) == 0)
4114                                 continue;
4115 
4116                         /* post_rxds will do a mod_timer */
4117                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4118                                 pending = 1;
4119                                 continue;
4120                         }
4121                         cp->cas_flags &= ~rmask;
4122                 }
4123         }
4124 
4125         if (CAS_PHY_MII(cp->phy_type)) {
4126                 u16 bmsr;
4127                 cas_mif_poll(cp, 0);
4128                 bmsr = cas_phy_read(cp, MII_BMSR);
4129                 /* WTZ: Solaris driver reads this twice, but that
4130                  * may be due to the PCS case and the use of a
4131                  * common implementation. Read it twice here to be
4132                  * safe.
4133                  */
4134                 bmsr = cas_phy_read(cp, MII_BMSR);
4135                 cas_mif_poll(cp, 1);
4136                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4137                 reset = cas_mii_link_check(cp, bmsr);
4138         } else {
4139                 reset = cas_pcs_link_check(cp);
4140         }
4141 
4142         if (reset)
4143                 goto done;
4144 
4145         /* check for tx state machine confusion */
4146         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4147                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4148                 u32 wptr, rptr;
4149                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4150 
4151                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4152                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4153                         netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4154                                      "tx err: MAC_STATE[%08x]\n", val);
4155                         reset = 1;
4156                         goto done;
4157                 }
4158 
4159                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4160                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4161                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4162                 if ((val == 0) && (wptr != rptr)) {
4163                         netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4164                                      "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4165                                      val, wptr, rptr);
4166                         reset = 1;
4167                 }
4168 
4169                 if (reset)
4170                         cas_hard_reset(cp);
4171         }
4172 
4173 done:
4174         if (reset) {
4175 #if 1
4176                 atomic_inc(&cp->reset_task_pending);
4177                 atomic_inc(&cp->reset_task_pending_all);
4178                 schedule_work(&cp->reset_task);
4179 #else
4180                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4181                 pr_err("reset called in cas_link_timer\n");
4182                 schedule_work(&cp->reset_task);
4183 #endif
4184         }
4185 
4186         if (!pending)
4187                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4188         cas_unlock_tx(cp);
4189         spin_unlock_irqrestore(&cp->lock, flags);
4190 }
4191 
4192 /* tiny buffers are used to avoid target abort issues with
4193  * older cassini's
4194  */
4195 static void cas_tx_tiny_free(struct cas *cp)
4196 {
4197         struct pci_dev *pdev = cp->pdev;
4198         int i;
4199 
4200         for (i = 0; i < N_TX_RINGS; i++) {
4201                 if (!cp->tx_tiny_bufs[i])
4202                         continue;
4203 
4204                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4205                                     cp->tx_tiny_bufs[i],
4206                                     cp->tx_tiny_dvma[i]);
4207                 cp->tx_tiny_bufs[i] = NULL;
4208         }
4209 }
4210 
4211 static int cas_tx_tiny_alloc(struct cas *cp)
4212 {
4213         struct pci_dev *pdev = cp->pdev;
4214         int i;
4215 
4216         for (i = 0; i < N_TX_RINGS; i++) {
4217                 cp->tx_tiny_bufs[i] =
4218                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4219                                              &cp->tx_tiny_dvma[i]);
4220                 if (!cp->tx_tiny_bufs[i]) {
4221                         cas_tx_tiny_free(cp);
4222                         return -1;
4223                 }
4224         }
4225         return 0;
4226 }
4227 
4228 
4229 static int cas_open(struct net_device *dev)
4230 {
4231         struct cas *cp = netdev_priv(dev);
4232         int hw_was_up, err;
4233         unsigned long flags;
4234 
4235         mutex_lock(&cp->pm_mutex);
4236 
4237         hw_was_up = cp->hw_running;
4238 
4239         /* The power-management mutex protects the hw_running
4240          * etc. state so it is safe to do this bit without cp->lock
4241          */
4242         if (!cp->hw_running) {
4243                 /* Reset the chip */
4244                 cas_lock_all_save(cp, flags);
4245                 /* We set the second arg to cas_reset to zero
4246                  * because cas_init_hw below will have its second
4247                  * argument set to non-zero, which will force
4248                  * autonegotiation to start.
4249                  */
4250                 cas_reset(cp, 0);
4251                 cp->hw_running = 1;
4252                 cas_unlock_all_restore(cp, flags);
4253         }
4254 
4255         err = -ENOMEM;
4256         if (cas_tx_tiny_alloc(cp) < 0)
4257                 goto err_unlock;
4258 
4259         /* alloc rx descriptors */
4260         if (cas_alloc_rxds(cp) < 0)
4261                 goto err_tx_tiny;
4262 
4263         /* allocate spares */
4264         cas_spare_init(cp);
4265         cas_spare_recover(cp, GFP_KERNEL);
4266 
4267         /* We can now request the interrupt as we know it's masked
4268          * on the controller. cassini+ has up to 4 interrupts
4269          * that can be used, but you need to do explicit pci interrupt
4270          * mapping to expose them
4271          */
4272         if (request_irq(cp->pdev->irq, cas_interrupt,
4273                         IRQF_SHARED, dev->name, (void *) dev)) {
4274                 netdev_err(cp->dev, "failed to request irq !\n");
4275                 err = -EAGAIN;
4276                 goto err_spare;
4277         }
4278 
4279 #ifdef USE_NAPI
4280         napi_enable(&cp->napi);
4281 #endif
4282         /* init hw */
4283         cas_lock_all_save(cp, flags);
4284         cas_clean_rings(cp);
4285         cas_init_hw(cp, !hw_was_up);
4286         cp->opened = 1;
4287         cas_unlock_all_restore(cp, flags);
4288 
4289         netif_start_queue(dev);
4290         mutex_unlock(&cp->pm_mutex);
4291         return 0;
4292 
4293 err_spare:
4294         cas_spare_free(cp);
4295         cas_free_rxds(cp);
4296 err_tx_tiny:
4297         cas_tx_tiny_free(cp);
4298 err_unlock:
4299         mutex_unlock(&cp->pm_mutex);
4300         return err;
4301 }
4302 
4303 static int cas_close(struct net_device *dev)
4304 {
4305         unsigned long flags;
4306         struct cas *cp = netdev_priv(dev);
4307 
4308 #ifdef USE_NAPI
4309         napi_disable(&cp->napi);
4310 #endif
4311         /* Make sure we don't get distracted by suspend/resume */
4312         mutex_lock(&cp->pm_mutex);
4313 
4314         netif_stop_queue(dev);
4315 
4316         /* Stop traffic, mark us closed */
4317         cas_lock_all_save(cp, flags);
4318         cp->opened = 0;
4319         cas_reset(cp, 0);
4320         cas_phy_init(cp);
4321         cas_begin_auto_negotiation(cp, NULL);
4322         cas_clean_rings(cp);
4323         cas_unlock_all_restore(cp, flags);
4324 
4325         free_irq(cp->pdev->irq, (void *) dev);
4326         cas_spare_free(cp);
4327         cas_free_rxds(cp);
4328         cas_tx_tiny_free(cp);
4329         mutex_unlock(&cp->pm_mutex);
4330         return 0;
4331 }
4332 
4333 static struct {
4334         const char name[ETH_GSTRING_LEN];
4335 } ethtool_cassini_statnames[] = {
4336         {"collisions"},
4337         {"rx_bytes"},
4338         {"rx_crc_errors"},
4339         {"rx_dropped"},
4340         {"rx_errors"},
4341         {"rx_fifo_errors"},
4342         {"rx_frame_errors"},
4343         {"rx_length_errors"},
4344         {"rx_over_errors"},
4345         {"rx_packets"},
4346         {"tx_aborted_errors"},
4347         {"tx_bytes"},
4348         {"tx_dropped"},
4349         {"tx_errors"},
4350         {"tx_fifo_errors"},
4351         {"tx_packets"}
4352 };
4353 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4354 
4355 static struct {
4356         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4357 } ethtool_register_table[] = {
4358         {-MII_BMSR},
4359         {-MII_BMCR},
4360         {REG_CAWR},
4361         {REG_INF_BURST},
4362         {REG_BIM_CFG},
4363         {REG_RX_CFG},
4364         {REG_HP_CFG},
4365         {REG_MAC_TX_CFG},
4366         {REG_MAC_RX_CFG},
4367         {REG_MAC_CTRL_CFG},
4368         {REG_MAC_XIF_CFG},
4369         {REG_MIF_CFG},
4370         {REG_PCS_CFG},
4371         {REG_SATURN_PCFG},
4372         {REG_PCS_MII_STATUS},
4373         {REG_PCS_STATE_MACHINE},
4374         {REG_MAC_COLL_EXCESS},
4375         {REG_MAC_COLL_LATE}
4376 };
4377 #define CAS_REG_LEN     ARRAY_SIZE(ethtool_register_table)
4378 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4379 
4380 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4381 {
4382         u8 *p;
4383         int i;
4384         unsigned long flags;
4385 
4386         spin_lock_irqsave(&cp->lock, flags);
4387         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4388                 u16 hval;
4389                 u32 val;
4390                 if (ethtool_register_table[i].offsets < 0) {
4391                         hval = cas_phy_read(cp,
4392                                     -ethtool_register_table[i].offsets);
4393                         val = hval;
4394                 } else {
4395                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4396                 }
4397                 memcpy(p, (u8 *)&val, sizeof(u32));
4398         }
4399         spin_unlock_irqrestore(&cp->lock, flags);
4400 }
4401 
4402 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4403 {
4404         struct cas *cp = netdev_priv(dev);
4405         struct net_device_stats *stats = cp->net_stats;
4406         unsigned long flags;
4407         int i;
4408         unsigned long tmp;
4409 
4410         /* we collate all of the stats into net_stats[N_TX_RING] */
4411         if (!cp->hw_running)
4412                 return stats + N_TX_RINGS;
4413 
4414         /* collect outstanding stats */
4415         /* WTZ: the Cassini spec gives these as 16 bit counters but
4416          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4417          * in case the chip somehow puts any garbage in the other bits.
4418          * Also, counter usage didn't seem to mach what Adrian did
4419          * in the parts of the code that set these quantities. Made
4420          * that consistent.
4421          */
4422         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4423         stats[N_TX_RINGS].rx_crc_errors +=
4424           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4425         stats[N_TX_RINGS].rx_frame_errors +=
4426                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4427         stats[N_TX_RINGS].rx_length_errors +=
4428                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4429 #if 1
4430         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4431                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4432         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4433         stats[N_TX_RINGS].collisions +=
4434           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4435 #else
4436         stats[N_TX_RINGS].tx_aborted_errors +=
4437                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4438         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4439                 readl(cp->regs + REG_MAC_COLL_LATE);
4440 #endif
4441         cas_clear_mac_err(cp);
4442 
4443         /* saved bits that are unique to ring 0 */
4444         spin_lock(&cp->stat_lock[0]);
4445         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4446         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4447         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4448         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4449         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4450         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4451         spin_unlock(&cp->stat_lock[0]);
4452 
4453         for (i = 0; i < N_TX_RINGS; i++) {
4454                 spin_lock(&cp->stat_lock[i]);
4455                 stats[N_TX_RINGS].rx_length_errors +=
4456                         stats[i].rx_length_errors;
4457                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4458                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4459                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4460                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4461                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4462                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4463                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4464                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4465                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4466                 memset(stats + i, 0, sizeof(struct net_device_stats));
4467                 spin_unlock(&cp->stat_lock[i]);
4468         }
4469         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4470         return stats + N_TX_RINGS;
4471 }
4472 
4473 
4474 static void cas_set_multicast(struct net_device *dev)
4475 {
4476         struct cas *cp = netdev_priv(dev);
4477         u32 rxcfg, rxcfg_new;
4478         unsigned long flags;
4479         int limit = STOP_TRIES;
4480 
4481         if (!cp->hw_running)
4482                 return;
4483 
4484         spin_lock_irqsave(&cp->lock, flags);
4485         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4486 
4487         /* disable RX MAC and wait for completion */
4488         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4489         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4490                 if (!limit--)
4491                         break;
4492                 udelay(10);
4493         }
4494 
4495         /* disable hash filter and wait for completion */
4496         limit = STOP_TRIES;
4497         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4498         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4499         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4500                 if (!limit--)
4501                         break;
4502                 udelay(10);
4503         }
4504 
4505         /* program hash filters */
4506         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4507         rxcfg |= rxcfg_new;
4508         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4509         spin_unlock_irqrestore(&cp->lock, flags);
4510 }
4511 
4512 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4513 {
4514         struct cas *cp = netdev_priv(dev);
4515         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4516         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4517         strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4518 }
4519 
4520 static int cas_get_link_ksettings(struct net_device *dev,
4521                                   struct ethtool_link_ksettings *cmd)
4522 {
4523         struct cas *cp = netdev_priv(dev);
4524         u16 bmcr;
4525         int full_duplex, speed, pause;
4526         unsigned long flags;
4527         enum link_state linkstate = link_up;
4528         u32 supported, advertising;
4529 
4530         advertising = 0;
4531         supported = SUPPORTED_Autoneg;
4532         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4533                 supported |= SUPPORTED_1000baseT_Full;
4534                 advertising |= ADVERTISED_1000baseT_Full;
4535         }
4536 
4537         /* Record PHY settings if HW is on. */
4538         spin_lock_irqsave(&cp->lock, flags);
4539         bmcr = 0;
4540         linkstate = cp->lstate;
4541         if (CAS_PHY_MII(cp->phy_type)) {
4542                 cmd->base.port = PORT_MII;
4543                 cmd->base.phy_address = cp->phy_addr;
4544                 advertising |= ADVERTISED_TP | ADVERTISED_MII |
4545                         ADVERTISED_10baseT_Half |
4546                         ADVERTISED_10baseT_Full |
4547                         ADVERTISED_100baseT_Half |
4548                         ADVERTISED_100baseT_Full;
4549 
4550                 supported |=
4551                         (SUPPORTED_10baseT_Half |
4552                          SUPPORTED_10baseT_Full |
4553                          SUPPORTED_100baseT_Half |
4554                          SUPPORTED_100baseT_Full |
4555                          SUPPORTED_TP | SUPPORTED_MII);
4556 
4557                 if (cp->hw_running) {
4558                         cas_mif_poll(cp, 0);
4559                         bmcr = cas_phy_read(cp, MII_BMCR);
4560                         cas_read_mii_link_mode(cp, &full_duplex,
4561                                                &speed, &pause);
4562                         cas_mif_poll(cp, 1);
4563                 }
4564 
4565         } else {
4566                 cmd->base.port = PORT_FIBRE;
4567                 cmd->base.phy_address = 0;
4568                 supported   |= SUPPORTED_FIBRE;
4569                 advertising |= ADVERTISED_FIBRE;
4570 
4571                 if (cp->hw_running) {
4572                         /* pcs uses the same bits as mii */
4573                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4574                         cas_read_pcs_link_mode(cp, &full_duplex,
4575                                                &speed, &pause);
4576                 }
4577         }
4578         spin_unlock_irqrestore(&cp->lock, flags);
4579 
4580         if (bmcr & BMCR_ANENABLE) {
4581                 advertising |= ADVERTISED_Autoneg;
4582                 cmd->base.autoneg = AUTONEG_ENABLE;
4583                 cmd->base.speed =  ((speed == 10) ?
4584                                             SPEED_10 :
4585                                             ((speed == 1000) ?
4586                                              SPEED_1000 : SPEED_100));
4587                 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4588         } else {
4589                 cmd->base.autoneg = AUTONEG_DISABLE;
4590                 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ?
4591                                             SPEED_1000 :
4592                                             ((bmcr & BMCR_SPEED100) ?
4593                                              SPEED_100 : SPEED_10));
4594                 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ?
4595                         DUPLEX_FULL : DUPLEX_HALF;
4596         }
4597         if (linkstate != link_up) {
4598                 /* Force these to "unknown" if the link is not up and
4599                  * autonogotiation in enabled. We can set the link
4600                  * speed to 0, but not cmd->duplex,
4601                  * because its legal values are 0 and 1.  Ethtool will
4602                  * print the value reported in parentheses after the
4603                  * word "Unknown" for unrecognized values.
4604                  *
4605                  * If in forced mode, we report the speed and duplex
4606                  * settings that we configured.
4607                  */
4608                 if (cp->link_cntl & BMCR_ANENABLE) {
4609                         cmd->base.speed = 0;
4610                         cmd->base.duplex = 0xff;
4611                 } else {
4612                         cmd->base.speed = SPEED_10;
4613                         if (cp->link_cntl & BMCR_SPEED100) {
4614                                 cmd->base.speed = SPEED_100;
4615                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4616                                 cmd->base.speed = SPEED_1000;
4617                         }
4618                         cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ?
4619                                 DUPLEX_FULL : DUPLEX_HALF;
4620                 }
4621         }
4622 
4623         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4624                                                 supported);
4625         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4626                                                 advertising);
4627 
4628         return 0;
4629 }
4630 
4631 static int cas_set_link_ksettings(struct net_device *dev,
4632                                   const struct ethtool_link_ksettings *cmd)
4633 {
4634         struct cas *cp = netdev_priv(dev);
4635         unsigned long flags;
4636         u32 speed = cmd->base.speed;
4637 
4638         /* Verify the settings we care about. */
4639         if (cmd->base.autoneg != AUTONEG_ENABLE &&
4640             cmd->base.autoneg != AUTONEG_DISABLE)
4641                 return -EINVAL;
4642 
4643         if (cmd->base.autoneg == AUTONEG_DISABLE &&
4644             ((speed != SPEED_1000 &&
4645               speed != SPEED_100 &&
4646               speed != SPEED_10) ||
4647              (cmd->base.duplex != DUPLEX_HALF &&
4648               cmd->base.duplex != DUPLEX_FULL)))
4649                 return -EINVAL;
4650 
4651         /* Apply settings and restart link process. */
4652         spin_lock_irqsave(&cp->lock, flags);
4653         cas_begin_auto_negotiation(cp, cmd);
4654         spin_unlock_irqrestore(&cp->lock, flags);
4655         return 0;
4656 }
4657 
4658 static int cas_nway_reset(struct net_device *dev)
4659 {
4660         struct cas *cp = netdev_priv(dev);
4661         unsigned long flags;
4662 
4663         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4664                 return -EINVAL;
4665 
4666         /* Restart link process. */
4667         spin_lock_irqsave(&cp->lock, flags);
4668         cas_begin_auto_negotiation(cp, NULL);
4669         spin_unlock_irqrestore(&cp->lock, flags);
4670 
4671         return 0;
4672 }
4673 
4674 static u32 cas_get_link(struct net_device *dev)
4675 {
4676         struct cas *cp = netdev_priv(dev);
4677         return cp->lstate == link_up;
4678 }
4679 
4680 static u32 cas_get_msglevel(struct net_device *dev)
4681 {
4682         struct cas *cp = netdev_priv(dev);
4683         return cp->msg_enable;
4684 }
4685 
4686 static void cas_set_msglevel(struct net_device *dev, u32 value)
4687 {
4688         struct cas *cp = netdev_priv(dev);
4689         cp->msg_enable = value;
4690 }
4691 
4692 static int cas_get_regs_len(struct net_device *dev)
4693 {
4694         struct cas *cp = netdev_priv(dev);
4695         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4696 }
4697 
4698 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4699                              void *p)
4700 {
4701         struct cas *cp = netdev_priv(dev);
4702         regs->version = 0;
4703         /* cas_read_regs handles locks (cp->lock).  */
4704         cas_read_regs(cp, p, regs->len / sizeof(u32));
4705 }
4706 
4707 static int cas_get_sset_count(struct net_device *dev, int sset)
4708 {
4709         switch (sset) {
4710         case ETH_SS_STATS:
4711                 return CAS_NUM_STAT_KEYS;
4712         default:
4713                 return -EOPNOTSUPP;
4714         }
4715 }
4716 
4717 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4718 {
4719          memcpy(data, &ethtool_cassini_statnames,
4720                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4721 }
4722 
4723 static void cas_get_ethtool_stats(struct net_device *dev,
4724                                       struct ethtool_stats *estats, u64 *data)
4725 {
4726         struct cas *cp = netdev_priv(dev);
4727         struct net_device_stats *stats = cas_get_stats(cp->dev);
4728         int i = 0;
4729         data[i++] = stats->collisions;
4730         data[i++] = stats->rx_bytes;
4731         data[i++] = stats->rx_crc_errors;
4732         data[i++] = stats->rx_dropped;
4733         data[i++] = stats->rx_errors;
4734         data[i++] = stats->rx_fifo_errors;
4735         data[i++] = stats->rx_frame_errors;
4736         data[i++] = stats->rx_length_errors;
4737         data[i++] = stats->rx_over_errors;
4738         data[i++] = stats->rx_packets;
4739         data[i++] = stats->tx_aborted_errors;
4740         data[i++] = stats->tx_bytes;
4741         data[i++] = stats->tx_dropped;
4742         data[i++] = stats->tx_errors;
4743         data[i++] = stats->tx_fifo_errors;
4744         data[i++] = stats->tx_packets;
4745         BUG_ON(i != CAS_NUM_STAT_KEYS);
4746 }
4747 
4748 static const struct ethtool_ops cas_ethtool_ops = {
4749         .get_drvinfo            = cas_get_drvinfo,
4750         .nway_reset             = cas_nway_reset,
4751         .get_link               = cas_get_link,
4752         .get_msglevel           = cas_get_msglevel,
4753         .set_msglevel           = cas_set_msglevel,
4754         .get_regs_len           = cas_get_regs_len,
4755         .get_regs               = cas_get_regs,
4756         .get_sset_count         = cas_get_sset_count,
4757         .get_strings            = cas_get_strings,
4758         .get_ethtool_stats      = cas_get_ethtool_stats,
4759         .get_link_ksettings     = cas_get_link_ksettings,
4760         .set_link_ksettings     = cas_set_link_ksettings,
4761 };
4762 
4763 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4764 {
4765         struct cas *cp = netdev_priv(dev);
4766         struct mii_ioctl_data *data = if_mii(ifr);
4767         unsigned long flags;
4768         int rc = -EOPNOTSUPP;
4769 
4770         /* Hold the PM mutex while doing ioctl's or we may collide
4771          * with open/close and power management and oops.
4772          */
4773         mutex_lock(&cp->pm_mutex);
4774         switch (cmd) {
4775         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4776                 data->phy_id = cp->phy_addr;
4777                 /* Fallthrough... */
4778 
4779         case SIOCGMIIREG:               /* Read MII PHY register. */
4780                 spin_lock_irqsave(&cp->lock, flags);
4781                 cas_mif_poll(cp, 0);
4782                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4783                 cas_mif_poll(cp, 1);
4784                 spin_unlock_irqrestore(&cp->lock, flags);
4785                 rc = 0;
4786                 break;
4787 
4788         case SIOCSMIIREG:               /* Write MII PHY register. */
4789                 spin_lock_irqsave(&cp->lock, flags);
4790                 cas_mif_poll(cp, 0);
4791                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4792                 cas_mif_poll(cp, 1);
4793                 spin_unlock_irqrestore(&cp->lock, flags);
4794                 break;
4795         default:
4796                 break;
4797         }
4798 
4799         mutex_unlock(&cp->pm_mutex);
4800         return rc;
4801 }
4802 
4803 /* When this chip sits underneath an Intel 31154 bridge, it is the
4804  * only subordinate device and we can tweak the bridge settings to
4805  * reflect that fact.
4806  */
4807 static void cas_program_bridge(struct pci_dev *cas_pdev)
4808 {
4809         struct pci_dev *pdev = cas_pdev->bus->self;
4810         u32 val;
4811 
4812         if (!pdev)
4813                 return;
4814 
4815         if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4816                 return;
4817 
4818         /* Clear bit 10 (Bus Parking Control) in the Secondary
4819          * Arbiter Control/Status Register which lives at offset
4820          * 0x41.  Using a 32-bit word read/modify/write at 0x40
4821          * is much simpler so that's how we do this.
4822          */
4823         pci_read_config_dword(pdev, 0x40, &val);
4824         val &= ~0x00040000;
4825         pci_write_config_dword(pdev, 0x40, val);
4826 
4827         /* Max out the Multi-Transaction Timer settings since
4828          * Cassini is the only device present.
4829          *
4830          * The register is 16-bit and lives at 0x50.  When the
4831          * settings are enabled, it extends the GRANT# signal
4832          * for a requestor after a transaction is complete.  This
4833          * allows the next request to run without first needing
4834          * to negotiate the GRANT# signal back.
4835          *
4836          * Bits 12:10 define the grant duration:
4837          *
4838          *      1       --      16 clocks
4839          *      2       --      32 clocks
4840          *      3       --      64 clocks
4841          *      4       --      128 clocks
4842          *      5       --      256 clocks
4843          *
4844          * All other values are illegal.
4845          *
4846          * Bits 09:00 define which REQ/GNT signal pairs get the
4847          * GRANT# signal treatment.  We set them all.
4848          */
4849         pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4850 
4851         /* The Read Prefecth Policy register is 16-bit and sits at
4852          * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4853          * enable it and max out all of the settings since only one
4854          * device is sitting underneath and thus bandwidth sharing is
4855          * not an issue.
4856          *
4857          * The register has several 3 bit fields, which indicates a
4858          * multiplier applied to the base amount of prefetching the
4859          * chip would do.  These fields are at:
4860          *
4861          *      15:13   ---     ReRead Primary Bus
4862          *      12:10   ---     FirstRead Primary Bus
4863          *      09:07   ---     ReRead Secondary Bus
4864          *      06:04   ---     FirstRead Secondary Bus
4865          *
4866          * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4867          * get enabled on.  Bit 3 is a grouped enabler which controls
4868          * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4869          * the individual REQ/GNT pairs [2:0].
4870          */
4871         pci_write_config_word(pdev, 0x52,
4872                               (0x7 << 13) |
4873                               (0x7 << 10) |
4874                               (0x7 <<  7) |
4875                               (0x7 <<  4) |
4876                               (0xf <<  0));
4877 
4878         /* Force cacheline size to 0x8 */
4879         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4880 
4881         /* Force latency timer to maximum setting so Cassini can
4882          * sit on the bus as long as it likes.
4883          */
4884         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4885 }
4886 
4887 static const struct net_device_ops cas_netdev_ops = {
4888         .ndo_open               = cas_open,
4889         .ndo_stop               = cas_close,
4890         .ndo_start_xmit         = cas_start_xmit,
4891         .ndo_get_stats          = cas_get_stats,
4892         .ndo_set_rx_mode        = cas_set_multicast,
4893         .ndo_do_ioctl           = cas_ioctl,
4894         .ndo_tx_timeout         = cas_tx_timeout,
4895         .ndo_change_mtu         = cas_change_mtu,
4896         .ndo_set_mac_address    = eth_mac_addr,
4897         .ndo_validate_addr      = eth_validate_addr,
4898 #ifdef CONFIG_NET_POLL_CONTROLLER
4899         .ndo_poll_controller    = cas_netpoll,
4900 #endif
4901 };
4902 
4903 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4904 {
4905         static int cas_version_printed = 0;
4906         unsigned long casreg_len;
4907         struct net_device *dev;
4908         struct cas *cp;
4909         int i, err, pci_using_dac;
4910         u16 pci_cmd;
4911         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4912 
4913         if (cas_version_printed++ == 0)
4914                 pr_info("%s", version);
4915 
4916         err = pci_enable_device(pdev);
4917         if (err) {
4918                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4919                 return err;
4920         }
4921 
4922         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4923                 dev_err(&pdev->dev, "Cannot find proper PCI device "
4924                        "base address, aborting\n");
4925                 err = -ENODEV;
4926                 goto err_out_disable_pdev;
4927         }
4928 
4929         dev = alloc_etherdev(sizeof(*cp));
4930         if (!dev) {
4931                 err = -ENOMEM;
4932                 goto err_out_disable_pdev;
4933         }
4934         SET_NETDEV_DEV(dev, &pdev->dev);
4935 
4936         err = pci_request_regions(pdev, dev->name);
4937         if (err) {
4938                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4939                 goto err_out_free_netdev;
4940         }
4941         pci_set_master(pdev);
4942 
4943         /* we must always turn on parity response or else parity
4944          * doesn't get generated properly. disable SERR/PERR as well.
4945          * in addition, we want to turn MWI on.
4946          */
4947         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4948         pci_cmd &= ~PCI_COMMAND_SERR;
4949         pci_cmd |= PCI_COMMAND_PARITY;
4950         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4951         if (pci_try_set_mwi(pdev))
4952                 pr_warn("Could not enable MWI for %s\n", pci_name(pdev));
4953 
4954         cas_program_bridge(pdev);
4955 
4956         /*
4957          * On some architectures, the default cache line size set
4958          * by pci_try_set_mwi reduces perforamnce.  We have to increase
4959          * it for this case.  To start, we'll print some configuration
4960          * data.
4961          */
4962 #if 1
4963         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4964                              &orig_cacheline_size);
4965         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4966                 cas_cacheline_size =
4967                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4968                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4969                 if (pci_write_config_byte(pdev,
4970                                           PCI_CACHE_LINE_SIZE,
4971                                           cas_cacheline_size)) {
4972                         dev_err(&pdev->dev, "Could not set PCI cache "
4973                                "line size\n");
4974                         goto err_out_free_res;
4975                 }
4976         }
4977 #endif
4978 
4979 
4980         /* Configure DMA attributes. */
4981         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4982                 pci_using_dac = 1;
4983                 err = pci_set_consistent_dma_mask(pdev,
4984                                                   DMA_BIT_MASK(64));
4985                 if (err < 0) {
4986                         dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
4987                                "for consistent allocations\n");
4988                         goto err_out_free_res;
4989                 }
4990 
4991         } else {
4992                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4993                 if (err) {
4994                         dev_err(&pdev->dev, "No usable DMA configuration, "
4995                                "aborting\n");
4996                         goto err_out_free_res;
4997                 }
4998                 pci_using_dac = 0;
4999         }
5000 
5001         casreg_len = pci_resource_len(pdev, 0);
5002 
5003         cp = netdev_priv(dev);
5004         cp->pdev = pdev;
5005 #if 1
5006         /* A value of 0 indicates we never explicitly set it */
5007         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5008 #endif
5009         cp->dev = dev;
5010         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5011           cassini_debug;
5012 
5013 #if defined(CONFIG_SPARC)
5014         cp->of_node = pci_device_to_OF_node(pdev);
5015 #endif
5016 
5017         cp->link_transition = LINK_TRANSITION_UNKNOWN;
5018         cp->link_transition_jiffies_valid = 0;
5019 
5020         spin_lock_init(&cp->lock);
5021         spin_lock_init(&cp->rx_inuse_lock);
5022         spin_lock_init(&cp->rx_spare_lock);
5023         for (i = 0; i < N_TX_RINGS; i++) {
5024                 spin_lock_init(&cp->stat_lock[i]);
5025                 spin_lock_init(&cp->tx_lock[i]);
5026         }
5027         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5028         mutex_init(&cp->pm_mutex);
5029 
5030         timer_setup(&cp->link_timer, cas_link_timer, 0);
5031 
5032 #if 1
5033         /* Just in case the implementation of atomic operations
5034          * change so that an explicit initialization is necessary.
5035          */
5036         atomic_set(&cp->reset_task_pending, 0);
5037         atomic_set(&cp->reset_task_pending_all, 0);
5038         atomic_set(&cp->reset_task_pending_spare, 0);
5039         atomic_set(&cp->reset_task_pending_mtu, 0);
5040 #endif
5041         INIT_WORK(&cp->reset_task, cas_reset_task);
5042 
5043         /* Default link parameters */
5044         if (link_mode >= 0 && link_mode < 6)
5045                 cp->link_cntl = link_modes[link_mode];
5046         else
5047                 cp->link_cntl = BMCR_ANENABLE;
5048         cp->lstate = link_down;
5049         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5050         netif_carrier_off(cp->dev);
5051         cp->timer_ticks = 0;
5052 
5053         /* give us access to cassini registers */
5054         cp->regs = pci_iomap(pdev, 0, casreg_len);
5055         if (!cp->regs) {
5056                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5057                 goto err_out_free_res;
5058         }
5059         cp->casreg_len = casreg_len;
5060 
5061         pci_save_state(pdev);
5062         cas_check_pci_invariants(cp);
5063         cas_hard_reset(cp);
5064         cas_reset(cp, 0);
5065         if (cas_check_invariants(cp))
5066                 goto err_out_iounmap;
5067         if (cp->cas_flags & CAS_FLAG_SATURN)
5068                 cas_saturn_firmware_init(cp);
5069 
5070         cp->init_block = (struct cas_init_block *)
5071                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5072                                      &cp->block_dvma);
5073         if (!cp->init_block) {
5074                 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5075                 goto err_out_iounmap;
5076         }
5077 
5078         for (i = 0; i < N_TX_RINGS; i++)
5079                 cp->init_txds[i] = cp->init_block->txds[i];
5080 
5081         for (i = 0; i < N_RX_DESC_RINGS; i++)
5082                 cp->init_rxds[i] = cp->init_block->rxds[i];
5083 
5084         for (i = 0; i < N_RX_COMP_RINGS; i++)
5085                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5086 
5087         for (i = 0; i < N_RX_FLOWS; i++)
5088                 skb_queue_head_init(&cp->rx_flows[i]);
5089 
5090         dev->netdev_ops = &cas_netdev_ops;
5091         dev->ethtool_ops = &cas_ethtool_ops;
5092         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5093 
5094 #ifdef USE_NAPI
5095         netif_napi_add(dev, &cp->napi, cas_poll, 64);
5096 #endif
5097         dev->irq = pdev->irq;
5098         dev->dma = 0;
5099 
5100         /* Cassini features. */
5101         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5102                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5103 
5104         if (pci_using_dac)
5105                 dev->features |= NETIF_F_HIGHDMA;
5106 
5107         /* MTU range: 60 - varies or 9000 */
5108         dev->min_mtu = CAS_MIN_MTU;
5109         dev->max_mtu = CAS_MAX_MTU;
5110 
5111         if (register_netdev(dev)) {
5112                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5113                 goto err_out_free_consistent;
5114         }
5115 
5116         i = readl(cp->regs + REG_BIM_CFG);
5117         netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5118                     (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5119                     (i & BIM_CFG_32BIT) ? "32" : "64",
5120                     (i & BIM_CFG_66MHZ) ? "66" : "33",
5121                     (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5122                     dev->dev_addr);
5123 
5124         pci_set_drvdata(pdev, dev);
5125         cp->hw_running = 1;
5126         cas_entropy_reset(cp);
5127         cas_phy_init(cp);
5128         cas_begin_auto_negotiation(cp, NULL);
5129         return 0;
5130 
5131 err_out_free_consistent:
5132         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5133                             cp->init_block, cp->block_dvma);
5134 
5135 err_out_iounmap:
5136         mutex_lock(&cp->pm_mutex);
5137         if (cp->hw_running)
5138                 cas_shutdown(cp);
5139         mutex_unlock(&cp->pm_mutex);
5140 
5141         pci_iounmap(pdev, cp->regs);
5142 
5143 
5144 err_out_free_res:
5145         pci_release_regions(pdev);
5146 
5147         /* Try to restore it in case the error occurred after we
5148          * set it.
5149          */
5150         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5151 
5152 err_out_free_netdev:
5153         free_netdev(dev);
5154 
5155 err_out_disable_pdev:
5156         pci_disable_device(pdev);
5157         return -ENODEV;
5158 }
5159 
5160 static void cas_remove_one(struct pci_dev *pdev)
5161 {
5162         struct net_device *dev = pci_get_drvdata(pdev);
5163         struct cas *cp;
5164         if (!dev)
5165                 return;
5166 
5167         cp = netdev_priv(dev);
5168         unregister_netdev(dev);
5169 
5170         vfree(cp->fw_data);
5171 
5172         mutex_lock(&cp->pm_mutex);
5173         cancel_work_sync(&cp->reset_task);
5174         if (cp->hw_running)
5175                 cas_shutdown(cp);
5176         mutex_unlock(&cp->pm_mutex);
5177 
5178 #if 1
5179         if (cp->orig_cacheline_size) {
5180                 /* Restore the cache line size if we had modified
5181                  * it.
5182                  */
5183                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5184                                       cp->orig_cacheline_size);
5185         }
5186 #endif
5187         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5188                             cp->init_block, cp->block_dvma);
5189         pci_iounmap(pdev, cp->regs);
5190         free_netdev(dev);
5191         pci_release_regions(pdev);
5192         pci_disable_device(pdev);
5193 }
5194 
5195 #ifdef CONFIG_PM
5196 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5197 {
5198         struct net_device *dev = pci_get_drvdata(pdev);
5199         struct cas *cp = netdev_priv(dev);
5200         unsigned long flags;
5201 
5202         mutex_lock(&cp->pm_mutex);
5203 
5204         /* If the driver is opened, we stop the DMA */
5205         if (cp->opened) {
5206                 netif_device_detach(dev);
5207 
5208                 cas_lock_all_save(cp, flags);
5209 
5210                 /* We can set the second arg of cas_reset to 0
5211                  * because on resume, we'll call cas_init_hw with
5212                  * its second arg set so that autonegotiation is
5213                  * restarted.
5214                  */
5215                 cas_reset(cp, 0);
5216                 cas_clean_rings(cp);
5217                 cas_unlock_all_restore(cp, flags);
5218         }
5219 
5220         if (cp->hw_running)
5221                 cas_shutdown(cp);
5222         mutex_unlock(&cp->pm_mutex);
5223 
5224         return 0;
5225 }
5226 
5227 static int cas_resume(struct pci_dev *pdev)
5228 {
5229         struct net_device *dev = pci_get_drvdata(pdev);
5230         struct cas *cp = netdev_priv(dev);
5231 
5232         netdev_info(dev, "resuming\n");
5233 
5234         mutex_lock(&cp->pm_mutex);
5235         cas_hard_reset(cp);
5236         if (cp->opened) {
5237                 unsigned long flags;
5238                 cas_lock_all_save(cp, flags);
5239                 cas_reset(cp, 0);
5240                 cp->hw_running = 1;
5241                 cas_clean_rings(cp);
5242                 cas_init_hw(cp, 1);
5243                 cas_unlock_all_restore(cp, flags);
5244 
5245                 netif_device_attach(dev);
5246         }
5247         mutex_unlock(&cp->pm_mutex);
5248         return 0;
5249 }
5250 #endif /* CONFIG_PM */
5251 
5252 static struct pci_driver cas_driver = {
5253         .name           = DRV_MODULE_NAME,
5254         .id_table       = cas_pci_tbl,
5255         .probe          = cas_init_one,
5256         .remove         = cas_remove_one,
5257 #ifdef CONFIG_PM
5258         .suspend        = cas_suspend,
5259         .resume         = cas_resume
5260 #endif
5261 };
5262 
5263 static int __init cas_init(void)
5264 {
5265         if (linkdown_timeout > 0)
5266                 link_transition_timeout = linkdown_timeout * HZ;
5267         else
5268                 link_transition_timeout = 0;
5269 
5270         return pci_register_driver(&cas_driver);
5271 }
5272 
5273 static void __exit cas_cleanup(void)
5274 {
5275         pci_unregister_driver(&cas_driver);
5276 }
5277 
5278 module_init(cas_init);
5279 module_exit(cas_cleanup);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/sun/cassini.c

DEFINITIONS
