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18
19 #define SIS900_TOTAL_SIZE 0x100
20
21
22 enum sis900_registers {
23 cr=0x0,
24 cfg=0x4,
25 mear=0x8,
26 ptscr=0xc,
27 isr=0x10,
28 imr=0x14,
29 ier=0x18,
30 epar=0x18,
31 txdp=0x20,
32 txcfg=0x24,
33 rxdp=0x30,
34 rxcfg=0x34,
35 flctrl=0x38,
36 rxlen=0x3c,
37 rfcr=0x48,
38 rfdr=0x4C,
39 pmctrl=0xB0,
40 pmer=0xB4
41 };
42
43
44 enum sis900_command_register_bits {
45 RELOAD = 0x00000400, ACCESSMODE = 0x00000200,
46 RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
47 TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
48 TxDIS = 0x00000002, TxENA = 0x00000001
49 };
50
51 enum sis900_configuration_register_bits {
52 DESCRFMT = 0x00000100 , REQALG = 0x00000080,
53 SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
54 PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
55
56 RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
57 EDB_MASTER_EN = 0x00002000
58 };
59
60 enum sis900_eeprom_access_register_bits {
61 MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010,
62 EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
63 EEDI = 0x00000001
64 };
65
66 enum sis900_interrupt_register_bits {
67 WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
68 TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
69 SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000,
70 RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
71 MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200,
72 TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040,
73 RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
74 RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001
75 };
76
77 enum sis900_interrupt_enable_register_bits {
78 IE = 0x00000001
79 };
80
81
82 #define MAX_DMA_RANGE 7
83 #define TxMXDMA_shift 20
84 #define RxMXDMA_shift 20
85
86 enum sis900_tx_rx_dma{
87 DMA_BURST_512 = 0, DMA_BURST_64 = 5
88 };
89
90
91 #define TX_FILL_THRESH 16
92 #define TxFILLT_shift 8
93 #define TxDRNT_shift 0
94 #define TxDRNT_100 48
95 #define TxDRNT_10 16
96
97 enum sis900_transmit_config_register_bits {
98 TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
99 TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
100 TxDRNT = 0x0000003F
101 };
102
103
104 #define RxDRNT_shift 1
105 #define RxDRNT_100 16
106 #define RxDRNT_10 24
107
108 enum sis900_reveive_config_register_bits {
109 RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
110 RxAJAB = 0x08000000, RxDRNT = 0x0000007F
111 };
112
113 #define RFAA_shift 28
114 #define RFADDR_shift 16
115
116 enum sis900_receive_filter_control_register_bits {
117 RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
118 RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
119 };
120
121 enum sis900_reveive_filter_data_mask {
122 RFDAT = 0x0000FFFF
123 };
124
125
126 enum sis900_eeprom_address {
127 EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
128 EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b
129 };
130
131
132 enum sis900_eeprom_command {
133 EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
134 EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
135 EEeraseAll = 0x0120, EEwriteAll = 0x0110,
136 EEaddrMask = 0x013F, EEcmdShift = 16
137 };
138
139
140 enum sis96x_eeprom_command {
141 EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
142 };
143
144
145 enum sis900_pci_registers {
146 CFGPMC = 0x40,
147 CFGPMCSR = 0x44
148 };
149
150
151 enum sis900_cfgpmc_register_bits {
152 PMVER = 0x00070000,
153 DSI = 0x00100000,
154 PMESP = 0xf8000000
155 };
156
157 enum sis900_pmesp_bits {
158 PME_D0 = 0x1,
159 PME_D1 = 0x2,
160 PME_D2 = 0x4,
161 PME_D3H = 0x8,
162 PME_D3C = 0x10
163 };
164
165
166 enum sis900_cfgpmcsr_register_bits {
167 PMESTS = 0x00004000,
168 PME_EN = 0x00000100,
169 PWR_STA = 0x00000003
170 };
171
172
173 enum sis900_power_management_control_register_bits {
174 LINKLOSS = 0x00000001,
175 LINKON = 0x00000002,
176 MAGICPKT = 0x00000400,
177 ALGORITHM = 0x00000800,
178 FRM1EN = 0x00100000,
179 FRM2EN = 0x00200000,
180 FRM3EN = 0x00400000,
181 FRM1ACS = 0x01000000,
182 FRM2ACS = 0x02000000,
183 FRM3ACS = 0x04000000,
184 WAKEALL = 0x40000000,
185 GATECLK = 0x80000000
186 };
187
188
189 #define MIIread 0x6000
190 #define MIIwrite 0x5002
191 #define MIIpmdShift 7
192 #define MIIregShift 2
193 #define MIIcmdLen 16
194 #define MIIcmdShift 16
195
196
197 enum sis900_buffer_status {
198 OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000,
199 SUPCRC = 0x10000000, INCCRC = 0x10000000,
200 OK = 0x08000000, DSIZE = 0x00000FFF
201 };
202
203 enum sis900_tx_buffer_status {
204 ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
205 DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000,
206 EXCCOLL = 0x00100000, COLCNT = 0x000F0000
207 };
208
209 enum sis900_rx_buffer_status {
210 OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000,
211 MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
212 RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000,
213 FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000
214 };
215
216
217 enum mii_registers {
218 MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
219 MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005,
220 MII_ANEXT = 0x0006
221 };
222
223
224 enum sis_mii_registers {
225 MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
226 MII_MASK = 0x0013, MII_RESV = 0x0014
227 };
228
229
230 enum ics_mii_registers {
231 MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
232 MII_EXTCTRL2 = 0x0013
233 };
234
235
236 enum amd_mii_registers {
237 MII_STATUS_SUMMARY = 0x0018
238 };
239
240
241 enum mii_control_register_bits {
242 MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
243 MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
244 MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
245 MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
246 };
247
248
249 enum mii_status_register_bits {
250 MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
251 MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
252 MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
253 MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
254 MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
255 MII_STAT_CAN_T4 = 0x8000
256 };
257
258 #define MII_ID1_OUI_LO 0xFC00
259 #define MII_ID1_MODEL 0x03F0
260 #define MII_ID1_REV 0x000F
261
262
263
264
265 enum mii_nway_register_bits {
266 MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
267 MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040,
268 MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100,
269 MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400,
270 MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000,
271 MII_NWAY_NP = 0x8000
272 };
273
274 enum mii_stsout_register_bits {
275 MII_STSOUT_LINK_FAIL = 0x4000,
276 MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040
277 };
278
279 enum mii_stsics_register_bits {
280 MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
281 MII_STSICS_LINKSTS = 0x0001
282 };
283
284 enum mii_stssum_register_bits {
285 MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
286 MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001
287 };
288
289 enum sis900_revision_id {
290 SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
291 SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83,
292 SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90,
293 SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03
294 };
295
296 enum sis630_revision_id {
297 SIS630A0 = 0x00, SIS630A1 = 0x01,
298 SIS630B0 = 0x10, SIS630B1 = 0x11
299 };
300
301 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
302 #define FDX_CAPABLE_HALF_SELECTED 1
303 #define FDX_CAPABLE_FULL_SELECTED 2
304
305 #define HW_SPEED_UNCONFIG 0
306 #define HW_SPEED_HOME 1
307 #define HW_SPEED_10_MBPS 10
308 #define HW_SPEED_100_MBPS 100
309 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
310
311 #define CRC_SIZE 4
312 #define MAC_HEADER_SIZE 14
313
314 #if IS_ENABLED(CONFIG_VLAN_8021Q)
315 #define MAX_FRAME_SIZE (1518 + 4)
316 #else
317 #define MAX_FRAME_SIZE 1518
318 #endif
319
320 #define TX_BUF_SIZE (MAX_FRAME_SIZE+18)
321 #define RX_BUF_SIZE (MAX_FRAME_SIZE+18)
322
323 #define NUM_TX_DESC 16
324 #define NUM_RX_DESC 16
325 #define TX_TOTAL_SIZE NUM_TX_DESC*sizeof(BufferDesc)
326 #define RX_TOTAL_SIZE NUM_RX_DESC*sizeof(BufferDesc)
327
328
329 #define SIS630_VENDOR_ID 0x1039
330 #define SIS630_DEVICE_ID 0x0630