root/drivers/net/ethernet/sfc/io.h

INCLUDED FROM

DEFINITIONS

1. _efx_writeq
2. _efx_readq
3. _efx_writed
4. _efx_readd
5. efx_writeo
6. efx_sram_writeq
7. efx_writed
8. efx_reado
9. efx_sram_readq
10. efx_readd
11. efx_writeo_table
12. efx_reado_table
13. efx_paged_reg
14. _efx_writeo_page
15. _efx_writed_page
16. _efx_writed_page_locked

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7 
   8 #ifndef EFX_IO_H
   9 #define EFX_IO_H
  10 
  11 #include <linux/io.h>
  12 #include <linux/spinlock.h>
  13 
  14 /**************************************************************************
  15  *
  16  * NIC register I/O
  17  *
  18  **************************************************************************
  19  *
  20  * Notes on locking strategy for the Falcon architecture:
  21  *
  22  * Many CSRs are very wide and cannot be read or written atomically.
  23  * Writes from the host are buffered by the Bus Interface Unit (BIU)
  24  * up to 128 bits.  Whenever the host writes part of such a register,
  25  * the BIU collects the written value and does not write to the
  26  * underlying register until all 4 dwords have been written.  A
  27  * similar buffering scheme applies to host access to the NIC's 64-bit
  28  * SRAM.
  29  *
  30  * Writes to different CSRs and 64-bit SRAM words must be serialised,
  31  * since interleaved access can result in lost writes.  We use
  32  * efx_nic::biu_lock for this.
  33  *
  34  * We also serialise reads from 128-bit CSRs and SRAM with the same
  35  * spinlock.  This may not be necessary, but it doesn't really matter
  36  * as there are no such reads on the fast path.
  37  *
  38  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
  39  * 128-bit but are special-cased in the BIU to avoid the need for
  40  * locking in the host:
  41  *
  42  * - They are write-only.
  43  * - The semantics of writing to these registers are such that
  44  *   replacing the low 96 bits with zero does not affect functionality.
  45  * - If the host writes to the last dword address of such a register
  46  *   (i.e. the high 32 bits) the underlying register will always be
  47  *   written.  If the collector and the current write together do not
  48  *   provide values for all 128 bits of the register, the low 96 bits
  49  *   will be written as zero.
  50  * - If the host writes to the address of any other part of such a
  51  *   register while the collector already holds values for some other
  52  *   register, the write is discarded and the collector maintains its
  53  *   current state.
  54  *
  55  * The EF10 architecture exposes very few registers to the host and
  56  * most of them are only 32 bits wide.  The only exceptions are the MC
  57  * doorbell register pair, which has its own latching, and
  58  * TX_DESC_UPD, which works in a similar way to the Falcon
  59  * architecture.
  60  */
  61 
  62 #if BITS_PER_LONG == 64
  63 #define EFX_USE_QWORD_IO 1
  64 #endif
  65 
  66 /* Hardware issue requires that only 64-bit naturally aligned writes
  67  * are seen by hardware. Its not strictly necessary to restrict to
  68  * x86_64 arch, but done for safety since unusual write combining behaviour
  69  * can break PIO.
  70  */
  71 #ifdef CONFIG_X86_64
  72 /* PIO is a win only if write-combining is possible */
  73 #ifdef ARCH_HAS_IOREMAP_WC
  74 #define EFX_USE_PIO 1
  75 #endif
  76 #endif
  77 
  78 #ifdef EFX_USE_QWORD_IO
  79 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
  80                                   unsigned int reg)
  81 {
  82         __raw_writeq((__force u64)value, efx->membase + reg);
  83 }
  84 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
  85 {
  86         return (__force __le64)__raw_readq(efx->membase + reg);
  87 }
  88 #endif
  89 
  90 static inline void _efx_writed(struct efx_nic *efx, __le32 value,
  91                                   unsigned int reg)
  92 {
  93         __raw_writel((__force u32)value, efx->membase + reg);
  94 }
  95 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
  96 {
  97         return (__force __le32)__raw_readl(efx->membase + reg);
  98 }
  99 
 100 /* Write a normal 128-bit CSR, locking as appropriate. */
 101 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,
 102                               unsigned int reg)
 103 {
 104         unsigned long flags __attribute__ ((unused));
 105 
 106         netif_vdbg(efx, hw, efx->net_dev,
 107                    "writing register %x with " EFX_OWORD_FMT "\n", reg,
 108                    EFX_OWORD_VAL(*value));
 109 
 110         spin_lock_irqsave(&efx->biu_lock, flags);
 111 #ifdef EFX_USE_QWORD_IO
 112         _efx_writeq(efx, value->u64[0], reg + 0);
 113         _efx_writeq(efx, value->u64[1], reg + 8);
 114 #else
 115         _efx_writed(efx, value->u32[0], reg + 0);
 116         _efx_writed(efx, value->u32[1], reg + 4);
 117         _efx_writed(efx, value->u32[2], reg + 8);
 118         _efx_writed(efx, value->u32[3], reg + 12);
 119 #endif
 120         spin_unlock_irqrestore(&efx->biu_lock, flags);
 121 }
 122 
 123 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
 124 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
 125                                    const efx_qword_t *value, unsigned int index)
 126 {
 127         unsigned int addr = index * sizeof(*value);
 128         unsigned long flags __attribute__ ((unused));
 129 
 130         netif_vdbg(efx, hw, efx->net_dev,
 131                    "writing SRAM address %x with " EFX_QWORD_FMT "\n",
 132                    addr, EFX_QWORD_VAL(*value));
 133 
 134         spin_lock_irqsave(&efx->biu_lock, flags);
 135 #ifdef EFX_USE_QWORD_IO
 136         __raw_writeq((__force u64)value->u64[0], membase + addr);
 137 #else
 138         __raw_writel((__force u32)value->u32[0], membase + addr);
 139         __raw_writel((__force u32)value->u32[1], membase + addr + 4);
 140 #endif
 141         spin_unlock_irqrestore(&efx->biu_lock, flags);
 142 }
 143 
 144 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
 145 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
 146                               unsigned int reg)
 147 {
 148         netif_vdbg(efx, hw, efx->net_dev,
 149                    "writing register %x with "EFX_DWORD_FMT"\n",
 150                    reg, EFX_DWORD_VAL(*value));
 151 
 152         /* No lock required */
 153         _efx_writed(efx, value->u32[0], reg);
 154 }
 155 
 156 /* Read a 128-bit CSR, locking as appropriate. */
 157 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
 158                              unsigned int reg)
 159 {
 160         unsigned long flags __attribute__ ((unused));
 161 
 162         spin_lock_irqsave(&efx->biu_lock, flags);
 163         value->u32[0] = _efx_readd(efx, reg + 0);
 164         value->u32[1] = _efx_readd(efx, reg + 4);
 165         value->u32[2] = _efx_readd(efx, reg + 8);
 166         value->u32[3] = _efx_readd(efx, reg + 12);
 167         spin_unlock_irqrestore(&efx->biu_lock, flags);
 168 
 169         netif_vdbg(efx, hw, efx->net_dev,
 170                    "read from register %x, got " EFX_OWORD_FMT "\n", reg,
 171                    EFX_OWORD_VAL(*value));
 172 }
 173 
 174 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
 175 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
 176                                   efx_qword_t *value, unsigned int index)
 177 {
 178         unsigned int addr = index * sizeof(*value);
 179         unsigned long flags __attribute__ ((unused));
 180 
 181         spin_lock_irqsave(&efx->biu_lock, flags);
 182 #ifdef EFX_USE_QWORD_IO
 183         value->u64[0] = (__force __le64)__raw_readq(membase + addr);
 184 #else
 185         value->u32[0] = (__force __le32)__raw_readl(membase + addr);
 186         value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
 187 #endif
 188         spin_unlock_irqrestore(&efx->biu_lock, flags);
 189 
 190         netif_vdbg(efx, hw, efx->net_dev,
 191                    "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
 192                    addr, EFX_QWORD_VAL(*value));
 193 }
 194 
 195 /* Read a 32-bit CSR or SRAM */
 196 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
 197                                 unsigned int reg)
 198 {
 199         value->u32[0] = _efx_readd(efx, reg);
 200         netif_vdbg(efx, hw, efx->net_dev,
 201                    "read from register %x, got "EFX_DWORD_FMT"\n",
 202                    reg, EFX_DWORD_VAL(*value));
 203 }
 204 
 205 /* Write a 128-bit CSR forming part of a table */
 206 static inline void
 207 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,
 208                  unsigned int reg, unsigned int index)
 209 {
 210         efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
 211 }
 212 
 213 /* Read a 128-bit CSR forming part of a table */
 214 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
 215                                      unsigned int reg, unsigned int index)
 216 {
 217         efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
 218 }
 219 
 220 /* default VI stride (step between per-VI registers) is 8K */
 221 #define EFX_DEFAULT_VI_STRIDE 0x2000
 222 
 223 /* Calculate offset to page-mapped register */
 224 static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
 225                                          unsigned int reg)
 226 {
 227         return page * efx->vi_stride + reg;
 228 }
 229 
 230 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
 231 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
 232                                     unsigned int reg, unsigned int page)
 233 {
 234         reg = efx_paged_reg(efx, page, reg);
 235 
 236         netif_vdbg(efx, hw, efx->net_dev,
 237                    "writing register %x with " EFX_OWORD_FMT "\n", reg,
 238                    EFX_OWORD_VAL(*value));
 239 
 240 #ifdef EFX_USE_QWORD_IO
 241         _efx_writeq(efx, value->u64[0], reg + 0);
 242         _efx_writeq(efx, value->u64[1], reg + 8);
 243 #else
 244         _efx_writed(efx, value->u32[0], reg + 0);
 245         _efx_writed(efx, value->u32[1], reg + 4);
 246         _efx_writed(efx, value->u32[2], reg + 8);
 247         _efx_writed(efx, value->u32[3], reg + 12);
 248 #endif
 249 }
 250 #define efx_writeo_page(efx, value, reg, page)                          \
 251         _efx_writeo_page(efx, value,                                    \
 252                          reg +                                          \
 253                          BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
 254                          page)
 255 
 256 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
 257  * high bits of RX_DESC_UPD or TX_DESC_UPD)
 258  */
 259 static inline void
 260 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
 261                  unsigned int reg, unsigned int page)
 262 {
 263         efx_writed(efx, value, efx_paged_reg(efx, page, reg));
 264 }
 265 #define efx_writed_page(efx, value, reg, page)                          \
 266         _efx_writed_page(efx, value,                                    \
 267                          reg +                                          \
 268                          BUILD_BUG_ON_ZERO((reg) != 0x400 &&            \
 269                                            (reg) != 0x420 &&            \
 270                                            (reg) != 0x830 &&            \
 271                                            (reg) != 0x83c &&            \
 272                                            (reg) != 0xa18 &&            \
 273                                            (reg) != 0xa1c),             \
 274                          page)
 275 
 276 /* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
 277  * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
 278  * collector register.
 279  */
 280 static inline void _efx_writed_page_locked(struct efx_nic *efx,
 281                                            const efx_dword_t *value,
 282                                            unsigned int reg,
 283                                            unsigned int page)
 284 {
 285         unsigned long flags __attribute__ ((unused));
 286 
 287         if (page == 0) {
 288                 spin_lock_irqsave(&efx->biu_lock, flags);
 289                 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
 290                 spin_unlock_irqrestore(&efx->biu_lock, flags);
 291         } else {
 292                 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
 293         }
 294 }
 295 #define efx_writed_page_locked(efx, value, reg, page)                   \
 296         _efx_writed_page_locked(efx, value,                             \
 297                                 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
 298                                 page)
 299 
 300 #endif /* EFX_IO_H */