root/drivers/net/ethernet/sfc/mcdi_pcol.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2009-2013 Solarflare Communications Inc.
   5  */
   6 
   7 
   8 #ifndef MCDI_PCOL_H
   9 #define MCDI_PCOL_H
  10 
  11 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
  12 /* Power-on reset state */
  13 #define MC_FW_STATE_POR (1)
  14 /* If this is set in MC_RESET_STATE_REG then it should be
  15  * possible to jump into IMEM without loading code from flash. */
  16 #define MC_FW_WARM_BOOT_OK (2)
  17 /* The MC main image has started to boot. */
  18 #define MC_FW_STATE_BOOTING (4)
  19 /* The Scheduler has started. */
  20 #define MC_FW_STATE_SCHED (8)
  21 /* If this is set in MC_RESET_STATE_REG then it should be
  22  * possible to jump into IMEM without loading code from flash.
  23  * Unlike a warm boot, assume DMEM has been reloaded, so that
  24  * the MC persistent data must be reinitialised. */
  25 #define MC_FW_TEPID_BOOT_OK (16)
  26 /* We have entered the main firmware via recovery mode.  This
  27  * means that MC persistent data must be reinitialised, but that
  28  * we shouldn't touch PCIe config. */
  29 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
  30 /* BIST state has been initialized */
  31 #define MC_FW_BIST_INIT_OK (128)
  32 
  33 /* Siena MC shared memmory offsets */
  34 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
  35 #define MC_SMEM_P0_DOORBELL_OFST        0x000
  36 #define MC_SMEM_P1_DOORBELL_OFST        0x004
  37 /* The rest of these are firmware-defined */
  38 #define MC_SMEM_P0_PDU_OFST             0x008
  39 #define MC_SMEM_P1_PDU_OFST             0x108
  40 #define MC_SMEM_PDU_LEN                 0x100
  41 #define MC_SMEM_P0_PTP_TIME_OFST        0x7f0
  42 #define MC_SMEM_P0_STATUS_OFST          0x7f8
  43 #define MC_SMEM_P1_STATUS_OFST          0x7fc
  44 
  45 /* Values to be written to the per-port status dword in shared
  46  * memory on reboot and assert */
  47 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
  48 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
  49 
  50 /* Check whether an mcfw version (in host order) belongs to a bootloader */
  51 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
  52 
  53 /* The current version of the MCDI protocol.
  54  *
  55  * Note that the ROM burnt into the card only talks V0, so at the very
  56  * least every driver must support version 0 and MCDI_PCOL_VERSION
  57  */
  58 #define MCDI_PCOL_VERSION 2
  59 
  60 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
  61 
  62 /* MCDI version 1
  63  *
  64  * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
  65  * structure, filled in by the client.
  66  *
  67  *       0       7  8     16    20     22  23  24    31
  68  *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
  69  *               |                      |   |
  70  *               |                      |   \--- Response
  71  *               |                      \------- Error
  72  *               \------------------------------ Resync (always set)
  73  *
  74  * The client writes it's request into MC shared memory, and rings the
  75  * doorbell. Each request is completed by either by the MC writting
  76  * back into shared memory, or by writting out an event.
  77  *
  78  * All MCDI commands support completion by shared memory response. Each
  79  * request may also contain additional data (accounted for by HEADER.LEN),
  80  * and some response's may also contain additional data (again, accounted
  81  * for by HEADER.LEN).
  82  *
  83  * Some MCDI commands support completion by event, in which any associated
  84  * response data is included in the event.
  85  *
  86  * The protocol requires one response to be delivered for every request, a
  87  * request should not be sent unless the response for the previous request
  88  * has been received (either by polling shared memory, or by receiving
  89  * an event).
  90  */
  91 
  92 /** Request/Response structure */
  93 #define MCDI_HEADER_OFST 0
  94 #define MCDI_HEADER_CODE_LBN 0
  95 #define MCDI_HEADER_CODE_WIDTH 7
  96 #define MCDI_HEADER_RESYNC_LBN 7
  97 #define MCDI_HEADER_RESYNC_WIDTH 1
  98 #define MCDI_HEADER_DATALEN_LBN 8
  99 #define MCDI_HEADER_DATALEN_WIDTH 8
 100 #define MCDI_HEADER_SEQ_LBN 16
 101 #define MCDI_HEADER_SEQ_WIDTH 4
 102 #define MCDI_HEADER_RSVD_LBN 20
 103 #define MCDI_HEADER_RSVD_WIDTH 1
 104 #define MCDI_HEADER_NOT_EPOCH_LBN 21
 105 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
 106 #define MCDI_HEADER_ERROR_LBN 22
 107 #define MCDI_HEADER_ERROR_WIDTH 1
 108 #define MCDI_HEADER_RESPONSE_LBN 23
 109 #define MCDI_HEADER_RESPONSE_WIDTH 1
 110 #define MCDI_HEADER_XFLAGS_LBN 24
 111 #define MCDI_HEADER_XFLAGS_WIDTH 8
 112 /* Request response using event */
 113 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
 114 /* Request (and signal) early doorbell return */
 115 #define MCDI_HEADER_XFLAGS_DBRET 0x02
 116 
 117 /* Maximum number of payload bytes */
 118 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
 119 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
 120 
 121 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
 122 
 123 
 124 /* The MC can generate events for two reasons:
 125  *   - To advance a shared memory request if XFLAGS_EVREQ was set
 126  *   - As a notification (link state, i2c event), controlled
 127  *     via MC_CMD_LOG_CTRL
 128  *
 129  * Both events share a common structure:
 130  *
 131  *  0      32     33      36    44     52     60
 132  * | Data | Cont | Level | Src | Code | Rsvd |
 133  *           |
 134  *           \ There is another event pending in this notification
 135  *
 136  * If Code==CMDDONE, then the fields are further interpreted as:
 137  *
 138  *   - LEVEL==INFO    Command succeeded
 139  *   - LEVEL==ERR     Command failed
 140  *
 141  *    0     8         16      24     32
 142  *   | Seq | Datalen | Errno | Rsvd |
 143  *
 144  *   These fields are taken directly out of the standard MCDI header, i.e.,
 145  *   LEVEL==ERR, Datalen == 0 => Reboot
 146  *
 147  * Events can be squirted out of the UART (using LOG_CTRL) without a
 148  * MCDI header.  An event can be distinguished from a MCDI response by
 149  * examining the first byte which is 0xc0.  This corresponds to the
 150  * non-existent MCDI command MC_CMD_DEBUG_LOG.
 151  *
 152  *      0         7        8
 153  *     | command | Resync |     = 0xc0
 154  *
 155  * Since the event is written in big-endian byte order, this works
 156  * providing bits 56-63 of the event are 0xc0.
 157  *
 158  *      56     60  63
 159  *     | Rsvd | Code |    = 0xc0
 160  *
 161  * Which means for convenience the event code is 0xc for all MC
 162  * generated events.
 163  */
 164 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
 165 
 166 
 167 /* Operation not permitted. */
 168 #define MC_CMD_ERR_EPERM 1
 169 /* Non-existent command target */
 170 #define MC_CMD_ERR_ENOENT 2
 171 /* assert() has killed the MC */
 172 #define MC_CMD_ERR_EINTR 4
 173 /* I/O failure */
 174 #define MC_CMD_ERR_EIO 5
 175 /* Already exists */
 176 #define MC_CMD_ERR_EEXIST 6
 177 /* Try again */
 178 #define MC_CMD_ERR_EAGAIN 11
 179 /* Out of memory */
 180 #define MC_CMD_ERR_ENOMEM 12
 181 /* Caller does not hold required locks */
 182 #define MC_CMD_ERR_EACCES 13
 183 /* Resource is currently unavailable (e.g. lock contention) */
 184 #define MC_CMD_ERR_EBUSY 16
 185 /* No such device */
 186 #define MC_CMD_ERR_ENODEV 19
 187 /* Invalid argument to target */
 188 #define MC_CMD_ERR_EINVAL 22
 189 /* Broken pipe */
 190 #define MC_CMD_ERR_EPIPE 32
 191 /* Read-only */
 192 #define MC_CMD_ERR_EROFS 30
 193 /* Out of range */
 194 #define MC_CMD_ERR_ERANGE 34
 195 /* Non-recursive resource is already acquired */
 196 #define MC_CMD_ERR_EDEADLK 35
 197 /* Operation not implemented */
 198 #define MC_CMD_ERR_ENOSYS 38
 199 /* Operation timed out */
 200 #define MC_CMD_ERR_ETIME 62
 201 /* Link has been severed */
 202 #define MC_CMD_ERR_ENOLINK 67
 203 /* Protocol error */
 204 #define MC_CMD_ERR_EPROTO 71
 205 /* Operation not supported */
 206 #define MC_CMD_ERR_ENOTSUP 95
 207 /* Address not available */
 208 #define MC_CMD_ERR_EADDRNOTAVAIL 99
 209 /* Not connected */
 210 #define MC_CMD_ERR_ENOTCONN 107
 211 /* Operation already in progress */
 212 #define MC_CMD_ERR_EALREADY 114
 213 
 214 /* Resource allocation failed. */
 215 #define MC_CMD_ERR_ALLOC_FAIL  0x1000
 216 /* V-adaptor not found. */
 217 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
 218 /* EVB port not found. */
 219 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
 220 /* V-switch not found. */
 221 #define MC_CMD_ERR_NO_VSWITCH  0x1003
 222 /* Too many VLAN tags. */
 223 #define MC_CMD_ERR_VLAN_LIMIT  0x1004
 224 /* Bad PCI function number. */
 225 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
 226 /* Invalid VLAN mode. */
 227 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
 228 /* Invalid v-switch type. */
 229 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
 230 /* Invalid v-port type. */
 231 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
 232 /* MAC address exists. */
 233 #define MC_CMD_ERR_MAC_EXIST 0x1009
 234 /* Slave core not present */
 235 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
 236 /* The datapath is disabled. */
 237 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
 238 /* The requesting client is not a function */
 239 #define MC_CMD_ERR_CLIENT_NOT_FN  0x100c
 240 /* The requested operation might require the
 241    command to be passed between MCs, and the
 242    transport doesn't support that.  Should
 243    only ever been seen over the UART. */
 244 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
 245 /* VLAN tag(s) exists */
 246 #define MC_CMD_ERR_VLAN_EXIST 0x100e
 247 /* No MAC address assigned to an EVB port */
 248 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
 249 /* Notifies the driver that the request has been relayed
 250  * to an admin function for authorization. The driver should
 251  * wait for a PROXY_RESPONSE event and then resend its request.
 252  * This error code is followed by a 32-bit handle that
 253  * helps matching it with the respective PROXY_RESPONSE event. */
 254 #define MC_CMD_ERR_PROXY_PENDING 0x1010
 255 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
 256 /* The request cannot be passed for authorization because
 257  * another request from the same function is currently being
 258  * authorized. The drvier should try again later. */
 259 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
 260 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
 261  * that has enabled proxying or BLOCK_INDEX points to a function that
 262  * doesn't await an authorization. */
 263 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
 264 /* This code is currently only used internally in FW. Its meaning is that
 265  * an operation failed due to lack of SR-IOV privilege.
 266  * Normally it is translated to EPERM by send_cmd_err(),
 267  * but it may also be used to trigger some special mechanism
 268  * for handling such case, e.g. to relay the failed request
 269  * to a designated admin function for authorization. */
 270 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
 271 /* Workaround 26807 could not be turned on/off because some functions
 272  * have already installed filters. See the comment at
 273  * MC_CMD_WORKAROUND_BUG26807.
 274  * May also returned for other operations such as sub-variant switching. */
 275 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
 276 /* The clock whose frequency you've attempted to set set
 277  * doesn't exist on this NIC */
 278 #define MC_CMD_ERR_NO_CLOCK 0x1015
 279 /* Returned by MC_CMD_TESTASSERT if the action that should
 280  * have caused an assertion failed to do so.  */
 281 #define MC_CMD_ERR_UNREACHABLE 0x1016
 282 /* This command needs to be processed in the background but there were no
 283  * resources to do so. Send it again after a command has completed. */
 284 #define MC_CMD_ERR_QUEUE_FULL 0x1017
 285 /* The operation could not be completed because the PCIe link has gone
 286  * away.  This error code is never expected to be returned over the TLP
 287  * transport. */
 288 #define MC_CMD_ERR_NO_PCIE 0x1018
 289 /* The operation could not be completed because the datapath has gone
 290  * away.  This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
 291  * datapath absence may be temporary*/
 292 #define MC_CMD_ERR_NO_DATAPATH 0x1019
 293 /* The operation could not complete because some VIs are allocated */
 294 #define MC_CMD_ERR_VIS_PRESENT 0x101a
 295 /* The operation could not complete because some PIO buffers are allocated */
 296 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
 297 
 298 #define MC_CMD_ERR_CODE_OFST 0
 299 
 300 /* We define 8 "escape" commands to allow
 301    for command number space extension */
 302 
 303 #define MC_CMD_CMD_SPACE_ESCAPE_0             0x78
 304 #define MC_CMD_CMD_SPACE_ESCAPE_1             0x79
 305 #define MC_CMD_CMD_SPACE_ESCAPE_2             0x7A
 306 #define MC_CMD_CMD_SPACE_ESCAPE_3             0x7B
 307 #define MC_CMD_CMD_SPACE_ESCAPE_4             0x7C
 308 #define MC_CMD_CMD_SPACE_ESCAPE_5             0x7D
 309 #define MC_CMD_CMD_SPACE_ESCAPE_6             0x7E
 310 #define MC_CMD_CMD_SPACE_ESCAPE_7             0x7F
 311 
 312 /* Vectors in the boot ROM */
 313 /* Point to the copycode entry point. */
 314 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
 315 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
 316 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
 317 /* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
 318 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
 319 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
 320 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
 321 /* Points to the recovery mode entry point. Same as above, but the right name. */
 322 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
 323 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
 324 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
 325 
 326 /* Points to noflash mode entry point. */
 327 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
 328 
 329 /* The command set exported by the boot ROM (MCDI v0) */
 330 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {         \
 331         (1 << MC_CMD_READ32)    |                       \
 332         (1 << MC_CMD_WRITE32)   |                       \
 333         (1 << MC_CMD_COPYCODE)  |                       \
 334         (1 << MC_CMD_GET_VERSION),                      \
 335         0, 0, 0 }
 336 
 337 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x)          \
 338         (MC_CMD_SENSOR_ENTRY_OFST + (_x))
 339 
 340 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n)             \
 341         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +             \
 342          MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST +          \
 343          (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
 344 
 345 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n)           \
 346         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +             \
 347          MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST +        \
 348          (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
 349 
 350 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n)               \
 351         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +             \
 352          MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST +            \
 353          (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
 354 
 355 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
 356  * stack ID (which must be in the range 1-255) along with an EVB port ID.
 357  */
 358 #define EVB_STACK_ID(n)  (((n) & 0xff) << 16)
 359 
 360 
 361 /* Version 2 adds an optional argument to error returns: the errno value
 362  * may be followed by the (0-based) number of the first argument that
 363  * could not be processed.
 364  */
 365 #define MC_CMD_ERR_ARG_OFST 4
 366 
 367 /* No space */
 368 #define MC_CMD_ERR_ENOSPC 28
 369 
 370 /* MCDI_EVENT structuredef */
 371 #define    MCDI_EVENT_LEN 8
 372 #define       MCDI_EVENT_CONT_LBN 32
 373 #define       MCDI_EVENT_CONT_WIDTH 1
 374 #define       MCDI_EVENT_LEVEL_LBN 33
 375 #define       MCDI_EVENT_LEVEL_WIDTH 3
 376 /* enum: Info. */
 377 #define          MCDI_EVENT_LEVEL_INFO 0x0
 378 /* enum: Warning. */
 379 #define          MCDI_EVENT_LEVEL_WARN 0x1
 380 /* enum: Error. */
 381 #define          MCDI_EVENT_LEVEL_ERR 0x2
 382 /* enum: Fatal. */
 383 #define          MCDI_EVENT_LEVEL_FATAL 0x3
 384 #define       MCDI_EVENT_DATA_OFST 0
 385 #define       MCDI_EVENT_DATA_LEN 4
 386 #define        MCDI_EVENT_CMDDONE_SEQ_LBN 0
 387 #define        MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
 388 #define        MCDI_EVENT_CMDDONE_DATALEN_LBN 8
 389 #define        MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
 390 #define        MCDI_EVENT_CMDDONE_ERRNO_LBN 16
 391 #define        MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
 392 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
 393 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
 394 #define        MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
 395 #define        MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
 396 /* enum: Link is down or link speed could not be determined */
 397 #define          MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
 398 /* enum: 100Mbs */
 399 #define          MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
 400 /* enum: 1Gbs */
 401 #define          MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
 402 /* enum: 10Gbs */
 403 #define          MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
 404 /* enum: 40Gbs */
 405 #define          MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
 406 /* enum: 25Gbs */
 407 #define          MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
 408 /* enum: 50Gbs */
 409 #define          MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
 410 /* enum: 100Gbs */
 411 #define          MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
 412 #define        MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
 413 #define        MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
 414 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
 415 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
 416 #define        MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
 417 #define        MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
 418 #define        MCDI_EVENT_SENSOREVT_STATE_LBN 8
 419 #define        MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
 420 #define        MCDI_EVENT_SENSOREVT_VALUE_LBN 16
 421 #define        MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
 422 #define        MCDI_EVENT_FWALERT_DATA_LBN 8
 423 #define        MCDI_EVENT_FWALERT_DATA_WIDTH 24
 424 #define        MCDI_EVENT_FWALERT_REASON_LBN 0
 425 #define        MCDI_EVENT_FWALERT_REASON_WIDTH 8
 426 /* enum: SRAM Access. */
 427 #define          MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
 428 #define        MCDI_EVENT_FLR_VF_LBN 0
 429 #define        MCDI_EVENT_FLR_VF_WIDTH 8
 430 #define        MCDI_EVENT_TX_ERR_TXQ_LBN 0
 431 #define        MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
 432 #define        MCDI_EVENT_TX_ERR_TYPE_LBN 12
 433 #define        MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
 434 /* enum: Descriptor loader reported failure */
 435 #define          MCDI_EVENT_TX_ERR_DL_FAIL 0x1
 436 /* enum: Descriptor ring empty and no EOP seen for packet */
 437 #define          MCDI_EVENT_TX_ERR_NO_EOP 0x2
 438 /* enum: Overlength packet */
 439 #define          MCDI_EVENT_TX_ERR_2BIG 0x3
 440 /* enum: Malformed option descriptor */
 441 #define          MCDI_EVENT_TX_BAD_OPTDESC 0x5
 442 /* enum: Option descriptor part way through a packet */
 443 #define          MCDI_EVENT_TX_OPT_IN_PKT 0x8
 444 /* enum: DMA or PIO data access error */
 445 #define          MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
 446 #define        MCDI_EVENT_TX_ERR_INFO_LBN 16
 447 #define        MCDI_EVENT_TX_ERR_INFO_WIDTH 16
 448 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
 449 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
 450 #define        MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
 451 #define        MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
 452 #define        MCDI_EVENT_PTP_ERR_TYPE_LBN 0
 453 #define        MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
 454 /* enum: PLL lost lock */
 455 #define          MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
 456 /* enum: Filter overflow (PDMA) */
 457 #define          MCDI_EVENT_PTP_ERR_FILTER 0x2
 458 /* enum: FIFO overflow (FPGA) */
 459 #define          MCDI_EVENT_PTP_ERR_FIFO 0x3
 460 /* enum: Merge queue overflow */
 461 #define          MCDI_EVENT_PTP_ERR_QUEUE 0x4
 462 #define        MCDI_EVENT_AOE_ERR_TYPE_LBN 0
 463 #define        MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
 464 /* enum: AOE failed to load - no valid image? */
 465 #define          MCDI_EVENT_AOE_NO_LOAD 0x1
 466 /* enum: AOE FC reported an exception */
 467 #define          MCDI_EVENT_AOE_FC_ASSERT 0x2
 468 /* enum: AOE FC watchdogged */
 469 #define          MCDI_EVENT_AOE_FC_WATCHDOG 0x3
 470 /* enum: AOE FC failed to start */
 471 #define          MCDI_EVENT_AOE_FC_NO_START 0x4
 472 /* enum: Generic AOE fault - likely to have been reported via other means too
 473  * but intended for use by aoex driver.
 474  */
 475 #define          MCDI_EVENT_AOE_FAULT 0x5
 476 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
 477 #define          MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
 478 /* enum: AOE loaded successfully */
 479 #define          MCDI_EVENT_AOE_LOAD 0x7
 480 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
 481 #define          MCDI_EVENT_AOE_DMA 0x8
 482 /* enum: AOE byteblaster connected/disconnected (Connection status in
 483  * AOE_ERR_DATA)
 484  */
 485 #define          MCDI_EVENT_AOE_BYTEBLASTER 0x9
 486 /* enum: DDR ECC status update */
 487 #define          MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
 488 /* enum: PTP status update */
 489 #define          MCDI_EVENT_AOE_PTP_STATUS 0xb
 490 /* enum: FPGA header incorrect */
 491 #define          MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
 492 /* enum: FPGA Powered Off due to error in powering up FPGA */
 493 #define          MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
 494 /* enum: AOE FPGA load failed due to MC to MUM communication failure */
 495 #define          MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
 496 /* enum: Notify that invalid flash type detected */
 497 #define          MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
 498 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */
 499 #define          MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
 500 /* enum: Failure to probe one or more FPGA boot flash chips */
 501 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
 502 /* enum: FPGA boot-flash contains an invalid image header */
 503 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
 504 /* enum: Failed to program clocks required by the FPGA */
 505 #define          MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
 506 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
 507 #define          MCDI_EVENT_AOE_FC_RUNNING 0x14
 508 #define        MCDI_EVENT_AOE_ERR_DATA_LBN 8
 509 #define        MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
 510 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
 511 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
 512 /* enum: FC Assert happened, but the register information is not available */
 513 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
 514 /* enum: The register information for FC Assert is ready for readinng by driver
 515  */
 516 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
 517 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
 518 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
 519 /* enum: Reading from NV failed */
 520 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
 521 /* enum: Invalid Magic Number if FPGA header */
 522 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
 523 /* enum: Invalid Silicon type detected in header */
 524 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
 525 /* enum: Unsupported VRatio */
 526 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
 527 /* enum: Unsupported DDR Type */
 528 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
 529 /* enum: DDR Voltage out of supported range */
 530 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
 531 /* enum: Unsupported DDR speed */
 532 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
 533 /* enum: Unsupported DDR size */
 534 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
 535 /* enum: Unsupported DDR rank */
 536 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
 537 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
 538 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
 539 /* enum: Primary boot flash */
 540 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
 541 /* enum: Secondary boot flash */
 542 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
 543 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
 544 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
 545 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
 546 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
 547 #define        MCDI_EVENT_RX_ERR_RXQ_LBN 0
 548 #define        MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
 549 #define        MCDI_EVENT_RX_ERR_TYPE_LBN 12
 550 #define        MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
 551 #define        MCDI_EVENT_RX_ERR_INFO_LBN 16
 552 #define        MCDI_EVENT_RX_ERR_INFO_WIDTH 16
 553 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
 554 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
 555 #define        MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
 556 #define        MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
 557 #define        MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
 558 #define        MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
 559 #define        MCDI_EVENT_MUM_ERR_TYPE_LBN 0
 560 #define        MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
 561 /* enum: MUM failed to load - no valid image? */
 562 #define          MCDI_EVENT_MUM_NO_LOAD 0x1
 563 /* enum: MUM f/w reported an exception */
 564 #define          MCDI_EVENT_MUM_ASSERT 0x2
 565 /* enum: MUM not kicking watchdog */
 566 #define          MCDI_EVENT_MUM_WATCHDOG 0x3
 567 #define        MCDI_EVENT_MUM_ERR_DATA_LBN 8
 568 #define        MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
 569 #define        MCDI_EVENT_DBRET_SEQ_LBN 0
 570 #define        MCDI_EVENT_DBRET_SEQ_WIDTH 8
 571 #define        MCDI_EVENT_SUC_ERR_TYPE_LBN 0
 572 #define        MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
 573 /* enum: Corrupted or bad SUC application. */
 574 #define          MCDI_EVENT_SUC_BAD_APP 0x1
 575 /* enum: SUC application reported an assert. */
 576 #define          MCDI_EVENT_SUC_ASSERT 0x2
 577 /* enum: SUC application reported an exception. */
 578 #define          MCDI_EVENT_SUC_EXCEPTION 0x3
 579 /* enum: SUC watchdog timer expired. */
 580 #define          MCDI_EVENT_SUC_WATCHDOG 0x4
 581 #define        MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
 582 #define        MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
 583 #define        MCDI_EVENT_SUC_ERR_DATA_LBN 8
 584 #define        MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
 585 #define       MCDI_EVENT_DATA_LBN 0
 586 #define       MCDI_EVENT_DATA_WIDTH 32
 587 #define       MCDI_EVENT_SRC_LBN 36
 588 #define       MCDI_EVENT_SRC_WIDTH 8
 589 #define       MCDI_EVENT_EV_CODE_LBN 60
 590 #define       MCDI_EVENT_EV_CODE_WIDTH 4
 591 #define       MCDI_EVENT_CODE_LBN 44
 592 #define       MCDI_EVENT_CODE_WIDTH 8
 593 /* enum: Event generated by host software */
 594 #define          MCDI_EVENT_SW_EVENT 0x0
 595 /* enum: Bad assert. */
 596 #define          MCDI_EVENT_CODE_BADSSERT 0x1
 597 /* enum: PM Notice. */
 598 #define          MCDI_EVENT_CODE_PMNOTICE 0x2
 599 /* enum: Command done. */
 600 #define          MCDI_EVENT_CODE_CMDDONE 0x3
 601 /* enum: Link change. */
 602 #define          MCDI_EVENT_CODE_LINKCHANGE 0x4
 603 /* enum: Sensor Event. */
 604 #define          MCDI_EVENT_CODE_SENSOREVT 0x5
 605 /* enum: Schedule error. */
 606 #define          MCDI_EVENT_CODE_SCHEDERR 0x6
 607 /* enum: Reboot. */
 608 #define          MCDI_EVENT_CODE_REBOOT 0x7
 609 /* enum: Mac stats DMA. */
 610 #define          MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
 611 /* enum: Firmware alert. */
 612 #define          MCDI_EVENT_CODE_FWALERT 0x9
 613 /* enum: Function level reset. */
 614 #define          MCDI_EVENT_CODE_FLR 0xa
 615 /* enum: Transmit error */
 616 #define          MCDI_EVENT_CODE_TX_ERR 0xb
 617 /* enum: Tx flush has completed */
 618 #define          MCDI_EVENT_CODE_TX_FLUSH 0xc
 619 /* enum: PTP packet received timestamp */
 620 #define          MCDI_EVENT_CODE_PTP_RX 0xd
 621 /* enum: PTP NIC failure */
 622 #define          MCDI_EVENT_CODE_PTP_FAULT 0xe
 623 /* enum: PTP PPS event */
 624 #define          MCDI_EVENT_CODE_PTP_PPS 0xf
 625 /* enum: Rx flush has completed */
 626 #define          MCDI_EVENT_CODE_RX_FLUSH 0x10
 627 /* enum: Receive error */
 628 #define          MCDI_EVENT_CODE_RX_ERR 0x11
 629 /* enum: AOE fault */
 630 #define          MCDI_EVENT_CODE_AOE 0x12
 631 /* enum: Network port calibration failed (VCAL). */
 632 #define          MCDI_EVENT_CODE_VCAL_FAIL 0x13
 633 /* enum: HW PPS event */
 634 #define          MCDI_EVENT_CODE_HW_PPS 0x14
 635 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
 636  * a different format)
 637  */
 638 #define          MCDI_EVENT_CODE_MC_REBOOT 0x15
 639 /* enum: the MC has detected a parity error */
 640 #define          MCDI_EVENT_CODE_PAR_ERR 0x16
 641 /* enum: the MC has detected a correctable error */
 642 #define          MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
 643 /* enum: the MC has detected an uncorrectable error */
 644 #define          MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
 645 /* enum: The MC has entered offline BIST mode */
 646 #define          MCDI_EVENT_CODE_MC_BIST 0x19
 647 /* enum: PTP tick event providing current NIC time */
 648 #define          MCDI_EVENT_CODE_PTP_TIME 0x1a
 649 /* enum: MUM fault */
 650 #define          MCDI_EVENT_CODE_MUM 0x1b
 651 /* enum: notify the designated PF of a new authorization request */
 652 #define          MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
 653 /* enum: notify a function that awaits an authorization that its request has
 654  * been processed and it may now resend the command
 655  */
 656 #define          MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
 657 /* enum: MCDI command accepted. New commands can be issued but this command is
 658  * not done yet.
 659  */
 660 #define          MCDI_EVENT_CODE_DBRET 0x1e
 661 /* enum: The MC has detected a fault on the SUC */
 662 #define          MCDI_EVENT_CODE_SUC 0x1f
 663 /* enum: Artificial event generated by host and posted via MC for test
 664  * purposes.
 665  */
 666 #define          MCDI_EVENT_CODE_TESTGEN 0xfa
 667 #define       MCDI_EVENT_CMDDONE_DATA_OFST 0
 668 #define       MCDI_EVENT_CMDDONE_DATA_LEN 4
 669 #define       MCDI_EVENT_CMDDONE_DATA_LBN 0
 670 #define       MCDI_EVENT_CMDDONE_DATA_WIDTH 32
 671 #define       MCDI_EVENT_LINKCHANGE_DATA_OFST 0
 672 #define       MCDI_EVENT_LINKCHANGE_DATA_LEN 4
 673 #define       MCDI_EVENT_LINKCHANGE_DATA_LBN 0
 674 #define       MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
 675 #define       MCDI_EVENT_SENSOREVT_DATA_OFST 0
 676 #define       MCDI_EVENT_SENSOREVT_DATA_LEN 4
 677 #define       MCDI_EVENT_SENSOREVT_DATA_LBN 0
 678 #define       MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
 679 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
 680 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
 681 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
 682 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
 683 #define       MCDI_EVENT_TX_ERR_DATA_OFST 0
 684 #define       MCDI_EVENT_TX_ERR_DATA_LEN 4
 685 #define       MCDI_EVENT_TX_ERR_DATA_LBN 0
 686 #define       MCDI_EVENT_TX_ERR_DATA_WIDTH 32
 687 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
 688  * timestamp
 689  */
 690 #define       MCDI_EVENT_PTP_SECONDS_OFST 0
 691 #define       MCDI_EVENT_PTP_SECONDS_LEN 4
 692 #define       MCDI_EVENT_PTP_SECONDS_LBN 0
 693 #define       MCDI_EVENT_PTP_SECONDS_WIDTH 32
 694 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
 695  * timestamp
 696  */
 697 #define       MCDI_EVENT_PTP_MAJOR_OFST 0
 698 #define       MCDI_EVENT_PTP_MAJOR_LEN 4
 699 #define       MCDI_EVENT_PTP_MAJOR_LBN 0
 700 #define       MCDI_EVENT_PTP_MAJOR_WIDTH 32
 701 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
 702  * of timestamp
 703  */
 704 #define       MCDI_EVENT_PTP_NANOSECONDS_OFST 0
 705 #define       MCDI_EVENT_PTP_NANOSECONDS_LEN 4
 706 #define       MCDI_EVENT_PTP_NANOSECONDS_LBN 0
 707 #define       MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
 708 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
 709  * timestamp
 710  */
 711 #define       MCDI_EVENT_PTP_MINOR_OFST 0
 712 #define       MCDI_EVENT_PTP_MINOR_LEN 4
 713 #define       MCDI_EVENT_PTP_MINOR_LBN 0
 714 #define       MCDI_EVENT_PTP_MINOR_WIDTH 32
 715 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
 716  */
 717 #define       MCDI_EVENT_PTP_UUID_OFST 0
 718 #define       MCDI_EVENT_PTP_UUID_LEN 4
 719 #define       MCDI_EVENT_PTP_UUID_LBN 0
 720 #define       MCDI_EVENT_PTP_UUID_WIDTH 32
 721 #define       MCDI_EVENT_RX_ERR_DATA_OFST 0
 722 #define       MCDI_EVENT_RX_ERR_DATA_LEN 4
 723 #define       MCDI_EVENT_RX_ERR_DATA_LBN 0
 724 #define       MCDI_EVENT_RX_ERR_DATA_WIDTH 32
 725 #define       MCDI_EVENT_PAR_ERR_DATA_OFST 0
 726 #define       MCDI_EVENT_PAR_ERR_DATA_LEN 4
 727 #define       MCDI_EVENT_PAR_ERR_DATA_LBN 0
 728 #define       MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
 729 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
 730 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
 731 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
 732 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
 733 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
 734 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
 735 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
 736 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
 737 /* For CODE_PTP_TIME events, the major value of the PTP clock */
 738 #define       MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
 739 #define       MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
 740 #define       MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
 741 #define       MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
 742 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
 743 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
 744 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
 745 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
 746  * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
 747  */
 748 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
 749 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
 750 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
 751  * whether the NIC clock has ever been set
 752  */
 753 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
 754 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
 755 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
 756  * whether the NIC and System clocks are in sync
 757  */
 758 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
 759 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
 760 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
 761  * the minor value of the PTP clock
 762  */
 763 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
 764 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
 765 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
 766  * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
 767  */
 768 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
 769 #define       MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
 770 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
 771 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
 772 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
 773 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
 774 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
 775 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
 776 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
 777 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
 778 /* Zero means that the request has been completed or authorized, and the driver
 779  * should resend it. A non-zero value means that the authorization has been
 780  * denied, and gives the reason. Typically it will be EPERM.
 781  */
 782 #define       MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
 783 #define       MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
 784 #define       MCDI_EVENT_DBRET_DATA_OFST 0
 785 #define       MCDI_EVENT_DBRET_DATA_LEN 4
 786 #define       MCDI_EVENT_DBRET_DATA_LBN 0
 787 #define       MCDI_EVENT_DBRET_DATA_WIDTH 32
 788 
 789 /* FCDI_EVENT structuredef */
 790 #define    FCDI_EVENT_LEN 8
 791 #define       FCDI_EVENT_CONT_LBN 32
 792 #define       FCDI_EVENT_CONT_WIDTH 1
 793 #define       FCDI_EVENT_LEVEL_LBN 33
 794 #define       FCDI_EVENT_LEVEL_WIDTH 3
 795 /* enum: Info. */
 796 #define          FCDI_EVENT_LEVEL_INFO 0x0
 797 /* enum: Warning. */
 798 #define          FCDI_EVENT_LEVEL_WARN 0x1
 799 /* enum: Error. */
 800 #define          FCDI_EVENT_LEVEL_ERR 0x2
 801 /* enum: Fatal. */
 802 #define          FCDI_EVENT_LEVEL_FATAL 0x3
 803 #define       FCDI_EVENT_DATA_OFST 0
 804 #define       FCDI_EVENT_DATA_LEN 4
 805 #define        FCDI_EVENT_LINK_STATE_STATUS_LBN 0
 806 #define        FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
 807 #define          FCDI_EVENT_LINK_DOWN 0x0 /* enum */
 808 #define          FCDI_EVENT_LINK_UP 0x1 /* enum */
 809 #define       FCDI_EVENT_DATA_LBN 0
 810 #define       FCDI_EVENT_DATA_WIDTH 32
 811 #define       FCDI_EVENT_SRC_LBN 36
 812 #define       FCDI_EVENT_SRC_WIDTH 8
 813 #define       FCDI_EVENT_EV_CODE_LBN 60
 814 #define       FCDI_EVENT_EV_CODE_WIDTH 4
 815 #define       FCDI_EVENT_CODE_LBN 44
 816 #define       FCDI_EVENT_CODE_WIDTH 8
 817 /* enum: The FC was rebooted. */
 818 #define          FCDI_EVENT_CODE_REBOOT 0x1
 819 /* enum: Bad assert. */
 820 #define          FCDI_EVENT_CODE_ASSERT 0x2
 821 /* enum: DDR3 test result. */
 822 #define          FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
 823 /* enum: Link status. */
 824 #define          FCDI_EVENT_CODE_LINK_STATE 0x4
 825 /* enum: A timed read is ready to be serviced. */
 826 #define          FCDI_EVENT_CODE_TIMED_READ 0x5
 827 /* enum: One or more PPS IN events */
 828 #define          FCDI_EVENT_CODE_PPS_IN 0x6
 829 /* enum: Tick event from PTP clock */
 830 #define          FCDI_EVENT_CODE_PTP_TICK 0x7
 831 /* enum: ECC error counters */
 832 #define          FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
 833 /* enum: Current status of PTP */
 834 #define          FCDI_EVENT_CODE_PTP_STATUS 0x9
 835 /* enum: Port id config to map MC-FC port idx */
 836 #define          FCDI_EVENT_CODE_PORT_CONFIG 0xa
 837 /* enum: Boot result or error code */
 838 #define          FCDI_EVENT_CODE_BOOT_RESULT 0xb
 839 #define       FCDI_EVENT_REBOOT_SRC_LBN 36
 840 #define       FCDI_EVENT_REBOOT_SRC_WIDTH 8
 841 #define          FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
 842 #define          FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
 843 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
 844 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
 845 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
 846 #define       FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
 847 #define       FCDI_EVENT_ASSERT_TYPE_LBN 36
 848 #define       FCDI_EVENT_ASSERT_TYPE_WIDTH 8
 849 #define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
 850 #define       FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
 851 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
 852 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
 853 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
 854 #define       FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
 855 #define       FCDI_EVENT_LINK_STATE_DATA_OFST 0
 856 #define       FCDI_EVENT_LINK_STATE_DATA_LEN 4
 857 #define       FCDI_EVENT_LINK_STATE_DATA_LBN 0
 858 #define       FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
 859 #define       FCDI_EVENT_PTP_STATE_OFST 0
 860 #define       FCDI_EVENT_PTP_STATE_LEN 4
 861 #define          FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
 862 #define          FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
 863 #define          FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
 864 #define       FCDI_EVENT_PTP_STATE_LBN 0
 865 #define       FCDI_EVENT_PTP_STATE_WIDTH 32
 866 #define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
 867 #define       FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
 868 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
 869 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
 870 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
 871 #define       FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
 872 /* Index of MC port being referred to */
 873 #define       FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
 874 #define       FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
 875 /* FC Port index that matches the MC port index in SRC */
 876 #define       FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
 877 #define       FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
 878 #define       FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
 879 #define       FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
 880 #define       FCDI_EVENT_BOOT_RESULT_OFST 0
 881 #define       FCDI_EVENT_BOOT_RESULT_LEN 4
 882 /*            Enum values, see field(s): */
 883 /*               MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
 884 #define       FCDI_EVENT_BOOT_RESULT_LBN 0
 885 #define       FCDI_EVENT_BOOT_RESULT_WIDTH 32
 886 
 887 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
 888  * to the MC. Note that this structure | is overlayed over a normal FCDI event
 889  * such that bits 32-63 containing | event code, level, source etc remain the
 890  * same. In this case the data | field of the header is defined to be the
 891  * number of timestamps
 892  */
 893 #define    FCDI_EXTENDED_EVENT_PPS_LENMIN 16
 894 #define    FCDI_EXTENDED_EVENT_PPS_LENMAX 248
 895 #define    FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
 896 /* Number of timestamps following */
 897 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
 898 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
 899 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
 900 #define       FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
 901 /* Seconds field of a timestamp record */
 902 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
 903 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
 904 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
 905 #define       FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
 906 /* Nanoseconds field of a timestamp record */
 907 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
 908 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
 909 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
 910 #define       FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
 911 /* Timestamp records comprising the event */
 912 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
 913 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
 914 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
 915 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
 916 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
 917 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
 918 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
 919 #define       FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
 920 
 921 /* MUM_EVENT structuredef */
 922 #define    MUM_EVENT_LEN 8
 923 #define       MUM_EVENT_CONT_LBN 32
 924 #define       MUM_EVENT_CONT_WIDTH 1
 925 #define       MUM_EVENT_LEVEL_LBN 33
 926 #define       MUM_EVENT_LEVEL_WIDTH 3
 927 /* enum: Info. */
 928 #define          MUM_EVENT_LEVEL_INFO 0x0
 929 /* enum: Warning. */
 930 #define          MUM_EVENT_LEVEL_WARN 0x1
 931 /* enum: Error. */
 932 #define          MUM_EVENT_LEVEL_ERR 0x2
 933 /* enum: Fatal. */
 934 #define          MUM_EVENT_LEVEL_FATAL 0x3
 935 #define       MUM_EVENT_DATA_OFST 0
 936 #define       MUM_EVENT_DATA_LEN 4
 937 #define        MUM_EVENT_SENSOR_ID_LBN 0
 938 #define        MUM_EVENT_SENSOR_ID_WIDTH 8
 939 /*             Enum values, see field(s): */
 940 /*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
 941 #define        MUM_EVENT_SENSOR_STATE_LBN 8
 942 #define        MUM_EVENT_SENSOR_STATE_WIDTH 8
 943 #define        MUM_EVENT_PORT_PHY_READY_LBN 0
 944 #define        MUM_EVENT_PORT_PHY_READY_WIDTH 1
 945 #define        MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
 946 #define        MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
 947 #define        MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
 948 #define        MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
 949 #define        MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
 950 #define        MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
 951 #define        MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
 952 #define        MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
 953 #define        MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
 954 #define        MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
 955 #define        MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
 956 #define        MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
 957 #define       MUM_EVENT_DATA_LBN 0
 958 #define       MUM_EVENT_DATA_WIDTH 32
 959 #define       MUM_EVENT_SRC_LBN 36
 960 #define       MUM_EVENT_SRC_WIDTH 8
 961 #define       MUM_EVENT_EV_CODE_LBN 60
 962 #define       MUM_EVENT_EV_CODE_WIDTH 4
 963 #define       MUM_EVENT_CODE_LBN 44
 964 #define       MUM_EVENT_CODE_WIDTH 8
 965 /* enum: The MUM was rebooted. */
 966 #define          MUM_EVENT_CODE_REBOOT 0x1
 967 /* enum: Bad assert. */
 968 #define          MUM_EVENT_CODE_ASSERT 0x2
 969 /* enum: Sensor failure. */
 970 #define          MUM_EVENT_CODE_SENSOR 0x3
 971 /* enum: Link fault has been asserted, or has cleared. */
 972 #define          MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
 973 #define       MUM_EVENT_SENSOR_DATA_OFST 0
 974 #define       MUM_EVENT_SENSOR_DATA_LEN 4
 975 #define       MUM_EVENT_SENSOR_DATA_LBN 0
 976 #define       MUM_EVENT_SENSOR_DATA_WIDTH 32
 977 #define       MUM_EVENT_PORT_PHY_FLAGS_OFST 0
 978 #define       MUM_EVENT_PORT_PHY_FLAGS_LEN 4
 979 #define       MUM_EVENT_PORT_PHY_FLAGS_LBN 0
 980 #define       MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
 981 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
 982 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
 983 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
 984 #define       MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
 985 #define       MUM_EVENT_PORT_PHY_CAPS_OFST 0
 986 #define       MUM_EVENT_PORT_PHY_CAPS_LEN 4
 987 #define       MUM_EVENT_PORT_PHY_CAPS_LBN 0
 988 #define       MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
 989 #define       MUM_EVENT_PORT_PHY_TECH_OFST 0
 990 #define       MUM_EVENT_PORT_PHY_TECH_LEN 4
 991 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
 992 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
 993 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
 994 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
 995 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
 996 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
 997 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
 998 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
 999 #define       MUM_EVENT_PORT_PHY_TECH_LBN 0
1000 #define       MUM_EVENT_PORT_PHY_TECH_WIDTH 32
1001 #define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
1002 #define       MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1003 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1004 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1005 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1006 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1007 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1008 #define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
1009 #define       MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1010 
1011 
1012 /***********************************/
1013 /* MC_CMD_READ32
1014  * Read multiple 32byte words from MC memory. Note - this command really
1015  * belongs to INSECURE category but is required by shmboot. The command handler
1016  * has additional checks to reject insecure calls.
1017  */
1018 #define MC_CMD_READ32 0x1
1019 
1020 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1021 
1022 /* MC_CMD_READ32_IN msgrequest */
1023 #define    MC_CMD_READ32_IN_LEN 8
1024 #define       MC_CMD_READ32_IN_ADDR_OFST 0
1025 #define       MC_CMD_READ32_IN_ADDR_LEN 4
1026 #define       MC_CMD_READ32_IN_NUMWORDS_OFST 4
1027 #define       MC_CMD_READ32_IN_NUMWORDS_LEN 4
1028 
1029 /* MC_CMD_READ32_OUT msgresponse */
1030 #define    MC_CMD_READ32_OUT_LENMIN 4
1031 #define    MC_CMD_READ32_OUT_LENMAX 252
1032 #define    MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1033 #define       MC_CMD_READ32_OUT_BUFFER_OFST 0
1034 #define       MC_CMD_READ32_OUT_BUFFER_LEN 4
1035 #define       MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1036 #define       MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1037 
1038 
1039 /***********************************/
1040 /* MC_CMD_WRITE32
1041  * Write multiple 32byte words to MC memory.
1042  */
1043 #define MC_CMD_WRITE32 0x2
1044 
1045 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1046 
1047 /* MC_CMD_WRITE32_IN msgrequest */
1048 #define    MC_CMD_WRITE32_IN_LENMIN 8
1049 #define    MC_CMD_WRITE32_IN_LENMAX 252
1050 #define    MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1051 #define       MC_CMD_WRITE32_IN_ADDR_OFST 0
1052 #define       MC_CMD_WRITE32_IN_ADDR_LEN 4
1053 #define       MC_CMD_WRITE32_IN_BUFFER_OFST 4
1054 #define       MC_CMD_WRITE32_IN_BUFFER_LEN 4
1055 #define       MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1056 #define       MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1057 
1058 /* MC_CMD_WRITE32_OUT msgresponse */
1059 #define    MC_CMD_WRITE32_OUT_LEN 0
1060 
1061 
1062 /***********************************/
1063 /* MC_CMD_COPYCODE
1064  * Copy MC code between two locations and jump. Note - this command really
1065  * belongs to INSECURE category but is required by shmboot. The command handler
1066  * has additional checks to reject insecure calls.
1067  */
1068 #define MC_CMD_COPYCODE 0x3
1069 
1070 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1071 
1072 /* MC_CMD_COPYCODE_IN msgrequest */
1073 #define    MC_CMD_COPYCODE_IN_LEN 16
1074 /* Source address
1075  *
1076  * The main image should be entered via a copy of a single word from and to a
1077  * magic address, which controls various aspects of the boot. The magic address
1078  * is a bitfield, with each bit as documented below.
1079  */
1080 #define       MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1081 #define       MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1082 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1083 #define          MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1084 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1085  * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
1086  */
1087 #define          MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1088 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1089  * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
1090  * below)
1091  */
1092 #define          MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1093 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
1094 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1095 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
1096 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1097 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
1098 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1099 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1100 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1101 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
1102 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1103 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
1104 #define        MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
1105 /* Destination address */
1106 #define       MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1107 #define       MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1108 #define       MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
1109 #define       MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1110 /* Address of where to jump after copy. */
1111 #define       MC_CMD_COPYCODE_IN_JUMP_OFST 12
1112 #define       MC_CMD_COPYCODE_IN_JUMP_LEN 4
1113 /* enum: Control should return to the caller rather than jumping */
1114 #define          MC_CMD_COPYCODE_JUMP_NONE 0x1
1115 
1116 /* MC_CMD_COPYCODE_OUT msgresponse */
1117 #define    MC_CMD_COPYCODE_OUT_LEN 0
1118 
1119 
1120 /***********************************/
1121 /* MC_CMD_SET_FUNC
1122  * Select function for function-specific commands.
1123  */
1124 #define MC_CMD_SET_FUNC 0x4
1125 
1126 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1127 
1128 /* MC_CMD_SET_FUNC_IN msgrequest */
1129 #define    MC_CMD_SET_FUNC_IN_LEN 4
1130 /* Set function */
1131 #define       MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1132 #define       MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1133 
1134 /* MC_CMD_SET_FUNC_OUT msgresponse */
1135 #define    MC_CMD_SET_FUNC_OUT_LEN 0
1136 
1137 
1138 /***********************************/
1139 /* MC_CMD_GET_BOOT_STATUS
1140  * Get the instruction address from which the MC booted.
1141  */
1142 #define MC_CMD_GET_BOOT_STATUS 0x5
1143 
1144 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1145 
1146 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1147 #define    MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1148 
1149 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1150 #define    MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1151 /* ?? */
1152 #define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1153 #define       MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1154 /* enum: indicates that the MC wasn't flash booted */
1155 #define          MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1156 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1157 #define       MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1158 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1159 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1160 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1161 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1162 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1163 #define        MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1164 
1165 
1166 /***********************************/
1167 /* MC_CMD_GET_ASSERTS
1168  * Get (and optionally clear) the current assertion status. Only
1169  * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1170  * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1171  */
1172 #define MC_CMD_GET_ASSERTS 0x6
1173 
1174 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1175 
1176 /* MC_CMD_GET_ASSERTS_IN msgrequest */
1177 #define    MC_CMD_GET_ASSERTS_IN_LEN 4
1178 /* Set to clear assertion */
1179 #define       MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1180 #define       MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1181 
1182 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
1183 #define    MC_CMD_GET_ASSERTS_OUT_LEN 140
1184 /* Assertion status flag. */
1185 #define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1186 #define       MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1187 /* enum: No assertions have failed. */
1188 #define          MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1189 /* enum: A system-level assertion has failed. */
1190 #define          MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1191 /* enum: A thread-level assertion has failed. */
1192 #define          MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1193 /* enum: The system was reset by the watchdog. */
1194 #define          MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1195 /* enum: An illegal address trap stopped the system (huntington and later) */
1196 #define          MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1197 /* Failing PC value */
1198 #define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1199 #define       MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1200 /* Saved GP regs */
1201 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1202 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1203 #define       MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1204 /* enum: A magic value hinting that the value in this register at the time of
1205  * the failure has likely been lost.
1206  */
1207 #define          MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1208 /* Failing thread address */
1209 #define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1210 #define       MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1211 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1212 #define       MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1213 
1214 
1215 /***********************************/
1216 /* MC_CMD_LOG_CTRL
1217  * Configure the output stream for log events such as link state changes,
1218  * sensor notifications and MCDI completions
1219  */
1220 #define MC_CMD_LOG_CTRL 0x7
1221 
1222 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1223 
1224 /* MC_CMD_LOG_CTRL_IN msgrequest */
1225 #define    MC_CMD_LOG_CTRL_IN_LEN 8
1226 /* Log destination */
1227 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1228 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1229 /* enum: UART. */
1230 #define          MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1231 /* enum: Event queue. */
1232 #define          MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1233 /* Legacy argument. Must be zero. */
1234 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1235 #define       MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1236 
1237 /* MC_CMD_LOG_CTRL_OUT msgresponse */
1238 #define    MC_CMD_LOG_CTRL_OUT_LEN 0
1239 
1240 
1241 /***********************************/
1242 /* MC_CMD_GET_VERSION
1243  * Get version information about the MC firmware.
1244  */
1245 #define MC_CMD_GET_VERSION 0x8
1246 
1247 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1248 
1249 /* MC_CMD_GET_VERSION_IN msgrequest */
1250 #define    MC_CMD_GET_VERSION_IN_LEN 0
1251 
1252 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
1253 #define    MC_CMD_GET_VERSION_EXT_IN_LEN 4
1254 /* placeholder, set to 0 */
1255 #define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1256 #define       MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1257 
1258 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
1259 #define    MC_CMD_GET_VERSION_V0_OUT_LEN 4
1260 #define       MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1261 #define       MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1262 /* enum: Reserved version number to indicate "any" version. */
1263 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1264 /* enum: Bootrom version value for Siena. */
1265 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1266 /* enum: Bootrom version value for Huntington. */
1267 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1268 /* enum: Bootrom version value for Medford2. */
1269 #define          MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1270 
1271 /* MC_CMD_GET_VERSION_OUT msgresponse */
1272 #define    MC_CMD_GET_VERSION_OUT_LEN 32
1273 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1274 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1275 /*            Enum values, see field(s): */
1276 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1277 #define       MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1278 #define       MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1279 /* 128bit mask of functions supported by the current firmware */
1280 #define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
1281 #define       MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
1282 #define       MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
1283 #define       MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
1284 #define       MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
1285 #define       MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
1286 
1287 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
1288 #define    MC_CMD_GET_VERSION_EXT_OUT_LEN 48
1289 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1290 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1291 /*            Enum values, see field(s): */
1292 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1293 #define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1294 #define       MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1295 /* 128bit mask of functions supported by the current firmware */
1296 #define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
1297 #define       MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
1298 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
1299 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
1300 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
1301 #define       MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
1302 /* extra info */
1303 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
1304 #define       MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
1305 
1306 
1307 /***********************************/
1308 /* MC_CMD_PTP
1309  * Perform PTP operation
1310  */
1311 #define MC_CMD_PTP 0xb
1312 
1313 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1314 
1315 /* MC_CMD_PTP_IN msgrequest */
1316 #define    MC_CMD_PTP_IN_LEN 1
1317 /* PTP operation code */
1318 #define       MC_CMD_PTP_IN_OP_OFST 0
1319 #define       MC_CMD_PTP_IN_OP_LEN 1
1320 /* enum: Enable PTP packet timestamping operation. */
1321 #define          MC_CMD_PTP_OP_ENABLE 0x1
1322 /* enum: Disable PTP packet timestamping operation. */
1323 #define          MC_CMD_PTP_OP_DISABLE 0x2
1324 /* enum: Send a PTP packet. This operation is used on Siena and Huntington.
1325  * From Medford onwards it is not supported: on those platforms PTP transmit
1326  * timestamping is done using the fast path.
1327  */
1328 #define          MC_CMD_PTP_OP_TRANSMIT 0x3
1329 /* enum: Read the current NIC time. */
1330 #define          MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1331 /* enum: Get the current PTP status. Note that the clock frequency returned (in
1332  * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
1333  */
1334 #define          MC_CMD_PTP_OP_STATUS 0x5
1335 /* enum: Adjust the PTP NIC's time. */
1336 #define          MC_CMD_PTP_OP_ADJUST 0x6
1337 /* enum: Synchronize host and NIC time. */
1338 #define          MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1339 /* enum: Basic manufacturing tests. Siena PTP adapters only. */
1340 #define          MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1341 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */
1342 #define          MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1343 /* enum: Reset some of the PTP related statistics */
1344 #define          MC_CMD_PTP_OP_RESET_STATS 0xa
1345 /* enum: Debug operations to MC. */
1346 #define          MC_CMD_PTP_OP_DEBUG 0xb
1347 /* enum: Read an FPGA register. Siena PTP adapters only. */
1348 #define          MC_CMD_PTP_OP_FPGAREAD 0xc
1349 /* enum: Write an FPGA register. Siena PTP adapters only. */
1350 #define          MC_CMD_PTP_OP_FPGAWRITE 0xd
1351 /* enum: Apply an offset to the NIC clock */
1352 #define          MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1353 /* enum: Change the frequency correction applied to the NIC clock */
1354 #define          MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1355 /* enum: Set the MC packet filter VLAN tags for received PTP packets.
1356  * Deprecated for Huntington onwards.
1357  */
1358 #define          MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1359 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
1360  * Huntington onwards.
1361  */
1362 #define          MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1363 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
1364  * for Huntington onwards.
1365  */
1366 #define          MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1367 /* enum: Set the clock source. Required for snapper tests on Huntington and
1368  * Medford. Not implemented for Siena or Medford2.
1369  */
1370 #define          MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1371 /* enum: Reset value of Timer Reg. Not implemented. */
1372 #define          MC_CMD_PTP_OP_RST_CLK 0x14
1373 /* enum: Enable the forwarding of PPS events to the host */
1374 #define          MC_CMD_PTP_OP_PPS_ENABLE 0x15
1375 /* enum: Get the time format used by this NIC for PTP operations */
1376 #define          MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1377 /* enum: Get the clock attributes. NOTE- extended version of
1378  * MC_CMD_PTP_OP_GET_TIME_FORMAT
1379  */
1380 #define          MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1381 /* enum: Get corrections that should be applied to the various different
1382  * timestamps
1383  */
1384 #define          MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1385 /* enum: Subscribe to receive periodic time events indicating the current NIC
1386  * time
1387  */
1388 #define          MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1389 /* enum: Unsubscribe to stop receiving time events */
1390 #define          MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1391 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
1392  * input on the same NIC. Siena PTP adapters only.
1393  */
1394 #define          MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1395 /* enum: Set the PTP sync status. Status is used by firmware to report to event
1396  * subscribers.
1397  */
1398 #define          MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1399 /* enum: Above this for future use. */
1400 #define          MC_CMD_PTP_OP_MAX 0x1c
1401 
1402 /* MC_CMD_PTP_IN_ENABLE msgrequest */
1403 #define    MC_CMD_PTP_IN_ENABLE_LEN 16
1404 #define       MC_CMD_PTP_IN_CMD_OFST 0
1405 #define       MC_CMD_PTP_IN_CMD_LEN 4
1406 #define       MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1407 #define       MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1408 /* Not used. Events are always sent to function relative queue 0. */
1409 #define       MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
1410 #define       MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1411 /* PTP timestamping mode. Not used from Huntington onwards. */
1412 #define       MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
1413 #define       MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1414 /* enum: PTP, version 1 */
1415 #define          MC_CMD_PTP_MODE_V1 0x0
1416 /* enum: PTP, version 1, with VLAN headers - deprecated */
1417 #define          MC_CMD_PTP_MODE_V1_VLAN 0x1
1418 /* enum: PTP, version 2 */
1419 #define          MC_CMD_PTP_MODE_V2 0x2
1420 /* enum: PTP, version 2, with VLAN headers - deprecated */
1421 #define          MC_CMD_PTP_MODE_V2_VLAN 0x3
1422 /* enum: PTP, version 2, with improved UUID filtering */
1423 #define          MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1424 /* enum: FCoE (seconds and microseconds) */
1425 #define          MC_CMD_PTP_MODE_FCOE 0x5
1426 
1427 /* MC_CMD_PTP_IN_DISABLE msgrequest */
1428 #define    MC_CMD_PTP_IN_DISABLE_LEN 8
1429 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1430 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1431 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1432 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1433 
1434 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
1435 #define    MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
1436 #define    MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
1437 #define    MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1438 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1439 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1440 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1441 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1442 /* Transmit packet length */
1443 #define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
1444 #define       MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1445 /* Transmit packet data */
1446 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
1447 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
1448 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
1449 #define       MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
1450 
1451 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
1452 #define    MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
1453 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1454 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1455 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1456 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1457 
1458 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
1459 #define    MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
1460 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1461 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1462 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1463 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1464 
1465 /* MC_CMD_PTP_IN_STATUS msgrequest */
1466 #define    MC_CMD_PTP_IN_STATUS_LEN 8
1467 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1468 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1469 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1470 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1471 
1472 /* MC_CMD_PTP_IN_ADJUST msgrequest */
1473 #define    MC_CMD_PTP_IN_ADJUST_LEN 24
1474 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1475 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1476 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1477 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1478 /* Frequency adjustment 40 bit fixed point ns */
1479 #define       MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
1480 #define       MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
1481 #define       MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
1482 #define       MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
1483 /* enum: Number of fractional bits in frequency adjustment */
1484 #define          MC_CMD_PTP_IN_ADJUST_BITS 0x28
1485 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1486  * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1487  * field.
1488  */
1489 #define          MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1490 /* Time adjustment in seconds */
1491 #define       MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
1492 #define       MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1493 /* Time adjustment major value */
1494 #define       MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
1495 #define       MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1496 /* Time adjustment in nanoseconds */
1497 #define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
1498 #define       MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1499 /* Time adjustment minor value */
1500 #define       MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
1501 #define       MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1502 
1503 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
1504 #define    MC_CMD_PTP_IN_ADJUST_V2_LEN 28
1505 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1506 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1507 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1508 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1509 /* Frequency adjustment 40 bit fixed point ns */
1510 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
1511 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
1512 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
1513 #define       MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
1514 /* enum: Number of fractional bits in frequency adjustment */
1515 /*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1516 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1517  * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1518  * field.
1519  */
1520 /*               MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1521 /* Time adjustment in seconds */
1522 #define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
1523 #define       MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1524 /* Time adjustment major value */
1525 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
1526 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1527 /* Time adjustment in nanoseconds */
1528 #define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
1529 #define       MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1530 /* Time adjustment minor value */
1531 #define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
1532 #define       MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1533 /* Upper 32bits of major time offset adjustment */
1534 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
1535 #define       MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1536 
1537 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
1538 #define    MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
1539 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1540 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1541 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1542 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1543 /* Number of time readings to capture */
1544 #define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
1545 #define       MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1546 /* Host address in which to write "synchronization started" indication (64
1547  * bits)
1548  */
1549 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
1550 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
1551 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
1552 #define       MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
1553 
1554 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
1555 #define    MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
1556 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1557 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1558 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1559 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1560 
1561 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
1562 #define    MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
1563 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1564 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1565 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1566 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1567 /* Enable or disable packet testing */
1568 #define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
1569 #define       MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1570 
1571 /* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
1572 #define    MC_CMD_PTP_IN_RESET_STATS_LEN 8
1573 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1574 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1575 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1576 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1577 
1578 /* MC_CMD_PTP_IN_DEBUG msgrequest */
1579 #define    MC_CMD_PTP_IN_DEBUG_LEN 12
1580 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1581 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1582 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1583 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1584 /* Debug operations */
1585 #define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
1586 #define       MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1587 
1588 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
1589 #define    MC_CMD_PTP_IN_FPGAREAD_LEN 16
1590 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1591 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1592 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1593 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1594 #define       MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
1595 #define       MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1596 #define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
1597 #define       MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1598 
1599 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
1600 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
1601 #define    MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1602 #define    MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1603 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1604 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1605 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1606 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1607 #define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
1608 #define       MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
1609 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
1610 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
1611 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
1612 #define       MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
1613 
1614 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
1615 #define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
1616 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1617 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1618 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1619 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1620 /* Time adjustment in seconds */
1621 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
1622 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
1623 /* Time adjustment major value */
1624 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
1625 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
1626 /* Time adjustment in nanoseconds */
1627 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
1628 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
1629 /* Time adjustment minor value */
1630 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
1631 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
1632 
1633 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
1634 #define    MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
1635 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1636 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1637 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1638 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1639 /* Time adjustment in seconds */
1640 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
1641 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
1642 /* Time adjustment major value */
1643 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
1644 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
1645 /* Time adjustment in nanoseconds */
1646 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
1647 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
1648 /* Time adjustment minor value */
1649 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
1650 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
1651 /* Upper 32bits of major time offset adjustment */
1652 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
1653 #define       MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
1654 
1655 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
1656 #define    MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
1657 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1658 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1659 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1660 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1661 /* Frequency adjustment 40 bit fixed point ns */
1662 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
1663 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
1664 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
1665 #define       MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
1666 /*            Enum values, see field(s): */
1667 /*               MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
1668 
1669 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
1670 #define    MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
1671 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1672 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1673 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1674 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1675 /* Number of VLAN tags, 0 if not VLAN */
1676 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
1677 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
1678 /* Set of VLAN tags to filter against */
1679 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
1680 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
1681 #define       MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
1682 
1683 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
1684 #define    MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
1685 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1686 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1687 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1688 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1689 /* 1 to enable UUID filtering, 0 to disable */
1690 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
1691 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
1692 /* UUID to filter against */
1693 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
1694 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
1695 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
1696 #define       MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
1697 
1698 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
1699 #define    MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
1700 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1701 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1702 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1703 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1704 /* 1 to enable Domain filtering, 0 to disable */
1705 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
1706 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
1707 /* Domain number to filter against */
1708 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
1709 #define       MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
1710 
1711 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
1712 #define    MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
1713 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1714 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1715 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1716 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1717 /* Set the clock source. */
1718 #define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
1719 #define       MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
1720 /* enum: Internal. */
1721 #define          MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1722 /* enum: External. */
1723 #define          MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1724 
1725 /* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
1726 #define    MC_CMD_PTP_IN_RST_CLK_LEN 8
1727 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1728 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1729 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1730 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1731 
1732 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
1733 #define    MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
1734 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1735 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1736 /* Enable or disable */
1737 #define       MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
1738 #define       MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
1739 /* enum: Enable */
1740 #define          MC_CMD_PTP_ENABLE_PPS 0x0
1741 /* enum: Disable */
1742 #define          MC_CMD_PTP_DISABLE_PPS 0x1
1743 /* Not used. Events are always sent to function relative queue 0. */
1744 #define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
1745 #define       MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
1746 
1747 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
1748 #define    MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
1749 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1750 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1751 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1752 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1753 
1754 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
1755 #define    MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
1756 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1757 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1758 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1759 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1760 
1761 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
1762 #define    MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
1763 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1764 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1765 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1766 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1767 
1768 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
1769 #define    MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
1770 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1771 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1772 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1773 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1774 /* Original field containing queue ID. Now extended to include flags. */
1775 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
1776 #define       MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
1777 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
1778 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
1779 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
1780 #define        MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
1781 
1782 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
1783 #define    MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
1784 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1785 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1786 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1787 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1788 /* Unsubscribe options */
1789 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
1790 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
1791 /* enum: Unsubscribe a single queue */
1792 #define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
1793 /* enum: Unsubscribe all queues */
1794 #define          MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
1795 /* Event queue ID */
1796 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
1797 #define       MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
1798 
1799 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
1800 #define    MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
1801 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1802 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1803 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1804 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1805 /* 1 to enable PPS test mode, 0 to disable and return result. */
1806 #define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
1807 #define       MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
1808 
1809 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
1810 #define    MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
1811 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
1812 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
1813 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1814 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1815 /* NIC - Host System Clock Synchronization status */
1816 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
1817 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
1818 /* enum: Host System clock and NIC clock are not in sync */
1819 #define          MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
1820 /* enum: Host System clock and NIC clock are synchronized */
1821 #define          MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
1822 /* If synchronized, number of seconds until clocks should be considered to be
1823  * no longer in sync.
1824  */
1825 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
1826 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
1827 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
1828 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
1829 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
1830 #define       MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
1831 
1832 /* MC_CMD_PTP_OUT msgresponse */
1833 #define    MC_CMD_PTP_OUT_LEN 0
1834 
1835 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
1836 #define    MC_CMD_PTP_OUT_TRANSMIT_LEN 8
1837 /* Value of seconds timestamp */
1838 #define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
1839 #define       MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
1840 /* Timestamp major value */
1841 #define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
1842 #define       MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
1843 /* Value of nanoseconds timestamp */
1844 #define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
1845 #define       MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
1846 /* Timestamp minor value */
1847 #define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
1848 #define       MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
1849 
1850 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
1851 #define    MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
1852 
1853 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
1854 #define    MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
1855 
1856 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
1857 #define    MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
1858 /* Value of seconds timestamp */
1859 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
1860 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
1861 /* Timestamp major value */
1862 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
1863 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
1864 /* Value of nanoseconds timestamp */
1865 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
1866 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
1867 /* Timestamp minor value */
1868 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
1869 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
1870 
1871 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
1872 #define    MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
1873 /* Value of seconds timestamp */
1874 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
1875 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
1876 /* Timestamp major value */
1877 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
1878 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
1879 /* Value of nanoseconds timestamp */
1880 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
1881 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
1882 /* Timestamp minor value */
1883 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
1884 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
1885 /* Upper 32bits of major timestamp value */
1886 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
1887 #define       MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
1888 
1889 /* MC_CMD_PTP_OUT_STATUS msgresponse */
1890 #define    MC_CMD_PTP_OUT_STATUS_LEN 64
1891 /* Frequency of NIC's hardware clock */
1892 #define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
1893 #define       MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
1894 /* Number of packets transmitted and timestamped */
1895 #define       MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
1896 #define       MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
1897 /* Number of packets received and timestamped */
1898 #define       MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
1899 #define       MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
1900 /* Number of packets timestamped by the FPGA */
1901 #define       MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
1902 #define       MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
1903 /* Number of packets filter matched */
1904 #define       MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
1905 #define       MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
1906 /* Number of packets not filter matched */
1907 #define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
1908 #define       MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
1909 /* Number of PPS overflows (noise on input?) */
1910 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
1911 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
1912 /* Number of PPS bad periods */
1913 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
1914 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
1915 /* Minimum period of PPS pulse in nanoseconds */
1916 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
1917 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
1918 /* Maximum period of PPS pulse in nanoseconds */
1919 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
1920 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
1921 /* Last period of PPS pulse in nanoseconds */
1922 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
1923 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
1924 /* Mean period of PPS pulse in nanoseconds */
1925 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
1926 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
1927 /* Minimum offset of PPS pulse in nanoseconds (signed) */
1928 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
1929 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
1930 /* Maximum offset of PPS pulse in nanoseconds (signed) */
1931 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
1932 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
1933 /* Last offset of PPS pulse in nanoseconds (signed) */
1934 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
1935 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
1936 /* Mean offset of PPS pulse in nanoseconds (signed) */
1937 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
1938 #define       MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
1939 
1940 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
1941 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
1942 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
1943 #define    MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
1944 /* A set of host and NIC times */
1945 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1946 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
1947 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
1948 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
1949 /* Host time immediately before NIC's hardware clock read */
1950 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
1951 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
1952 /* Value of seconds timestamp */
1953 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
1954 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
1955 /* Timestamp major value */
1956 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
1957 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
1958 /* Value of nanoseconds timestamp */
1959 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
1960 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
1961 /* Timestamp minor value */
1962 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
1963 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
1964 /* Host time immediately after NIC's hardware clock read */
1965 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
1966 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
1967 /* Number of nanoseconds waited after reading NIC's hardware clock */
1968 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
1969 #define       MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
1970 
1971 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
1972 #define    MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
1973 /* Results of testing */
1974 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
1975 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
1976 /* enum: Successful test */
1977 #define          MC_CMD_PTP_MANF_SUCCESS 0x0
1978 /* enum: FPGA load failed */
1979 #define          MC_CMD_PTP_MANF_FPGA_LOAD 0x1
1980 /* enum: FPGA version invalid */
1981 #define          MC_CMD_PTP_MANF_FPGA_VERSION 0x2
1982 /* enum: FPGA registers incorrect */
1983 #define          MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
1984 /* enum: Oscillator possibly not working? */
1985 #define          MC_CMD_PTP_MANF_OSCILLATOR 0x4
1986 /* enum: Timestamps not increasing */
1987 #define          MC_CMD_PTP_MANF_TIMESTAMPS 0x5
1988 /* enum: Mismatched packet count */
1989 #define          MC_CMD_PTP_MANF_PACKET_COUNT 0x6
1990 /* enum: Mismatched packet count (Siena filter and FPGA) */
1991 #define          MC_CMD_PTP_MANF_FILTER_COUNT 0x7
1992 /* enum: Not enough packets to perform timestamp check */
1993 #define          MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
1994 /* enum: Timestamp trigger GPIO not working */
1995 #define          MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
1996 /* enum: Insufficient PPS events to perform checks */
1997 #define          MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
1998 /* enum: PPS time event period not sufficiently close to 1s. */
1999 #define          MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2000 /* enum: PPS time event nS reading not sufficiently close to zero. */
2001 #define          MC_CMD_PTP_MANF_PPS_NS 0xc
2002 /* enum: PTP peripheral registers incorrect */
2003 #define          MC_CMD_PTP_MANF_REGISTERS 0xd
2004 /* enum: Failed to read time from PTP peripheral */
2005 #define          MC_CMD_PTP_MANF_CLOCK_READ 0xe
2006 /* Presence of external oscillator */
2007 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2008 #define       MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2009 
2010 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
2011 #define    MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
2012 /* Results of testing */
2013 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2014 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2015 /* Number of packets received by FPGA */
2016 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2017 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2018 /* Number of packets received by Siena filters */
2019 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
2020 #define       MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2021 
2022 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
2023 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2024 #define    MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2025 #define    MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2026 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2027 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2028 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2029 #define       MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2030 
2031 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
2032 #define    MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2033 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2034  * operations that pass times between the host and firmware. If this operation
2035  * is not supported (older firmware) a format of seconds and nanoseconds should
2036  * be assumed. Note this enum is deprecated. Do not add to it- use the
2037  * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
2038  */
2039 #define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2040 #define       MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2041 /* enum: Times are in seconds and nanoseconds */
2042 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2043 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2044 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2045 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2046 #define          MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2047 
2048 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
2049 #define    MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
2050 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2051  * operations that pass times between the host and firmware. If this operation
2052  * is not supported (older firmware) a format of seconds and nanoseconds should
2053  * be assumed.
2054  */
2055 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2056 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2057 /* enum: Times are in seconds and nanoseconds */
2058 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2059 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2060 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2061 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2062 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2063 /* enum: Major register units are seconds, minor units are quarter nanoseconds
2064  */
2065 #define          MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2066 /* Minimum acceptable value for a corrected synchronization timeset. When
2067  * comparing host and NIC clock times, the MC returns a set of samples that
2068  * contain the host start and end time, the MC time when the host start was
2069  * detected and the time the MC waited between reading the time and detecting
2070  * the host end. The corrected sync window is the difference between the host
2071  * end and start times minus the time that the MC waited for host end.
2072  */
2073 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2074 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2075 /* Various PTP capabilities */
2076 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
2077 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2078 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2079 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2080 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
2081 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2082 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
2083 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2084 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
2085 #define        MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
2086 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
2087 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2088 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
2089 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2090 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
2091 #define       MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2092 
2093 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
2094 #define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
2095 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2096 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2097 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2098 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2099 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2100 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2101 /* Uncorrected error on PPS output in NIC clock format */
2102 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
2103 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2104 /* Uncorrected error on PPS input in NIC clock format */
2105 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
2106 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2107 
2108 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
2109 #define    MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
2110 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2111 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2112 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2113 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2114 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2115 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2116 /* Uncorrected error on PPS output in NIC clock format */
2117 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
2118 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2119 /* Uncorrected error on PPS input in NIC clock format */
2120 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
2121 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2122 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2123 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
2124 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2125 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2126 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
2127 #define       MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2128 
2129 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
2130 #define    MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2131 /* Results of testing */
2132 #define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2133 #define       MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2134 /*            Enum values, see field(s): */
2135 /*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
2136 
2137 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
2138 #define    MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2139 
2140 
2141 /***********************************/
2142 /* MC_CMD_CSR_READ32
2143  * Read 32bit words from the indirect memory map.
2144  */
2145 #define MC_CMD_CSR_READ32 0xc
2146 
2147 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2148 
2149 /* MC_CMD_CSR_READ32_IN msgrequest */
2150 #define    MC_CMD_CSR_READ32_IN_LEN 12
2151 /* Address */
2152 #define       MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2153 #define       MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2154 #define       MC_CMD_CSR_READ32_IN_STEP_OFST 4
2155 #define       MC_CMD_CSR_READ32_IN_STEP_LEN 4
2156 #define       MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
2157 #define       MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2158 
2159 /* MC_CMD_CSR_READ32_OUT msgresponse */
2160 #define    MC_CMD_CSR_READ32_OUT_LENMIN 4
2161 #define    MC_CMD_CSR_READ32_OUT_LENMAX 252
2162 #define    MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2163 /* The last dword is the status, not a value read */
2164 #define       MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2165 #define       MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2166 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2167 #define       MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2168 
2169 
2170 /***********************************/
2171 /* MC_CMD_CSR_WRITE32
2172  * Write 32bit dwords to the indirect memory map.
2173  */
2174 #define MC_CMD_CSR_WRITE32 0xd
2175 
2176 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2177 
2178 /* MC_CMD_CSR_WRITE32_IN msgrequest */
2179 #define    MC_CMD_CSR_WRITE32_IN_LENMIN 12
2180 #define    MC_CMD_CSR_WRITE32_IN_LENMAX 252
2181 #define    MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2182 /* Address */
2183 #define       MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2184 #define       MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2185 #define       MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2186 #define       MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2187 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
2188 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2189 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2190 #define       MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2191 
2192 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
2193 #define    MC_CMD_CSR_WRITE32_OUT_LEN 4
2194 #define       MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2195 #define       MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2196 
2197 
2198 /***********************************/
2199 /* MC_CMD_HP
2200  * These commands are used for HP related features. They are grouped under one
2201  * MCDI command to avoid creating too many MCDI commands.
2202  */
2203 #define MC_CMD_HP 0x54
2204 
2205 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2206 
2207 /* MC_CMD_HP_IN msgrequest */
2208 #define    MC_CMD_HP_IN_LEN 16
2209 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2210  * the specified address with the specified interval.When address is NULL,
2211  * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2212  * state / 2: (debug) Show temperature reported by one of the supported
2213  * sensors.
2214  */
2215 #define       MC_CMD_HP_IN_SUBCMD_OFST 0
2216 #define       MC_CMD_HP_IN_SUBCMD_LEN 4
2217 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2218 #define          MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2219 /* enum: Last known valid HP sub-command. */
2220 #define          MC_CMD_HP_IN_LAST_SUBCMD 0x0
2221 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2222  */
2223 #define       MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2224 #define       MC_CMD_HP_IN_OCSD_ADDR_LEN 8
2225 #define       MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2226 #define       MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
2227 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
2228  * NULL.)
2229  */
2230 #define       MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
2231 #define       MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2232 
2233 /* MC_CMD_HP_OUT msgresponse */
2234 #define    MC_CMD_HP_OUT_LEN 4
2235 #define       MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2236 #define       MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2237 /* enum: OCSD stopped for this card. */
2238 #define          MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2239 /* enum: OCSD was successfully started with the address provided. */
2240 #define          MC_CMD_HP_OUT_OCSD_STARTED 0x2
2241 /* enum: OCSD was already started for this card. */
2242 #define          MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2243 
2244 
2245 /***********************************/
2246 /* MC_CMD_STACKINFO
2247  * Get stack information.
2248  */
2249 #define MC_CMD_STACKINFO 0xf
2250 
2251 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2252 
2253 /* MC_CMD_STACKINFO_IN msgrequest */
2254 #define    MC_CMD_STACKINFO_IN_LEN 0
2255 
2256 /* MC_CMD_STACKINFO_OUT msgresponse */
2257 #define    MC_CMD_STACKINFO_OUT_LENMIN 12
2258 #define    MC_CMD_STACKINFO_OUT_LENMAX 252
2259 #define    MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2260 /* (thread ptr, stack size, free space) for each thread in system */
2261 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2262 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
2263 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2264 #define       MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2265 
2266 
2267 /***********************************/
2268 /* MC_CMD_MDIO_READ
2269  * MDIO register read.
2270  */
2271 #define MC_CMD_MDIO_READ 0x10
2272 
2273 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2274 
2275 /* MC_CMD_MDIO_READ_IN msgrequest */
2276 #define    MC_CMD_MDIO_READ_IN_LEN 16
2277 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2278  * external devices.
2279  */
2280 #define       MC_CMD_MDIO_READ_IN_BUS_OFST 0
2281 #define       MC_CMD_MDIO_READ_IN_BUS_LEN 4
2282 /* enum: Internal. */
2283 #define          MC_CMD_MDIO_BUS_INTERNAL 0x0
2284 /* enum: External. */
2285 #define          MC_CMD_MDIO_BUS_EXTERNAL 0x1
2286 /* Port address */
2287 #define       MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2288 #define       MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2289 /* Device Address or clause 22. */
2290 #define       MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
2291 #define       MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2292 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2293  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2294  */
2295 #define          MC_CMD_MDIO_CLAUSE22 0x20
2296 /* Address */
2297 #define       MC_CMD_MDIO_READ_IN_ADDR_OFST 12
2298 #define       MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2299 
2300 /* MC_CMD_MDIO_READ_OUT msgresponse */
2301 #define    MC_CMD_MDIO_READ_OUT_LEN 8
2302 /* Value */
2303 #define       MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2304 #define       MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2305 /* Status the MDIO commands return the raw status bits from the MDIO block. A
2306  * "good" transaction should have the DONE bit set and all other bits clear.
2307  */
2308 #define       MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2309 #define       MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2310 /* enum: Good. */
2311 #define          MC_CMD_MDIO_STATUS_GOOD 0x8
2312 
2313 
2314 /***********************************/
2315 /* MC_CMD_MDIO_WRITE
2316  * MDIO register write.
2317  */
2318 #define MC_CMD_MDIO_WRITE 0x11
2319 
2320 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2321 
2322 /* MC_CMD_MDIO_WRITE_IN msgrequest */
2323 #define    MC_CMD_MDIO_WRITE_IN_LEN 20
2324 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2325  * external devices.
2326  */
2327 #define       MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2328 #define       MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2329 /* enum: Internal. */
2330 /*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2331 /* enum: External. */
2332 /*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2333 /* Port address */
2334 #define       MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2335 #define       MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2336 /* Device Address or clause 22. */
2337 #define       MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
2338 #define       MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2339 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2340  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2341  */
2342 /*               MC_CMD_MDIO_CLAUSE22 0x20 */
2343 /* Address */
2344 #define       MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
2345 #define       MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2346 /* Value */
2347 #define       MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
2348 #define       MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2349 
2350 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
2351 #define    MC_CMD_MDIO_WRITE_OUT_LEN 4
2352 /* Status; the MDIO commands return the raw status bits from the MDIO block. A
2353  * "good" transaction should have the DONE bit set and all other bits clear.
2354  */
2355 #define       MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2356 #define       MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2357 /* enum: Good. */
2358 /*               MC_CMD_MDIO_STATUS_GOOD 0x8 */
2359 
2360 
2361 /***********************************/
2362 /* MC_CMD_DBI_WRITE
2363  * Write DBI register(s).
2364  */
2365 #define MC_CMD_DBI_WRITE 0x12
2366 
2367 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2368 
2369 /* MC_CMD_DBI_WRITE_IN msgrequest */
2370 #define    MC_CMD_DBI_WRITE_IN_LENMIN 12
2371 #define    MC_CMD_DBI_WRITE_IN_LENMAX 252
2372 #define    MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2373 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2374  * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
2375  */
2376 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2377 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
2378 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2379 #define       MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2380 
2381 /* MC_CMD_DBI_WRITE_OUT msgresponse */
2382 #define    MC_CMD_DBI_WRITE_OUT_LEN 0
2383 
2384 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
2385 #define    MC_CMD_DBIWROP_TYPEDEF_LEN 12
2386 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2387 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2388 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2389 #define       MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
2390 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2391 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2392 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
2393 #define        MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
2394 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
2395 #define        MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2396 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
2397 #define        MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
2398 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
2399 #define       MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
2400 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
2401 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2402 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
2403 #define       MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
2404 
2405 
2406 /***********************************/
2407 /* MC_CMD_PORT_READ32
2408  * Read a 32-bit register from the indirect port register map. The port to
2409  * access is implied by the Shared memory channel used.
2410  */
2411 #define MC_CMD_PORT_READ32 0x14
2412 
2413 /* MC_CMD_PORT_READ32_IN msgrequest */
2414 #define    MC_CMD_PORT_READ32_IN_LEN 4
2415 /* Address */
2416 #define       MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2417 #define       MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2418 
2419 /* MC_CMD_PORT_READ32_OUT msgresponse */
2420 #define    MC_CMD_PORT_READ32_OUT_LEN 8
2421 /* Value */
2422 #define       MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2423 #define       MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2424 /* Status */
2425 #define       MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2426 #define       MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2427 
2428 
2429 /***********************************/
2430 /* MC_CMD_PORT_WRITE32
2431  * Write a 32-bit register to the indirect port register map. The port to
2432  * access is implied by the Shared memory channel used.
2433  */
2434 #define MC_CMD_PORT_WRITE32 0x15
2435 
2436 /* MC_CMD_PORT_WRITE32_IN msgrequest */
2437 #define    MC_CMD_PORT_WRITE32_IN_LEN 8
2438 /* Address */
2439 #define       MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2440 #define       MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2441 /* Value */
2442 #define       MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2443 #define       MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2444 
2445 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
2446 #define    MC_CMD_PORT_WRITE32_OUT_LEN 4
2447 /* Status */
2448 #define       MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2449 #define       MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2450 
2451 
2452 /***********************************/
2453 /* MC_CMD_PORT_READ128
2454  * Read a 128-bit register from the indirect port register map. The port to
2455  * access is implied by the Shared memory channel used.
2456  */
2457 #define MC_CMD_PORT_READ128 0x16
2458 
2459 /* MC_CMD_PORT_READ128_IN msgrequest */
2460 #define    MC_CMD_PORT_READ128_IN_LEN 4
2461 /* Address */
2462 #define       MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2463 #define       MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2464 
2465 /* MC_CMD_PORT_READ128_OUT msgresponse */
2466 #define    MC_CMD_PORT_READ128_OUT_LEN 20
2467 /* Value */
2468 #define       MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2469 #define       MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
2470 /* Status */
2471 #define       MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
2472 #define       MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2473 
2474 
2475 /***********************************/
2476 /* MC_CMD_PORT_WRITE128
2477  * Write a 128-bit register to the indirect port register map. The port to
2478  * access is implied by the Shared memory channel used.
2479  */
2480 #define MC_CMD_PORT_WRITE128 0x17
2481 
2482 /* MC_CMD_PORT_WRITE128_IN msgrequest */
2483 #define    MC_CMD_PORT_WRITE128_IN_LEN 20
2484 /* Address */
2485 #define       MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2486 #define       MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2487 /* Value */
2488 #define       MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2489 #define       MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
2490 
2491 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
2492 #define    MC_CMD_PORT_WRITE128_OUT_LEN 4
2493 /* Status */
2494 #define       MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2495 #define       MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2496 
2497 /* MC_CMD_CAPABILITIES structuredef */
2498 #define    MC_CMD_CAPABILITIES_LEN 4
2499 /* Small buf table. */
2500 #define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2501 #define       MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
2502 /* Turbo mode (for Maranello). */
2503 #define       MC_CMD_CAPABILITIES_TURBO_LBN 1
2504 #define       MC_CMD_CAPABILITIES_TURBO_WIDTH 1
2505 /* Turbo mode active (for Maranello). */
2506 #define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
2507 #define       MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
2508 /* PTP offload. */
2509 #define       MC_CMD_CAPABILITIES_PTP_LBN 3
2510 #define       MC_CMD_CAPABILITIES_PTP_WIDTH 1
2511 /* AOE mode. */
2512 #define       MC_CMD_CAPABILITIES_AOE_LBN 4
2513 #define       MC_CMD_CAPABILITIES_AOE_WIDTH 1
2514 /* AOE mode active. */
2515 #define       MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
2516 #define       MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
2517 /* AOE mode active. */
2518 #define       MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
2519 #define       MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
2520 #define       MC_CMD_CAPABILITIES_RESERVED_LBN 7
2521 #define       MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
2522 
2523 
2524 /***********************************/
2525 /* MC_CMD_GET_BOARD_CFG
2526  * Returns the MC firmware configuration structure.
2527  */
2528 #define MC_CMD_GET_BOARD_CFG 0x18
2529 
2530 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2531 
2532 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
2533 #define    MC_CMD_GET_BOARD_CFG_IN_LEN 0
2534 
2535 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
2536 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
2537 #define    MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2538 #define    MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2539 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2540 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2541 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2542 #define       MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
2543 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
2544  * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2545  */
2546 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
2547 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2548 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
2549  * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2550  */
2551 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
2552 #define       MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2553 /* Base MAC address for Siena Port0. Unused on EF10 and later (use
2554  * MC_CMD_GET_MAC_ADDRESSES).
2555  */
2556 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
2557 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
2558 /* Base MAC address for Siena Port1. Unused on EF10 and later (use
2559  * MC_CMD_GET_MAC_ADDRESSES).
2560  */
2561 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
2562 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
2563 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
2564  * MC_CMD_GET_MAC_ADDRESSES).
2565  */
2566 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
2567 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2568 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
2569  * MC_CMD_GET_MAC_ADDRESSES).
2570  */
2571 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
2572 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
2573 /* Increment between addresses in MAC address pool for Siena Port0. Unused on
2574  * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
2575  */
2576 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
2577 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
2578 /* Increment between addresses in MAC address pool for Siena Port1. Unused on
2579  * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
2580  */
2581 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
2582 #define       MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
2583 /* Siena only. This field contains a 16-bit value for each of the types of
2584  * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
2585  * specific board type, but otherwise have no meaning to the MC; they are used
2586  * by the driver to manage selection of appropriate firmware updates. Unused on
2587  * EF10 and later (use MC_CMD_NVRAM_METADATA).
2588  */
2589 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
2590 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
2591 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
2592 #define       MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
2593 
2594 
2595 /***********************************/
2596 /* MC_CMD_DBI_READX
2597  * Read DBI register(s) -- extended functionality
2598  */
2599 #define MC_CMD_DBI_READX 0x19
2600 
2601 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2602 
2603 /* MC_CMD_DBI_READX_IN msgrequest */
2604 #define    MC_CMD_DBI_READX_IN_LENMIN 8
2605 #define    MC_CMD_DBI_READX_IN_LENMAX 248
2606 #define    MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
2607 /* Each Read op consists of an address (offset 0), VF/CS2) */
2608 #define       MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
2609 #define       MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
2610 #define       MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
2611 #define       MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
2612 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
2613 #define       MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
2614 
2615 /* MC_CMD_DBI_READX_OUT msgresponse */
2616 #define    MC_CMD_DBI_READX_OUT_LENMIN 4
2617 #define    MC_CMD_DBI_READX_OUT_LENMAX 252
2618 #define    MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
2619 /* Value */
2620 #define       MC_CMD_DBI_READX_OUT_VALUE_OFST 0
2621 #define       MC_CMD_DBI_READX_OUT_VALUE_LEN 4
2622 #define       MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
2623 #define       MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
2624 
2625 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
2626 #define    MC_CMD_DBIRDOP_TYPEDEF_LEN 8
2627 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
2628 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
2629 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
2630 #define       MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
2631 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
2632 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
2633 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
2634 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
2635 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
2636 #define        MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
2637 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
2638 #define        MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
2639 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
2640 #define       MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
2641 
2642 
2643 /***********************************/
2644 /* MC_CMD_SET_RAND_SEED
2645  * Set the 16byte seed for the MC pseudo-random generator.
2646  */
2647 #define MC_CMD_SET_RAND_SEED 0x1a
2648 
2649 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2650 
2651 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
2652 #define    MC_CMD_SET_RAND_SEED_IN_LEN 16
2653 /* Seed value. */
2654 #define       MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
2655 #define       MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
2656 
2657 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
2658 #define    MC_CMD_SET_RAND_SEED_OUT_LEN 0
2659 
2660 
2661 /***********************************/
2662 /* MC_CMD_LTSSM_HIST
2663  * Retrieve the history of the LTSSM, if the build supports it.
2664  */
2665 #define MC_CMD_LTSSM_HIST 0x1b
2666 
2667 /* MC_CMD_LTSSM_HIST_IN msgrequest */
2668 #define    MC_CMD_LTSSM_HIST_IN_LEN 0
2669 
2670 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
2671 #define    MC_CMD_LTSSM_HIST_OUT_LENMIN 0
2672 #define    MC_CMD_LTSSM_HIST_OUT_LENMAX 252
2673 #define    MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
2674 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
2675 #define       MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
2676 #define       MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
2677 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
2678 #define       MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
2679 
2680 
2681 /***********************************/
2682 /* MC_CMD_DRV_ATTACH
2683  * Inform MCPU that this port is managed on the host (i.e. driver active). For
2684  * Huntington, also request the preferred datapath firmware to use if possible
2685  * (it may not be possible for this request to be fulfilled; the driver must
2686  * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
2687  * features are actually available). The FIRMWARE_ID field is ignored by older
2688  * platforms.
2689  */
2690 #define MC_CMD_DRV_ATTACH 0x1c
2691 
2692 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2693 
2694 /* MC_CMD_DRV_ATTACH_IN msgrequest */
2695 #define    MC_CMD_DRV_ATTACH_IN_LEN 12
2696 /* new state to set if UPDATE=1 */
2697 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
2698 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
2699 #define        MC_CMD_DRV_ATTACH_LBN 0
2700 #define        MC_CMD_DRV_ATTACH_WIDTH 1
2701 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
2702 #define        MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
2703 #define        MC_CMD_DRV_PREBOOT_LBN 1
2704 #define        MC_CMD_DRV_PREBOOT_WIDTH 1
2705 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
2706 #define        MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
2707 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
2708 #define        MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
2709 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
2710 #define        MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
2711 /* 1 to set new state, or 0 to just report the existing state */
2712 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
2713 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
2714 /* preferred datapath firmware (for Huntington; ignored for Siena) */
2715 #define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
2716 #define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
2717 /* enum: Prefer to use full featured firmware */
2718 #define          MC_CMD_FW_FULL_FEATURED 0x0
2719 /* enum: Prefer to use firmware with fewer features but lower latency */
2720 #define          MC_CMD_FW_LOW_LATENCY 0x1
2721 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
2722 #define          MC_CMD_FW_PACKED_STREAM 0x2
2723 /* enum: Prefer to use firmware with fewer features and simpler TX event
2724  * batching but higher TX packet rate
2725  */
2726 #define          MC_CMD_FW_HIGH_TX_RATE 0x3
2727 /* enum: Reserved value */
2728 #define          MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
2729 /* enum: Prefer to use firmware with additional "rules engine" filtering
2730  * support
2731  */
2732 #define          MC_CMD_FW_RULES_ENGINE 0x5
2733 /* enum: Prefer to use firmware with additional DPDK support */
2734 #define          MC_CMD_FW_DPDK 0x6
2735 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
2736  * bug69716)
2737  */
2738 #define          MC_CMD_FW_L3XUDP 0x7
2739 /* enum: Only this option is allowed for non-admin functions */
2740 #define          MC_CMD_FW_DONT_CARE 0xffffffff
2741 
2742 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
2743 #define    MC_CMD_DRV_ATTACH_OUT_LEN 4
2744 /* previous or existing state, see the bitmask at NEW_STATE */
2745 #define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
2746 #define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
2747 
2748 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
2749 #define    MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
2750 /* previous or existing state, see the bitmask at NEW_STATE */
2751 #define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
2752 #define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
2753 /* Flags associated with this function */
2754 #define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
2755 #define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
2756 /* enum: Labels the lowest-numbered function visible to the OS */
2757 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
2758 /* enum: The function can control the link state of the physical port it is
2759  * bound to.
2760  */
2761 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
2762 /* enum: The function can perform privileged operations */
2763 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
2764 /* enum: The function does not have an active port associated with it. The port
2765  * refers to the Sorrento external FPGA port.
2766  */
2767 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
2768 /* enum: If set, indicates that VI spreading is currently enabled. Will always
2769  * indicate the current state, regardless of the value in the WANT_VI_SPREADING
2770  * input.
2771  */
2772 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
2773 
2774 
2775 /***********************************/
2776 /* MC_CMD_SHMUART
2777  * Route UART output to circular buffer in shared memory instead.
2778  */
2779 #define MC_CMD_SHMUART 0x1f
2780 
2781 /* MC_CMD_SHMUART_IN msgrequest */
2782 #define    MC_CMD_SHMUART_IN_LEN 4
2783 /* ??? */
2784 #define       MC_CMD_SHMUART_IN_FLAG_OFST 0
2785 #define       MC_CMD_SHMUART_IN_FLAG_LEN 4
2786 
2787 /* MC_CMD_SHMUART_OUT msgresponse */
2788 #define    MC_CMD_SHMUART_OUT_LEN 0
2789 
2790 
2791 /***********************************/
2792 /* MC_CMD_PORT_RESET
2793  * Generic per-port reset. There is no equivalent for per-board reset. Locks
2794  * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
2795  * use MC_CMD_ENTITY_RESET instead.
2796  */
2797 #define MC_CMD_PORT_RESET 0x20
2798 
2799 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2800 
2801 /* MC_CMD_PORT_RESET_IN msgrequest */
2802 #define    MC_CMD_PORT_RESET_IN_LEN 0
2803 
2804 /* MC_CMD_PORT_RESET_OUT msgresponse */
2805 #define    MC_CMD_PORT_RESET_OUT_LEN 0
2806 
2807 
2808 /***********************************/
2809 /* MC_CMD_ENTITY_RESET
2810  * Generic per-resource reset. There is no equivalent for per-board reset.
2811  * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
2812  * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
2813  */
2814 #define MC_CMD_ENTITY_RESET 0x20
2815 /*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
2816 
2817 /* MC_CMD_ENTITY_RESET_IN msgrequest */
2818 #define    MC_CMD_ENTITY_RESET_IN_LEN 4
2819 /* Optional flags field. Omitting this will perform a "legacy" reset action
2820  * (TBD).
2821  */
2822 #define       MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
2823 #define       MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
2824 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
2825 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
2826 
2827 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
2828 #define    MC_CMD_ENTITY_RESET_OUT_LEN 0
2829 
2830 
2831 /***********************************/
2832 /* MC_CMD_PCIE_CREDITS
2833  * Read instantaneous and minimum flow control thresholds.
2834  */
2835 #define MC_CMD_PCIE_CREDITS 0x21
2836 
2837 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
2838 #define    MC_CMD_PCIE_CREDITS_IN_LEN 8
2839 /* poll period. 0 is disabled */
2840 #define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
2841 #define       MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
2842 /* wipe statistics */
2843 #define       MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
2844 #define       MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
2845 
2846 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
2847 #define    MC_CMD_PCIE_CREDITS_OUT_LEN 16
2848 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
2849 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
2850 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
2851 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
2852 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
2853 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
2854 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
2855 #define       MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
2856 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
2857 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
2858 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
2859 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
2860 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
2861 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
2862 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
2863 #define       MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
2864 
2865 
2866 /***********************************/
2867 /* MC_CMD_RXD_MONITOR
2868  * Get histogram of RX queue fill level.
2869  */
2870 #define MC_CMD_RXD_MONITOR 0x22
2871 
2872 /* MC_CMD_RXD_MONITOR_IN msgrequest */
2873 #define    MC_CMD_RXD_MONITOR_IN_LEN 12
2874 #define       MC_CMD_RXD_MONITOR_IN_QID_OFST 0
2875 #define       MC_CMD_RXD_MONITOR_IN_QID_LEN 4
2876 #define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
2877 #define       MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
2878 #define       MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
2879 #define       MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
2880 
2881 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
2882 #define    MC_CMD_RXD_MONITOR_OUT_LEN 80
2883 #define       MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
2884 #define       MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
2885 #define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
2886 #define       MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
2887 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
2888 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
2889 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
2890 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
2891 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
2892 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
2893 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
2894 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
2895 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
2896 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
2897 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
2898 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
2899 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
2900 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
2901 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
2902 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
2903 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
2904 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
2905 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
2906 #define       MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
2907 #define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
2908 #define       MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
2909 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
2910 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
2911 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
2912 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
2913 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
2914 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
2915 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
2916 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
2917 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
2918 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
2919 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
2920 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
2921 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
2922 #define       MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
2923 
2924 
2925 /***********************************/
2926 /* MC_CMD_PUTS
2927  * Copy the given ASCII string out onto UART and/or out of the network port.
2928  */
2929 #define MC_CMD_PUTS 0x23
2930 
2931 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2932 
2933 /* MC_CMD_PUTS_IN msgrequest */
2934 #define    MC_CMD_PUTS_IN_LENMIN 13
2935 #define    MC_CMD_PUTS_IN_LENMAX 252
2936 #define    MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
2937 #define       MC_CMD_PUTS_IN_DEST_OFST 0
2938 #define       MC_CMD_PUTS_IN_DEST_LEN 4
2939 #define        MC_CMD_PUTS_IN_UART_LBN 0
2940 #define        MC_CMD_PUTS_IN_UART_WIDTH 1
2941 #define        MC_CMD_PUTS_IN_PORT_LBN 1
2942 #define        MC_CMD_PUTS_IN_PORT_WIDTH 1
2943 #define       MC_CMD_PUTS_IN_DHOST_OFST 4
2944 #define       MC_CMD_PUTS_IN_DHOST_LEN 6
2945 #define       MC_CMD_PUTS_IN_STRING_OFST 12
2946 #define       MC_CMD_PUTS_IN_STRING_LEN 1
2947 #define       MC_CMD_PUTS_IN_STRING_MINNUM 1
2948 #define       MC_CMD_PUTS_IN_STRING_MAXNUM 240
2949 
2950 /* MC_CMD_PUTS_OUT msgresponse */
2951 #define    MC_CMD_PUTS_OUT_LEN 0
2952 
2953 
2954 /***********************************/
2955 /* MC_CMD_GET_PHY_CFG
2956  * Report PHY configuration. This guarantees to succeed even if the PHY is in a
2957  * 'zombie' state. Locks required: None
2958  */
2959 #define MC_CMD_GET_PHY_CFG 0x24
2960 
2961 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2962 
2963 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
2964 #define    MC_CMD_GET_PHY_CFG_IN_LEN 0
2965 
2966 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
2967 #define    MC_CMD_GET_PHY_CFG_OUT_LEN 72
2968 /* flags */
2969 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
2970 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
2971 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
2972 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
2973 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
2974 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
2975 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
2976 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
2977 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
2978 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
2979 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
2980 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
2981 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
2982 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
2983 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
2984 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
2985 /* ?? */
2986 #define       MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
2987 #define       MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
2988 /* Bitmask of supported capabilities */
2989 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
2990 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
2991 #define        MC_CMD_PHY_CAP_10HDX_LBN 1
2992 #define        MC_CMD_PHY_CAP_10HDX_WIDTH 1
2993 #define        MC_CMD_PHY_CAP_10FDX_LBN 2
2994 #define        MC_CMD_PHY_CAP_10FDX_WIDTH 1
2995 #define        MC_CMD_PHY_CAP_100HDX_LBN 3
2996 #define        MC_CMD_PHY_CAP_100HDX_WIDTH 1
2997 #define        MC_CMD_PHY_CAP_100FDX_LBN 4
2998 #define        MC_CMD_PHY_CAP_100FDX_WIDTH 1
2999 #define        MC_CMD_PHY_CAP_1000HDX_LBN 5
3000 #define        MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3001 #define        MC_CMD_PHY_CAP_1000FDX_LBN 6
3002 #define        MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3003 #define        MC_CMD_PHY_CAP_10000FDX_LBN 7
3004 #define        MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3005 #define        MC_CMD_PHY_CAP_PAUSE_LBN 8
3006 #define        MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3007 #define        MC_CMD_PHY_CAP_ASYM_LBN 9
3008 #define        MC_CMD_PHY_CAP_ASYM_WIDTH 1
3009 #define        MC_CMD_PHY_CAP_AN_LBN 10
3010 #define        MC_CMD_PHY_CAP_AN_WIDTH 1
3011 #define        MC_CMD_PHY_CAP_40000FDX_LBN 11
3012 #define        MC_CMD_PHY_CAP_40000FDX_WIDTH 1
3013 #define        MC_CMD_PHY_CAP_DDM_LBN 12
3014 #define        MC_CMD_PHY_CAP_DDM_WIDTH 1
3015 #define        MC_CMD_PHY_CAP_100000FDX_LBN 13
3016 #define        MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3017 #define        MC_CMD_PHY_CAP_25000FDX_LBN 14
3018 #define        MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3019 #define        MC_CMD_PHY_CAP_50000FDX_LBN 15
3020 #define        MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3021 #define        MC_CMD_PHY_CAP_BASER_FEC_LBN 16
3022 #define        MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3023 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
3024 #define        MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3025 #define        MC_CMD_PHY_CAP_RS_FEC_LBN 18
3026 #define        MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3027 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
3028 #define        MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3029 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
3030 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3031 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
3032 #define        MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
3033 /* ?? */
3034 #define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
3035 #define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3036 /* ?? */
3037 #define       MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
3038 #define       MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3039 /* ?? */
3040 #define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
3041 #define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3042 /* ?? */
3043 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
3044 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
3045 /* ?? */
3046 #define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
3047 #define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3048 /* enum: Xaui. */
3049 #define          MC_CMD_MEDIA_XAUI 0x1
3050 /* enum: CX4. */
3051 #define          MC_CMD_MEDIA_CX4 0x2
3052 /* enum: KX4. */
3053 #define          MC_CMD_MEDIA_KX4 0x3
3054 /* enum: XFP Far. */
3055 #define          MC_CMD_MEDIA_XFP 0x4
3056 /* enum: SFP+. */
3057 #define          MC_CMD_MEDIA_SFP_PLUS 0x5
3058 /* enum: 10GBaseT. */
3059 #define          MC_CMD_MEDIA_BASE_T 0x6
3060 /* enum: QSFP+. */
3061 #define          MC_CMD_MEDIA_QSFP_PLUS 0x7
3062 #define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
3063 #define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3064 /* enum: Native clause 22 */
3065 #define          MC_CMD_MMD_CLAUSE22 0x0
3066 #define          MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3067 #define          MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3068 #define          MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3069 #define          MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3070 #define          MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3071 #define          MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3072 #define          MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3073 /* enum: Clause22 proxied over clause45 by PHY. */
3074 #define          MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3075 #define          MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3076 #define          MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3077 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
3078 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
3079 
3080 
3081 /***********************************/
3082 /* MC_CMD_START_BIST
3083  * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
3084  * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3085  */
3086 #define MC_CMD_START_BIST 0x25
3087 
3088 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3089 
3090 /* MC_CMD_START_BIST_IN msgrequest */
3091 #define    MC_CMD_START_BIST_IN_LEN 4
3092 /* Type of test. */
3093 #define       MC_CMD_START_BIST_IN_TYPE_OFST 0
3094 #define       MC_CMD_START_BIST_IN_TYPE_LEN 4
3095 /* enum: Run the PHY's short cable BIST. */
3096 #define          MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3097 /* enum: Run the PHY's long cable BIST. */
3098 #define          MC_CMD_PHY_BIST_CABLE_LONG 0x2
3099 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
3100 #define          MC_CMD_BPX_SERDES_BIST 0x3
3101 /* enum: Run the MC loopback tests. */
3102 #define          MC_CMD_MC_LOOPBACK_BIST 0x4
3103 /* enum: Run the PHY's standard BIST. */
3104 #define          MC_CMD_PHY_BIST 0x5
3105 /* enum: Run MC RAM test. */
3106 #define          MC_CMD_MC_MEM_BIST 0x6
3107 /* enum: Run Port RAM test. */
3108 #define          MC_CMD_PORT_MEM_BIST 0x7
3109 /* enum: Run register test. */
3110 #define          MC_CMD_REG_BIST 0x8
3111 
3112 /* MC_CMD_START_BIST_OUT msgresponse */
3113 #define    MC_CMD_START_BIST_OUT_LEN 0
3114 
3115 
3116 /***********************************/
3117 /* MC_CMD_POLL_BIST
3118  * Poll for BIST completion. Returns a single status code, and optionally some
3119  * PHY specific bist output. The driver should only consume the BIST output
3120  * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
3121  * successfully parse the BIST output, it should still respect the pass/Fail in
3122  * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3123  * EACCES (if PHY_LOCK is not held).
3124  */
3125 #define MC_CMD_POLL_BIST 0x26
3126 
3127 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3128 
3129 /* MC_CMD_POLL_BIST_IN msgrequest */
3130 #define    MC_CMD_POLL_BIST_IN_LEN 0
3131 
3132 /* MC_CMD_POLL_BIST_OUT msgresponse */
3133 #define    MC_CMD_POLL_BIST_OUT_LEN 8
3134 /* result */
3135 #define       MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3136 #define       MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3137 /* enum: Running. */
3138 #define          MC_CMD_POLL_BIST_RUNNING 0x1
3139 /* enum: Passed. */
3140 #define          MC_CMD_POLL_BIST_PASSED 0x2
3141 /* enum: Failed. */
3142 #define          MC_CMD_POLL_BIST_FAILED 0x3
3143 /* enum: Timed-out. */
3144 #define          MC_CMD_POLL_BIST_TIMEOUT 0x4
3145 #define       MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3146 #define       MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3147 
3148 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
3149 #define    MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
3150 /* result */
3151 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3152 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3153 /*            Enum values, see field(s): */
3154 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3155 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3156 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3157 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
3158 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3159 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
3160 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3161 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
3162 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3163 /* Status of each channel A */
3164 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
3165 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3166 /* enum: Ok. */
3167 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3168 /* enum: Open. */
3169 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3170 /* enum: Intra-pair short. */
3171 #define          MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3172 /* enum: Inter-pair short. */
3173 #define          MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3174 /* enum: Busy. */
3175 #define          MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3176 /* Status of each channel B */
3177 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
3178 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3179 /*            Enum values, see field(s): */
3180 /*               CABLE_STATUS_A */
3181 /* Status of each channel C */
3182 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
3183 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3184 /*            Enum values, see field(s): */
3185 /*               CABLE_STATUS_A */
3186 /* Status of each channel D */
3187 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
3188 #define       MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3189 /*            Enum values, see field(s): */
3190 /*               CABLE_STATUS_A */
3191 
3192 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
3193 #define    MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
3194 /* result */
3195 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3196 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3197 /*            Enum values, see field(s): */
3198 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3199 #define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3200 #define       MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3201 /* enum: Complete. */
3202 #define          MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3203 /* enum: Bus switch off I2C write. */
3204 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3205 /* enum: Bus switch off I2C no access IO exp. */
3206 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3207 /* enum: Bus switch off I2C no access module. */
3208 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3209 /* enum: IO exp I2C configure. */
3210 #define          MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3211 /* enum: Bus switch I2C no cross talk. */
3212 #define          MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3213 /* enum: Module presence. */
3214 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3215 /* enum: Module ID I2C access. */
3216 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3217 /* enum: Module ID sane value. */
3218 #define          MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3219 
3220 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
3221 #define    MC_CMD_POLL_BIST_OUT_MEM_LEN 36
3222 /* result */
3223 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3224 /*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3225 /*            Enum values, see field(s): */
3226 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3227 #define       MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3228 #define       MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3229 /* enum: Test has completed. */
3230 #define          MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3231 /* enum: RAM test - walk ones. */
3232 #define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3233 /* enum: RAM test - walk zeros. */
3234 #define          MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3235 /* enum: RAM test - walking inversions zeros/ones. */
3236 #define          MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3237 /* enum: RAM test - walking inversions checkerboard. */
3238 #define          MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3239 /* enum: Register test - set / clear individual bits. */
3240 #define          MC_CMD_POLL_BIST_MEM_REG 0x5
3241 /* enum: ECC error detected. */
3242 #define          MC_CMD_POLL_BIST_MEM_ECC 0x6
3243 /* Failure address, only valid if result is POLL_BIST_FAILED */
3244 #define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
3245 #define       MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3246 /* Bus or address space to which the failure address corresponds */
3247 #define       MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
3248 #define       MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3249 /* enum: MC MIPS bus. */
3250 #define          MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3251 /* enum: CSR IREG bus. */
3252 #define          MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3253 /* enum: RX0 DPCPU bus. */
3254 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3255 /* enum: TX0 DPCPU bus. */
3256 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3257 /* enum: TX1 DPCPU bus. */
3258 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3259 /* enum: RX0 DICPU bus. */
3260 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3261 /* enum: TX DICPU bus. */
3262 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3263 /* enum: RX1 DPCPU bus. */
3264 #define          MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3265 /* enum: RX1 DICPU bus. */
3266 #define          MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3267 /* Pattern written to RAM / register */
3268 #define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
3269 #define       MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3270 /* Actual value read from RAM / register */
3271 #define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
3272 #define       MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3273 /* ECC error mask */
3274 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
3275 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3276 /* ECC parity error mask */
3277 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
3278 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3279 /* ECC fatal error mask */
3280 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
3281 #define       MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3282 
3283 
3284 /***********************************/
3285 /* MC_CMD_FLUSH_RX_QUEUES
3286  * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
3287  * flushes should be initiated via this MCDI operation, rather than via
3288  * directly writing FLUSH_CMD.
3289  *
3290  * The flush is completed (either done/fail) asynchronously (after this command
3291  * returns). The driver must still wait for flush done/failure events as usual.
3292  */
3293 #define MC_CMD_FLUSH_RX_QUEUES 0x27
3294 
3295 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
3296 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3297 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3298 #define    MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3299 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3300 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3301 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3302 #define       MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3303 
3304 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
3305 #define    MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3306 
3307 
3308 /***********************************/
3309 /* MC_CMD_GET_LOOPBACK_MODES
3310  * Returns a bitmask of loopback modes available at each speed.
3311  */
3312 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3313 
3314 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3315 
3316 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
3317 #define    MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3318 
3319 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
3320 #define    MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
3321 /* Supported loopbacks. */
3322 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3323 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
3324 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3325 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3326 /* enum: None. */
3327 #define          MC_CMD_LOOPBACK_NONE 0x0
3328 /* enum: Data. */
3329 #define          MC_CMD_LOOPBACK_DATA 0x1
3330 /* enum: GMAC. */
3331 #define          MC_CMD_LOOPBACK_GMAC 0x2
3332 /* enum: XGMII. */
3333 #define          MC_CMD_LOOPBACK_XGMII 0x3
3334 /* enum: XGXS. */
3335 #define          MC_CMD_LOOPBACK_XGXS 0x4
3336 /* enum: XAUI. */
3337 #define          MC_CMD_LOOPBACK_XAUI 0x5
3338 /* enum: GMII. */
3339 #define          MC_CMD_LOOPBACK_GMII 0x6
3340 /* enum: SGMII. */
3341 #define          MC_CMD_LOOPBACK_SGMII 0x7
3342 /* enum: XGBR. */
3343 #define          MC_CMD_LOOPBACK_XGBR 0x8
3344 /* enum: XFI. */
3345 #define          MC_CMD_LOOPBACK_XFI 0x9
3346 /* enum: XAUI Far. */
3347 #define          MC_CMD_LOOPBACK_XAUI_FAR 0xa
3348 /* enum: GMII Far. */
3349 #define          MC_CMD_LOOPBACK_GMII_FAR 0xb
3350 /* enum: SGMII Far. */
3351 #define          MC_CMD_LOOPBACK_SGMII_FAR 0xc
3352 /* enum: XFI Far. */
3353 #define          MC_CMD_LOOPBACK_XFI_FAR 0xd
3354 /* enum: GPhy. */
3355 #define          MC_CMD_LOOPBACK_GPHY 0xe
3356 /* enum: PhyXS. */
3357 #define          MC_CMD_LOOPBACK_PHYXS 0xf
3358 /* enum: PCS. */
3359 #define          MC_CMD_LOOPBACK_PCS 0x10
3360 /* enum: PMA-PMD. */
3361 #define          MC_CMD_LOOPBACK_PMAPMD 0x11
3362 /* enum: Cross-Port. */
3363 #define          MC_CMD_LOOPBACK_XPORT 0x12
3364 /* enum: XGMII-Wireside. */
3365 #define          MC_CMD_LOOPBACK_XGMII_WS 0x13
3366 /* enum: XAUI Wireside. */
3367 #define          MC_CMD_LOOPBACK_XAUI_WS 0x14
3368 /* enum: XAUI Wireside Far. */
3369 #define          MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3370 /* enum: XAUI Wireside near. */
3371 #define          MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3372 /* enum: GMII Wireside. */
3373 #define          MC_CMD_LOOPBACK_GMII_WS 0x17
3374 /* enum: XFI Wireside. */
3375 #define          MC_CMD_LOOPBACK_XFI_WS 0x18
3376 /* enum: XFI Wireside Far. */
3377 #define          MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3378 /* enum: PhyXS Wireside. */
3379 #define          MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3380 /* enum: PMA lanes MAC-Serdes. */
3381 #define          MC_CMD_LOOPBACK_PMA_INT 0x1b
3382 /* enum: KR Serdes Parallel (Encoder). */
3383 #define          MC_CMD_LOOPBACK_SD_NEAR 0x1c
3384 /* enum: KR Serdes Serial. */
3385 #define          MC_CMD_LOOPBACK_SD_FAR 0x1d
3386 /* enum: PMA lanes MAC-Serdes Wireside. */
3387 #define          MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3388 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3389 #define          MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3390 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3391 #define          MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3392 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3393 #define          MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3394 /* enum: KR Serdes Serial Wireside. */
3395 #define          MC_CMD_LOOPBACK_SD_FES_WS 0x22
3396 /* enum: Near side of AOE Siena side port */
3397 #define          MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3398 /* enum: Medford Wireside datapath loopback */
3399 #define          MC_CMD_LOOPBACK_DATA_WS 0x24
3400 /* enum: Force link up without setting up any physical loopback (snapper use
3401  * only)
3402  */
3403 #define          MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
3404 /* Supported loopbacks. */
3405 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
3406 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
3407 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
3408 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
3409 /*            Enum values, see field(s): */
3410 /*               100M */
3411 /* Supported loopbacks. */
3412 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
3413 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
3414 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
3415 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
3416 /*            Enum values, see field(s): */
3417 /*               100M */
3418 /* Supported loopbacks. */
3419 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
3420 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
3421 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
3422 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
3423 /*            Enum values, see field(s): */
3424 /*               100M */
3425 /* Supported loopbacks. */
3426 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
3427 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
3428 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
3429 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
3430 /*            Enum values, see field(s): */
3431 /*               100M */
3432 
3433 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
3434  * newer NICs with 25G/50G/100G support
3435  */
3436 #define    MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
3437 /* Supported loopbacks. */
3438 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
3439 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
3440 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
3441 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
3442 /* enum: None. */
3443 /*               MC_CMD_LOOPBACK_NONE 0x0 */
3444 /* enum: Data. */
3445 /*               MC_CMD_LOOPBACK_DATA 0x1 */
3446 /* enum: GMAC. */
3447 /*               MC_CMD_LOOPBACK_GMAC 0x2 */
3448 /* enum: XGMII. */
3449 /*               MC_CMD_LOOPBACK_XGMII 0x3 */
3450 /* enum: XGXS. */
3451 /*               MC_CMD_LOOPBACK_XGXS 0x4 */
3452 /* enum: XAUI. */
3453 /*               MC_CMD_LOOPBACK_XAUI 0x5 */
3454 /* enum: GMII. */
3455 /*               MC_CMD_LOOPBACK_GMII 0x6 */
3456 /* enum: SGMII. */
3457 /*               MC_CMD_LOOPBACK_SGMII 0x7 */
3458 /* enum: XGBR. */
3459 /*               MC_CMD_LOOPBACK_XGBR 0x8 */
3460 /* enum: XFI. */
3461 /*               MC_CMD_LOOPBACK_XFI 0x9 */
3462 /* enum: XAUI Far. */
3463 /*               MC_CMD_LOOPBACK_XAUI_FAR 0xa */
3464 /* enum: GMII Far. */
3465 /*               MC_CMD_LOOPBACK_GMII_FAR 0xb */
3466 /* enum: SGMII Far. */
3467 /*               MC_CMD_LOOPBACK_SGMII_FAR 0xc */
3468 /* enum: XFI Far. */
3469 /*               MC_CMD_LOOPBACK_XFI_FAR 0xd */
3470 /* enum: GPhy. */
3471 /*               MC_CMD_LOOPBACK_GPHY 0xe */
3472 /* enum: PhyXS. */
3473 /*               MC_CMD_LOOPBACK_PHYXS 0xf */
3474 /* enum: PCS. */
3475 /*               MC_CMD_LOOPBACK_PCS 0x10 */
3476 /* enum: PMA-PMD. */
3477 /*               MC_CMD_LOOPBACK_PMAPMD 0x11 */
3478 /* enum: Cross-Port. */
3479 /*               MC_CMD_LOOPBACK_XPORT 0x12 */
3480 /* enum: XGMII-Wireside. */
3481 /*               MC_CMD_LOOPBACK_XGMII_WS 0x13 */
3482 /* enum: XAUI Wireside. */
3483 /*               MC_CMD_LOOPBACK_XAUI_WS 0x14 */
3484 /* enum: XAUI Wireside Far. */
3485 /*               MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
3486 /* enum: XAUI Wireside near. */
3487 /*               MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
3488 /* enum: GMII Wireside. */
3489 /*               MC_CMD_LOOPBACK_GMII_WS 0x17 */
3490 /* enum: XFI Wireside. */
3491 /*               MC_CMD_LOOPBACK_XFI_WS 0x18 */
3492 /* enum: XFI Wireside Far. */
3493 /*               MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
3494 /* enum: PhyXS Wireside. */
3495 /*               MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
3496 /* enum: PMA lanes MAC-Serdes. */
3497 /*               MC_CMD_LOOPBACK_PMA_INT 0x1b */
3498 /* enum: KR Serdes Parallel (Encoder). */
3499 /*               MC_CMD_LOOPBACK_SD_NEAR 0x1c */
3500 /* enum: KR Serdes Serial. */
3501 /*               MC_CMD_LOOPBACK_SD_FAR 0x1d */
3502 /* enum: PMA lanes MAC-Serdes Wireside. */
3503 /*               MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
3504 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3505 /*               MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
3506 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3507 /*               MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
3508 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3509 /*               MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
3510 /* enum: KR Serdes Serial Wireside. */
3511 /*               MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
3512 /* enum: Near side of AOE Siena side port */
3513 /*               MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
3514 /* enum: Medford Wireside datapath loopback */
3515 /*               MC_CMD_LOOPBACK_DATA_WS 0x24 */
3516 /* enum: Force link up without setting up any physical loopback (snapper use
3517  * only)
3518  */
3519 /*               MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
3520 /* Supported loopbacks. */
3521 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
3522 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
3523 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
3524 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
3525 /*            Enum values, see field(s): */
3526 /*               100M */
3527 /* Supported loopbacks. */
3528 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
3529 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
3530 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
3531 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
3532 /*            Enum values, see field(s): */
3533 /*               100M */
3534 /* Supported loopbacks. */
3535 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
3536 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
3537 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
3538 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
3539 /*            Enum values, see field(s): */
3540 /*               100M */
3541 /* Supported loopbacks. */
3542 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
3543 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
3544 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
3545 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
3546 /*            Enum values, see field(s): */
3547 /*               100M */
3548 /* Supported 25G loopbacks. */
3549 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
3550 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
3551 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
3552 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
3553 /*            Enum values, see field(s): */
3554 /*               100M */
3555 /* Supported 50 loopbacks. */
3556 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
3557 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
3558 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
3559 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
3560 /*            Enum values, see field(s): */
3561 /*               100M */
3562 /* Supported 100G loopbacks. */
3563 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
3564 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
3565 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
3566 #define       MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
3567 /*            Enum values, see field(s): */
3568 /*               100M */
3569 
3570 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
3571 #define    AN_TYPE_LEN 4
3572 #define       AN_TYPE_TYPE_OFST 0
3573 #define       AN_TYPE_TYPE_LEN 4
3574 /* enum: None, AN disabled or not supported */
3575 #define          MC_CMD_AN_NONE 0x0
3576 /* enum: Clause 28 - BASE-T */
3577 #define          MC_CMD_AN_CLAUSE28 0x1
3578 /* enum: Clause 37 - BASE-X */
3579 #define          MC_CMD_AN_CLAUSE37 0x2
3580 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
3581  * assemblies. Includes Clause 72/Clause 92 link-training.
3582  */
3583 #define          MC_CMD_AN_CLAUSE73 0x3
3584 #define       AN_TYPE_TYPE_LBN 0
3585 #define       AN_TYPE_TYPE_WIDTH 32
3586 
3587 /* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
3588  */
3589 #define    FEC_TYPE_LEN 4
3590 #define       FEC_TYPE_TYPE_OFST 0
3591 #define       FEC_TYPE_TYPE_LEN 4
3592 /* enum: No FEC */
3593 #define          MC_CMD_FEC_NONE 0x0
3594 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
3595 #define          MC_CMD_FEC_BASER 0x1
3596 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
3597 #define          MC_CMD_FEC_RS 0x2
3598 #define       FEC_TYPE_TYPE_LBN 0
3599 #define       FEC_TYPE_TYPE_WIDTH 32
3600 
3601 
3602 /***********************************/
3603 /* MC_CMD_GET_LINK
3604  * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
3605  * ETIME.
3606  */
3607 #define MC_CMD_GET_LINK 0x29
3608 
3609 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3610 
3611 /* MC_CMD_GET_LINK_IN msgrequest */
3612 #define    MC_CMD_GET_LINK_IN_LEN 0
3613 
3614 /* MC_CMD_GET_LINK_OUT msgresponse */
3615 #define    MC_CMD_GET_LINK_OUT_LEN 28
3616 /* Near-side advertised capabilities. Refer to
3617  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3618  */
3619 #define       MC_CMD_GET_LINK_OUT_CAP_OFST 0
3620 #define       MC_CMD_GET_LINK_OUT_CAP_LEN 4
3621 /* Link-partner advertised capabilities. Refer to
3622  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3623  */
3624 #define       MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
3625 #define       MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
3626 /* Autonegotiated speed in mbit/s. The link may still be down even if this
3627  * reads non-zero.
3628  */
3629 #define       MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
3630 #define       MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
3631 /* Current loopback setting. */
3632 #define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
3633 #define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
3634 /*            Enum values, see field(s): */
3635 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3636 #define       MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
3637 #define       MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
3638 #define        MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
3639 #define        MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
3640 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
3641 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
3642 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
3643 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
3644 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
3645 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
3646 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
3647 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
3648 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
3649 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
3650 /* This returns the negotiated flow control value. */
3651 #define       MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
3652 #define       MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
3653 /*            Enum values, see field(s): */
3654 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
3655 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
3656 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
3657 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
3658 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
3659 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
3660 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
3661 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
3662 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
3663 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
3664 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
3665 
3666 /* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
3667 #define    MC_CMD_GET_LINK_OUT_V2_LEN 44
3668 /* Near-side advertised capabilities. Refer to
3669  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3670  */
3671 #define       MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
3672 #define       MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
3673 /* Link-partner advertised capabilities. Refer to
3674  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3675  */
3676 #define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
3677 #define       MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
3678 /* Autonegotiated speed in mbit/s. The link may still be down even if this
3679  * reads non-zero.
3680  */
3681 #define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
3682 #define       MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
3683 /* Current loopback setting. */
3684 #define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
3685 #define       MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
3686 /*            Enum values, see field(s): */
3687 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3688 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
3689 #define       MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
3690 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
3691 #define        MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
3692 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
3693 #define        MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
3694 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
3695 #define        MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
3696 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
3697 #define        MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
3698 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
3699 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
3700 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
3701 #define        MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
3702 /* This returns the negotiated flow control value. */
3703 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
3704 #define       MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
3705 /*            Enum values, see field(s): */
3706 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
3707 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
3708 #define       MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
3709 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
3710 /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
3711 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
3712 /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
3713 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
3714 /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
3715 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
3716 /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
3717 /* True local device capabilities (taking into account currently used PMD/MDI,
3718  * e.g. plugged-in module). In general, subset of
3719  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
3720  * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
3721  * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
3722  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3723  */
3724 #define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
3725 #define       MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
3726 /* Auto-negotiation type used on the link */
3727 #define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
3728 #define       MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
3729 /*            Enum values, see field(s): */
3730 /*               AN_TYPE/TYPE */
3731 /* Forward error correction used on the link */
3732 #define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
3733 #define       MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
3734 /*            Enum values, see field(s): */
3735 /*               FEC_TYPE/TYPE */
3736 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
3737 #define       MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
3738 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
3739 #define        MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
3740 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
3741 #define        MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
3742 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
3743 #define        MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
3744 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
3745 #define        MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
3746 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
3747 #define        MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
3748 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
3749 #define        MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
3750 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
3751 #define        MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
3752 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
3753 #define        MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
3754 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
3755 #define        MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
3756 
3757 
3758 /***********************************/
3759 /* MC_CMD_SET_LINK
3760  * Write the unified MAC/PHY link configuration. Locks required: None. Return
3761  * code: 0, EINVAL, ETIME
3762  */
3763 #define MC_CMD_SET_LINK 0x2a
3764 
3765 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
3766 
3767 /* MC_CMD_SET_LINK_IN msgrequest */
3768 #define    MC_CMD_SET_LINK_IN_LEN 16
3769 /* Near-side advertised capabilities. Refer to
3770  * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
3771  */
3772 #define       MC_CMD_SET_LINK_IN_CAP_OFST 0
3773 #define       MC_CMD_SET_LINK_IN_CAP_LEN 4
3774 /* Flags */
3775 #define       MC_CMD_SET_LINK_IN_FLAGS_OFST 4
3776 #define       MC_CMD_SET_LINK_IN_FLAGS_LEN 4
3777 #define        MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
3778 #define        MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
3779 #define        MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
3780 #define        MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
3781 #define        MC_CMD_SET_LINK_IN_TXDIS_LBN 2
3782 #define        MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
3783 /* Loopback mode. */
3784 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
3785 #define       MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
3786 /*            Enum values, see field(s): */
3787 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3788 /* A loopback speed of "0" is supported, and means (choose any available
3789  * speed).
3790  */
3791 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
3792 #define       MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
3793 
3794 /* MC_CMD_SET_LINK_OUT msgresponse */
3795 #define    MC_CMD_SET_LINK_OUT_LEN 0
3796 
3797 
3798 /***********************************/
3799 /* MC_CMD_SET_ID_LED
3800  * Set identification LED state. Locks required: None. Return code: 0, EINVAL
3801  */
3802 #define MC_CMD_SET_ID_LED 0x2b
3803 
3804 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
3805 
3806 /* MC_CMD_SET_ID_LED_IN msgrequest */
3807 #define    MC_CMD_SET_ID_LED_IN_LEN 4
3808 /* Set LED state. */
3809 #define       MC_CMD_SET_ID_LED_IN_STATE_OFST 0
3810 #define       MC_CMD_SET_ID_LED_IN_STATE_LEN 4
3811 #define          MC_CMD_LED_OFF 0x0 /* enum */
3812 #define          MC_CMD_LED_ON 0x1 /* enum */
3813 #define          MC_CMD_LED_DEFAULT 0x2 /* enum */
3814 
3815 /* MC_CMD_SET_ID_LED_OUT msgresponse */
3816 #define    MC_CMD_SET_ID_LED_OUT_LEN 0
3817 
3818 
3819 /***********************************/
3820 /* MC_CMD_SET_MAC
3821  * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
3822  */
3823 #define MC_CMD_SET_MAC 0x2c
3824 
3825 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3826 
3827 /* MC_CMD_SET_MAC_IN msgrequest */
3828 #define    MC_CMD_SET_MAC_IN_LEN 28
3829 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3830  * EtherII, VLAN, bug16011 padding).
3831  */
3832 #define       MC_CMD_SET_MAC_IN_MTU_OFST 0
3833 #define       MC_CMD_SET_MAC_IN_MTU_LEN 4
3834 #define       MC_CMD_SET_MAC_IN_DRAIN_OFST 4
3835 #define       MC_CMD_SET_MAC_IN_DRAIN_LEN 4
3836 #define       MC_CMD_SET_MAC_IN_ADDR_OFST 8
3837 #define       MC_CMD_SET_MAC_IN_ADDR_LEN 8
3838 #define       MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
3839 #define       MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
3840 #define       MC_CMD_SET_MAC_IN_REJECT_OFST 16
3841 #define       MC_CMD_SET_MAC_IN_REJECT_LEN 4
3842 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
3843 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
3844 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
3845 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
3846 #define       MC_CMD_SET_MAC_IN_FCNTL_OFST 20
3847 #define       MC_CMD_SET_MAC_IN_FCNTL_LEN 4
3848 /* enum: Flow control is off. */
3849 #define          MC_CMD_FCNTL_OFF 0x0
3850 /* enum: Respond to flow control. */
3851 #define          MC_CMD_FCNTL_RESPOND 0x1
3852 /* enum: Respond to and Issue flow control. */
3853 #define          MC_CMD_FCNTL_BIDIR 0x2
3854 /* enum: Auto neg flow control. */
3855 #define          MC_CMD_FCNTL_AUTO 0x3
3856 /* enum: Priority flow control (eftest builds only). */
3857 #define          MC_CMD_FCNTL_QBB 0x4
3858 /* enum: Issue flow control. */
3859 #define          MC_CMD_FCNTL_GENERATE 0x5
3860 #define       MC_CMD_SET_MAC_IN_FLAGS_OFST 24
3861 #define       MC_CMD_SET_MAC_IN_FLAGS_LEN 4
3862 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
3863 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
3864 
3865 /* MC_CMD_SET_MAC_EXT_IN msgrequest */
3866 #define    MC_CMD_SET_MAC_EXT_IN_LEN 32
3867 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3868  * EtherII, VLAN, bug16011 padding).
3869  */
3870 #define       MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
3871 #define       MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
3872 #define       MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
3873 #define       MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
3874 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
3875 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
3876 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
3877 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
3878 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
3879 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
3880 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
3881 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
3882 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
3883 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
3884 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
3885 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
3886 /* enum: Flow control is off. */
3887 /*               MC_CMD_FCNTL_OFF 0x0 */
3888 /* enum: Respond to flow control. */
3889 /*               MC_CMD_FCNTL_RESPOND 0x1 */
3890 /* enum: Respond to and Issue flow control. */
3891 /*               MC_CMD_FCNTL_BIDIR 0x2 */
3892 /* enum: Auto neg flow control. */
3893 /*               MC_CMD_FCNTL_AUTO 0x3 */
3894 /* enum: Priority flow control (eftest builds only). */
3895 /*               MC_CMD_FCNTL_QBB 0x4 */
3896 /* enum: Issue flow control. */
3897 /*               MC_CMD_FCNTL_GENERATE 0x5 */
3898 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
3899 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
3900 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
3901 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
3902 /* Select which parameters to configure. A parameter will only be modified if
3903  * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
3904  * capabilities then this field is ignored (and all flags are assumed to be
3905  * set).
3906  */
3907 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
3908 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
3909 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
3910 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
3911 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
3912 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
3913 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
3914 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
3915 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
3916 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
3917 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
3918 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
3919 
3920 /* MC_CMD_SET_MAC_OUT msgresponse */
3921 #define    MC_CMD_SET_MAC_OUT_LEN 0
3922 
3923 /* MC_CMD_SET_MAC_V2_OUT msgresponse */
3924 #define    MC_CMD_SET_MAC_V2_OUT_LEN 4
3925 /* MTU as configured after processing the request. See comment at
3926  * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
3927  * to 0.
3928  */
3929 #define       MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
3930 #define       MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
3931 
3932 
3933 /***********************************/
3934 /* MC_CMD_PHY_STATS
3935  * Get generic PHY statistics. This call returns the statistics for a generic
3936  * PHY in a sparse array (indexed by the enumerate). Each value is represented
3937  * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
3938  * statistics may be read from the message response. If DMA_ADDR != 0, then the
3939  * statistics are dmad to that (page-aligned location). Locks required: None.
3940  * Returns: 0, ETIME
3941  */
3942 #define MC_CMD_PHY_STATS 0x2d
3943 
3944 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
3945 
3946 /* MC_CMD_PHY_STATS_IN msgrequest */
3947 #define    MC_CMD_PHY_STATS_IN_LEN 8
3948 /* ??? */
3949 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
3950 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
3951 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
3952 #define       MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
3953 
3954 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
3955 #define    MC_CMD_PHY_STATS_OUT_DMA_LEN 0
3956 
3957 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
3958 #define    MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
3959 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3960 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
3961 #define       MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
3962 /* enum: OUI. */
3963 #define          MC_CMD_OUI 0x0
3964 /* enum: PMA-PMD Link Up. */
3965 #define          MC_CMD_PMA_PMD_LINK_UP 0x1
3966 /* enum: PMA-PMD RX Fault. */
3967 #define          MC_CMD_PMA_PMD_RX_FAULT 0x2
3968 /* enum: PMA-PMD TX Fault. */
3969 #define          MC_CMD_PMA_PMD_TX_FAULT 0x3
3970 /* enum: PMA-PMD Signal */
3971 #define          MC_CMD_PMA_PMD_SIGNAL 0x4
3972 /* enum: PMA-PMD SNR A. */
3973 #define          MC_CMD_PMA_PMD_SNR_A 0x5
3974 /* enum: PMA-PMD SNR B. */
3975 #define          MC_CMD_PMA_PMD_SNR_B 0x6
3976 /* enum: PMA-PMD SNR C. */
3977 #define          MC_CMD_PMA_PMD_SNR_C 0x7
3978 /* enum: PMA-PMD SNR D. */
3979 #define          MC_CMD_PMA_PMD_SNR_D 0x8
3980 /* enum: PCS Link Up. */
3981 #define          MC_CMD_PCS_LINK_UP 0x9
3982 /* enum: PCS RX Fault. */
3983 #define          MC_CMD_PCS_RX_FAULT 0xa
3984 /* enum: PCS TX Fault. */
3985 #define          MC_CMD_PCS_TX_FAULT 0xb
3986 /* enum: PCS BER. */
3987 #define          MC_CMD_PCS_BER 0xc
3988 /* enum: PCS Block Errors. */
3989 #define          MC_CMD_PCS_BLOCK_ERRORS 0xd
3990 /* enum: PhyXS Link Up. */
3991 #define          MC_CMD_PHYXS_LINK_UP 0xe
3992 /* enum: PhyXS RX Fault. */
3993 #define          MC_CMD_PHYXS_RX_FAULT 0xf
3994 /* enum: PhyXS TX Fault. */
3995 #define          MC_CMD_PHYXS_TX_FAULT 0x10
3996 /* enum: PhyXS Align. */
3997 #define          MC_CMD_PHYXS_ALIGN 0x11
3998 /* enum: PhyXS Sync. */
3999 #define          MC_CMD_PHYXS_SYNC 0x12
4000 /* enum: AN link-up. */
4001 #define          MC_CMD_AN_LINK_UP 0x13
4002 /* enum: AN Complete. */
4003 #define          MC_CMD_AN_COMPLETE 0x14
4004 /* enum: AN 10GBaseT Status. */
4005 #define          MC_CMD_AN_10GBT_STATUS 0x15
4006 /* enum: Clause 22 Link-Up. */
4007 #define          MC_CMD_CL22_LINK_UP 0x16
4008 /* enum: (Last entry) */
4009 #define          MC_CMD_PHY_NSTATS 0x17
4010 
4011 
4012 /***********************************/
4013 /* MC_CMD_MAC_STATS
4014  * Get generic MAC statistics. This call returns unified statistics maintained
4015  * by the MC as it switches between the GMAC and XMAC. The MC will write out
4016  * all supported stats. The driver should zero initialise the buffer to
4017  * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
4018  * performed, and the statistics may be read from the message response. If
4019  * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4020  * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
4021  * effect. Returns: 0, ETIME
4022  */
4023 #define MC_CMD_MAC_STATS 0x2e
4024 
4025 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4026 
4027 /* MC_CMD_MAC_STATS_IN msgrequest */
4028 #define    MC_CMD_MAC_STATS_IN_LEN 20
4029 /* ??? */
4030 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
4031 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
4032 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
4033 #define       MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
4034 #define       MC_CMD_MAC_STATS_IN_CMD_OFST 8
4035 #define       MC_CMD_MAC_STATS_IN_CMD_LEN 4
4036 #define        MC_CMD_MAC_STATS_IN_DMA_LBN 0
4037 #define        MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
4038 #define        MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
4039 #define        MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
4040 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
4041 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
4042 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
4043 #define        MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
4044 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
4045 #define        MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
4046 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
4047 #define        MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
4048 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
4049 #define        MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
4050 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
4051  * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
4052  * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
4053  * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
4054  */
4055 #define       MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
4056 #define       MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
4057 /* port id so vadapter stats can be provided */
4058 #define       MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
4059 #define       MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
4060 
4061 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
4062 #define    MC_CMD_MAC_STATS_OUT_DMA_LEN 0
4063 
4064 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
4065 #define    MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
4066 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4067 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
4068 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
4069 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
4070 #define       MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
4071 #define          MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4072 #define          MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4073 #define          MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4074 #define          MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4075 #define          MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4076 #define          MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4077 #define          MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4078 #define          MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4079 #define          MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4080 #define          MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4081 #define          MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4082 #define          MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4083 #define          MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4084 #define          MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4085 #define          MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4086 #define          MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4087 #define          MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4088 #define          MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4089 #define          MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4090 #define          MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4091 #define          MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4092 #define          MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4093 #define          MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4094 #define          MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4095 #define          MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4096 #define          MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4097 #define          MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4098 #define          MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4099 #define          MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4100 #define          MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4101 #define          MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4102 #define          MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4103 #define          MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4104 #define          MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4105 #define          MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4106 #define          MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4107 #define          MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4108 #define          MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4109 #define          MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4110 #define          MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4111 #define          MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4112 #define          MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4113 #define          MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4114 #define          MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4115 #define          MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4116 #define          MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4117 #define          MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4118 #define          MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4119 #define          MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4120 #define          MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4121 #define          MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4122 #define          MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4123 #define          MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4124 #define          MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4125 #define          MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4126 #define          MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4127 #define          MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4128 #define          MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4129 #define          MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4130 #define          MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4131 #define          MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4132 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4133  * capability only.
4134  */
4135 #define          MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4136 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
4137  * PM_AND_RXDP_COUNTERS capability only.
4138  */
4139 #define          MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4140 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4141  * capability only.
4142  */
4143 #define          MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4144 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
4145  * PM_AND_RXDP_COUNTERS capability only.
4146  */
4147 #define          MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4148 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4149  * capability only.
4150  */
4151 #define          MC_CMD_MAC_PM_TRUNC_QBB 0x40
4152 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4153  * capability only.
4154  */
4155 #define          MC_CMD_MAC_PM_DISCARD_QBB 0x41
4156 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4157  * capability only.
4158  */
4159 #define          MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4160 /* enum: RXDP counter: Number of packets dropped due to the queue being
4161  * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4162  */
4163 #define          MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4164 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
4165  * with PM_AND_RXDP_COUNTERS capability only.
4166  */
4167 #define          MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4168 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4169  * PM_AND_RXDP_COUNTERS capability only.
4170  */
4171 #define          MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4172 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
4173  * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4174  */
4175 #define          MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4176 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
4177  * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4178  */
4179 #define          MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4180 #define          MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4181 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4182 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4183 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4184 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4185 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4186 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4187 #define          MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4188 #define          MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4189 #define          MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4190 #define          MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4191 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4192 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4193 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4194 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4195 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4196 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4197 #define          MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4198 #define          MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4199 #define          MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4200 /* enum: Start of GMAC stats buffer space, for Siena only. */
4201 #define          MC_CMD_GMAC_DMABUF_START 0x40
4202 /* enum: End of GMAC stats buffer space, for Siena only. */
4203 #define          MC_CMD_GMAC_DMABUF_END 0x5f
4204 /* enum: GENERATION_END value, used together with GENERATION_START to verify
4205  * consistency of DMAd data. For legacy firmware / drivers without extended
4206  * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
4207  * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
4208  * this value is invalid/ reserved and GENERATION_END is written as the last
4209  * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4210  * this is consistent with the legacy behaviour, in the sense that entry 96 is
4211  * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4212  * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4213  */
4214 #define          MC_CMD_MAC_GENERATION_END 0x60
4215 #define          MC_CMD_MAC_NSTATS 0x61 /* enum */
4216 
4217 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
4218 #define    MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4219 
4220 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
4221 #define    MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
4222 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4223 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
4224 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4225 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4226 #define       MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
4227 /* enum: Start of FEC stats buffer space, Medford2 and up */
4228 #define          MC_CMD_MAC_FEC_DMABUF_START 0x61
4229 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4230  */
4231 #define          MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4232 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4233  */
4234 #define          MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4235 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4236 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4237 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4238 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4239 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4240 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4241 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4242 #define          MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4243 /* enum: This includes the space at offset 103 which is the final
4244  * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
4245  */
4246 #define          MC_CMD_MAC_NSTATS_V2 0x68
4247 /*            Other enum values, see field(s): */
4248 /*               MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
4249 
4250 /* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
4251 #define    MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
4252 
4253 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
4254 #define    MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
4255 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
4256 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
4257 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
4258 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
4259 #define       MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
4260 /* enum: Start of CTPIO stats buffer space, Medford2 and up */
4261 #define          MC_CMD_MAC_CTPIO_DMABUF_START 0x68
4262 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
4263  * target VI
4264  */
4265 #define          MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
4266 /* enum: Number of times a CTPIO send wrote beyond frame end (informational
4267  * only)
4268  */
4269 #define          MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
4270 /* enum: Number of CTPIO failures because the TX doorbell was written before
4271  * the end of the frame data
4272  */
4273 #define          MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
4274 /* enum: Number of CTPIO failures because the internal FIFO overflowed */
4275 #define          MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
4276 /* enum: Number of CTPIO failures because the host did not deliver data fast
4277  * enough to avoid MAC underflow
4278  */
4279 #define          MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
4280 /* enum: Number of CTPIO failures because the host did not deliver all the
4281  * frame data within the timeout
4282  */
4283 #define          MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
4284 /* enum: Number of CTPIO failures because the frame data arrived out of order
4285  * or with gaps
4286  */
4287 #define          MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
4288 /* enum: Number of CTPIO failures because the host started a new frame before
4289  * completing the previous one
4290  */
4291 #define          MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
4292 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
4293  * or not 32-bit aligned
4294  */
4295 #define          MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
4296 /* enum: Number of CTPIO fallbacks because another VI on the same port was
4297  * sending a CTPIO frame
4298  */
4299 #define          MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
4300 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
4301  */
4302 #define          MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
4303 /* enum: Number of CTPIO fallbacks because length in header was less than 29
4304  * bytes
4305  */
4306 #define          MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
4307 /* enum: Total number of successful CTPIO sends on this port */
4308 #define          MC_CMD_MAC_CTPIO_SUCCESS 0x74
4309 /* enum: Total number of CTPIO fallbacks on this port */
4310 #define          MC_CMD_MAC_CTPIO_FALLBACK 0x75
4311 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or
4312  * not
4313  */
4314 #define          MC_CMD_MAC_CTPIO_POISON 0x76
4315 /* enum: Total number of CTPIO erased frames on this port */
4316 #define          MC_CMD_MAC_CTPIO_ERASE 0x77
4317 /* enum: This includes the space at offset 120 which is the final
4318  * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
4319  */
4320 #define          MC_CMD_MAC_NSTATS_V3 0x79
4321 /*            Other enum values, see field(s): */
4322 /*               MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
4323 
4324 
4325 /***********************************/
4326 /* MC_CMD_SRIOV
4327  * to be documented
4328  */
4329 #define MC_CMD_SRIOV 0x30
4330 
4331 /* MC_CMD_SRIOV_IN msgrequest */
4332 #define    MC_CMD_SRIOV_IN_LEN 12
4333 #define       MC_CMD_SRIOV_IN_ENABLE_OFST 0
4334 #define       MC_CMD_SRIOV_IN_ENABLE_LEN 4
4335 #define       MC_CMD_SRIOV_IN_VI_BASE_OFST 4
4336 #define       MC_CMD_SRIOV_IN_VI_BASE_LEN 4
4337 #define       MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
4338 #define       MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
4339 
4340 /* MC_CMD_SRIOV_OUT msgresponse */
4341 #define    MC_CMD_SRIOV_OUT_LEN 8
4342 #define       MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
4343 #define       MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
4344 #define       MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
4345 #define       MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
4346 
4347 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
4348 #define    MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
4349 /* this is only used for the first record */
4350 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
4351 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
4352 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
4353 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
4354 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
4355 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
4356 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
4357 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
4358 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
4359 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
4360 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
4361 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
4362 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
4363 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
4364 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
4365 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
4366 #define          MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
4367 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
4368 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
4369 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
4370 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
4371 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
4372 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
4373 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
4374 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
4375 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
4376 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
4377 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
4378 #define       MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
4379 
4380 
4381 /***********************************/
4382 /* MC_CMD_MEMCPY
4383  * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
4384  * embedded directly in the command.
4385  *
4386  * A common pattern is for a client to use generation counts to signal a dma
4387  * update of a datastructure. To facilitate this, this MCDI operation can
4388  * contain multiple requests which are executed in strict order. Requests take
4389  * the form of duplicating the entire MCDI request continuously (including the
4390  * requests record, which is ignored in all but the first structure)
4391  *
4392  * The source data can either come from a DMA from the host, or it can be
4393  * embedded within the request directly, thereby eliminating a DMA read. To
4394  * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
4395  * ADDR_LO=offset, and inserts the data at %offset from the start of the
4396  * payload. It's the callers responsibility to ensure that the embedded data
4397  * doesn't overlap the records.
4398  *
4399  * Returns: 0, EINVAL (invalid RID)
4400  */
4401 #define MC_CMD_MEMCPY 0x31
4402 
4403 /* MC_CMD_MEMCPY_IN msgrequest */
4404 #define    MC_CMD_MEMCPY_IN_LENMIN 32
4405 #define    MC_CMD_MEMCPY_IN_LENMAX 224
4406 #define    MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
4407 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
4408 #define       MC_CMD_MEMCPY_IN_RECORD_OFST 0
4409 #define       MC_CMD_MEMCPY_IN_RECORD_LEN 32
4410 #define       MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
4411 #define       MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
4412 
4413 /* MC_CMD_MEMCPY_OUT msgresponse */
4414 #define    MC_CMD_MEMCPY_OUT_LEN 0
4415 
4416 
4417 /***********************************/
4418 /* MC_CMD_WOL_FILTER_SET
4419  * Set a WoL filter.
4420  */
4421 #define MC_CMD_WOL_FILTER_SET 0x32
4422 
4423 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
4424 
4425 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
4426 #define    MC_CMD_WOL_FILTER_SET_IN_LEN 192
4427 #define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
4428 #define       MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
4429 #define          MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
4430 #define          MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
4431 /* A type value of 1 is unused. */
4432 #define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
4433 #define       MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
4434 /* enum: Magic */
4435 #define          MC_CMD_WOL_TYPE_MAGIC 0x0
4436 /* enum: MS Windows Magic */
4437 #define          MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
4438 /* enum: IPv4 Syn */
4439 #define          MC_CMD_WOL_TYPE_IPV4_SYN 0x3
4440 /* enum: IPv6 Syn */
4441 #define          MC_CMD_WOL_TYPE_IPV6_SYN 0x4
4442 /* enum: Bitmap */
4443 #define          MC_CMD_WOL_TYPE_BITMAP 0x5
4444 /* enum: Link */
4445 #define          MC_CMD_WOL_TYPE_LINK 0x6
4446 /* enum: (Above this for future use) */
4447 #define          MC_CMD_WOL_TYPE_MAX 0x7
4448 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
4449 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
4450 #define       MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
4451 
4452 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
4453 #define    MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
4454 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4455 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4456 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4457 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4458 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
4459 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
4460 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
4461 #define       MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
4462 
4463 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
4464 #define    MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
4465 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4466 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4467 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4468 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4469 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
4470 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
4471 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
4472 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
4473 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
4474 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
4475 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
4476 #define       MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
4477 
4478 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
4479 #define    MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
4480 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4481 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4482 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4483 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4484 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
4485 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
4486 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
4487 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
4488 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
4489 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
4490 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
4491 #define       MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
4492 
4493 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
4494 #define    MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
4495 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4496 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4497 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4498 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4499 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
4500 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
4501 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
4502 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
4503 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
4504 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
4505 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
4506 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
4507 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
4508 #define       MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
4509 
4510 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
4511 #define    MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
4512 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4513 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4514 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4515 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4516 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
4517 #define       MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
4518 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
4519 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
4520 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
4521 #define        MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
4522 
4523 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
4524 #define    MC_CMD_WOL_FILTER_SET_OUT_LEN 4
4525 #define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
4526 #define       MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
4527 
4528 
4529 /***********************************/
4530 /* MC_CMD_WOL_FILTER_REMOVE
4531  * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
4532  */
4533 #define MC_CMD_WOL_FILTER_REMOVE 0x33
4534 
4535 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
4536 
4537 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
4538 #define    MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
4539 #define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
4540 #define       MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
4541 
4542 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
4543 #define    MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
4544 
4545 
4546 /***********************************/
4547 /* MC_CMD_WOL_FILTER_RESET
4548  * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
4549  * ENOSYS
4550  */
4551 #define MC_CMD_WOL_FILTER_RESET 0x34
4552 
4553 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
4554 
4555 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
4556 #define    MC_CMD_WOL_FILTER_RESET_IN_LEN 4
4557 #define       MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
4558 #define       MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
4559 #define          MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
4560 #define          MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
4561 
4562 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
4563 #define    MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
4564 
4565 
4566 /***********************************/
4567 /* MC_CMD_SET_MCAST_HASH
4568  * Set the MCAST hash value without otherwise reconfiguring the MAC
4569  */
4570 #define MC_CMD_SET_MCAST_HASH 0x35
4571 
4572 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
4573 #define    MC_CMD_SET_MCAST_HASH_IN_LEN 32
4574 #define       MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
4575 #define       MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
4576 #define       MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
4577 #define       MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
4578 
4579 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
4580 #define    MC_CMD_SET_MCAST_HASH_OUT_LEN 0
4581 
4582 
4583 /***********************************/
4584 /* MC_CMD_NVRAM_TYPES
4585  * Return bitfield indicating available types of virtual NVRAM partitions.
4586  * Locks required: none. Returns: 0
4587  */
4588 #define MC_CMD_NVRAM_TYPES 0x36
4589 
4590 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4591 
4592 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
4593 #define    MC_CMD_NVRAM_TYPES_IN_LEN 0
4594 
4595 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
4596 #define    MC_CMD_NVRAM_TYPES_OUT_LEN 4
4597 /* Bit mask of supported types. */
4598 #define       MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
4599 #define       MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
4600 /* enum: Disabled callisto. */
4601 #define          MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
4602 /* enum: MC firmware. */
4603 #define          MC_CMD_NVRAM_TYPE_MC_FW 0x1
4604 /* enum: MC backup firmware. */
4605 #define          MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
4606 /* enum: Static configuration Port0. */
4607 #define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
4608 /* enum: Static configuration Port1. */
4609 #define          MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
4610 /* enum: Dynamic configuration Port0. */
4611 #define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
4612 /* enum: Dynamic configuration Port1. */
4613 #define          MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
4614 /* enum: Expansion Rom. */
4615 #define          MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
4616 /* enum: Expansion Rom Configuration Port0. */
4617 #define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
4618 /* enum: Expansion Rom Configuration Port1. */
4619 #define          MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
4620 /* enum: Phy Configuration Port0. */
4621 #define          MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
4622 /* enum: Phy Configuration Port1. */
4623 #define          MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
4624 /* enum: Log. */
4625 #define          MC_CMD_NVRAM_TYPE_LOG 0xc
4626 /* enum: FPGA image. */
4627 #define          MC_CMD_NVRAM_TYPE_FPGA 0xd
4628 /* enum: FPGA backup image */
4629 #define          MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
4630 /* enum: FC firmware. */
4631 #define          MC_CMD_NVRAM_TYPE_FC_FW 0xf
4632 /* enum: FC backup firmware. */
4633 #define          MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
4634 /* enum: CPLD image. */
4635 #define          MC_CMD_NVRAM_TYPE_CPLD 0x11
4636 /* enum: Licensing information. */
4637 #define          MC_CMD_NVRAM_TYPE_LICENSE 0x12
4638 /* enum: FC Log. */
4639 #define          MC_CMD_NVRAM_TYPE_FC_LOG 0x13
4640 /* enum: Additional flash on FPGA. */
4641 #define          MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
4642 
4643 
4644 /***********************************/
4645 /* MC_CMD_NVRAM_INFO
4646  * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
4647  * EINVAL (bad type).
4648  */
4649 #define MC_CMD_NVRAM_INFO 0x37
4650 
4651 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4652 
4653 /* MC_CMD_NVRAM_INFO_IN msgrequest */
4654 #define    MC_CMD_NVRAM_INFO_IN_LEN 4
4655 #define       MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
4656 #define       MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
4657 /*            Enum values, see field(s): */
4658 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4659 
4660 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
4661 #define    MC_CMD_NVRAM_INFO_OUT_LEN 24
4662 #define       MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
4663 #define       MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
4664 /*            Enum values, see field(s): */
4665 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4666 #define       MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
4667 #define       MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
4668 #define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
4669 #define       MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
4670 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
4671 #define       MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
4672 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
4673 #define        MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
4674 #define        MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
4675 #define        MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
4676 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
4677 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
4678 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
4679 #define        MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
4680 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
4681 #define        MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
4682 #define        MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
4683 #define        MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
4684 #define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
4685 #define       MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
4686 #define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
4687 #define       MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
4688 
4689 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
4690 #define    MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
4691 #define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
4692 #define       MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
4693 /*            Enum values, see field(s): */
4694 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4695 #define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
4696 #define       MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
4697 #define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
4698 #define       MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
4699 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
4700 #define       MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
4701 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
4702 #define        MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
4703 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
4704 #define        MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
4705 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
4706 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
4707 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
4708 #define        MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
4709 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
4710 #define        MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
4711 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
4712 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
4713 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
4714 #define       MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
4715 /* Writes must be multiples of this size. Added to support the MUM on Sorrento.
4716  */
4717 #define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
4718 #define       MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
4719 
4720 
4721 /***********************************/
4722 /* MC_CMD_NVRAM_UPDATE_START
4723  * Start a group of update operations on a virtual NVRAM partition. Locks
4724  * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
4725  * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
4726  * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
4727  * i.e. static config, dynamic config and expansion ROM config. Attempting to
4728  * perform this operation on a restricted partition will return the error
4729  * EPERM.
4730  */
4731 #define MC_CMD_NVRAM_UPDATE_START 0x38
4732 
4733 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4734 
4735 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
4736  * Use NVRAM_UPDATE_START_V2_IN in new code
4737  */
4738 #define    MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
4739 #define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
4740 #define       MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
4741 /*            Enum values, see field(s): */
4742 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4743 
4744 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
4745  * request with additional flags indicating version of command in use. See
4746  * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
4747  * paired up with NVRAM_UPDATE_FINISH_V2_IN.
4748  */
4749 #define    MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
4750 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
4751 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
4752 /*            Enum values, see field(s): */
4753 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4754 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
4755 #define       MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
4756 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4757 #define        MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4758 
4759 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
4760 #define    MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
4761 
4762 
4763 /***********************************/
4764 /* MC_CMD_NVRAM_READ
4765  * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
4766  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4767  * PHY_LOCK required and not held)
4768  */
4769 #define MC_CMD_NVRAM_READ 0x39
4770 
4771 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4772 
4773 /* MC_CMD_NVRAM_READ_IN msgrequest */
4774 #define    MC_CMD_NVRAM_READ_IN_LEN 12
4775 #define       MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
4776 #define       MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
4777 /*            Enum values, see field(s): */
4778 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4779 #define       MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
4780 #define       MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
4781 /* amount to read in bytes */
4782 #define       MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
4783 #define       MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
4784 
4785 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
4786 #define    MC_CMD_NVRAM_READ_IN_V2_LEN 16
4787 #define       MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
4788 #define       MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
4789 /*            Enum values, see field(s): */
4790 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4791 #define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
4792 #define       MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
4793 /* amount to read in bytes */
4794 #define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
4795 #define       MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
4796 /* Optional control info. If a partition is stored with an A/B versioning
4797  * scheme (i.e. in more than one physical partition in NVRAM) the host can set
4798  * this to control which underlying physical partition is used to read data
4799  * from. This allows it to perform a read-modify-write-verify with the write
4800  * lock continuously held by calling NVRAM_UPDATE_START, reading the old
4801  * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
4802  * verifying by reading with MODE=TARGET_BACKUP.
4803  */
4804 #define       MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
4805 #define       MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
4806 /* enum: Same as omitting MODE: caller sees data in current partition unless it
4807  * holds the write lock in which case it sees data in the partition it is
4808  * updating.
4809  */
4810 #define          MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
4811 /* enum: Read from the current partition of an A/B pair, even if holding the
4812  * write lock.
4813  */
4814 #define          MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
4815 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
4816  * pair
4817  */
4818 #define          MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
4819 
4820 /* MC_CMD_NVRAM_READ_OUT msgresponse */
4821 #define    MC_CMD_NVRAM_READ_OUT_LENMIN 1
4822 #define    MC_CMD_NVRAM_READ_OUT_LENMAX 252
4823 #define    MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
4824 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
4825 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
4826 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
4827 #define       MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
4828 
4829 
4830 /***********************************/
4831 /* MC_CMD_NVRAM_WRITE
4832  * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
4833  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4834  * PHY_LOCK required and not held)
4835  */
4836 #define MC_CMD_NVRAM_WRITE 0x3a
4837 
4838 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4839 
4840 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
4841 #define    MC_CMD_NVRAM_WRITE_IN_LENMIN 13
4842 #define    MC_CMD_NVRAM_WRITE_IN_LENMAX 252
4843 #define    MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
4844 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
4845 #define       MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
4846 /*            Enum values, see field(s): */
4847 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4848 #define       MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
4849 #define       MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
4850 #define       MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
4851 #define       MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
4852 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
4853 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
4854 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
4855 #define       MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
4856 
4857 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
4858 #define    MC_CMD_NVRAM_WRITE_OUT_LEN 0
4859 
4860 
4861 /***********************************/
4862 /* MC_CMD_NVRAM_ERASE
4863  * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
4864  * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4865  * PHY_LOCK required and not held)
4866  */
4867 #define MC_CMD_NVRAM_ERASE 0x3b
4868 
4869 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4870 
4871 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
4872 #define    MC_CMD_NVRAM_ERASE_IN_LEN 12
4873 #define       MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
4874 #define       MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
4875 /*            Enum values, see field(s): */
4876 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4877 #define       MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
4878 #define       MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
4879 #define       MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
4880 #define       MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
4881 
4882 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
4883 #define    MC_CMD_NVRAM_ERASE_OUT_LEN 0
4884 
4885 
4886 /***********************************/
4887 /* MC_CMD_NVRAM_UPDATE_FINISH
4888  * Finish a group of update operations on a virtual NVRAM partition. Locks
4889  * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
4890  * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
4891  * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
4892  * partition types i.e. static config, dynamic config and expansion ROM config.
4893  * Attempting to perform this operation on a restricted partition will return
4894  * the error EPERM.
4895  */
4896 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
4897 
4898 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4899 
4900 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
4901  * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
4902  */
4903 #define    MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
4904 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
4905 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
4906 /*            Enum values, see field(s): */
4907 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4908 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
4909 #define       MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
4910 
4911 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
4912  * request with additional flags indicating version of NVRAM_UPDATE commands in
4913  * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
4914  * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
4915  */
4916 #define    MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
4917 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
4918 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
4919 /*            Enum values, see field(s): */
4920 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4921 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
4922 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
4923 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
4924 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
4925 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4926 #define        MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4927 
4928 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
4929  * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
4930  */
4931 #define    MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
4932 
4933 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
4934  *
4935  * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
4936  * firmware validation where applicable back to the host.
4937  *
4938  * Medford only: For signed firmware images, such as those for medford, the MC
4939  * firmware verifies the signature before marking the firmware image as valid.
4940  * This process takes a few seconds to complete. So is likely to take more than
4941  * the MCDI timeout. Hence signature verification is initiated when
4942  * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
4943  * MCDI command is run in a background MCDI processing thread. This response
4944  * payload includes the results of the signature verification. Note that the
4945  * per-partition nvram lock in firmware is only released after the verification
4946  * has completed.
4947  */
4948 #define    MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
4949 /* Result of nvram update completion processing */
4950 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
4951 #define       MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
4952 /* enum: Invalid return code; only non-zero values are defined. Defined as
4953  * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
4954  */
4955 #define          MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
4956 /* enum: Verify succeeded without any errors. */
4957 #define          MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
4958 /* enum: CMS format verification failed due to an internal error. */
4959 #define          MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
4960 /* enum: Invalid CMS format in image metadata. */
4961 #define          MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
4962 /* enum: Message digest verification failed due to an internal error. */
4963 #define          MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
4964 /* enum: Error in message digest calculated over the reflash-header, payload
4965  * and reflash-trailer.
4966  */
4967 #define          MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
4968 /* enum: Signature verification failed due to an internal error. */
4969 #define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
4970 /* enum: There are no valid signatures in the image. */
4971 #define          MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
4972 /* enum: Trusted approvers verification failed due to an internal error. */
4973 #define          MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
4974 /* enum: The Trusted approver's list is empty. */
4975 #define          MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
4976 /* enum: Signature chain verification failed due to an internal error. */
4977 #define          MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
4978 /* enum: The signers of the signatures in the image are not listed in the
4979  * Trusted approver's list.
4980  */
4981 #define          MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
4982 /* enum: The image contains a test-signed certificate, but the adapter accepts
4983  * only production signed images.
4984  */
4985 #define          MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
4986 /* enum: The image has a lower security level than the current firmware. */
4987 #define          MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
4988 
4989 
4990 /***********************************/
4991 /* MC_CMD_REBOOT
4992  * Reboot the MC.
4993  *
4994  * The AFTER_ASSERTION flag is intended to be used when the driver notices an
4995  * assertion failure (at which point it is expected to perform a complete tear
4996  * down and reinitialise), to allow both ports to reset the MC once in an
4997  * atomic fashion.
4998  *
4999  * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
5000  * which means that they will automatically reboot out of the assertion
5001  * handler, so this is in practise an optional operation. It is still
5002  * recommended that drivers execute this to support custom firmwares with
5003  * REBOOT_ON_ASSERT=0.
5004  *
5005  * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
5006  * DATALEN=0
5007  */
5008 #define MC_CMD_REBOOT 0x3d
5009 
5010 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5011 
5012 /* MC_CMD_REBOOT_IN msgrequest */
5013 #define    MC_CMD_REBOOT_IN_LEN 4
5014 #define       MC_CMD_REBOOT_IN_FLAGS_OFST 0
5015 #define       MC_CMD_REBOOT_IN_FLAGS_LEN 4
5016 #define          MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5017 
5018 /* MC_CMD_REBOOT_OUT msgresponse */
5019 #define    MC_CMD_REBOOT_OUT_LEN 0
5020 
5021 
5022 /***********************************/
5023 /* MC_CMD_SCHEDINFO
5024  * Request scheduler info. Locks required: NONE. Returns: An array of
5025  * (timeslice,maximum overrun), one for each thread, in ascending order of
5026  * thread address.
5027  */
5028 #define MC_CMD_SCHEDINFO 0x3e
5029 
5030 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5031 
5032 /* MC_CMD_SCHEDINFO_IN msgrequest */
5033 #define    MC_CMD_SCHEDINFO_IN_LEN 0
5034 
5035 /* MC_CMD_SCHEDINFO_OUT msgresponse */
5036 #define    MC_CMD_SCHEDINFO_OUT_LENMIN 4
5037 #define    MC_CMD_SCHEDINFO_OUT_LENMAX 252
5038 #define    MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5039 #define       MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
5040 #define       MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
5041 #define       MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
5042 #define       MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
5043 
5044 
5045 /***********************************/
5046 /* MC_CMD_REBOOT_MODE
5047  * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
5048  * mode to the specified value. Returns the old mode.
5049  */
5050 #define MC_CMD_REBOOT_MODE 0x3f
5051 
5052 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5053 
5054 /* MC_CMD_REBOOT_MODE_IN msgrequest */
5055 #define    MC_CMD_REBOOT_MODE_IN_LEN 4
5056 #define       MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
5057 #define       MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
5058 /* enum: Normal. */
5059 #define          MC_CMD_REBOOT_MODE_NORMAL 0x0
5060 /* enum: Power-on Reset. */
5061 #define          MC_CMD_REBOOT_MODE_POR 0x2
5062 /* enum: Snapper. */
5063 #define          MC_CMD_REBOOT_MODE_SNAPPER 0x3
5064 /* enum: snapper fake POR */
5065 #define          MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5066 #define        MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
5067 #define        MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
5068 
5069 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
5070 #define    MC_CMD_REBOOT_MODE_OUT_LEN 4
5071 #define       MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
5072 #define       MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
5073 
5074 
5075 /***********************************/
5076 /* MC_CMD_SENSOR_INFO
5077  * Returns information about every available sensor.
5078  *
5079  * Each sensor has a single (16bit) value, and a corresponding state. The
5080  * mapping between value and state is nominally determined by the MC, but may
5081  * be implemented using up to 2 ranges per sensor.
5082  *
5083  * This call returns a mask (32bit) of the sensors that are supported by this
5084  * platform, then an array of sensor information structures, in order of sensor
5085  * type (but without gaps for unimplemented sensors). Each structure defines
5086  * the ranges for the corresponding sensor. An unused range is indicated by
5087  * equal limit values. If one range is used, a value outside that range results
5088  * in STATE_FATAL. If two ranges are used, a value outside the second range
5089  * results in STATE_FATAL while a value outside the first and inside the second
5090  * range results in STATE_WARNING.
5091  *
5092  * Sensor masks and sensor information arrays are organised into pages. For
5093  * backward compatibility, older host software can only use sensors in page 0.
5094  * Bit 32 in the sensor mask was previously unused, and is no reserved for use
5095  * as the next page flag.
5096  *
5097  * If the request does not contain a PAGE value then firmware will only return
5098  * page 0 of sensor information, with bit 31 in the sensor mask cleared.
5099  *
5100  * If the request contains a PAGE value then firmware responds with the sensor
5101  * mask and sensor information array for that page of sensors. In this case bit
5102  * 31 in the mask is set if another page exists.
5103  *
5104  * Locks required: None Returns: 0
5105  */
5106 #define MC_CMD_SENSOR_INFO 0x41
5107 
5108 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5109 
5110 /* MC_CMD_SENSOR_INFO_IN msgrequest */
5111 #define    MC_CMD_SENSOR_INFO_IN_LEN 0
5112 
5113 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
5114 #define    MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
5115 /* Which page of sensors to report.
5116  *
5117  * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5118  *
5119  * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5120  */
5121 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
5122 #define       MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
5123 
5124 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
5125 #define    MC_CMD_SENSOR_INFO_OUT_LENMIN 4
5126 #define    MC_CMD_SENSOR_INFO_OUT_LENMAX 252
5127 #define    MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5128 #define       MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
5129 #define       MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
5130 /* enum: Controller temperature: degC */
5131 #define          MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
5132 /* enum: Phy common temperature: degC */
5133 #define          MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
5134 /* enum: Controller cooling: bool */
5135 #define          MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
5136 /* enum: Phy 0 temperature: degC */
5137 #define          MC_CMD_SENSOR_PHY0_TEMP 0x3
5138 /* enum: Phy 0 cooling: bool */
5139 #define          MC_CMD_SENSOR_PHY0_COOLING 0x4
5140 /* enum: Phy 1 temperature: degC */
5141 #define          MC_CMD_SENSOR_PHY1_TEMP 0x5
5142 /* enum: Phy 1 cooling: bool */
5143 #define          MC_CMD_SENSOR_PHY1_COOLING 0x6
5144 /* enum: 1.0v power: mV */
5145 #define          MC_CMD_SENSOR_IN_1V0 0x7
5146 /* enum: 1.2v power: mV */
5147 #define          MC_CMD_SENSOR_IN_1V2 0x8
5148 /* enum: 1.8v power: mV */
5149 #define          MC_CMD_SENSOR_IN_1V8 0x9
5150 /* enum: 2.5v power: mV */
5151 #define          MC_CMD_SENSOR_IN_2V5 0xa
5152 /* enum: 3.3v power: mV */
5153 #define          MC_CMD_SENSOR_IN_3V3 0xb
5154 /* enum: 12v power: mV */
5155 #define          MC_CMD_SENSOR_IN_12V0 0xc
5156 /* enum: 1.2v analogue power: mV */
5157 #define          MC_CMD_SENSOR_IN_1V2A 0xd
5158 /* enum: reference voltage: mV */
5159 #define          MC_CMD_SENSOR_IN_VREF 0xe
5160 /* enum: AOE FPGA power: mV */
5161 #define          MC_CMD_SENSOR_OUT_VAOE 0xf
5162 /* enum: AOE FPGA temperature: degC */
5163 #define          MC_CMD_SENSOR_AOE_TEMP 0x10
5164 /* enum: AOE FPGA PSU temperature: degC */
5165 #define          MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
5166 /* enum: AOE PSU temperature: degC */
5167 #define          MC_CMD_SENSOR_PSU_TEMP 0x12
5168 /* enum: Fan 0 speed: RPM */
5169 #define          MC_CMD_SENSOR_FAN_0 0x13
5170 /* enum: Fan 1 speed: RPM */
5171 #define          MC_CMD_SENSOR_FAN_1 0x14
5172 /* enum: Fan 2 speed: RPM */
5173 #define          MC_CMD_SENSOR_FAN_2 0x15
5174 /* enum: Fan 3 speed: RPM */
5175 #define          MC_CMD_SENSOR_FAN_3 0x16
5176 /* enum: Fan 4 speed: RPM */
5177 #define          MC_CMD_SENSOR_FAN_4 0x17
5178 /* enum: AOE FPGA input power: mV */
5179 #define          MC_CMD_SENSOR_IN_VAOE 0x18
5180 /* enum: AOE FPGA current: mA */
5181 #define          MC_CMD_SENSOR_OUT_IAOE 0x19
5182 /* enum: AOE FPGA input current: mA */
5183 #define          MC_CMD_SENSOR_IN_IAOE 0x1a
5184 /* enum: NIC power consumption: W */
5185 #define          MC_CMD_SENSOR_NIC_POWER 0x1b
5186 /* enum: 0.9v power voltage: mV */
5187 #define          MC_CMD_SENSOR_IN_0V9 0x1c
5188 /* enum: 0.9v power current: mA */
5189 #define          MC_CMD_SENSOR_IN_I0V9 0x1d
5190 /* enum: 1.2v power current: mA */
5191 #define          MC_CMD_SENSOR_IN_I1V2 0x1e
5192 /* enum: Not a sensor: reserved for the next page flag */
5193 #define          MC_CMD_SENSOR_PAGE0_NEXT 0x1f
5194 /* enum: 0.9v power voltage (at ADC): mV */
5195 #define          MC_CMD_SENSOR_IN_0V9_ADC 0x20
5196 /* enum: Controller temperature 2: degC */
5197 #define          MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
5198 /* enum: Voltage regulator internal temperature: degC */
5199 #define          MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
5200 /* enum: 0.9V voltage regulator temperature: degC */
5201 #define          MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
5202 /* enum: 1.2V voltage regulator temperature: degC */
5203 #define          MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
5204 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
5205 #define          MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
5206 /* enum: controller internal temperature (internal ADC): degC */
5207 #define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
5208 /* enum: controller internal temperature sensor voltage (external ADC): mV */
5209 #define          MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
5210 /* enum: controller internal temperature (external ADC): degC */
5211 #define          MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
5212 /* enum: ambient temperature: degC */
5213 #define          MC_CMD_SENSOR_AMBIENT_TEMP 0x29
5214 /* enum: air flow: bool */
5215 #define          MC_CMD_SENSOR_AIRFLOW 0x2a
5216 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
5217 #define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
5218 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
5219 #define          MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
5220 /* enum: Hotpoint temperature: degC */
5221 #define          MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
5222 /* enum: Port 0 PHY power switch over-current: bool */
5223 #define          MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
5224 /* enum: Port 1 PHY power switch over-current: bool */
5225 #define          MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
5226 /* enum: Mop-up microcontroller reference voltage: mV */
5227 #define          MC_CMD_SENSOR_MUM_VCC 0x30
5228 /* enum: 0.9v power phase A voltage: mV */
5229 #define          MC_CMD_SENSOR_IN_0V9_A 0x31
5230 /* enum: 0.9v power phase A current: mA */
5231 #define          MC_CMD_SENSOR_IN_I0V9_A 0x32
5232 /* enum: 0.9V voltage regulator phase A temperature: degC */
5233 #define          MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
5234 /* enum: 0.9v power phase B voltage: mV */
5235 #define          MC_CMD_SENSOR_IN_0V9_B 0x34
5236 /* enum: 0.9v power phase B current: mA */
5237 #define          MC_CMD_SENSOR_IN_I0V9_B 0x35
5238 /* enum: 0.9V voltage regulator phase B temperature: degC */
5239 #define          MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
5240 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
5241 #define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
5242 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
5243 #define          MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
5244 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
5245 #define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
5246 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
5247 #define          MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
5248 /* enum: CCOM RTS temperature: degC */
5249 #define          MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
5250 /* enum: Not a sensor: reserved for the next page flag */
5251 #define          MC_CMD_SENSOR_PAGE1_NEXT 0x3f
5252 /* enum: controller internal temperature sensor voltage on master core
5253  * (internal ADC): mV
5254  */
5255 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
5256 /* enum: controller internal temperature on master core (internal ADC): degC */
5257 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
5258 /* enum: controller internal temperature sensor voltage on master core
5259  * (external ADC): mV
5260  */
5261 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
5262 /* enum: controller internal temperature on master core (external ADC): degC */
5263 #define          MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
5264 /* enum: controller internal temperature on slave core sensor voltage (internal
5265  * ADC): mV
5266  */
5267 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
5268 /* enum: controller internal temperature on slave core (internal ADC): degC */
5269 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
5270 /* enum: controller internal temperature on slave core sensor voltage (external
5271  * ADC): mV
5272  */
5273 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
5274 /* enum: controller internal temperature on slave core (external ADC): degC */
5275 #define          MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
5276 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */
5277 #define          MC_CMD_SENSOR_SODIMM_VOUT 0x49
5278 /* enum: Temperature of SODIMM 0 (if installed): degC */
5279 #define          MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
5280 /* enum: Temperature of SODIMM 1 (if installed): degC */
5281 #define          MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
5282 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
5283 #define          MC_CMD_SENSOR_PHY0_VCC 0x4c
5284 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
5285 #define          MC_CMD_SENSOR_PHY1_VCC 0x4d
5286 /* enum: Controller die temperature (TDIODE): degC */
5287 #define          MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
5288 /* enum: Board temperature (front): degC */
5289 #define          MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
5290 /* enum: Board temperature (back): degC */
5291 #define          MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
5292 /* enum: 1.8v power current: mA */
5293 #define          MC_CMD_SENSOR_IN_I1V8 0x51
5294 /* enum: 2.5v power current: mA */
5295 #define          MC_CMD_SENSOR_IN_I2V5 0x52
5296 /* enum: 3.3v power current: mA */
5297 #define          MC_CMD_SENSOR_IN_I3V3 0x53
5298 /* enum: 12v power current: mA */
5299 #define          MC_CMD_SENSOR_IN_I12V0 0x54
5300 /* enum: 1.3v power: mV */
5301 #define          MC_CMD_SENSOR_IN_1V3 0x55
5302 /* enum: 1.3v power current: mA */
5303 #define          MC_CMD_SENSOR_IN_I1V3 0x56
5304 /* enum: Not a sensor: reserved for the next page flag */
5305 #define          MC_CMD_SENSOR_PAGE2_NEXT 0x5f
5306 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5307 #define       MC_CMD_SENSOR_ENTRY_OFST 4
5308 #define       MC_CMD_SENSOR_ENTRY_LEN 8
5309 #define       MC_CMD_SENSOR_ENTRY_LO_OFST 4
5310 #define       MC_CMD_SENSOR_ENTRY_HI_OFST 8
5311 #define       MC_CMD_SENSOR_ENTRY_MINNUM 0
5312 #define       MC_CMD_SENSOR_ENTRY_MAXNUM 31
5313 
5314 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
5315 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
5316 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
5317 #define    MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
5318 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
5319 #define       MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
5320 /*            Enum values, see field(s): */
5321 /*               MC_CMD_SENSOR_INFO_OUT */
5322 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
5323 #define        MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
5324 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5325 /*            MC_CMD_SENSOR_ENTRY_OFST 4 */
5326 /*            MC_CMD_SENSOR_ENTRY_LEN 8 */
5327 /*            MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
5328 /*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
5329 /*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */
5330 /*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
5331 
5332 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
5333 #define    MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
5334 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
5335 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
5336 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
5337 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
5338 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
5339 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
5340 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
5341 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
5342 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
5343 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
5344 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
5345 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
5346 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
5347 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
5348 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
5349 #define       MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
5350 
5351 
5352 /***********************************/
5353 /* MC_CMD_READ_SENSORS
5354  * Returns the current reading from each sensor. DMAs an array of sensor
5355  * readings, in order of sensor type (but without gaps for unimplemented
5356  * sensors), into host memory. Each array element is a
5357  * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
5358  *
5359  * If the request does not contain the LENGTH field then only sensors 0 to 30
5360  * are reported, to avoid DMA buffer overflow in older host software. If the
5361  * sensor reading require more space than the LENGTH allows, then return
5362  * EINVAL.
5363  *
5364  * The MC will send a SENSOREVT event every time any sensor changes state. The
5365  * driver is responsible for ensuring that it doesn't miss any events. The
5366  * board will function normally if all sensors are in STATE_OK or
5367  * STATE_WARNING. Otherwise the board should not be expected to function.
5368  */
5369 #define MC_CMD_READ_SENSORS 0x42
5370 
5371 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5372 
5373 /* MC_CMD_READ_SENSORS_IN msgrequest */
5374 #define    MC_CMD_READ_SENSORS_IN_LEN 8
5375 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5376 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
5377 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
5378 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
5379 #define       MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
5380 
5381 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
5382 #define    MC_CMD_READ_SENSORS_EXT_IN_LEN 12
5383 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5384 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
5385 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
5386 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
5387 #define       MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
5388 /* Size in bytes of host buffer. */
5389 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
5390 #define       MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
5391 
5392 /* MC_CMD_READ_SENSORS_OUT msgresponse */
5393 #define    MC_CMD_READ_SENSORS_OUT_LEN 0
5394 
5395 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
5396 #define    MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
5397 
5398 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
5399 #define    MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
5400 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
5401 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
5402 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
5403 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
5404 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
5405 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
5406 /* enum: Ok. */
5407 #define          MC_CMD_SENSOR_STATE_OK 0x0
5408 /* enum: Breached warning threshold. */
5409 #define          MC_CMD_SENSOR_STATE_WARNING 0x1
5410 /* enum: Breached fatal threshold. */
5411 #define          MC_CMD_SENSOR_STATE_FATAL 0x2
5412 /* enum: Fault with sensor. */
5413 #define          MC_CMD_SENSOR_STATE_BROKEN 0x3
5414 /* enum: Sensor is working but does not currently have a reading. */
5415 #define          MC_CMD_SENSOR_STATE_NO_READING 0x4
5416 /* enum: Sensor initialisation failed. */
5417 #define          MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
5418 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
5419 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
5420 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
5421 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
5422 /*            Enum values, see field(s): */
5423 /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5424 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
5425 #define       MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
5426 
5427 
5428 /***********************************/
5429 /* MC_CMD_GET_PHY_STATE
5430  * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
5431  * (e.g. due to missing or corrupted firmware). Locks required: None. Return
5432  * code: 0
5433  */
5434 #define MC_CMD_GET_PHY_STATE 0x43
5435 
5436 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5437 
5438 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
5439 #define    MC_CMD_GET_PHY_STATE_IN_LEN 0
5440 
5441 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
5442 #define    MC_CMD_GET_PHY_STATE_OUT_LEN 4
5443 #define       MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
5444 #define       MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
5445 /* enum: Ok. */
5446 #define          MC_CMD_PHY_STATE_OK 0x1
5447 /* enum: Faulty. */
5448 #define          MC_CMD_PHY_STATE_ZOMBIE 0x2
5449 
5450 
5451 /***********************************/
5452 /* MC_CMD_SETUP_8021QBB
5453  * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
5454  * disable 802.Qbb for a given priority.
5455  */
5456 #define MC_CMD_SETUP_8021QBB 0x44
5457 
5458 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
5459 #define    MC_CMD_SETUP_8021QBB_IN_LEN 32
5460 #define       MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
5461 #define       MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
5462 
5463 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
5464 #define    MC_CMD_SETUP_8021QBB_OUT_LEN 0
5465 
5466 
5467 /***********************************/
5468 /* MC_CMD_WOL_FILTER_GET
5469  * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
5470  */
5471 #define MC_CMD_WOL_FILTER_GET 0x45
5472 
5473 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
5474 
5475 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
5476 #define    MC_CMD_WOL_FILTER_GET_IN_LEN 0
5477 
5478 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
5479 #define    MC_CMD_WOL_FILTER_GET_OUT_LEN 4
5480 #define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
5481 #define       MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
5482 
5483 
5484 /***********************************/
5485 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
5486  * Add a protocol offload to NIC for lights-out state. Locks required: None.
5487  * Returns: 0, ENOSYS
5488  */
5489 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
5490 
5491 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
5492 
5493 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
5494 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
5495 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
5496 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
5497 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5498 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5499 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
5500 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
5501 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
5502 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
5503 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
5504 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
5505 
5506 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
5507 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
5508 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5509 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5510 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
5511 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
5512 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
5513 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
5514 
5515 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
5516 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
5517 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5518 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5519 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
5520 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
5521 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
5522 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
5523 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
5524 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
5525 
5526 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5527 #define    MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
5528 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
5529 #define       MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
5530 
5531 
5532 /***********************************/
5533 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
5534  * Remove a protocol offload from NIC for lights-out state. Locks required:
5535  * None. Returns: 0, ENOSYS
5536  */
5537 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
5538 
5539 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
5540 
5541 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
5542 #define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
5543 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5544 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5545 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
5546 #define       MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
5547 
5548 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5549 #define    MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
5550 
5551 
5552 /***********************************/
5553 /* MC_CMD_MAC_RESET_RESTORE
5554  * Restore MAC after block reset. Locks required: None. Returns: 0.
5555  */
5556 #define MC_CMD_MAC_RESET_RESTORE 0x48
5557 
5558 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
5559 #define    MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
5560 
5561 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
5562 #define    MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
5563 
5564 
5565 /***********************************/
5566 /* MC_CMD_TESTASSERT
5567  * Deliberately trigger an assert-detonation in the firmware for testing
5568  * purposes (i.e. to allow tests that the driver copes gracefully). Locks
5569  * required: None Returns: 0
5570  */
5571 #define MC_CMD_TESTASSERT 0x49
5572 
5573 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5574 
5575 /* MC_CMD_TESTASSERT_IN msgrequest */
5576 #define    MC_CMD_TESTASSERT_IN_LEN 0
5577 
5578 /* MC_CMD_TESTASSERT_OUT msgresponse */
5579 #define    MC_CMD_TESTASSERT_OUT_LEN 0
5580 
5581 /* MC_CMD_TESTASSERT_V2_IN msgrequest */
5582 #define    MC_CMD_TESTASSERT_V2_IN_LEN 4
5583 /* How to provoke the assertion */
5584 #define       MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
5585 #define       MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
5586 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
5587  * you're testing firmware, this is what you want.
5588  */
5589 #define          MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
5590 /* enum: Assert using assert(0); */
5591 #define          MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
5592 /* enum: Deliberately trigger a watchdog */
5593 #define          MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
5594 /* enum: Deliberately trigger a trap by loading from an invalid address */
5595 #define          MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
5596 /* enum: Deliberately trigger a trap by storing to an invalid address */
5597 #define          MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
5598 /* enum: Jump to an invalid address */
5599 #define          MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
5600 
5601 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */
5602 #define    MC_CMD_TESTASSERT_V2_OUT_LEN 0
5603 
5604 
5605 /***********************************/
5606 /* MC_CMD_WORKAROUND
5607  * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
5608  * understand the given workaround number - which should not be treated as a
5609  * hard error by client code. This op does not imply any semantics about each
5610  * workaround, that's between the driver and the mcfw on a per-workaround
5611  * basis. Locks required: None. Returns: 0, EINVAL .
5612  */
5613 #define MC_CMD_WORKAROUND 0x4a
5614 
5615 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5616 
5617 /* MC_CMD_WORKAROUND_IN msgrequest */
5618 #define    MC_CMD_WORKAROUND_IN_LEN 8
5619 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
5620 #define       MC_CMD_WORKAROUND_IN_TYPE_OFST 0
5621 #define       MC_CMD_WORKAROUND_IN_TYPE_LEN 4
5622 /* enum: Bug 17230 work around. */
5623 #define          MC_CMD_WORKAROUND_BUG17230 0x1
5624 /* enum: Bug 35388 work around (unsafe EVQ writes). */
5625 #define          MC_CMD_WORKAROUND_BUG35388 0x2
5626 /* enum: Bug35017 workaround (A64 tables must be identity map) */
5627 #define          MC_CMD_WORKAROUND_BUG35017 0x3
5628 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
5629 #define          MC_CMD_WORKAROUND_BUG41750 0x4
5630 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
5631  * - before adding code that queries this workaround, remember that there's
5632  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
5633  * and will hence (incorrectly) report that the bug doesn't exist.
5634  */
5635 #define          MC_CMD_WORKAROUND_BUG42008 0x5
5636 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
5637  * This feature cannot be turned on/off while there are any filters already
5638  * present. The behaviour in such case depends on the acting client's privilege
5639  * level. If the client has the admin privilege, then all functions that have
5640  * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
5641  * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
5642  */
5643 #define          MC_CMD_WORKAROUND_BUG26807 0x6
5644 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
5645 #define          MC_CMD_WORKAROUND_BUG61265 0x7
5646 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
5647  * the workaround
5648  */
5649 #define       MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
5650 #define       MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
5651 
5652 /* MC_CMD_WORKAROUND_OUT msgresponse */
5653 #define    MC_CMD_WORKAROUND_OUT_LEN 0
5654 
5655 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
5656  * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
5657  */
5658 #define    MC_CMD_WORKAROUND_EXT_OUT_LEN 4
5659 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
5660 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
5661 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
5662 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
5663 
5664 
5665 /***********************************/
5666 /* MC_CMD_GET_PHY_MEDIA_INFO
5667  * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
5668  * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
5669  * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
5670  * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
5671  * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
5672  * Anything else: currently undefined. Locks required: None. Return code: 0.
5673  */
5674 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
5675 
5676 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5677 
5678 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
5679 #define    MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
5680 #define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
5681 #define       MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
5682 
5683 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
5684 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
5685 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
5686 #define    MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
5687 /* in bytes */
5688 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
5689 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
5690 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
5691 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
5692 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
5693 #define       MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
5694 
5695 
5696 /***********************************/
5697 /* MC_CMD_NVRAM_TEST
5698  * Test a particular NVRAM partition for valid contents (where "valid" depends
5699  * on the type of partition).
5700  */
5701 #define MC_CMD_NVRAM_TEST 0x4c
5702 
5703 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5704 
5705 /* MC_CMD_NVRAM_TEST_IN msgrequest */
5706 #define    MC_CMD_NVRAM_TEST_IN_LEN 4
5707 #define       MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
5708 #define       MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
5709 /*            Enum values, see field(s): */
5710 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5711 
5712 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
5713 #define    MC_CMD_NVRAM_TEST_OUT_LEN 4
5714 #define       MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
5715 #define       MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
5716 /* enum: Passed. */
5717 #define          MC_CMD_NVRAM_TEST_PASS 0x0
5718 /* enum: Failed. */
5719 #define          MC_CMD_NVRAM_TEST_FAIL 0x1
5720 /* enum: Not supported. */
5721 #define          MC_CMD_NVRAM_TEST_NOTSUPP 0x2
5722 
5723 
5724 /***********************************/
5725 /* MC_CMD_MRSFP_TWEAK
5726  * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
5727  * I2C I/O expander bits are always read; if equaliser parameters are supplied,
5728  * they are configured first. Locks required: None. Return code: 0, EINVAL.
5729  */
5730 #define MC_CMD_MRSFP_TWEAK 0x4d
5731 
5732 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
5733 #define    MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
5734 /* 0-6 low->high de-emph. */
5735 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
5736 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
5737 /* 0-8 low->high ref.V */
5738 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
5739 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
5740 /* 0-8 0-8 low->high boost */
5741 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
5742 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
5743 /* 0-8 low->high ref.V */
5744 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
5745 #define       MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
5746 
5747 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
5748 #define    MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
5749 
5750 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
5751 #define    MC_CMD_MRSFP_TWEAK_OUT_LEN 12
5752 /* input bits */
5753 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
5754 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
5755 /* output bits */
5756 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
5757 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
5758 /* direction */
5759 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
5760 #define       MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
5761 /* enum: Out. */
5762 #define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
5763 /* enum: In. */
5764 #define          MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
5765 
5766 
5767 /***********************************/
5768 /* MC_CMD_SENSOR_SET_LIMS
5769  * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
5770  * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
5771  * of range.
5772  */
5773 #define MC_CMD_SENSOR_SET_LIMS 0x4e
5774 
5775 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5776 
5777 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
5778 #define    MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
5779 #define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
5780 #define       MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
5781 /*            Enum values, see field(s): */
5782 /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5783 /* interpretation is is sensor-specific. */
5784 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
5785 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
5786 /* interpretation is is sensor-specific. */
5787 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
5788 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
5789 /* interpretation is is sensor-specific. */
5790 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
5791 #define       MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
5792 /* interpretation is is sensor-specific. */
5793 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
5794 #define       MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
5795 
5796 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
5797 #define    MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
5798 
5799 
5800 /***********************************/
5801 /* MC_CMD_GET_RESOURCE_LIMITS
5802  */
5803 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
5804 
5805 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
5806 #define    MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
5807 
5808 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
5809 #define    MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
5810 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
5811 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
5812 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
5813 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
5814 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
5815 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
5816 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
5817 #define       MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
5818 
5819 
5820 /***********************************/
5821 /* MC_CMD_NVRAM_PARTITIONS
5822  * Reads the list of available virtual NVRAM partition types. Locks required:
5823  * none. Returns: 0, EINVAL (bad type).
5824  */
5825 #define MC_CMD_NVRAM_PARTITIONS 0x51
5826 
5827 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5828 
5829 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
5830 #define    MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
5831 
5832 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
5833 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
5834 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
5835 #define    MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
5836 /* total number of partitions */
5837 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
5838 #define       MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
5839 /* type ID code for each of NUM_PARTITIONS partitions */
5840 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
5841 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
5842 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
5843 #define       MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
5844 
5845 
5846 /***********************************/
5847 /* MC_CMD_NVRAM_METADATA
5848  * Reads soft metadata for a virtual NVRAM partition type. Locks required:
5849  * none. Returns: 0, EINVAL (bad type).
5850  */
5851 #define MC_CMD_NVRAM_METADATA 0x52
5852 
5853 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5854 
5855 /* MC_CMD_NVRAM_METADATA_IN msgrequest */
5856 #define    MC_CMD_NVRAM_METADATA_IN_LEN 4
5857 /* Partition type ID code */
5858 #define       MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
5859 #define       MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
5860 
5861 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
5862 #define    MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
5863 #define    MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
5864 #define    MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
5865 /* Partition type ID code */
5866 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
5867 #define       MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
5868 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
5869 #define       MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
5870 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
5871 #define        MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
5872 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
5873 #define        MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
5874 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
5875 #define        MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
5876 /* Subtype ID code for content of this partition */
5877 #define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
5878 #define       MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
5879 /* 1st component of W.X.Y.Z version number for content of this partition */
5880 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
5881 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
5882 /* 2nd component of W.X.Y.Z version number for content of this partition */
5883 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
5884 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
5885 /* 3rd component of W.X.Y.Z version number for content of this partition */
5886 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
5887 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
5888 /* 4th component of W.X.Y.Z version number for content of this partition */
5889 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
5890 #define       MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
5891 /* Zero-terminated string describing the content of this partition */
5892 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
5893 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
5894 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
5895 #define       MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
5896 
5897 
5898 /***********************************/
5899 /* MC_CMD_GET_MAC_ADDRESSES
5900  * Returns the base MAC, count and stride for the requesting function
5901  */
5902 #define MC_CMD_GET_MAC_ADDRESSES 0x55
5903 
5904 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5905 
5906 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
5907 #define    MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
5908 
5909 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
5910 #define    MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
5911 /* Base MAC address */
5912 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
5913 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
5914 /* Padding */
5915 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
5916 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
5917 /* Number of allocated MAC addresses */
5918 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
5919 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
5920 /* Spacing of allocated MAC addresses */
5921 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
5922 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
5923 
5924 
5925 /***********************************/
5926 /* MC_CMD_CLP
5927  * Perform a CLP related operation
5928  */
5929 #define MC_CMD_CLP 0x56
5930 
5931 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5932 
5933 /* MC_CMD_CLP_IN msgrequest */
5934 #define    MC_CMD_CLP_IN_LEN 4
5935 /* Sub operation */
5936 #define       MC_CMD_CLP_IN_OP_OFST 0
5937 #define       MC_CMD_CLP_IN_OP_LEN 4
5938 /* enum: Return to factory default settings */
5939 #define          MC_CMD_CLP_OP_DEFAULT 0x1
5940 /* enum: Set MAC address */
5941 #define          MC_CMD_CLP_OP_SET_MAC 0x2
5942 /* enum: Get MAC address */
5943 #define          MC_CMD_CLP_OP_GET_MAC 0x3
5944 /* enum: Set UEFI/GPXE boot mode */
5945 #define          MC_CMD_CLP_OP_SET_BOOT 0x4
5946 /* enum: Get UEFI/GPXE boot mode */
5947 #define          MC_CMD_CLP_OP_GET_BOOT 0x5
5948 
5949 /* MC_CMD_CLP_OUT msgresponse */
5950 #define    MC_CMD_CLP_OUT_LEN 0
5951 
5952 /* MC_CMD_CLP_IN_DEFAULT msgrequest */
5953 #define    MC_CMD_CLP_IN_DEFAULT_LEN 4
5954 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5955 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5956 
5957 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */
5958 #define    MC_CMD_CLP_OUT_DEFAULT_LEN 0
5959 
5960 /* MC_CMD_CLP_IN_SET_MAC msgrequest */
5961 #define    MC_CMD_CLP_IN_SET_MAC_LEN 12
5962 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5963 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5964 /* MAC address assigned to port */
5965 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
5966 #define       MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
5967 /* Padding */
5968 #define       MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
5969 #define       MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
5970 
5971 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
5972 #define    MC_CMD_CLP_OUT_SET_MAC_LEN 0
5973 
5974 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
5975 #define    MC_CMD_CLP_IN_GET_MAC_LEN 4
5976 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5977 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5978 
5979 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
5980 #define    MC_CMD_CLP_OUT_GET_MAC_LEN 8
5981 /* MAC address assigned to port */
5982 #define       MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
5983 #define       MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
5984 /* Padding */
5985 #define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
5986 #define       MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
5987 
5988 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */
5989 #define    MC_CMD_CLP_IN_SET_BOOT_LEN 5
5990 /*            MC_CMD_CLP_IN_OP_OFST 0 */
5991 /*            MC_CMD_CLP_IN_OP_LEN 4 */
5992 /* Boot flag */
5993 #define       MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
5994 #define       MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
5995 
5996 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
5997 #define    MC_CMD_CLP_OUT_SET_BOOT_LEN 0
5998 
5999 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */
6000 #define    MC_CMD_CLP_IN_GET_BOOT_LEN 4
6001 /*            MC_CMD_CLP_IN_OP_OFST 0 */
6002 /*            MC_CMD_CLP_IN_OP_LEN 4 */
6003 
6004 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
6005 #define    MC_CMD_CLP_OUT_GET_BOOT_LEN 4
6006 /* Boot flag */
6007 #define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
6008 #define       MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
6009 /* Padding */
6010 #define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
6011 #define       MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
6012 
6013 
6014 /***********************************/
6015 /* MC_CMD_MUM
6016  * Perform a MUM operation
6017  */
6018 #define MC_CMD_MUM 0x57
6019 
6020 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
6021 
6022 /* MC_CMD_MUM_IN msgrequest */
6023 #define    MC_CMD_MUM_IN_LEN 4
6024 #define       MC_CMD_MUM_IN_OP_HDR_OFST 0
6025 #define       MC_CMD_MUM_IN_OP_HDR_LEN 4
6026 #define        MC_CMD_MUM_IN_OP_LBN 0
6027 #define        MC_CMD_MUM_IN_OP_WIDTH 8
6028 /* enum: NULL MCDI command to MUM */
6029 #define          MC_CMD_MUM_OP_NULL 0x1
6030 /* enum: Get MUM version */
6031 #define          MC_CMD_MUM_OP_GET_VERSION 0x2
6032 /* enum: Issue raw I2C command to MUM */
6033 #define          MC_CMD_MUM_OP_RAW_CMD 0x3
6034 /* enum: Read from registers on devices connected to MUM. */
6035 #define          MC_CMD_MUM_OP_READ 0x4
6036 /* enum: Write to registers on devices connected to MUM. */
6037 #define          MC_CMD_MUM_OP_WRITE 0x5
6038 /* enum: Control UART logging. */
6039 #define          MC_CMD_MUM_OP_LOG 0x6
6040 /* enum: Operations on MUM GPIO lines */
6041 #define          MC_CMD_MUM_OP_GPIO 0x7
6042 /* enum: Get sensor readings from MUM */
6043 #define          MC_CMD_MUM_OP_READ_SENSORS 0x8
6044 /* enum: Initiate clock programming on the MUM */
6045 #define          MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
6046 /* enum: Initiate FPGA load from flash on the MUM */
6047 #define          MC_CMD_MUM_OP_FPGA_LOAD 0xa
6048 /* enum: Request sensor reading from MUM ADC resulting from earlier request via
6049  * MUM ATB
6050  */
6051 #define          MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
6052 /* enum: Send commands relating to the QSFP ports via the MUM for PHY
6053  * operations
6054  */
6055 #define          MC_CMD_MUM_OP_QSFP 0xc
6056 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
6057  * level) from MUM
6058  */
6059 #define          MC_CMD_MUM_OP_READ_DDR_INFO 0xd
6060 
6061 /* MC_CMD_MUM_IN_NULL msgrequest */
6062 #define    MC_CMD_MUM_IN_NULL_LEN 4
6063 /* MUM cmd header */
6064 #define       MC_CMD_MUM_IN_CMD_OFST 0
6065 #define       MC_CMD_MUM_IN_CMD_LEN 4
6066 
6067 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */
6068 #define    MC_CMD_MUM_IN_GET_VERSION_LEN 4
6069 /* MUM cmd header */
6070 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6071 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6072 
6073 /* MC_CMD_MUM_IN_READ msgrequest */
6074 #define    MC_CMD_MUM_IN_READ_LEN 16
6075 /* MUM cmd header */
6076 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6077 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6078 /* ID of (device connected to MUM) to read from registers of */
6079 #define       MC_CMD_MUM_IN_READ_DEVICE_OFST 4
6080 #define       MC_CMD_MUM_IN_READ_DEVICE_LEN 4
6081 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6082 #define          MC_CMD_MUM_DEV_HITTITE 0x1
6083 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
6084 #define          MC_CMD_MUM_DEV_HITTITE_NIC 0x2
6085 /* 32-bit address to read from */
6086 #define       MC_CMD_MUM_IN_READ_ADDR_OFST 8
6087 #define       MC_CMD_MUM_IN_READ_ADDR_LEN 4
6088 /* Number of words to read. */
6089 #define       MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
6090 #define       MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
6091 
6092 /* MC_CMD_MUM_IN_WRITE msgrequest */
6093 #define    MC_CMD_MUM_IN_WRITE_LENMIN 16
6094 #define    MC_CMD_MUM_IN_WRITE_LENMAX 252
6095 #define    MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
6096 /* MUM cmd header */
6097 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6098 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6099 /* ID of (device connected to MUM) to write to registers of */
6100 #define       MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
6101 #define       MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
6102 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6103 /*               MC_CMD_MUM_DEV_HITTITE 0x1 */
6104 /* 32-bit address to write to */
6105 #define       MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
6106 #define       MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
6107 /* Words to write */
6108 #define       MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
6109 #define       MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
6110 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
6111 #define       MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
6112 
6113 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */
6114 #define    MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
6115 #define    MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
6116 #define    MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
6117 /* MUM cmd header */
6118 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6119 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6120 /* MUM I2C cmd code */
6121 #define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
6122 #define       MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
6123 /* Number of bytes to write */
6124 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
6125 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
6126 /* Number of bytes to read */
6127 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
6128 #define       MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
6129 /* Bytes to write */
6130 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
6131 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
6132 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
6133 #define       MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
6134 
6135 /* MC_CMD_MUM_IN_LOG msgrequest */
6136 #define    MC_CMD_MUM_IN_LOG_LEN 8
6137 /* MUM cmd header */
6138 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6139 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6140 #define       MC_CMD_MUM_IN_LOG_OP_OFST 4
6141 #define       MC_CMD_MUM_IN_LOG_OP_LEN 4
6142 #define          MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
6143 
6144 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
6145 #define    MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
6146 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6147 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6148 /*            MC_CMD_MUM_IN_LOG_OP_OFST 4 */
6149 /*            MC_CMD_MUM_IN_LOG_OP_LEN 4 */
6150 /* Enable/disable debug output to UART */
6151 #define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
6152 #define       MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
6153 
6154 /* MC_CMD_MUM_IN_GPIO msgrequest */
6155 #define    MC_CMD_MUM_IN_GPIO_LEN 8
6156 /* MUM cmd header */
6157 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6158 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6159 #define       MC_CMD_MUM_IN_GPIO_HDR_OFST 4
6160 #define       MC_CMD_MUM_IN_GPIO_HDR_LEN 4
6161 #define        MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
6162 #define        MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
6163 #define          MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
6164 #define          MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
6165 #define          MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
6166 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
6167 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
6168 #define          MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
6169 
6170 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
6171 #define    MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
6172 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6173 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6174 #define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
6175 #define       MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
6176 
6177 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
6178 #define    MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
6179 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6180 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6181 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
6182 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
6183 /* The first 32-bit word to be written to the GPIO OUT register. */
6184 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
6185 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
6186 /* The second 32-bit word to be written to the GPIO OUT register. */
6187 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
6188 #define       MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
6189 
6190 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
6191 #define    MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
6192 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6193 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6194 #define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
6195 #define       MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
6196 
6197 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
6198 #define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
6199 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6200 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6201 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
6202 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
6203 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
6204 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
6205 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
6206 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
6207 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
6208 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
6209 
6210 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
6211 #define    MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
6212 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6213 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6214 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
6215 #define       MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
6216 
6217 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */
6218 #define    MC_CMD_MUM_IN_GPIO_OP_LEN 8
6219 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6220 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6221 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
6222 #define       MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
6223 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
6224 #define        MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
6225 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
6226 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
6227 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
6228 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
6229 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
6230 #define        MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
6231 
6232 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
6233 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
6234 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6235 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6236 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
6237 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
6238 
6239 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
6240 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
6241 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6242 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6243 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
6244 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
6245 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
6246 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
6247 
6248 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
6249 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
6250 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6251 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6252 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
6253 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
6254 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
6255 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
6256 
6257 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
6258 #define    MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
6259 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6260 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6261 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
6262 #define       MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
6263 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
6264 #define        MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
6265 
6266 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
6267 #define    MC_CMD_MUM_IN_READ_SENSORS_LEN 8
6268 /* MUM cmd header */
6269 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6270 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6271 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
6272 #define       MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
6273 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
6274 #define        MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
6275 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
6276 #define        MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
6277 
6278 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
6279 #define    MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
6280 /* MUM cmd header */
6281 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6282 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6283 /* Bit-mask of clocks to be programmed */
6284 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
6285 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
6286 #define          MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
6287 #define          MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
6288 #define          MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
6289 /* Control flags for clock programming */
6290 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
6291 #define       MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
6292 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
6293 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
6294 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
6295 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
6296 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
6297 #define        MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
6298 
6299 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
6300 #define    MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
6301 /* MUM cmd header */
6302 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6303 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6304 /* Enable/Disable FPGA config from flash */
6305 #define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
6306 #define       MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
6307 
6308 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
6309 #define    MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
6310 /* MUM cmd header */
6311 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6312 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6313 
6314 /* MC_CMD_MUM_IN_QSFP msgrequest */
6315 #define    MC_CMD_MUM_IN_QSFP_LEN 12
6316 /* MUM cmd header */
6317 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6318 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6319 #define       MC_CMD_MUM_IN_QSFP_HDR_OFST 4
6320 #define       MC_CMD_MUM_IN_QSFP_HDR_LEN 4
6321 #define        MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
6322 #define        MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
6323 #define          MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
6324 #define          MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
6325 #define          MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
6326 #define          MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
6327 #define          MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
6328 #define          MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
6329 #define       MC_CMD_MUM_IN_QSFP_IDX_OFST 8
6330 #define       MC_CMD_MUM_IN_QSFP_IDX_LEN 4
6331 
6332 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
6333 #define    MC_CMD_MUM_IN_QSFP_INIT_LEN 16
6334 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6335 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6336 #define       MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
6337 #define       MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
6338 #define       MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
6339 #define       MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
6340 #define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
6341 #define       MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
6342 
6343 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
6344 #define    MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
6345 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6346 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6347 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
6348 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
6349 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
6350 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
6351 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
6352 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
6353 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
6354 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
6355 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
6356 #define       MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
6357 
6358 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
6359 #define    MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
6360 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6361 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6362 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
6363 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
6364 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
6365 #define       MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
6366 
6367 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
6368 #define    MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
6369 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6370 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6371 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
6372 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
6373 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
6374 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
6375 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
6376 #define       MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
6377 
6378 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
6379 #define    MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
6380 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6381 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6382 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
6383 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
6384 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
6385 #define       MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
6386 
6387 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
6388 #define    MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
6389 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6390 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6391 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
6392 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
6393 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
6394 #define       MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
6395 
6396 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
6397 #define    MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
6398 /* MUM cmd header */
6399 /*            MC_CMD_MUM_IN_CMD_OFST 0 */
6400 /*            MC_CMD_MUM_IN_CMD_LEN 4 */
6401 
6402 /* MC_CMD_MUM_OUT msgresponse */
6403 #define    MC_CMD_MUM_OUT_LEN 0
6404 
6405 /* MC_CMD_MUM_OUT_NULL msgresponse */
6406 #define    MC_CMD_MUM_OUT_NULL_LEN 0
6407 
6408 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
6409 #define    MC_CMD_MUM_OUT_GET_VERSION_LEN 12
6410 #define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
6411 #define       MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
6412 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
6413 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
6414 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
6415 #define       MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
6416 
6417 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
6418 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
6419 #define    MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
6420 #define    MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
6421 /* returned data */
6422 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
6423 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
6424 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
6425 #define       MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
6426 
6427 /* MC_CMD_MUM_OUT_READ msgresponse */
6428 #define    MC_CMD_MUM_OUT_READ_LENMIN 4
6429 #define    MC_CMD_MUM_OUT_READ_LENMAX 252
6430 #define    MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
6431 #define       MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
6432 #define       MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
6433 #define       MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
6434 #define       MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
6435 
6436 /* MC_CMD_MUM_OUT_WRITE msgresponse */
6437 #define    MC_CMD_MUM_OUT_WRITE_LEN 0
6438 
6439 /* MC_CMD_MUM_OUT_LOG msgresponse */
6440 #define    MC_CMD_MUM_OUT_LOG_LEN 0
6441 
6442 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
6443 #define    MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
6444 
6445 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
6446 #define    MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
6447 /* The first 32-bit word read from the GPIO IN register. */
6448 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
6449 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
6450 /* The second 32-bit word read from the GPIO IN register. */
6451 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
6452 #define       MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
6453 
6454 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
6455 #define    MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
6456 
6457 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
6458 #define    MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
6459 /* The first 32-bit word read from the GPIO OUT register. */
6460 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
6461 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
6462 /* The second 32-bit word read from the GPIO OUT register. */
6463 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
6464 #define       MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
6465 
6466 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
6467 #define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
6468 
6469 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
6470 #define    MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
6471 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
6472 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
6473 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
6474 #define       MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
6475 
6476 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
6477 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
6478 #define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
6479 #define       MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
6480 
6481 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
6482 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
6483 
6484 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
6485 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
6486 
6487 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
6488 #define    MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
6489 
6490 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
6491 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
6492 #define    MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
6493 #define    MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
6494 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
6495 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
6496 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
6497 #define       MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
6498 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
6499 #define        MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
6500 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
6501 #define        MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
6502 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
6503 #define        MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
6504 
6505 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
6506 #define    MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
6507 #define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
6508 #define       MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
6509 
6510 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
6511 #define    MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
6512 
6513 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
6514 #define    MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
6515 #define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
6516 #define       MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
6517 
6518 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
6519 #define    MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
6520 
6521 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
6522 #define    MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
6523 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
6524 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
6525 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
6526 #define       MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
6527 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
6528 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
6529 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
6530 #define        MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
6531 
6532 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
6533 #define    MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
6534 #define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
6535 #define       MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
6536 
6537 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
6538 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
6539 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
6540 #define    MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
6541 /* in bytes */
6542 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
6543 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
6544 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
6545 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
6546 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
6547 #define       MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
6548 
6549 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
6550 #define    MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
6551 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
6552 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
6553 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
6554 #define       MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
6555 
6556 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
6557 #define    MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
6558 #define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
6559 #define       MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
6560 
6561 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
6562 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
6563 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
6564 #define    MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
6565 /* Discrete (soldered) DDR resistor strap info */
6566 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
6567 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
6568 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
6569 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
6570 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
6571 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
6572 /* Number of SODIMM info records */
6573 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
6574 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
6575 /* Array of SODIMM info records */
6576 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
6577 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
6578 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
6579 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
6580 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
6581 #define       MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
6582 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
6583 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
6584 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
6585 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
6586 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
6587 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
6588 /* enum: Total number of SODIMM banks */
6589 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
6590 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
6591 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
6592 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
6593 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
6594 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
6595 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
6596 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
6597 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
6598 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
6599 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
6600 /* enum: Values 5-15 are reserved for future usage */
6601 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
6602 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
6603 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
6604 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
6605 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
6606 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
6607 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
6608 /* enum: No module present */
6609 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
6610 /* enum: Module present supported and powered on */
6611 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
6612 /* enum: Module present but bad type */
6613 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
6614 /* enum: Module present but incompatible voltage */
6615 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
6616 /* enum: Module present but unknown SPD */
6617 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
6618 /* enum: Module present but slot cannot support it */
6619 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
6620 /* enum: Modules may or may not be present, but cannot establish contact by I2C
6621  */
6622 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
6623 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
6624 #define        MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
6625 
6626 /* MC_CMD_RESOURCE_SPECIFIER enum */
6627 /* enum: Any */
6628 #define          MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
6629 /* enum: None */
6630 #define          MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
6631 
6632 /* EVB_PORT_ID structuredef */
6633 #define    EVB_PORT_ID_LEN 4
6634 #define       EVB_PORT_ID_PORT_ID_OFST 0
6635 #define       EVB_PORT_ID_PORT_ID_LEN 4
6636 /* enum: An invalid port handle. */
6637 #define          EVB_PORT_ID_NULL 0x0
6638 /* enum: The port assigned to this function.. */
6639 #define          EVB_PORT_ID_ASSIGNED 0x1000000
6640 /* enum: External network port 0 */
6641 #define          EVB_PORT_ID_MAC0 0x2000000
6642 /* enum: External network port 1 */
6643 #define          EVB_PORT_ID_MAC1 0x2000001
6644 /* enum: External network port 2 */
6645 #define          EVB_PORT_ID_MAC2 0x2000002
6646 /* enum: External network port 3 */
6647 #define          EVB_PORT_ID_MAC3 0x2000003
6648 #define       EVB_PORT_ID_PORT_ID_LBN 0
6649 #define       EVB_PORT_ID_PORT_ID_WIDTH 32
6650 
6651 /* EVB_VLAN_TAG structuredef */
6652 #define    EVB_VLAN_TAG_LEN 2
6653 /* The VLAN tag value */
6654 #define       EVB_VLAN_TAG_VLAN_ID_LBN 0
6655 #define       EVB_VLAN_TAG_VLAN_ID_WIDTH 12
6656 #define       EVB_VLAN_TAG_MODE_LBN 12
6657 #define       EVB_VLAN_TAG_MODE_WIDTH 4
6658 /* enum: Insert the VLAN. */
6659 #define          EVB_VLAN_TAG_INSERT 0x0
6660 /* enum: Replace the VLAN if already present. */
6661 #define          EVB_VLAN_TAG_REPLACE 0x1
6662 
6663 /* BUFTBL_ENTRY structuredef */
6664 #define    BUFTBL_ENTRY_LEN 12
6665 /* the owner ID */
6666 #define       BUFTBL_ENTRY_OID_OFST 0
6667 #define       BUFTBL_ENTRY_OID_LEN 2
6668 #define       BUFTBL_ENTRY_OID_LBN 0
6669 #define       BUFTBL_ENTRY_OID_WIDTH 16
6670 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
6671 #define       BUFTBL_ENTRY_PGSZ_OFST 2
6672 #define       BUFTBL_ENTRY_PGSZ_LEN 2
6673 #define       BUFTBL_ENTRY_PGSZ_LBN 16
6674 #define       BUFTBL_ENTRY_PGSZ_WIDTH 16
6675 /* the raw 64-bit address field from the SMC, not adjusted for page size */
6676 #define       BUFTBL_ENTRY_RAWADDR_OFST 4
6677 #define       BUFTBL_ENTRY_RAWADDR_LEN 8
6678 #define       BUFTBL_ENTRY_RAWADDR_LO_OFST 4
6679 #define       BUFTBL_ENTRY_RAWADDR_HI_OFST 8
6680 #define       BUFTBL_ENTRY_RAWADDR_LBN 32
6681 #define       BUFTBL_ENTRY_RAWADDR_WIDTH 64
6682 
6683 /* NVRAM_PARTITION_TYPE structuredef */
6684 #define    NVRAM_PARTITION_TYPE_LEN 2
6685 #define       NVRAM_PARTITION_TYPE_ID_OFST 0
6686 #define       NVRAM_PARTITION_TYPE_ID_LEN 2
6687 /* enum: Primary MC firmware partition */
6688 #define          NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
6689 /* enum: Secondary MC firmware partition */
6690 #define          NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
6691 /* enum: Expansion ROM partition */
6692 #define          NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
6693 /* enum: Static configuration TLV partition */
6694 #define          NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
6695 /* enum: Dynamic configuration TLV partition */
6696 #define          NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
6697 /* enum: Expansion ROM configuration data for port 0 */
6698 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
6699 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
6700 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
6701 /* enum: Expansion ROM configuration data for port 1 */
6702 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
6703 /* enum: Expansion ROM configuration data for port 2 */
6704 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
6705 /* enum: Expansion ROM configuration data for port 3 */
6706 #define          NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
6707 /* enum: Non-volatile log output partition */
6708 #define          NVRAM_PARTITION_TYPE_LOG 0x700
6709 /* enum: Non-volatile log output of second core on dual-core device */
6710 #define          NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
6711 /* enum: Device state dump output partition */
6712 #define          NVRAM_PARTITION_TYPE_DUMP 0x800
6713 /* enum: Application license key storage partition */
6714 #define          NVRAM_PARTITION_TYPE_LICENSE 0x900
6715 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
6716 #define          NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
6717 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
6718 #define          NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
6719 /* enum: Primary FPGA partition */
6720 #define          NVRAM_PARTITION_TYPE_FPGA 0xb00
6721 /* enum: Secondary FPGA partition */
6722 #define          NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
6723 /* enum: FC firmware partition */
6724 #define          NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
6725 /* enum: FC License partition */
6726 #define          NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
6727 /* enum: Non-volatile log output partition for FC */
6728 #define          NVRAM_PARTITION_TYPE_FC_LOG 0xb04
6729 /* enum: MUM firmware partition */
6730 #define          NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
6731 /* enum: SUC firmware partition (this is intentionally an alias of
6732  * MUM_FIRMWARE)
6733  */
6734 #define          NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
6735 /* enum: MUM Non-volatile log output partition. */
6736 #define          NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
6737 /* enum: MUM Application table partition. */
6738 #define          NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
6739 /* enum: MUM boot rom partition. */
6740 #define          NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
6741 /* enum: MUM production signatures & calibration rom partition. */
6742 #define          NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
6743 /* enum: MUM user signatures & calibration rom partition. */
6744 #define          NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
6745 /* enum: MUM fuses and lockbits partition. */
6746 #define          NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
6747 /* enum: UEFI expansion ROM if separate from PXE */
6748 #define          NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
6749 /* enum: Used by the expansion ROM for logging */
6750 #define          NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
6751 /* enum: Used for XIP code of shmbooted images */
6752 #define          NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
6753 /* enum: Spare partition 2 */
6754 #define          NVRAM_PARTITION_TYPE_SPARE_2 0x1200
6755 /* enum: Manufacturing partition. Used during manufacture to pass information
6756  * between XJTAG and Manftest.
6757  */
6758 #define          NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
6759 /* enum: Spare partition 4 */
6760 #define          NVRAM_PARTITION_TYPE_SPARE_4 0x1400
6761 /* enum: Spare partition 5 */
6762 #define          NVRAM_PARTITION_TYPE_SPARE_5 0x1500
6763 /* enum: Partition for reporting MC status. See mc_flash_layout.h
6764  * medford_mc_status_hdr_t for layout on Medford.
6765  */
6766 #define          NVRAM_PARTITION_TYPE_STATUS 0x1600
6767 /* enum: Spare partition 13 */
6768 #define          NVRAM_PARTITION_TYPE_SPARE_13 0x1700
6769 /* enum: Spare partition 14 */
6770 #define          NVRAM_PARTITION_TYPE_SPARE_14 0x1800
6771 /* enum: Spare partition 15 */
6772 #define          NVRAM_PARTITION_TYPE_SPARE_15 0x1900
6773 /* enum: Spare partition 16 */
6774 #define          NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
6775 /* enum: Factory defaults for dynamic configuration */
6776 #define          NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
6777 /* enum: Factory defaults for expansion ROM configuration */
6778 #define          NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
6779 /* enum: Field Replaceable Unit inventory information for use on IPMI
6780  * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
6781  * subset of the information stored in this partition.
6782  */
6783 #define          NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
6784 /* enum: Bundle image partition */
6785 #define          NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
6786 /* enum: Bundle metadata partition that holds additional information related to
6787  * a bundle update in TLV format
6788  */
6789 #define          NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
6790 /* enum: Bundle update non-volatile log output partition */
6791 #define          NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
6792 /* enum: Start of reserved value range (firmware may use for any purpose) */
6793 #define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
6794 /* enum: End of reserved value range (firmware may use for any purpose) */
6795 #define          NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
6796 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
6797 #define          NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
6798 /* enum: Partition map (real map as stored in flash) */
6799 #define          NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
6800 #define       NVRAM_PARTITION_TYPE_ID_LBN 0
6801 #define       NVRAM_PARTITION_TYPE_ID_WIDTH 16
6802 
6803 /* LICENSED_APP_ID structuredef */
6804 #define    LICENSED_APP_ID_LEN 4
6805 #define       LICENSED_APP_ID_ID_OFST 0
6806 #define       LICENSED_APP_ID_ID_LEN 4
6807 /* enum: OpenOnload */
6808 #define          LICENSED_APP_ID_ONLOAD 0x1
6809 /* enum: PTP timestamping */
6810 #define          LICENSED_APP_ID_PTP 0x2
6811 /* enum: SolarCapture Pro */
6812 #define          LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
6813 /* enum: SolarSecure filter engine */
6814 #define          LICENSED_APP_ID_SOLARSECURE 0x8
6815 /* enum: Performance monitor */
6816 #define          LICENSED_APP_ID_PERF_MONITOR 0x10
6817 /* enum: SolarCapture Live */
6818 #define          LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
6819 /* enum: Capture SolarSystem */
6820 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
6821 /* enum: Network Access Control */
6822 #define          LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
6823 /* enum: TCP Direct */
6824 #define          LICENSED_APP_ID_TCP_DIRECT 0x100
6825 /* enum: Low Latency */
6826 #define          LICENSED_APP_ID_LOW_LATENCY 0x200
6827 /* enum: SolarCapture Tap */
6828 #define          LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
6829 /* enum: Capture SolarSystem 40G */
6830 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
6831 /* enum: Capture SolarSystem 1G */
6832 #define          LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
6833 /* enum: ScaleOut Onload */
6834 #define          LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
6835 /* enum: SCS Network Analytics Dashboard */
6836 #define          LICENSED_APP_ID_DSHBRD 0x4000
6837 /* enum: SolarCapture Trading Analytics */
6838 #define          LICENSED_APP_ID_SCATRD 0x8000
6839 #define       LICENSED_APP_ID_ID_LBN 0
6840 #define       LICENSED_APP_ID_ID_WIDTH 32
6841 
6842 /* LICENSED_FEATURES structuredef */
6843 #define    LICENSED_FEATURES_LEN 8
6844 /* Bitmask of licensed firmware features */
6845 #define       LICENSED_FEATURES_MASK_OFST 0
6846 #define       LICENSED_FEATURES_MASK_LEN 8
6847 #define       LICENSED_FEATURES_MASK_LO_OFST 0
6848 #define       LICENSED_FEATURES_MASK_HI_OFST 4
6849 #define        LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
6850 #define        LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
6851 #define        LICENSED_FEATURES_PIO_LBN 1
6852 #define        LICENSED_FEATURES_PIO_WIDTH 1
6853 #define        LICENSED_FEATURES_EVQ_TIMER_LBN 2
6854 #define        LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
6855 #define        LICENSED_FEATURES_CLOCK_LBN 3
6856 #define        LICENSED_FEATURES_CLOCK_WIDTH 1
6857 #define        LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
6858 #define        LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
6859 #define        LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
6860 #define        LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
6861 #define        LICENSED_FEATURES_RX_SNIFF_LBN 6
6862 #define        LICENSED_FEATURES_RX_SNIFF_WIDTH 1
6863 #define        LICENSED_FEATURES_TX_SNIFF_LBN 7
6864 #define        LICENSED_FEATURES_TX_SNIFF_WIDTH 1
6865 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
6866 #define        LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6867 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
6868 #define        LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6869 #define       LICENSED_FEATURES_MASK_LBN 0
6870 #define       LICENSED_FEATURES_MASK_WIDTH 64
6871 
6872 /* LICENSED_V3_APPS structuredef */
6873 #define    LICENSED_V3_APPS_LEN 8
6874 /* Bitmask of licensed applications */
6875 #define       LICENSED_V3_APPS_MASK_OFST 0
6876 #define       LICENSED_V3_APPS_MASK_LEN 8
6877 #define       LICENSED_V3_APPS_MASK_LO_OFST 0
6878 #define       LICENSED_V3_APPS_MASK_HI_OFST 4
6879 #define        LICENSED_V3_APPS_ONLOAD_LBN 0
6880 #define        LICENSED_V3_APPS_ONLOAD_WIDTH 1
6881 #define        LICENSED_V3_APPS_PTP_LBN 1
6882 #define        LICENSED_V3_APPS_PTP_WIDTH 1
6883 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
6884 #define        LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
6885 #define        LICENSED_V3_APPS_SOLARSECURE_LBN 3
6886 #define        LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
6887 #define        LICENSED_V3_APPS_PERF_MONITOR_LBN 4
6888 #define        LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
6889 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
6890 #define        LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
6891 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
6892 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
6893 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
6894 #define        LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
6895 #define        LICENSED_V3_APPS_TCP_DIRECT_LBN 8
6896 #define        LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
6897 #define        LICENSED_V3_APPS_LOW_LATENCY_LBN 9
6898 #define        LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
6899 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
6900 #define        LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
6901 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
6902 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
6903 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
6904 #define        LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
6905 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
6906 #define        LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
6907 #define        LICENSED_V3_APPS_DSHBRD_LBN 14
6908 #define        LICENSED_V3_APPS_DSHBRD_WIDTH 1
6909 #define        LICENSED_V3_APPS_SCATRD_LBN 15
6910 #define        LICENSED_V3_APPS_SCATRD_WIDTH 1
6911 #define       LICENSED_V3_APPS_MASK_LBN 0
6912 #define       LICENSED_V3_APPS_MASK_WIDTH 64
6913 
6914 /* LICENSED_V3_FEATURES structuredef */
6915 #define    LICENSED_V3_FEATURES_LEN 8
6916 /* Bitmask of licensed firmware features */
6917 #define       LICENSED_V3_FEATURES_MASK_OFST 0
6918 #define       LICENSED_V3_FEATURES_MASK_LEN 8
6919 #define       LICENSED_V3_FEATURES_MASK_LO_OFST 0
6920 #define       LICENSED_V3_FEATURES_MASK_HI_OFST 4
6921 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
6922 #define        LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
6923 #define        LICENSED_V3_FEATURES_PIO_LBN 1
6924 #define        LICENSED_V3_FEATURES_PIO_WIDTH 1
6925 #define        LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
6926 #define        LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
6927 #define        LICENSED_V3_FEATURES_CLOCK_LBN 3
6928 #define        LICENSED_V3_FEATURES_CLOCK_WIDTH 1
6929 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
6930 #define        LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
6931 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
6932 #define        LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
6933 #define        LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
6934 #define        LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
6935 #define        LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
6936 #define        LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
6937 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
6938 #define        LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6939 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
6940 #define        LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6941 #define       LICENSED_V3_FEATURES_MASK_LBN 0
6942 #define       LICENSED_V3_FEATURES_MASK_WIDTH 64
6943 
6944 /* TX_TIMESTAMP_EVENT structuredef */
6945 #define    TX_TIMESTAMP_EVENT_LEN 6
6946 /* lower 16 bits of timestamp data */
6947 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
6948 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
6949 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
6950 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
6951 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp
6952  */
6953 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
6954 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
6955 /* enum: This is a TX completion event, not a timestamp */
6956 #define          TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
6957 /* enum: This is a TX completion event for a CTPIO transmit. The event format
6958  * is the same as for TX_EV_COMPLETION.
6959  */
6960 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
6961 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
6962  * event format is the same as for TX_EV_TSTAMP_LO
6963  */
6964 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
6965 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
6966  * event format is the same as for TX_EV_TSTAMP_HI
6967  */
6968 #define          TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
6969 /* enum: This is the low part of a TX timestamp event */
6970 #define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
6971 /* enum: This is the high part of a TX timestamp event */
6972 #define          TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
6973 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
6974 #define       TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
6975 /* upper 16 bits of timestamp data */
6976 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
6977 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
6978 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
6979 #define       TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
6980 
6981 /* RSS_MODE structuredef */
6982 #define    RSS_MODE_LEN 1
6983 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
6984  * be considered as 4 bits selecting which fields are included in the hash. (A
6985  * value 0 effectively disables RSS spreading for the packet type.) The YAML
6986  * generation tools require this structure to be a whole number of bytes wide,
6987  * but only 4 bits are relevant.
6988  */
6989 #define       RSS_MODE_HASH_SELECTOR_OFST 0
6990 #define       RSS_MODE_HASH_SELECTOR_LEN 1
6991 #define        RSS_MODE_HASH_SRC_ADDR_LBN 0
6992 #define        RSS_MODE_HASH_SRC_ADDR_WIDTH 1
6993 #define        RSS_MODE_HASH_DST_ADDR_LBN 1
6994 #define        RSS_MODE_HASH_DST_ADDR_WIDTH 1
6995 #define        RSS_MODE_HASH_SRC_PORT_LBN 2
6996 #define        RSS_MODE_HASH_SRC_PORT_WIDTH 1
6997 #define        RSS_MODE_HASH_DST_PORT_LBN 3
6998 #define        RSS_MODE_HASH_DST_PORT_WIDTH 1
6999 #define       RSS_MODE_HASH_SELECTOR_LBN 0
7000 #define       RSS_MODE_HASH_SELECTOR_WIDTH 8
7001 
7002 /* CTPIO_STATS_MAP structuredef */
7003 #define    CTPIO_STATS_MAP_LEN 4
7004 /* The (function relative) VI number */
7005 #define       CTPIO_STATS_MAP_VI_OFST 0
7006 #define       CTPIO_STATS_MAP_VI_LEN 2
7007 #define       CTPIO_STATS_MAP_VI_LBN 0
7008 #define       CTPIO_STATS_MAP_VI_WIDTH 16
7009 /* The target bucket for the VI */
7010 #define       CTPIO_STATS_MAP_BUCKET_OFST 2
7011 #define       CTPIO_STATS_MAP_BUCKET_LEN 2
7012 #define       CTPIO_STATS_MAP_BUCKET_LBN 16
7013 #define       CTPIO_STATS_MAP_BUCKET_WIDTH 16
7014 
7015 
7016 /***********************************/
7017 /* MC_CMD_READ_REGS
7018  * Get a dump of the MCPU registers
7019  */
7020 #define MC_CMD_READ_REGS 0x50
7021 
7022 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
7023 
7024 /* MC_CMD_READ_REGS_IN msgrequest */
7025 #define    MC_CMD_READ_REGS_IN_LEN 0
7026 
7027 /* MC_CMD_READ_REGS_OUT msgresponse */
7028 #define    MC_CMD_READ_REGS_OUT_LEN 308
7029 /* Whether the corresponding register entry contains a valid value */
7030 #define       MC_CMD_READ_REGS_OUT_MASK_OFST 0
7031 #define       MC_CMD_READ_REGS_OUT_MASK_LEN 16
7032 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
7033  * fir, fp)
7034  */
7035 #define       MC_CMD_READ_REGS_OUT_REGS_OFST 16
7036 #define       MC_CMD_READ_REGS_OUT_REGS_LEN 4
7037 #define       MC_CMD_READ_REGS_OUT_REGS_NUM 73
7038 
7039 
7040 /***********************************/
7041 /* MC_CMD_INIT_EVQ
7042  * Set up an event queue according to the supplied parameters. The IN arguments
7043  * end with an address for each 4k of host memory required to back the EVQ.
7044  */
7045 #define MC_CMD_INIT_EVQ 0x80
7046 
7047 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7048 
7049 /* MC_CMD_INIT_EVQ_IN msgrequest */
7050 #define    MC_CMD_INIT_EVQ_IN_LENMIN 44
7051 #define    MC_CMD_INIT_EVQ_IN_LENMAX 548
7052 #define    MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
7053 /* Size, in entries */
7054 #define       MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
7055 #define       MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
7056 /* Desired instance. Must be set to a specific instance, which is a function
7057  * local queue index.
7058  */
7059 #define       MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
7060 #define       MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
7061 /* The initial timer value. The load value is ignored if the timer mode is DIS.
7062  */
7063 #define       MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
7064 #define       MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
7065 /* The reload value is ignored in one-shot modes */
7066 #define       MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
7067 #define       MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
7068 /* tbd */
7069 #define       MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
7070 #define       MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
7071 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
7072 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
7073 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
7074 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
7075 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
7076 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
7077 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
7078 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
7079 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
7080 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
7081 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
7082 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
7083 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
7084 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
7085 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
7086 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
7087 /* enum: Disabled */
7088 #define          MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
7089 /* enum: Immediate */
7090 #define          MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
7091 /* enum: Triggered */
7092 #define          MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
7093 /* enum: Hold-off */
7094 #define          MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
7095 /* Target EVQ for wakeups if in wakeup mode. */
7096 #define       MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
7097 #define       MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
7098 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
7099  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
7100  * purposes.
7101  */
7102 #define       MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
7103 #define       MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
7104 /* Event Counter Mode. */
7105 #define       MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
7106 #define       MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
7107 /* enum: Disabled */
7108 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
7109 /* enum: Disabled */
7110 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
7111 /* enum: Disabled */
7112 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
7113 /* enum: Disabled */
7114 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
7115 /* Event queue packet count threshold. */
7116 #define       MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
7117 #define       MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
7118 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7119 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
7120 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
7121 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
7122 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
7123 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
7124 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
7125 
7126 /* MC_CMD_INIT_EVQ_OUT msgresponse */
7127 #define    MC_CMD_INIT_EVQ_OUT_LEN 4
7128 /* Only valid if INTRFLAG was true */
7129 #define       MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
7130 #define       MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
7131 
7132 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
7133 #define    MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
7134 #define    MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
7135 #define    MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
7136 /* Size, in entries */
7137 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
7138 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
7139 /* Desired instance. Must be set to a specific instance, which is a function
7140  * local queue index.
7141  */
7142 #define       MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
7143 #define       MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
7144 /* The initial timer value. The load value is ignored if the timer mode is DIS.
7145  */
7146 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
7147 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
7148 /* The reload value is ignored in one-shot modes */
7149 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
7150 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
7151 /* tbd */
7152 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
7153 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
7154 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
7155 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
7156 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
7157 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
7158 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
7159 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
7160 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
7161 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
7162 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
7163 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
7164 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
7165 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
7166 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
7167 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
7168 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
7169 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
7170 /* enum: All initialisation flags specified by host. */
7171 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
7172 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7173  * over-ridden by firmware based on licenses and firmware variant in order to
7174  * provide the lowest latency achievable. See
7175  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7176  */
7177 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
7178 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7179  * over-ridden by firmware based on licenses and firmware variant in order to
7180  * provide the best throughput achievable. See
7181  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7182  */
7183 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
7184 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
7185  * firmware based on licenses and firmware variant. See
7186  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
7187  */
7188 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
7189 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
7190 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
7191 /* enum: Disabled */
7192 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
7193 /* enum: Immediate */
7194 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
7195 /* enum: Triggered */
7196 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
7197 /* enum: Hold-off */
7198 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
7199 /* Target EVQ for wakeups if in wakeup mode. */
7200 #define       MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
7201 #define       MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
7202 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
7203  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
7204  * purposes.
7205  */
7206 #define       MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
7207 #define       MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
7208 /* Event Counter Mode. */
7209 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
7210 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
7211 /* enum: Disabled */
7212 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
7213 /* enum: Disabled */
7214 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
7215 /* enum: Disabled */
7216 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
7217 /* enum: Disabled */
7218 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
7219 /* Event queue packet count threshold. */
7220 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
7221 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
7222 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7223 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
7224 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
7225 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
7226 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
7227 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
7228 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
7229 
7230 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
7231 #define    MC_CMD_INIT_EVQ_V2_OUT_LEN 8
7232 /* Only valid if INTRFLAG was true */
7233 #define       MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
7234 #define       MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
7235 /* Actual configuration applied on the card */
7236 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
7237 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
7238 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
7239 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
7240 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
7241 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
7242 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
7243 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
7244 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
7245 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
7246 
7247 /* QUEUE_CRC_MODE structuredef */
7248 #define    QUEUE_CRC_MODE_LEN 1
7249 #define       QUEUE_CRC_MODE_MODE_LBN 0
7250 #define       QUEUE_CRC_MODE_MODE_WIDTH 4
7251 /* enum: No CRC. */
7252 #define          QUEUE_CRC_MODE_NONE 0x0
7253 /* enum: CRC Fiber channel over ethernet. */
7254 #define          QUEUE_CRC_MODE_FCOE 0x1
7255 /* enum: CRC (digest) iSCSI header only. */
7256 #define          QUEUE_CRC_MODE_ISCSI_HDR 0x2
7257 /* enum: CRC (digest) iSCSI header and payload. */
7258 #define          QUEUE_CRC_MODE_ISCSI 0x3
7259 /* enum: CRC Fiber channel over IP over ethernet. */
7260 #define          QUEUE_CRC_MODE_FCOIPOE 0x4
7261 /* enum: CRC MPA. */
7262 #define          QUEUE_CRC_MODE_MPA 0x5
7263 #define       QUEUE_CRC_MODE_SPARE_LBN 4
7264 #define       QUEUE_CRC_MODE_SPARE_WIDTH 4
7265 
7266 
7267 /***********************************/
7268 /* MC_CMD_INIT_RXQ
7269  * set up a receive queue according to the supplied parameters. The IN
7270  * arguments end with an address for each 4k of host memory required to back
7271  * the RXQ.
7272  */
7273 #define MC_CMD_INIT_RXQ 0x81
7274 
7275 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7276 
7277 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
7278  * in new code.
7279  */
7280 #define    MC_CMD_INIT_RXQ_IN_LENMIN 36
7281 #define    MC_CMD_INIT_RXQ_IN_LENMAX 252
7282 #define    MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
7283 /* Size, in entries */
7284 #define       MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
7285 #define       MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
7286 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
7287  */
7288 #define       MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
7289 #define       MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
7290 /* The value to put in the event data. Check hardware spec. for valid range. */
7291 #define       MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
7292 #define       MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
7293 /* Desired instance. Must be set to a specific instance, which is a function
7294  * local queue index.
7295  */
7296 #define       MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
7297 #define       MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
7298 /* There will be more flags here. */
7299 #define       MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
7300 #define       MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
7301 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
7302 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7303 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
7304 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
7305 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
7306 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7307 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
7308 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
7309 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
7310 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
7311 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
7312 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
7313 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
7314 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7315 #define        MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
7316 #define        MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
7317 /* Owner ID to use if in buffer mode (zero if physical) */
7318 #define       MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
7319 #define       MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
7320 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7321 #define       MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
7322 #define       MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
7323 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7324 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
7325 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
7326 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
7327 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
7328 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
7329 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
7330 
7331 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
7332  * flags
7333  */
7334 #define    MC_CMD_INIT_RXQ_EXT_IN_LEN 544
7335 /* Size, in entries */
7336 #define       MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
7337 #define       MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
7338 /* The EVQ to send events to. This is an index originally specified to
7339  * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
7340  */
7341 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
7342 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
7343 /* The value to put in the event data. Check hardware spec. for valid range.
7344  * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
7345  * == PACKED_STREAM.
7346  */
7347 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
7348 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
7349 /* Desired instance. Must be set to a specific instance, which is a function
7350  * local queue index.
7351  */
7352 #define       MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
7353 #define       MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
7354 /* There will be more flags here. */
7355 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
7356 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
7357 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7358 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7359 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
7360 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
7361 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
7362 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7363 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
7364 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
7365 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
7366 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
7367 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
7368 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
7369 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
7370 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7371 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
7372 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
7373 /* enum: One packet per descriptor (for normal networking) */
7374 #define          MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
7375 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7376 #define          MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
7377 /* enum: Pack multiple packets into large descriptors using the format designed
7378  * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
7379  * multiple fixed-size packet buffers within each bucket. For a full
7380  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
7381  * firmware.
7382  */
7383 #define          MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7384 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
7385 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
7386 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
7387 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
7388 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
7389 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
7390 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
7391 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
7392 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
7393 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
7394 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
7395 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
7396 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
7397 /* Owner ID to use if in buffer mode (zero if physical) */
7398 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
7399 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
7400 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7401 #define       MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
7402 #define       MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
7403 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7404 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
7405 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
7406 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7407 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7408 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
7409 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
7410 #define       MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
7411 #define       MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
7412 
7413 /* MC_CMD_INIT_RXQ_V3_IN msgrequest */
7414 #define    MC_CMD_INIT_RXQ_V3_IN_LEN 560
7415 /* Size, in entries */
7416 #define       MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
7417 #define       MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
7418 /* The EVQ to send events to. This is an index originally specified to
7419  * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
7420  */
7421 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
7422 #define       MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
7423 /* The value to put in the event data. Check hardware spec. for valid range.
7424  * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE
7425  * == PACKED_STREAM.
7426  */
7427 #define       MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
7428 #define       MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
7429 /* Desired instance. Must be set to a specific instance, which is a function
7430  * local queue index.
7431  */
7432 #define       MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
7433 #define       MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
7434 /* There will be more flags here. */
7435 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
7436 #define       MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
7437 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
7438 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
7439 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
7440 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
7441 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
7442 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
7443 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
7444 #define        MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
7445 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
7446 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
7447 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
7448 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
7449 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
7450 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7451 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
7452 #define        MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
7453 /* enum: One packet per descriptor (for normal networking) */
7454 #define          MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
7455 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7456 #define          MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
7457 /* enum: Pack multiple packets into large descriptors using the format designed
7458  * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
7459  * multiple fixed-size packet buffers within each bucket. For a full
7460  * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
7461  * firmware.
7462  */
7463 #define          MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7464 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
7465 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
7466 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
7467 #define        MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
7468 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
7469 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
7470 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
7471 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
7472 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
7473 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
7474 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
7475 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
7476 #define        MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
7477 /* Owner ID to use if in buffer mode (zero if physical) */
7478 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
7479 #define       MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
7480 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7481 #define       MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
7482 #define       MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
7483 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7484 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
7485 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
7486 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
7487 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
7488 #define       MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
7489 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
7490 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
7491 #define       MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
7492 /* The number of packet buffers that will be contained within each
7493  * EQUAL_STRIDE_PACKED_STREAM format bucket supplied by the driver. This field
7494  * is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7495  */
7496 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
7497 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
7498 /* The length in bytes of the area in each packet buffer that can be written to
7499  * by the adapter. This is used to store the packet prefix and the packet
7500  * payload. This length does not include any end padding added by the driver.
7501  * This field is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7502  */
7503 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
7504 #define       MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
7505 /* The length in bytes of a single packet buffer within a
7506  * EQUAL_STRIDE_PACKED_STREAM format bucket. This field is ignored unless
7507  * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7508  */
7509 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
7510 #define       MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
7511 /* The maximum time in nanoseconds that the datapath will be backpressured if
7512  * there are no RX descriptors available. If the timeout is reached and there
7513  * are still no descriptors then the packet will be dropped. A timeout of 0
7514  * means the datapath will never be blocked. This field is ignored unless
7515  * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.
7516  */
7517 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
7518 #define       MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
7519 
7520 /* MC_CMD_INIT_RXQ_OUT msgresponse */
7521 #define    MC_CMD_INIT_RXQ_OUT_LEN 0
7522 
7523 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
7524 #define    MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
7525 
7526 /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
7527 #define    MC_CMD_INIT_RXQ_V3_OUT_LEN 0
7528 
7529 
7530 /***********************************/
7531 /* MC_CMD_INIT_TXQ
7532  */
7533 #define MC_CMD_INIT_TXQ 0x82
7534 
7535 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7536 
7537 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
7538  * in new code.
7539  */
7540 #define    MC_CMD_INIT_TXQ_IN_LENMIN 36
7541 #define    MC_CMD_INIT_TXQ_IN_LENMAX 252
7542 #define    MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
7543 /* Size, in entries */
7544 #define       MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
7545 #define       MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
7546 /* The EVQ to send events to. This is an index originally specified to
7547  * INIT_EVQ.
7548  */
7549 #define       MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
7550 #define       MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
7551 /* The value to put in the event data. Check hardware spec. for valid range. */
7552 #define       MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
7553 #define       MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
7554 /* Desired instance. Must be set to a specific instance, which is a function
7555  * local queue index.
7556  */
7557 #define       MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
7558 #define       MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
7559 /* There will be more flags here. */
7560 #define       MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
7561 #define       MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
7562 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
7563 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7564 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
7565 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7566 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
7567 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7568 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
7569 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7570 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
7571 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
7572 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
7573 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7574 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
7575 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
7576 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7577 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7578 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7579 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7580 /* Owner ID to use if in buffer mode (zero if physical) */
7581 #define       MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
7582 #define       MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
7583 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7584 #define       MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
7585 #define       MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
7586 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7587 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
7588 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
7589 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
7590 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
7591 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
7592 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
7593 
7594 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
7595  * flags
7596  */
7597 #define    MC_CMD_INIT_TXQ_EXT_IN_LEN 544
7598 /* Size, in entries */
7599 #define       MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
7600 #define       MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
7601 /* The EVQ to send events to. This is an index originally specified to
7602  * INIT_EVQ.
7603  */
7604 #define       MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
7605 #define       MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
7606 /* The value to put in the event data. Check hardware spec. for valid range. */
7607 #define       MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
7608 #define       MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
7609 /* Desired instance. Must be set to a specific instance, which is a function
7610  * local queue index.
7611  */
7612 #define       MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
7613 #define       MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
7614 /* There will be more flags here. */
7615 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
7616 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
7617 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7618 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7619 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
7620 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7621 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
7622 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7623 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
7624 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7625 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
7626 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
7627 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
7628 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7629 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
7630 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
7631 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7632 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7633 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7634 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7635 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
7636 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
7637 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
7638 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
7639 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
7640 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
7641 /* Owner ID to use if in buffer mode (zero if physical) */
7642 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
7643 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
7644 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7645 #define       MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
7646 #define       MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
7647 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7648 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
7649 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
7650 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7651 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7652 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
7653 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
7654 /* Flags related to Qbb flow control mode. */
7655 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
7656 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
7657 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
7658 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
7659 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
7660 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
7661 
7662 /* MC_CMD_INIT_TXQ_OUT msgresponse */
7663 #define    MC_CMD_INIT_TXQ_OUT_LEN 0
7664 
7665 
7666 /***********************************/
7667 /* MC_CMD_FINI_EVQ
7668  * Teardown an EVQ.
7669  *
7670  * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
7671  * or the operation will fail with EBUSY
7672  */
7673 #define MC_CMD_FINI_EVQ 0x83
7674 
7675 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7676 
7677 /* MC_CMD_FINI_EVQ_IN msgrequest */
7678 #define    MC_CMD_FINI_EVQ_IN_LEN 4
7679 /* Instance of EVQ to destroy. Should be the same instance as that previously
7680  * passed to INIT_EVQ
7681  */
7682 #define       MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
7683 #define       MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
7684 
7685 /* MC_CMD_FINI_EVQ_OUT msgresponse */
7686 #define    MC_CMD_FINI_EVQ_OUT_LEN 0
7687 
7688 
7689 /***********************************/
7690 /* MC_CMD_FINI_RXQ
7691  * Teardown a RXQ.
7692  */
7693 #define MC_CMD_FINI_RXQ 0x84
7694 
7695 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7696 
7697 /* MC_CMD_FINI_RXQ_IN msgrequest */
7698 #define    MC_CMD_FINI_RXQ_IN_LEN 4
7699 /* Instance of RXQ to destroy */
7700 #define       MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
7701 #define       MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
7702 
7703 /* MC_CMD_FINI_RXQ_OUT msgresponse */
7704 #define    MC_CMD_FINI_RXQ_OUT_LEN 0
7705 
7706 
7707 /***********************************/
7708 /* MC_CMD_FINI_TXQ
7709  * Teardown a TXQ.
7710  */
7711 #define MC_CMD_FINI_TXQ 0x85
7712 
7713 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7714 
7715 /* MC_CMD_FINI_TXQ_IN msgrequest */
7716 #define    MC_CMD_FINI_TXQ_IN_LEN 4
7717 /* Instance of TXQ to destroy */
7718 #define       MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
7719 #define       MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
7720 
7721 /* MC_CMD_FINI_TXQ_OUT msgresponse */
7722 #define    MC_CMD_FINI_TXQ_OUT_LEN 0
7723 
7724 
7725 /***********************************/
7726 /* MC_CMD_DRIVER_EVENT
7727  * Generate an event on an EVQ belonging to the function issuing the command.
7728  */
7729 #define MC_CMD_DRIVER_EVENT 0x86
7730 
7731 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7732 
7733 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
7734 #define    MC_CMD_DRIVER_EVENT_IN_LEN 12
7735 /* Handle of target EVQ */
7736 #define       MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
7737 #define       MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
7738 /* Bits 0 - 63 of event */
7739 #define       MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
7740 #define       MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
7741 #define       MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
7742 #define       MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
7743 
7744 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */
7745 #define    MC_CMD_DRIVER_EVENT_OUT_LEN 0
7746 
7747 
7748 /***********************************/
7749 /* MC_CMD_PROXY_CMD
7750  * Execute an arbitrary MCDI command on behalf of a different function, subject
7751  * to security restrictions. The command to be proxied follows immediately
7752  * afterward in the host buffer (or on the UART). This command supercedes
7753  * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
7754  */
7755 #define MC_CMD_PROXY_CMD 0x5b
7756 
7757 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7758 
7759 /* MC_CMD_PROXY_CMD_IN msgrequest */
7760 #define    MC_CMD_PROXY_CMD_IN_LEN 4
7761 /* The handle of the target function. */
7762 #define       MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
7763 #define       MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
7764 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
7765 #define        MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
7766 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
7767 #define        MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
7768 #define          MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
7769 
7770 /* MC_CMD_PROXY_CMD_OUT msgresponse */
7771 #define    MC_CMD_PROXY_CMD_OUT_LEN 0
7772 
7773 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to
7774  * manage proxied requests
7775  */
7776 #define    MC_PROXY_STATUS_BUFFER_LEN 16
7777 /* Handle allocated by the firmware for this proxy transaction */
7778 #define       MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
7779 #define       MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
7780 /* enum: An invalid handle. */
7781 #define          MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
7782 #define       MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
7783 #define       MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
7784 /* The requesting physical function number */
7785 #define       MC_PROXY_STATUS_BUFFER_PF_OFST 4
7786 #define       MC_PROXY_STATUS_BUFFER_PF_LEN 2
7787 #define       MC_PROXY_STATUS_BUFFER_PF_LBN 32
7788 #define       MC_PROXY_STATUS_BUFFER_PF_WIDTH 16
7789 /* The requesting virtual function number. Set to VF_NULL if the target is a
7790  * PF.
7791  */
7792 #define       MC_PROXY_STATUS_BUFFER_VF_OFST 6
7793 #define       MC_PROXY_STATUS_BUFFER_VF_LEN 2
7794 #define       MC_PROXY_STATUS_BUFFER_VF_LBN 48
7795 #define       MC_PROXY_STATUS_BUFFER_VF_WIDTH 16
7796 /* The target function RID. */
7797 #define       MC_PROXY_STATUS_BUFFER_RID_OFST 8
7798 #define       MC_PROXY_STATUS_BUFFER_RID_LEN 2
7799 #define       MC_PROXY_STATUS_BUFFER_RID_LBN 64
7800 #define       MC_PROXY_STATUS_BUFFER_RID_WIDTH 16
7801 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */
7802 #define       MC_PROXY_STATUS_BUFFER_STATUS_OFST 10
7803 #define       MC_PROXY_STATUS_BUFFER_STATUS_LEN 2
7804 #define       MC_PROXY_STATUS_BUFFER_STATUS_LBN 80
7805 #define       MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16
7806 /* If a request is authorized rather than carried out by the host, this is the
7807  * elevated privilege mask granted to the requesting function.
7808  */
7809 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12
7810 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
7811 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96
7812 #define       MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32
7813 
7814 
7815 /***********************************/
7816 /* MC_CMD_PROXY_CONFIGURE
7817  * Enable/disable authorization of MCDI requests from unprivileged functions by
7818  * a designated admin function
7819  */
7820 #define MC_CMD_PROXY_CONFIGURE 0x58
7821 
7822 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7823 
7824 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */
7825 #define    MC_CMD_PROXY_CONFIGURE_IN_LEN 108
7826 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
7827 #define       MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
7828 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
7829 #define        MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
7830 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7831  * of blocks, each of the size REQUEST_BLOCK_SIZE.
7832  */
7833 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
7834 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
7835 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
7836 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
7837 /* Must be a power of 2 */
7838 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
7839 #define       MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
7840 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7841  * of blocks, each of the size REPLY_BLOCK_SIZE.
7842  */
7843 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
7844 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
7845 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7846 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7847 /* Must be a power of 2 */
7848 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
7849 #define       MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
7850 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7851  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7852  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7853  */
7854 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
7855 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
7856 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
7857 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
7858 /* Must be a power of 2, or zero if this buffer is not provided */
7859 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
7860 #define       MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
7861 /* Applies to all three buffers */
7862 #define       MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40
7863 #define       MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
7864 /* A bit mask defining which MCDI operations may be proxied */
7865 #define       MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44
7866 #define       MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64
7867 
7868 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */
7869 #define    MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
7870 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
7871 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
7872 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
7873 #define        MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
7874 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7875  * of blocks, each of the size REQUEST_BLOCK_SIZE.
7876  */
7877 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
7878 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
7879 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
7880 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
7881 /* Must be a power of 2 */
7882 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
7883 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
7884 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7885  * of blocks, each of the size REPLY_BLOCK_SIZE.
7886  */
7887 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
7888 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
7889 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7890 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7891 /* Must be a power of 2 */
7892 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
7893 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
7894 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7895  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7896  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7897  */
7898 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
7899 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
7900 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
7901 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
7902 /* Must be a power of 2, or zero if this buffer is not provided */
7903 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
7904 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
7905 /* Applies to all three buffers */
7906 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40
7907 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
7908 /* A bit mask defining which MCDI operations may be proxied */
7909 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44
7910 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64
7911 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108
7912 #define       MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
7913 
7914 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */
7915 #define    MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
7916 
7917 
7918 /***********************************/
7919 /* MC_CMD_PROXY_COMPLETE
7920  * Tells FW that a requested proxy operation has either been completed (by
7921  * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the
7922  * function that enabled proxying/authorization (by using
7923  * MC_CMD_PROXY_CONFIGURE).
7924  */
7925 #define MC_CMD_PROXY_COMPLETE 0x5f
7926 
7927 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7928 
7929 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */
7930 #define    MC_CMD_PROXY_COMPLETE_IN_LEN 12
7931 #define       MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
7932 #define       MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
7933 #define       MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
7934 #define       MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
7935 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
7936  * is stored in the REPLY_BUFF.
7937  */
7938 #define          MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
7939 /* enum: The operation has been authorized. The originating function may now
7940  * try again.
7941  */
7942 #define          MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
7943 /* enum: The operation has been declined. */
7944 #define          MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
7945 /* enum: The authorization failed because the relevant application did not
7946  * respond in time.
7947  */
7948 #define          MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
7949 #define       MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8
7950 #define       MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
7951 
7952 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */
7953 #define    MC_CMD_PROXY_COMPLETE_OUT_LEN 0
7954 
7955 
7956 /***********************************/
7957 /* MC_CMD_ALLOC_BUFTBL_CHUNK
7958  * Allocate a set of buffer table entries using the specified owner ID. This
7959  * operation allocates the required buffer table entries (and fails if it
7960  * cannot do so). The buffer table entries will initially be zeroed.
7961  */
7962 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
7963 
7964 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7965 
7966 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
7967 #define    MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
7968 /* Owner ID to use */
7969 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
7970 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
7971 /* Size of buffer table pages to use, in bytes (note that only a few values are
7972  * legal on any specific hardware).
7973  */
7974 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
7975 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
7976 
7977 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
7978 #define    MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
7979 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
7980 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
7981 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
7982 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
7983 /* Buffer table IDs for use in DMA descriptors. */
7984 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
7985 #define       MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
7986 
7987 
7988 /***********************************/
7989 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
7990  * Reprogram a set of buffer table entries in the specified chunk.
7991  */
7992 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
7993 
7994 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7995 
7996 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
7997 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
7998 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
7999 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
8000 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
8001 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
8002 /* ID */
8003 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
8004 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
8005 /* Num entries */
8006 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
8007 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
8008 /* Buffer table entry address */
8009 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
8010 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
8011 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
8012 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
8013 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
8014 #define       MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
8015 
8016 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
8017 #define    MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
8018 
8019 
8020 /***********************************/
8021 /* MC_CMD_FREE_BUFTBL_CHUNK
8022  */
8023 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
8024 
8025 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8026 
8027 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
8028 #define    MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
8029 #define       MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
8030 #define       MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
8031 
8032 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
8033 #define    MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
8034 
8035 
8036 /***********************************/
8037 /* MC_CMD_FILTER_OP
8038  * Multiplexed MCDI call for filter operations
8039  */
8040 #define MC_CMD_FILTER_OP 0x8a
8041 
8042 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8043 
8044 /* MC_CMD_FILTER_OP_IN msgrequest */
8045 #define    MC_CMD_FILTER_OP_IN_LEN 108
8046 /* identifies the type of operation requested */
8047 #define       MC_CMD_FILTER_OP_IN_OP_OFST 0
8048 #define       MC_CMD_FILTER_OP_IN_OP_LEN 4
8049 /* enum: single-recipient filter insert */
8050 #define          MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
8051 /* enum: single-recipient filter remove */
8052 #define          MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
8053 /* enum: multi-recipient filter subscribe */
8054 #define          MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
8055 /* enum: multi-recipient filter unsubscribe */
8056 #define          MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
8057 /* enum: replace one recipient with another (warning - the filter handle may
8058  * change)
8059  */
8060 #define          MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
8061 /* filter handle (for remove / unsubscribe operations) */
8062 #define       MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
8063 #define       MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
8064 #define       MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
8065 #define       MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
8066 /* The port ID associated with the v-adaptor which should contain this filter.
8067  */
8068 #define       MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
8069 #define       MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
8070 /* fields to include in match criteria */
8071 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
8072 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
8073 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
8074 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
8075 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
8076 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
8077 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
8078 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
8079 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
8080 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
8081 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
8082 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
8083 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
8084 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
8085 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
8086 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
8087 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
8088 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
8089 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
8090 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
8091 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
8092 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
8093 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
8094 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
8095 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
8096 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
8097 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8098 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8099 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8100 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8101 /* receive destination */
8102 #define       MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
8103 #define       MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
8104 /* enum: drop packets */
8105 #define          MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
8106 /* enum: receive to host */
8107 #define          MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
8108 /* enum: receive to MC */
8109 #define          MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
8110 /* enum: loop back to TXDP 0 */
8111 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
8112 /* enum: loop back to TXDP 1 */
8113 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
8114 /* receive queue handle (for multiple queue modes, this is the base queue) */
8115 #define       MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
8116 #define       MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
8117 /* receive mode */
8118 #define       MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
8119 #define       MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
8120 /* enum: receive to just the specified queue */
8121 #define          MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
8122 /* enum: receive to multiple queues using RSS context */
8123 #define          MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
8124 /* enum: receive to multiple queues using .1p mapping */
8125 #define          MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
8126 /* enum: install a filter entry that will never match; for test purposes only
8127  */
8128 #define          MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8129 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8130  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8131  * MC_CMD_DOT1P_MAPPING_ALLOC.
8132  */
8133 #define       MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
8134 #define       MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
8135 /* transmit domain (reserved; set to 0) */
8136 #define       MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
8137 #define       MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
8138 /* transmit destination (either set the MAC and/or PM bits for explicit
8139  * control, or set this field to TX_DEST_DEFAULT for sensible default
8140  * behaviour)
8141  */
8142 #define       MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
8143 #define       MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
8144 /* enum: request default behaviour (based on filter type) */
8145 #define          MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
8146 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
8147 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
8148 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
8149 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
8150 /* source MAC address to match (as bytes in network order) */
8151 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
8152 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
8153 /* source port to match (as bytes in network order) */
8154 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
8155 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
8156 /* destination MAC address to match (as bytes in network order) */
8157 #define       MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
8158 #define       MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
8159 /* destination port to match (as bytes in network order) */
8160 #define       MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
8161 #define       MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
8162 /* Ethernet type to match (as bytes in network order) */
8163 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
8164 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
8165 /* Inner VLAN tag to match (as bytes in network order) */
8166 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
8167 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
8168 /* Outer VLAN tag to match (as bytes in network order) */
8169 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
8170 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
8171 /* IP protocol to match (in low byte; set high byte to 0) */
8172 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
8173 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
8174 /* Firmware defined register 0 to match (reserved; set to 0) */
8175 #define       MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
8176 #define       MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
8177 /* Firmware defined register 1 to match (reserved; set to 0) */
8178 #define       MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
8179 #define       MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
8180 /* source IP address to match (as bytes in network order; set last 12 bytes to
8181  * 0 for IPv4 address)
8182  */
8183 #define       MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
8184 #define       MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
8185 /* destination IP address to match (as bytes in network order; set last 12
8186  * bytes to 0 for IPv4 address)
8187  */
8188 #define       MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
8189 #define       MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
8190 
8191 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
8192  * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
8193  * supported on Medford only).
8194  */
8195 #define    MC_CMD_FILTER_OP_EXT_IN_LEN 172
8196 /* identifies the type of operation requested */
8197 #define       MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
8198 #define       MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
8199 /*            Enum values, see field(s): */
8200 /*               MC_CMD_FILTER_OP_IN/OP */
8201 /* filter handle (for remove / unsubscribe operations) */
8202 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
8203 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
8204 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
8205 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
8206 /* The port ID associated with the v-adaptor which should contain this filter.
8207  */
8208 #define       MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
8209 #define       MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
8210 /* fields to include in match criteria */
8211 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
8212 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
8213 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
8214 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
8215 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
8216 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
8217 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
8218 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
8219 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
8220 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
8221 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
8222 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
8223 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
8224 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
8225 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
8226 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
8227 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
8228 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
8229 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
8230 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
8231 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
8232 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
8233 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
8234 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
8235 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
8236 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
8237 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
8238 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
8239 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
8240 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
8241 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
8242 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
8243 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
8244 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
8245 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
8246 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
8247 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
8248 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
8249 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
8250 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
8251 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
8252 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
8253 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
8254 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
8255 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
8256 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
8257 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
8258 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
8259 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
8260 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
8261 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
8262 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
8263 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
8264 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
8265 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8266 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8267 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8268 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8269 /* receive destination */
8270 #define       MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
8271 #define       MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
8272 /* enum: drop packets */
8273 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
8274 /* enum: receive to host */
8275 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
8276 /* enum: receive to MC */
8277 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
8278 /* enum: loop back to TXDP 0 */
8279 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
8280 /* enum: loop back to TXDP 1 */
8281 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
8282 /* receive queue handle (for multiple queue modes, this is the base queue) */
8283 #define       MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
8284 #define       MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
8285 /* receive mode */
8286 #define       MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
8287 #define       MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
8288 /* enum: receive to just the specified queue */
8289 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
8290 /* enum: receive to multiple queues using RSS context */
8291 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
8292 /* enum: receive to multiple queues using .1p mapping */
8293 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
8294 /* enum: install a filter entry that will never match; for test purposes only
8295  */
8296 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8297 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8298  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8299  * MC_CMD_DOT1P_MAPPING_ALLOC.
8300  */
8301 #define       MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
8302 #define       MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
8303 /* transmit domain (reserved; set to 0) */
8304 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
8305 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
8306 /* transmit destination (either set the MAC and/or PM bits for explicit
8307  * control, or set this field to TX_DEST_DEFAULT for sensible default
8308  * behaviour)
8309  */
8310 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
8311 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
8312 /* enum: request default behaviour (based on filter type) */
8313 #define          MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
8314 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
8315 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
8316 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
8317 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
8318 /* source MAC address to match (as bytes in network order) */
8319 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
8320 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
8321 /* source port to match (as bytes in network order) */
8322 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
8323 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
8324 /* destination MAC address to match (as bytes in network order) */
8325 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
8326 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
8327 /* destination port to match (as bytes in network order) */
8328 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
8329 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
8330 /* Ethernet type to match (as bytes in network order) */
8331 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
8332 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
8333 /* Inner VLAN tag to match (as bytes in network order) */
8334 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
8335 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
8336 /* Outer VLAN tag to match (as bytes in network order) */
8337 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
8338 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
8339 /* IP protocol to match (in low byte; set high byte to 0) */
8340 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
8341 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
8342 /* Firmware defined register 0 to match (reserved; set to 0) */
8343 #define       MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
8344 #define       MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
8345 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
8346  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8347  * VXLAN/NVGRE, or 1 for Geneve)
8348  */
8349 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
8350 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
8351 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
8352 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
8353 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
8354 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
8355 /* enum: Match VXLAN traffic with this VNI */
8356 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
8357 /* enum: Match Geneve traffic with this VNI */
8358 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
8359 /* enum: Reserved for experimental development use */
8360 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8361 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
8362 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
8363 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
8364 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
8365 /* enum: Match NVGRE traffic with this VSID */
8366 #define          MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
8367 /* source IP address to match (as bytes in network order; set last 12 bytes to
8368  * 0 for IPv4 address)
8369  */
8370 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
8371 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
8372 /* destination IP address to match (as bytes in network order; set last 12
8373  * bytes to 0 for IPv4 address)
8374  */
8375 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
8376 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
8377 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
8378  * order)
8379  */
8380 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
8381 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
8382 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
8383 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
8384 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
8385 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
8386  * network order)
8387  */
8388 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
8389 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
8390 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
8391  * order)
8392  */
8393 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
8394 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
8395 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
8396  */
8397 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
8398 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
8399 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
8400  */
8401 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
8402 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
8403 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
8404  */
8405 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
8406 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
8407 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
8408  * 0)
8409  */
8410 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
8411 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
8412 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8413  * to 0)
8414  */
8415 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
8416 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
8417 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
8418  * to 0)
8419  */
8420 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
8421 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
8422 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
8423  * order; set last 12 bytes to 0 for IPv4 address)
8424  */
8425 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
8426 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
8427 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
8428  * order; set last 12 bytes to 0 for IPv4 address)
8429  */
8430 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
8431 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
8432 
8433 /* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
8434  * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via
8435  * its rte_flow API. This extension is only useful with the sfc_efx driver
8436  * included as part of DPDK, used in conjunction with the dpdk datapath
8437  * firmware variant.
8438  */
8439 #define    MC_CMD_FILTER_OP_V3_IN_LEN 180
8440 /* identifies the type of operation requested */
8441 #define       MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
8442 #define       MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
8443 /*            Enum values, see field(s): */
8444 /*               MC_CMD_FILTER_OP_IN/OP */
8445 /* filter handle (for remove / unsubscribe operations) */
8446 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
8447 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
8448 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
8449 #define       MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
8450 /* The port ID associated with the v-adaptor which should contain this filter.
8451  */
8452 #define       MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
8453 #define       MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
8454 /* fields to include in match criteria */
8455 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
8456 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
8457 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
8458 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
8459 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
8460 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
8461 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
8462 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
8463 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
8464 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
8465 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
8466 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
8467 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
8468 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
8469 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
8470 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
8471 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
8472 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
8473 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
8474 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
8475 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
8476 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
8477 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
8478 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
8479 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
8480 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
8481 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
8482 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
8483 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
8484 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
8485 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
8486 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
8487 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
8488 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
8489 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
8490 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
8491 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
8492 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
8493 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
8494 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
8495 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
8496 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
8497 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
8498 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
8499 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
8500 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
8501 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
8502 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
8503 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
8504 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
8505 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
8506 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
8507 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
8508 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
8509 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
8510 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
8511 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
8512 #define        MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
8513 /* receive destination */
8514 #define       MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
8515 #define       MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
8516 /* enum: drop packets */
8517 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
8518 /* enum: receive to host */
8519 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
8520 /* enum: receive to MC */
8521 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
8522 /* enum: loop back to TXDP 0 */
8523 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
8524 /* enum: loop back to TXDP 1 */
8525 #define          MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
8526 /* receive queue handle (for multiple queue modes, this is the base queue) */
8527 #define       MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
8528 #define       MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
8529 /* receive mode */
8530 #define       MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
8531 #define       MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
8532 /* enum: receive to just the specified queue */
8533 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
8534 /* enum: receive to multiple queues using RSS context */
8535 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
8536 /* enum: receive to multiple queues using .1p mapping */
8537 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
8538 /* enum: install a filter entry that will never match; for test purposes only
8539  */
8540 #define          MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8541 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
8542  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
8543  * MC_CMD_DOT1P_MAPPING_ALLOC.
8544  */
8545 #define       MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
8546 #define       MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
8547 /* transmit domain (reserved; set to 0) */
8548 #define       MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
8549 #define       MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
8550 /* transmit destination (either set the MAC and/or PM bits for explicit
8551  * control, or set this field to TX_DEST_DEFAULT for sensible default
8552  * behaviour)
8553  */
8554 #define       MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
8555 #define       MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
8556 /* enum: request default behaviour (based on filter type) */
8557 #define          MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
8558 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
8559 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
8560 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
8561 #define        MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
8562 /* source MAC address to match (as bytes in network order) */
8563 #define       MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
8564 #define       MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
8565 /* source port to match (as bytes in network order) */
8566 #define       MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
8567 #define       MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
8568 /* destination MAC address to match (as bytes in network order) */
8569 #define       MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
8570 #define       MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
8571 /* destination port to match (as bytes in network order) */
8572 #define       MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
8573 #define       MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
8574 /* Ethernet type to match (as bytes in network order) */
8575 #define       MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
8576 #define       MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
8577 /* Inner VLAN tag to match (as bytes in network order) */
8578 #define       MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
8579 #define       MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
8580 /* Outer VLAN tag to match (as bytes in network order) */
8581 #define       MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
8582 #define       MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
8583 /* IP protocol to match (in low byte; set high byte to 0) */
8584 #define       MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
8585 #define       MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
8586 /* Firmware defined register 0 to match (reserved; set to 0) */
8587 #define       MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
8588 #define       MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
8589 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
8590  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8591  * VXLAN/NVGRE, or 1 for Geneve)
8592  */
8593 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
8594 #define       MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
8595 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
8596 #define        MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
8597 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
8598 #define        MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
8599 /* enum: Match VXLAN traffic with this VNI */
8600 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
8601 /* enum: Match Geneve traffic with this VNI */
8602 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
8603 /* enum: Reserved for experimental development use */
8604 #define          MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8605 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
8606 #define        MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
8607 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
8608 #define        MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
8609 /* enum: Match NVGRE traffic with this VSID */
8610 #define          MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
8611 /* source IP address to match (as bytes in network order; set last 12 bytes to
8612  * 0 for IPv4 address)
8613  */
8614 #define       MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
8615 #define       MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
8616 /* destination IP address to match (as bytes in network order; set last 12
8617  * bytes to 0 for IPv4 address)
8618  */
8619 #define       MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
8620 #define       MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
8621 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
8622  * order)
8623  */
8624 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
8625 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
8626 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
8627 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
8628 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
8629 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
8630  * network order)
8631  */
8632 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
8633 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
8634 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
8635  * order)
8636  */
8637 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
8638 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
8639 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
8640  */
8641 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
8642 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
8643 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
8644  */
8645 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
8646 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
8647 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
8648  */
8649 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
8650 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
8651 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
8652  * 0)
8653  */
8654 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
8655 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
8656 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8657  * to 0)
8658  */
8659 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
8660 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
8661 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
8662  * to 0)
8663  */
8664 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
8665 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
8666 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
8667  * order; set last 12 bytes to 0 for IPv4 address)
8668  */
8669 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
8670 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
8671 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
8672  * order; set last 12 bytes to 0 for IPv4 address)
8673  */
8674 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
8675 #define       MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
8676 /* Set an action for all packets matching this filter. The DPDK driver and dpdk
8677  * f/w variant use their own specific delivery structures, which are documented
8678  * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
8679  * other than MATCH_ACTION_NONE when the NIC is running another f/w variant
8680  * will cause the filter insertion to fail with ENOTSUP.
8681  */
8682 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
8683 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
8684 /* enum: do nothing extra */
8685 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
8686 /* enum: Set the match flag in the packet prefix for packets matching the
8687  * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
8688  * support the DPDK rte_flow "FLAG" action.
8689  */
8690 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
8691 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
8692  * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
8693  * support the DPDK rte_flow "MARK" action.
8694  */
8695 #define          MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
8696 /* the mark value for MATCH_ACTION_MARK */
8697 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
8698 #define       MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
8699 
8700 /* MC_CMD_FILTER_OP_OUT msgresponse */
8701 #define    MC_CMD_FILTER_OP_OUT_LEN 12
8702 /* identifies the type of operation requested */
8703 #define       MC_CMD_FILTER_OP_OUT_OP_OFST 0
8704 #define       MC_CMD_FILTER_OP_OUT_OP_LEN 4
8705 /*            Enum values, see field(s): */
8706 /*               MC_CMD_FILTER_OP_IN/OP */
8707 /* Returned filter handle (for insert / subscribe operations). Note that these
8708  * handles should be considered opaque to the host, although a value of
8709  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8710  */
8711 #define       MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
8712 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
8713 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
8714 #define       MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
8715 /* enum: guaranteed invalid filter handle (low 32 bits) */
8716 #define          MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
8717 /* enum: guaranteed invalid filter handle (high 32 bits) */
8718 #define          MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
8719 
8720 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
8721 #define    MC_CMD_FILTER_OP_EXT_OUT_LEN 12
8722 /* identifies the type of operation requested */
8723 #define       MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
8724 #define       MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
8725 /*            Enum values, see field(s): */
8726 /*               MC_CMD_FILTER_OP_EXT_IN/OP */
8727 /* Returned filter handle (for insert / subscribe operations). Note that these
8728  * handles should be considered opaque to the host, although a value of
8729  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8730  */
8731 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
8732 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
8733 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
8734 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
8735 /*            Enum values, see field(s): */
8736 /*               MC_CMD_FILTER_OP_OUT/HANDLE */
8737 
8738 
8739 /***********************************/
8740 /* MC_CMD_GET_PARSER_DISP_INFO
8741  * Get information related to the parser-dispatcher subsystem
8742  */
8743 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
8744 
8745 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8746 
8747 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
8748 #define    MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
8749 /* identifies the type of operation requested */
8750 #define       MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
8751 #define       MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
8752 /* enum: read the list of supported RX filter matches */
8753 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
8754 /* enum: read flags indicating restrictions on filter insertion for the calling
8755  * client
8756  */
8757 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
8758 /* enum: read properties relating to security rules (Medford-only; for use by
8759  * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
8760  */
8761 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
8762 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE
8763  * encapsulated frames, which follow a different match sequence to normal
8764  * frames (Medford only)
8765  */
8766 #define          MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
8767 
8768 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
8769 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
8770 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
8771 #define    MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
8772 /* identifies the type of operation requested */
8773 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
8774 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
8775 /*            Enum values, see field(s): */
8776 /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8777 /* number of supported match types */
8778 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
8779 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
8780 /* array of supported match types (valid MATCH_FIELDS values for
8781  * MC_CMD_FILTER_OP) sorted in decreasing priority order
8782  */
8783 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
8784 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
8785 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
8786 #define       MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
8787 
8788 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
8789 #define    MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
8790 /* identifies the type of operation requested */
8791 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
8792 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
8793 /*            Enum values, see field(s): */
8794 /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8795 /* bitfield of filter insertion restrictions */
8796 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
8797 #define       MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
8798 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
8799 #define        MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
8800 
8801 
8802 /***********************************/
8803 /* MC_CMD_PARSER_DISP_RW
8804  * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
8805  * Please note that this interface is only of use to debug tools which have
8806  * knowledge of firmware and hardware data structures; nothing here is intended
8807  * for use by normal driver code. Note that although this command is in the
8808  * Admin privilege group, in tamperproof adapters, only read operations are
8809  * permitted.
8810  */
8811 #define MC_CMD_PARSER_DISP_RW 0xe5
8812 
8813 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8814 
8815 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */
8816 #define    MC_CMD_PARSER_DISP_RW_IN_LEN 32
8817 /* identifies the target of the operation */
8818 #define       MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
8819 #define       MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
8820 /* enum: RX dispatcher CPU */
8821 #define          MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
8822 /* enum: TX dispatcher CPU */
8823 #define          MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
8824 /* enum: Lookup engine (with original metadata format). Deprecated; used only
8825  * by cmdclient as a fallback for very old Huntington firmware, and not
8826  * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA
8827  * instead.
8828  */
8829 #define          MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
8830 /* enum: Lookup engine (with requested metadata format) */
8831 #define          MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
8832 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
8833 #define          MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
8834 /* enum: RX1 dispatcher CPU (only valid for Medford) */
8835 #define          MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
8836 /* enum: Miscellaneous other state (only valid for Medford) */
8837 #define          MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
8838 /* identifies the type of operation requested */
8839 #define       MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
8840 #define       MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
8841 /* enum: Read a word of DICPU DMEM or a LUE entry */
8842 #define          MC_CMD_PARSER_DISP_RW_IN_READ 0x0
8843 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
8844  * tamperproof adapters.
8845  */
8846 #define          MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
8847 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
8848  * permitted on tamperproof adapters.
8849  */
8850 #define          MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
8851 /* data memory address (DICPU targets) or LUE index (LUE targets) */
8852 #define       MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
8853 #define       MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
8854 /* selector (for MISC_STATE target) */
8855 #define       MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
8856 #define       MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
8857 /* enum: Port to datapath mapping */
8858 #define          MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
8859 /* value to write (for DMEM writes) */
8860 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
8861 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
8862 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8863 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
8864 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
8865 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8866 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
8867 #define       MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
8868 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */
8869 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12
8870 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
8871 /* value to write (for LUE writes) */
8872 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
8873 #define       MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
8874 
8875 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
8876 #define    MC_CMD_PARSER_DISP_RW_OUT_LEN 52
8877 /* value read (for DMEM reads) */
8878 #define       MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
8879 #define       MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
8880 /* value read (for LUE reads) */
8881 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
8882 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
8883 /* up to 8 32-bit words of additional soft state from the LUE manager (the
8884  * exact content is firmware-dependent and intended only for debug use)
8885  */
8886 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
8887 #define       MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
8888 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */
8889 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
8890 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
8891 #define       MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
8892 #define          MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
8893 #define          MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
8894 
8895 
8896 /***********************************/
8897 /* MC_CMD_GET_PF_COUNT
8898  * Get number of PFs on the device.
8899  */
8900 #define MC_CMD_GET_PF_COUNT 0xb6
8901 
8902 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8903 
8904 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
8905 #define    MC_CMD_GET_PF_COUNT_IN_LEN 0
8906 
8907 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
8908 #define    MC_CMD_GET_PF_COUNT_OUT_LEN 1
8909 /* Identifies the number of PFs on the device. */
8910 #define       MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
8911 #define       MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
8912 
8913 
8914 /***********************************/
8915 /* MC_CMD_SET_PF_COUNT
8916  * Set number of PFs on the device.
8917  */
8918 #define MC_CMD_SET_PF_COUNT 0xb7
8919 
8920 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
8921 #define    MC_CMD_SET_PF_COUNT_IN_LEN 4
8922 /* New number of PFs on the device. */
8923 #define       MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
8924 #define       MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
8925 
8926 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
8927 #define    MC_CMD_SET_PF_COUNT_OUT_LEN 0
8928 
8929 
8930 /***********************************/
8931 /* MC_CMD_GET_PORT_ASSIGNMENT
8932  * Get port assignment for current PCI function.
8933  */
8934 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
8935 
8936 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8937 
8938 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
8939 #define    MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
8940 
8941 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
8942 #define    MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
8943 /* Identifies the port assignment for this function. */
8944 #define       MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
8945 #define       MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
8946 
8947 
8948 /***********************************/
8949 /* MC_CMD_SET_PORT_ASSIGNMENT
8950  * Set port assignment for current PCI function.
8951  */
8952 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
8953 
8954 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8955 
8956 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
8957 #define    MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
8958 /* Identifies the port assignment for this function. */
8959 #define       MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
8960 #define       MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
8961 
8962 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
8963 #define    MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
8964 
8965 
8966 /***********************************/
8967 /* MC_CMD_ALLOC_VIS
8968  * Allocate VIs for current PCI function.
8969  */
8970 #define MC_CMD_ALLOC_VIS 0x8b
8971 
8972 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8973 
8974 /* MC_CMD_ALLOC_VIS_IN msgrequest */
8975 #define    MC_CMD_ALLOC_VIS_IN_LEN 8
8976 /* The minimum number of VIs that is acceptable */
8977 #define       MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
8978 #define       MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
8979 /* The maximum number of VIs that would be useful */
8980 #define       MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
8981 #define       MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
8982 
8983 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
8984  * Use extended version in new code.
8985  */
8986 #define    MC_CMD_ALLOC_VIS_OUT_LEN 8
8987 /* The number of VIs allocated on this function */
8988 #define       MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
8989 #define       MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
8990 /* The base absolute VI number allocated to this function. Required to
8991  * correctly interpret wakeup events.
8992  */
8993 #define       MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
8994 #define       MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
8995 
8996 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
8997 #define    MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
8998 /* The number of VIs allocated on this function */
8999 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
9000 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
9001 /* The base absolute VI number allocated to this function. Required to
9002  * correctly interpret wakeup events.
9003  */
9004 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
9005 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
9006 /* Function's port vi_shift value (always 0 on Huntington) */
9007 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
9008 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
9009 
9010 
9011 /***********************************/
9012 /* MC_CMD_FREE_VIS
9013  * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
9014  * but not freed.
9015  */
9016 #define MC_CMD_FREE_VIS 0x8c
9017 
9018 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9019 
9020 /* MC_CMD_FREE_VIS_IN msgrequest */
9021 #define    MC_CMD_FREE_VIS_IN_LEN 0
9022 
9023 /* MC_CMD_FREE_VIS_OUT msgresponse */
9024 #define    MC_CMD_FREE_VIS_OUT_LEN 0
9025 
9026 
9027 /***********************************/
9028 /* MC_CMD_GET_SRIOV_CFG
9029  * Get SRIOV config for this PF.
9030  */
9031 #define MC_CMD_GET_SRIOV_CFG 0xba
9032 
9033 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9034 
9035 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
9036 #define    MC_CMD_GET_SRIOV_CFG_IN_LEN 0
9037 
9038 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
9039 #define    MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
9040 /* Number of VFs currently enabled. */
9041 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
9042 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
9043 /* Max number of VFs before sriov stride and offset may need to be changed. */
9044 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
9045 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
9046 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
9047 #define       MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
9048 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
9049 #define        MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
9050 /* RID offset of first VF from PF. */
9051 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
9052 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
9053 /* RID offset of each subsequent VF from the previous. */
9054 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
9055 #define       MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
9056 
9057 
9058 /***********************************/
9059 /* MC_CMD_SET_SRIOV_CFG
9060  * Set SRIOV config for this PF.
9061  */
9062 #define MC_CMD_SET_SRIOV_CFG 0xbb
9063 
9064 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9065 
9066 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
9067 #define    MC_CMD_SET_SRIOV_CFG_IN_LEN 20
9068 /* Number of VFs currently enabled. */
9069 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
9070 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
9071 /* Max number of VFs before sriov stride and offset may need to be changed. */
9072 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
9073 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
9074 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
9075 #define       MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
9076 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
9077 #define        MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
9078 /* RID offset of first VF from PF, or 0 for no change, or
9079  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
9080  */
9081 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
9082 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
9083 /* RID offset of each subsequent VF from the previous, 0 for no change, or
9084  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
9085  */
9086 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
9087 #define       MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
9088 
9089 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
9090 #define    MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
9091 
9092 
9093 /***********************************/
9094 /* MC_CMD_GET_VI_ALLOC_INFO
9095  * Get information about number of VI's and base VI number allocated to this
9096  * function.
9097  */
9098 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
9099 
9100 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9101 
9102 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
9103 #define    MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
9104 
9105 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
9106 #define    MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
9107 /* The number of VIs allocated on this function */
9108 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
9109 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
9110 /* The base absolute VI number allocated to this function. Required to
9111  * correctly interpret wakeup events.
9112  */
9113 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
9114 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
9115 /* Function's port vi_shift value (always 0 on Huntington) */
9116 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
9117 #define       MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
9118 
9119 
9120 /***********************************/
9121 /* MC_CMD_DUMP_VI_STATE
9122  * For CmdClient use. Dump pertinent information on a specific absolute VI.
9123  */
9124 #define MC_CMD_DUMP_VI_STATE 0x8e
9125 
9126 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9127 
9128 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */
9129 #define    MC_CMD_DUMP_VI_STATE_IN_LEN 4
9130 /* The VI number to query. */
9131 #define       MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
9132 #define       MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
9133 
9134 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
9135 #define    MC_CMD_DUMP_VI_STATE_OUT_LEN 96
9136 /* The PF part of the function owning this VI. */
9137 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
9138 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
9139 /* The VF part of the function owning this VI. */
9140 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
9141 #define       MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
9142 /* Base of VIs allocated to this function. */
9143 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
9144 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
9145 /* Count of VIs allocated to the owner function. */
9146 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
9147 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
9148 /* Base interrupt vector allocated to this function. */
9149 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
9150 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
9151 /* Number of interrupt vectors allocated to this function. */
9152 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
9153 #define       MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
9154 /* Raw evq ptr table data. */
9155 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
9156 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
9157 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
9158 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
9159 /* Raw evq timer table data. */
9160 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
9161 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
9162 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
9163 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
9164 /* Combined metadata field. */
9165 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
9166 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
9167 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
9168 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
9169 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
9170 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
9171 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
9172 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
9173 /* TXDPCPU raw table data for queue. */
9174 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
9175 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
9176 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
9177 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
9178 /* TXDPCPU raw table data for queue. */
9179 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
9180 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
9181 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
9182 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
9183 /* TXDPCPU raw table data for queue. */
9184 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
9185 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
9186 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
9187 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
9188 /* Combined metadata field. */
9189 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
9190 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
9191 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
9192 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
9193 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
9194 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
9195 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
9196 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
9197 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
9198 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
9199 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
9200 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
9201 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
9202 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
9203 /* RXDPCPU raw table data for queue. */
9204 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
9205 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
9206 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
9207 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
9208 /* RXDPCPU raw table data for queue. */
9209 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
9210 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
9211 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
9212 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
9213 /* Reserved, currently 0. */
9214 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
9215 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
9216 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
9217 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
9218 /* Combined metadata field. */
9219 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
9220 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
9221 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
9222 #define       MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
9223 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
9224 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
9225 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
9226 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
9227 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
9228 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
9229 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
9230 #define        MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
9231 
9232 
9233 /***********************************/
9234 /* MC_CMD_ALLOC_PIOBUF
9235  * Allocate a push I/O buffer for later use with a tx queue.
9236  */
9237 #define MC_CMD_ALLOC_PIOBUF 0x8f
9238 
9239 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9240 
9241 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
9242 #define    MC_CMD_ALLOC_PIOBUF_IN_LEN 0
9243 
9244 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
9245 #define    MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
9246 /* Handle for allocated push I/O buffer. */
9247 #define       MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
9248 #define       MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
9249 
9250 
9251 /***********************************/
9252 /* MC_CMD_FREE_PIOBUF
9253  * Free a push I/O buffer.
9254  */
9255 #define MC_CMD_FREE_PIOBUF 0x90
9256 
9257 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9258 
9259 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
9260 #define    MC_CMD_FREE_PIOBUF_IN_LEN 4
9261 /* Handle for allocated push I/O buffer. */
9262 #define       MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
9263 #define       MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
9264 
9265 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
9266 #define    MC_CMD_FREE_PIOBUF_OUT_LEN 0
9267 
9268 
9269 /***********************************/
9270 /* MC_CMD_GET_VI_TLP_PROCESSING
9271  * Get TLP steering and ordering information for a VI.
9272  */
9273 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
9274 
9275 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9276 
9277 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
9278 #define    MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
9279 /* VI number to get information for. */
9280 #define       MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9281 #define       MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
9282 
9283 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
9284 #define    MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
9285 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9286 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
9287 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
9288 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9289 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
9290 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
9291 /* Use Relaxed ordering model for TLPs on this VI. */
9292 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
9293 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
9294 /* Use ID based ordering for TLPs on this VI. */
9295 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
9296 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
9297 /* Set no snoop bit for TLPs on this VI. */
9298 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
9299 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
9300 /* Enable TPH for TLPs on this VI. */
9301 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
9302 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
9303 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
9304 #define       MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
9305 
9306 
9307 /***********************************/
9308 /* MC_CMD_SET_VI_TLP_PROCESSING
9309  * Set TLP steering and ordering information for a VI.
9310  */
9311 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
9312 
9313 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9314 
9315 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
9316 #define    MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
9317 /* VI number to set information for. */
9318 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9319 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
9320 /* Transaction processing steering hint 1 for use with the Rx Queue. */
9321 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
9322 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
9323 /* Transaction processing steering hint 2 for use with the Ev Queue. */
9324 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
9325 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
9326 /* Use Relaxed ordering model for TLPs on this VI. */
9327 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
9328 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
9329 /* Use ID based ordering for TLPs on this VI. */
9330 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
9331 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
9332 /* Set the no snoop bit for TLPs on this VI. */
9333 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
9334 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
9335 /* Enable TPH for TLPs on this VI. */
9336 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
9337 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
9338 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
9339 #define       MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
9340 
9341 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
9342 #define    MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
9343 
9344 
9345 /***********************************/
9346 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS
9347  * Get global PCIe steering and transaction processing configuration.
9348  */
9349 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
9350 
9351 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9352 
9353 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
9354 #define    MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
9355 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9356 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
9357 /* enum: MISC. */
9358 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
9359 /* enum: IDO. */
9360 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
9361 /* enum: RO. */
9362 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
9363 /* enum: TPH Type. */
9364 #define          MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
9365 
9366 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
9367 #define    MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
9368 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
9369 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
9370 /*            Enum values, see field(s): */
9371 /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
9372 /* Amalgamated TLP info word. */
9373 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
9374 #define       MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
9375 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
9376 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
9377 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
9378 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
9379 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
9380 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
9381 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
9382 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
9383 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
9384 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
9385 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
9386 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
9387 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
9388 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
9389 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
9390 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
9391 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
9392 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
9393 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
9394 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
9395 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
9396 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
9397 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9398 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
9399 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
9400 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
9401 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
9402 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
9403 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
9404 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
9405 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
9406 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
9407 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
9408 #define        MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
9409 
9410 
9411 /***********************************/
9412 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS
9413  * Set global PCIe steering and transaction processing configuration.
9414  */
9415 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
9416 
9417 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9418 
9419 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
9420 #define    MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
9421 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9422 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
9423 /*            Enum values, see field(s): */
9424 /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
9425 /* Amalgamated TLP info word. */
9426 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
9427 #define       MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
9428 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
9429 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
9430 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
9431 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
9432 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
9433 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
9434 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
9435 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
9436 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
9437 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
9438 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
9439 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
9440 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
9441 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
9442 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
9443 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
9444 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9445 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
9446 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
9447 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
9448 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
9449 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
9450 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
9451 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
9452 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
9453 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
9454 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
9455 #define        MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
9456 
9457 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
9458 #define    MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
9459 
9460 
9461 /***********************************/
9462 /* MC_CMD_SATELLITE_DOWNLOAD
9463  * Download a new set of images to the satellite CPUs from the host.
9464  */
9465 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
9466 
9467 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
9468 
9469 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
9470  * are subtle, and so downloads must proceed in a number of phases.
9471  *
9472  * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
9473  *
9474  * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
9475  * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
9476  * be a checksum (a simple 32-bit sum) of the transferred data. An individual
9477  * download may be aborted using CHUNK_ID_ABORT.
9478  *
9479  * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
9480  * similar to PHASE_IMEMS.
9481  *
9482  * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
9483  *
9484  * After any error (a requested abort is not considered to be an error) the
9485  * sequence must be restarted from PHASE_RESET.
9486  */
9487 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
9488 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
9489 #define    MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
9490 /* Download phase. (Note: the IDLE phase is used internally and is never valid
9491  * in a command from the host.)
9492  */
9493 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
9494 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
9495 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
9496 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
9497 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
9498 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
9499 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
9500 /* Target for download. (These match the blob numbers defined in
9501  * mc_flash_layout.h.)
9502  */
9503 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
9504 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
9505 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9506 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
9507 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9508 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
9509 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9510 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
9511 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9512 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
9513 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9514 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
9515 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9516 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
9517 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9518 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
9519 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9520 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
9521 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9522 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
9523 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9524 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
9525 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9526 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
9527 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9528 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
9529 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9530 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
9531 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9532 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
9533 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9534 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
9535 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9536 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
9537 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
9538 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
9539 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
9540 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
9541 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
9542 /* enum: Last chunk, containing checksum rather than data */
9543 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
9544 /* enum: Abort download of this item */
9545 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
9546 /* Length of this chunk in bytes */
9547 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
9548 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
9549 /* Data for this chunk */
9550 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
9551 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
9552 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
9553 #define       MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
9554 
9555 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
9556 #define    MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
9557 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
9558 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
9559 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
9560 /* Extra status information */
9561 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
9562 #define       MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
9563 /* enum: Code download OK, completed. */
9564 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
9565 /* enum: Code download aborted as requested. */
9566 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
9567 /* enum: Code download OK so far, send next chunk. */
9568 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
9569 /* enum: Download phases out of sequence */
9570 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
9571 /* enum: Bad target for this phase */
9572 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
9573 /* enum: Chunk ID out of sequence */
9574 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
9575 /* enum: Chunk length zero or too large */
9576 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
9577 /* enum: Checksum was incorrect */
9578 #define          MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
9579 
9580 
9581 /***********************************/
9582 /* MC_CMD_GET_CAPABILITIES
9583  * Get device capabilities.
9584  *
9585  * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
9586  * reference inherent device capabilities as opposed to current NVRAM config.
9587  */
9588 #define MC_CMD_GET_CAPABILITIES 0xbe
9589 
9590 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9591 
9592 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */
9593 #define    MC_CMD_GET_CAPABILITIES_IN_LEN 0
9594 
9595 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
9596 #define    MC_CMD_GET_CAPABILITIES_OUT_LEN 20
9597 /* First word of flags. */
9598 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
9599 #define       MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
9600 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
9601 #define        MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
9602 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
9603 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
9604 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
9605 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
9606 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9607 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9608 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
9609 #define        MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9610 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9611 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9612 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
9613 #define        MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
9614 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9615 #define        MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9616 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9617 #define        MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9618 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9619 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9620 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
9621 #define        MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9622 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
9623 #define        MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
9624 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9625 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9626 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
9627 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
9628 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
9629 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
9630 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
9631 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
9632 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
9633 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
9634 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
9635 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
9636 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
9637 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
9638 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
9639 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
9640 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
9641 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
9642 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
9643 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
9644 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
9645 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
9646 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
9647 #define        MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9648 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9649 #define        MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9650 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
9651 #define        MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
9652 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9653 #define        MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9654 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
9655 #define        MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
9656 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
9657 #define        MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
9658 /* RxDPCPU firmware id. */
9659 #define       MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
9660 #define       MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
9661 /* enum: Standard RXDP firmware */
9662 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
9663 /* enum: Low latency RXDP firmware */
9664 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
9665 /* enum: Packed stream RXDP firmware */
9666 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
9667 /* enum: Rules engine RXDP firmware */
9668 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
9669 /* enum: DPDK RXDP firmware */
9670 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
9671 /* enum: BIST RXDP firmware */
9672 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
9673 /* enum: RXDP Test firmware image 1 */
9674 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9675 /* enum: RXDP Test firmware image 2 */
9676 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9677 /* enum: RXDP Test firmware image 3 */
9678 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9679 /* enum: RXDP Test firmware image 4 */
9680 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9681 /* enum: RXDP Test firmware image 5 */
9682 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
9683 /* enum: RXDP Test firmware image 6 */
9684 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9685 /* enum: RXDP Test firmware image 7 */
9686 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9687 /* enum: RXDP Test firmware image 8 */
9688 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9689 /* enum: RXDP Test firmware image 9 */
9690 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9691 /* enum: RXDP Test firmware image 10 */
9692 #define          MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
9693 /* TxDPCPU firmware id. */
9694 #define       MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
9695 #define       MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
9696 /* enum: Standard TXDP firmware */
9697 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
9698 /* enum: Low latency TXDP firmware */
9699 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
9700 /* enum: High packet rate TXDP firmware */
9701 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
9702 /* enum: Rules engine TXDP firmware */
9703 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
9704 /* enum: DPDK TXDP firmware */
9705 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
9706 /* enum: BIST TXDP firmware */
9707 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
9708 /* enum: TXDP Test firmware image 1 */
9709 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9710 /* enum: TXDP Test firmware image 2 */
9711 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9712 /* enum: TXDP CSR bus test firmware */
9713 #define          MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
9714 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
9715 #define       MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
9716 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
9717 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9718 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9719 #define        MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9720 /* enum: reserved value - do not use (may indicate alternative interpretation
9721  * of REV field in future)
9722  */
9723 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
9724 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9725  * development only)
9726  */
9727 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9728 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9729  * (Huntington development only)
9730  */
9731 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9732 /* enum: Full featured RX PD production firmware */
9733 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9734 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9735 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9736 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9737  * (Huntington development only)
9738  */
9739 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9740 /* enum: Low latency RX PD production firmware */
9741 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9742 /* enum: Packed stream RX PD production firmware */
9743 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9744 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9745  * tests (Medford development only)
9746  */
9747 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9748 /* enum: Rules engine RX PD production firmware */
9749 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9750 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9751 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
9752 /* enum: DPDK RX PD production firmware */
9753 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
9754 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9755 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9756 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9757  * encapsulations (Medford development only)
9758  */
9759 #define          MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9760 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
9761 #define       MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
9762 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
9763 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9764 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9765 #define        MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9766 /* enum: reserved value - do not use (may indicate alternative interpretation
9767  * of REV field in future)
9768  */
9769 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
9770 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9771  * development only)
9772  */
9773 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9774 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9775  * (Huntington development only)
9776  */
9777 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9778 /* enum: Full featured TX PD production firmware */
9779 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9780 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9781 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9782 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9783  * (Huntington development only)
9784  */
9785 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9786 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9787 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9788  * tests (Medford development only)
9789  */
9790 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9791 /* enum: Rules engine TX PD production firmware */
9792 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9793 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9794 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
9795 /* enum: DPDK TX PD production firmware */
9796 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
9797 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9798 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9799 /* Hardware capabilities of NIC */
9800 #define       MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
9801 #define       MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
9802 /* Licensed capabilities */
9803 #define       MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
9804 #define       MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
9805 
9806 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
9807 #define    MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
9808 
9809 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
9810 #define    MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
9811 /* First word of flags. */
9812 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
9813 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
9814 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
9815 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
9816 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
9817 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
9818 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
9819 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
9820 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9821 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9822 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
9823 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9824 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9825 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9826 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
9827 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
9828 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9829 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9830 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9831 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9832 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9833 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9834 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
9835 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9836 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
9837 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
9838 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9839 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9840 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
9841 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
9842 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
9843 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
9844 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
9845 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
9846 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
9847 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
9848 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
9849 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
9850 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
9851 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
9852 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
9853 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
9854 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
9855 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
9856 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
9857 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
9858 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
9859 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
9860 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
9861 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9862 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9863 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9864 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
9865 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
9866 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9867 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9868 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
9869 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
9870 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
9871 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
9872 /* RxDPCPU firmware id. */
9873 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
9874 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
9875 /* enum: Standard RXDP firmware */
9876 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
9877 /* enum: Low latency RXDP firmware */
9878 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
9879 /* enum: Packed stream RXDP firmware */
9880 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
9881 /* enum: Rules engine RXDP firmware */
9882 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
9883 /* enum: DPDK RXDP firmware */
9884 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
9885 /* enum: BIST RXDP firmware */
9886 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
9887 /* enum: RXDP Test firmware image 1 */
9888 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9889 /* enum: RXDP Test firmware image 2 */
9890 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9891 /* enum: RXDP Test firmware image 3 */
9892 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9893 /* enum: RXDP Test firmware image 4 */
9894 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9895 /* enum: RXDP Test firmware image 5 */
9896 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
9897 /* enum: RXDP Test firmware image 6 */
9898 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9899 /* enum: RXDP Test firmware image 7 */
9900 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9901 /* enum: RXDP Test firmware image 8 */
9902 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9903 /* enum: RXDP Test firmware image 9 */
9904 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9905 /* enum: RXDP Test firmware image 10 */
9906 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
9907 /* TxDPCPU firmware id. */
9908 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
9909 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
9910 /* enum: Standard TXDP firmware */
9911 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
9912 /* enum: Low latency TXDP firmware */
9913 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
9914 /* enum: High packet rate TXDP firmware */
9915 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
9916 /* enum: Rules engine TXDP firmware */
9917 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
9918 /* enum: DPDK TXDP firmware */
9919 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
9920 /* enum: BIST TXDP firmware */
9921 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
9922 /* enum: TXDP Test firmware image 1 */
9923 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9924 /* enum: TXDP Test firmware image 2 */
9925 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9926 /* enum: TXDP CSR bus test firmware */
9927 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
9928 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
9929 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
9930 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
9931 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9932 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9933 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9934 /* enum: reserved value - do not use (may indicate alternative interpretation
9935  * of REV field in future)
9936  */
9937 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
9938 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9939  * development only)
9940  */
9941 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9942 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9943  * (Huntington development only)
9944  */
9945 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9946 /* enum: Full featured RX PD production firmware */
9947 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9948 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9949 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9950 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9951  * (Huntington development only)
9952  */
9953 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9954 /* enum: Low latency RX PD production firmware */
9955 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9956 /* enum: Packed stream RX PD production firmware */
9957 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9958 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9959  * tests (Medford development only)
9960  */
9961 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9962 /* enum: Rules engine RX PD production firmware */
9963 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9964 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9965 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
9966 /* enum: DPDK RX PD production firmware */
9967 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
9968 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9969 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9970 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9971  * encapsulations (Medford development only)
9972  */
9973 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9974 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
9975 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
9976 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
9977 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9978 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9979 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9980 /* enum: reserved value - do not use (may indicate alternative interpretation
9981  * of REV field in future)
9982  */
9983 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
9984 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9985  * development only)
9986  */
9987 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9988 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9989  * (Huntington development only)
9990  */
9991 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9992 /* enum: Full featured TX PD production firmware */
9993 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9994 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9995 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9996 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9997  * (Huntington development only)
9998  */
9999 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10000 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10001 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10002  * tests (Medford development only)
10003  */
10004 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10005 /* enum: Rules engine TX PD production firmware */
10006 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10007 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10008 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10009 /* enum: DPDK TX PD production firmware */
10010 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
10011 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10012 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10013 /* Hardware capabilities of NIC */
10014 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
10015 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
10016 /* Licensed capabilities */
10017 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
10018 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
10019 /* Second word of flags. Not present on older firmware (check the length). */
10020 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
10021 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
10022 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
10023 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
10024 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
10025 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10026 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
10027 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
10028 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
10029 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
10030 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
10031 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
10032 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
10033 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10034 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10035 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10036 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
10037 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
10038 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
10039 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10040 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
10041 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
10042 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
10043 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
10044 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
10045 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
10046 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10047 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10048 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
10049 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
10050 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
10051 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
10052 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
10053 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
10054 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
10055 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
10056 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
10057 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
10058 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10059 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10060 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
10061 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
10062 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
10063 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
10064 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10065 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10066 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
10067 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
10068 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10069 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10070 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
10071 #define        MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
10072 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10073  * on older firmware (check the length).
10074  */
10075 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10076 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10077 /* One byte per PF containing the number of the external port assigned to this
10078  * PF, indexed by PF number. Special values indicate that a PF is either not
10079  * present or not assigned.
10080  */
10081 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10082 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10083 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10084 /* enum: The caller is not permitted to access information on this PF. */
10085 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
10086 /* enum: PF does not exist. */
10087 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
10088 /* enum: PF does exist but is not assigned to any external port. */
10089 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
10090 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10091  * in this field. It is intended for a possible future situation where a more
10092  * complex scheme of PFs to ports mapping is being used. The future driver
10093  * should look for a new field supporting the new scheme. The current/old
10094  * driver should treat this value as PF_NOT_ASSIGNED.
10095  */
10096 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10097 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10098  * special value indicates that a PF is not present.
10099  */
10100 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
10101 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
10102 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
10103 /* enum: The caller is not permitted to access information on this PF. */
10104 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
10105 /* enum: PF does not exist. */
10106 /*               MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
10107 /* Number of VIs available for each external port */
10108 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
10109 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
10110 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
10111 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10112  * equals (2 ^ RX_DESC_CACHE_SIZE)
10113  */
10114 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
10115 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
10116 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10117  * equals (2 ^ TX_DESC_CACHE_SIZE)
10118  */
10119 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
10120 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
10121 /* Total number of available PIO buffers */
10122 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
10123 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
10124 /* Size of a single PIO buffer */
10125 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
10126 #define       MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
10127 
10128 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
10129 #define    MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
10130 /* First word of flags. */
10131 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
10132 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
10133 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
10134 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
10135 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
10136 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
10137 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
10138 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
10139 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10140 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10141 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
10142 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10143 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10144 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10145 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
10146 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
10147 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10148 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10149 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10150 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10151 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10152 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10153 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
10154 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10155 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
10156 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
10157 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10158 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10159 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
10160 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
10161 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
10162 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
10163 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
10164 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
10165 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
10166 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
10167 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
10168 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
10169 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
10170 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
10171 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
10172 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
10173 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
10174 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
10175 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
10176 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
10177 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
10178 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
10179 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
10180 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10181 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10182 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10183 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
10184 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
10185 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10186 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10187 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
10188 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
10189 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
10190 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
10191 /* RxDPCPU firmware id. */
10192 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
10193 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
10194 /* enum: Standard RXDP firmware */
10195 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
10196 /* enum: Low latency RXDP firmware */
10197 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
10198 /* enum: Packed stream RXDP firmware */
10199 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
10200 /* enum: Rules engine RXDP firmware */
10201 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
10202 /* enum: DPDK RXDP firmware */
10203 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
10204 /* enum: BIST RXDP firmware */
10205 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
10206 /* enum: RXDP Test firmware image 1 */
10207 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10208 /* enum: RXDP Test firmware image 2 */
10209 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10210 /* enum: RXDP Test firmware image 3 */
10211 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10212 /* enum: RXDP Test firmware image 4 */
10213 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10214 /* enum: RXDP Test firmware image 5 */
10215 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
10216 /* enum: RXDP Test firmware image 6 */
10217 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10218 /* enum: RXDP Test firmware image 7 */
10219 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10220 /* enum: RXDP Test firmware image 8 */
10221 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10222 /* enum: RXDP Test firmware image 9 */
10223 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10224 /* enum: RXDP Test firmware image 10 */
10225 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
10226 /* TxDPCPU firmware id. */
10227 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
10228 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
10229 /* enum: Standard TXDP firmware */
10230 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
10231 /* enum: Low latency TXDP firmware */
10232 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
10233 /* enum: High packet rate TXDP firmware */
10234 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
10235 /* enum: Rules engine TXDP firmware */
10236 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
10237 /* enum: DPDK TXDP firmware */
10238 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
10239 /* enum: BIST TXDP firmware */
10240 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
10241 /* enum: TXDP Test firmware image 1 */
10242 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10243 /* enum: TXDP Test firmware image 2 */
10244 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10245 /* enum: TXDP CSR bus test firmware */
10246 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
10247 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
10248 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
10249 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
10250 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10251 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10252 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10253 /* enum: reserved value - do not use (may indicate alternative interpretation
10254  * of REV field in future)
10255  */
10256 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
10257 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10258  * development only)
10259  */
10260 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10261 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10262  * (Huntington development only)
10263  */
10264 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10265 /* enum: Full featured RX PD production firmware */
10266 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10267 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10268 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10269 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10270  * (Huntington development only)
10271  */
10272 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10273 /* enum: Low latency RX PD production firmware */
10274 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10275 /* enum: Packed stream RX PD production firmware */
10276 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10277 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10278  * tests (Medford development only)
10279  */
10280 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10281 /* enum: Rules engine RX PD production firmware */
10282 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10283 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10284 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10285 /* enum: DPDK RX PD production firmware */
10286 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
10287 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10288 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10289 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10290  * encapsulations (Medford development only)
10291  */
10292 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10293 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
10294 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
10295 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
10296 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10297 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10298 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10299 /* enum: reserved value - do not use (may indicate alternative interpretation
10300  * of REV field in future)
10301  */
10302 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
10303 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10304  * development only)
10305  */
10306 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10307 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10308  * (Huntington development only)
10309  */
10310 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10311 /* enum: Full featured TX PD production firmware */
10312 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10313 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10314 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10315 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10316  * (Huntington development only)
10317  */
10318 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10319 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10320 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10321  * tests (Medford development only)
10322  */
10323 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10324 /* enum: Rules engine TX PD production firmware */
10325 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10326 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10327 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10328 /* enum: DPDK TX PD production firmware */
10329 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
10330 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10331 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10332 /* Hardware capabilities of NIC */
10333 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
10334 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
10335 /* Licensed capabilities */
10336 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
10337 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
10338 /* Second word of flags. Not present on older firmware (check the length). */
10339 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
10340 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
10341 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
10342 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
10343 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
10344 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10345 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
10346 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
10347 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
10348 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
10349 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
10350 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
10351 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
10352 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10353 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10354 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10355 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
10356 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
10357 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
10358 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10359 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
10360 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
10361 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
10362 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
10363 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
10364 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
10365 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10366 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10367 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
10368 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
10369 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
10370 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
10371 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
10372 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
10373 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
10374 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
10375 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
10376 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
10377 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10378 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10379 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
10380 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
10381 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
10382 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
10383 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10384 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10385 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
10386 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
10387 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10388 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10389 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
10390 #define        MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
10391 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10392  * on older firmware (check the length).
10393  */
10394 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10395 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10396 /* One byte per PF containing the number of the external port assigned to this
10397  * PF, indexed by PF number. Special values indicate that a PF is either not
10398  * present or not assigned.
10399  */
10400 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10401 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10402 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10403 /* enum: The caller is not permitted to access information on this PF. */
10404 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
10405 /* enum: PF does not exist. */
10406 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
10407 /* enum: PF does exist but is not assigned to any external port. */
10408 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
10409 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10410  * in this field. It is intended for a possible future situation where a more
10411  * complex scheme of PFs to ports mapping is being used. The future driver
10412  * should look for a new field supporting the new scheme. The current/old
10413  * driver should treat this value as PF_NOT_ASSIGNED.
10414  */
10415 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10416 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10417  * special value indicates that a PF is not present.
10418  */
10419 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
10420 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
10421 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
10422 /* enum: The caller is not permitted to access information on this PF. */
10423 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
10424 /* enum: PF does not exist. */
10425 /*               MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
10426 /* Number of VIs available for each external port */
10427 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
10428 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
10429 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
10430 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10431  * equals (2 ^ RX_DESC_CACHE_SIZE)
10432  */
10433 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
10434 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
10435 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10436  * equals (2 ^ TX_DESC_CACHE_SIZE)
10437  */
10438 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
10439 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
10440 /* Total number of available PIO buffers */
10441 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
10442 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
10443 /* Size of a single PIO buffer */
10444 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
10445 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
10446 /* On chips later than Medford the amount of address space assigned to each VI
10447  * is configurable. This is a global setting that the driver must query to
10448  * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
10449  * with 8k VI windows.
10450  */
10451 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
10452 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
10453 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10454  * CTPIO is not mapped.
10455  */
10456 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
10457 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10458 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
10459 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10460 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
10461 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
10462  * (SF-115995-SW) in the present configuration of firmware and port mode.
10463  */
10464 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
10465 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
10466 /* Number of buffers per adapter that can be used for VFIFO Stuffing
10467  * (SF-115995-SW) in the present configuration of firmware and port mode.
10468  */
10469 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
10470 #define       MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
10471 
10472 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
10473 #define    MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
10474 /* First word of flags. */
10475 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
10476 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
10477 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
10478 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
10479 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
10480 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
10481 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
10482 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
10483 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10484 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10485 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
10486 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10487 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10488 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10489 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
10490 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
10491 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10492 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10493 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10494 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10495 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10496 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10497 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
10498 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10499 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
10500 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
10501 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10502 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10503 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
10504 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
10505 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
10506 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
10507 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
10508 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
10509 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
10510 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
10511 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
10512 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
10513 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
10514 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
10515 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
10516 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
10517 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
10518 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
10519 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
10520 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
10521 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
10522 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
10523 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
10524 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10525 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10526 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10527 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
10528 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
10529 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10530 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10531 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
10532 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
10533 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
10534 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
10535 /* RxDPCPU firmware id. */
10536 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
10537 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
10538 /* enum: Standard RXDP firmware */
10539 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
10540 /* enum: Low latency RXDP firmware */
10541 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
10542 /* enum: Packed stream RXDP firmware */
10543 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
10544 /* enum: Rules engine RXDP firmware */
10545 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
10546 /* enum: DPDK RXDP firmware */
10547 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
10548 /* enum: BIST RXDP firmware */
10549 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
10550 /* enum: RXDP Test firmware image 1 */
10551 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10552 /* enum: RXDP Test firmware image 2 */
10553 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10554 /* enum: RXDP Test firmware image 3 */
10555 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10556 /* enum: RXDP Test firmware image 4 */
10557 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10558 /* enum: RXDP Test firmware image 5 */
10559 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
10560 /* enum: RXDP Test firmware image 6 */
10561 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10562 /* enum: RXDP Test firmware image 7 */
10563 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10564 /* enum: RXDP Test firmware image 8 */
10565 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10566 /* enum: RXDP Test firmware image 9 */
10567 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10568 /* enum: RXDP Test firmware image 10 */
10569 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
10570 /* TxDPCPU firmware id. */
10571 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
10572 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
10573 /* enum: Standard TXDP firmware */
10574 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
10575 /* enum: Low latency TXDP firmware */
10576 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
10577 /* enum: High packet rate TXDP firmware */
10578 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
10579 /* enum: Rules engine TXDP firmware */
10580 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
10581 /* enum: DPDK TXDP firmware */
10582 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
10583 /* enum: BIST TXDP firmware */
10584 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
10585 /* enum: TXDP Test firmware image 1 */
10586 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10587 /* enum: TXDP Test firmware image 2 */
10588 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10589 /* enum: TXDP CSR bus test firmware */
10590 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
10591 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
10592 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
10593 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
10594 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
10595 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
10596 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
10597 /* enum: reserved value - do not use (may indicate alternative interpretation
10598  * of REV field in future)
10599  */
10600 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
10601 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10602  * development only)
10603  */
10604 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10605 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10606  * (Huntington development only)
10607  */
10608 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10609 /* enum: Full featured RX PD production firmware */
10610 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10611 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10612 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10613 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10614  * (Huntington development only)
10615  */
10616 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10617 /* enum: Low latency RX PD production firmware */
10618 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10619 /* enum: Packed stream RX PD production firmware */
10620 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10621 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10622  * tests (Medford development only)
10623  */
10624 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10625 /* enum: Rules engine RX PD production firmware */
10626 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10627 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10628 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10629 /* enum: DPDK RX PD production firmware */
10630 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
10631 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10632 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10633 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10634  * encapsulations (Medford development only)
10635  */
10636 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10637 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
10638 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
10639 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
10640 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10641 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10642 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10643 /* enum: reserved value - do not use (may indicate alternative interpretation
10644  * of REV field in future)
10645  */
10646 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
10647 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10648  * development only)
10649  */
10650 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10651 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10652  * (Huntington development only)
10653  */
10654 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10655 /* enum: Full featured TX PD production firmware */
10656 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10657 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10658 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10659 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10660  * (Huntington development only)
10661  */
10662 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10663 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10664 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10665  * tests (Medford development only)
10666  */
10667 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10668 /* enum: Rules engine TX PD production firmware */
10669 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10670 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10671 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10672 /* enum: DPDK TX PD production firmware */
10673 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
10674 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10675 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10676 /* Hardware capabilities of NIC */
10677 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
10678 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
10679 /* Licensed capabilities */
10680 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
10681 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
10682 /* Second word of flags. Not present on older firmware (check the length). */
10683 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
10684 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
10685 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
10686 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
10687 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
10688 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10689 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
10690 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
10691 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
10692 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
10693 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
10694 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
10695 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
10696 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10697 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10698 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10699 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
10700 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
10701 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
10702 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10703 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
10704 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
10705 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
10706 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
10707 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
10708 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
10709 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10710 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10711 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
10712 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
10713 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
10714 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
10715 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
10716 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
10717 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
10718 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
10719 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
10720 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
10721 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
10722 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
10723 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
10724 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
10725 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
10726 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
10727 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
10728 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
10729 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
10730 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
10731 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
10732 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
10733 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
10734 #define        MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
10735 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10736  * on older firmware (check the length).
10737  */
10738 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10739 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10740 /* One byte per PF containing the number of the external port assigned to this
10741  * PF, indexed by PF number. Special values indicate that a PF is either not
10742  * present or not assigned.
10743  */
10744 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10745 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10746 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10747 /* enum: The caller is not permitted to access information on this PF. */
10748 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
10749 /* enum: PF does not exist. */
10750 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
10751 /* enum: PF does exist but is not assigned to any external port. */
10752 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
10753 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10754  * in this field. It is intended for a possible future situation where a more
10755  * complex scheme of PFs to ports mapping is being used. The future driver
10756  * should look for a new field supporting the new scheme. The current/old
10757  * driver should treat this value as PF_NOT_ASSIGNED.
10758  */
10759 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10760 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10761  * special value indicates that a PF is not present.
10762  */
10763 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
10764 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
10765 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
10766 /* enum: The caller is not permitted to access information on this PF. */
10767 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
10768 /* enum: PF does not exist. */
10769 /*               MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
10770 /* Number of VIs available for each external port */
10771 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
10772 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
10773 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
10774 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10775  * equals (2 ^ RX_DESC_CACHE_SIZE)
10776  */
10777 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
10778 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
10779 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10780  * equals (2 ^ TX_DESC_CACHE_SIZE)
10781  */
10782 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
10783 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
10784 /* Total number of available PIO buffers */
10785 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
10786 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
10787 /* Size of a single PIO buffer */
10788 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
10789 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
10790 /* On chips later than Medford the amount of address space assigned to each VI
10791  * is configurable. This is a global setting that the driver must query to
10792  * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
10793  * with 8k VI windows.
10794  */
10795 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
10796 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
10797 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10798  * CTPIO is not mapped.
10799  */
10800 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
10801 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10802 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
10803 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10804 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
10805 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
10806  * (SF-115995-SW) in the present configuration of firmware and port mode.
10807  */
10808 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
10809 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
10810 /* Number of buffers per adapter that can be used for VFIFO Stuffing
10811  * (SF-115995-SW) in the present configuration of firmware and port mode.
10812  */
10813 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
10814 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
10815 /* Entry count in the MAC stats array, including the final GENERATION_END
10816  * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
10817  * hold at least this many 64-bit stats values, if they wish to receive all
10818  * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
10819  * stats array returned will be truncated.
10820  */
10821 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
10822 #define       MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
10823 
10824 
10825 /***********************************/
10826 /* MC_CMD_V2_EXTN
10827  * Encapsulation for a v2 extended command
10828  */
10829 #define MC_CMD_V2_EXTN 0x7f
10830 
10831 /* MC_CMD_V2_EXTN_IN msgrequest */
10832 #define    MC_CMD_V2_EXTN_IN_LEN 4
10833 /* the extended command number */
10834 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
10835 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
10836 #define       MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
10837 #define       MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
10838 /* the actual length of the encapsulated command (which is not in the v1
10839  * header)
10840  */
10841 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
10842 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
10843 #define       MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
10844 #define       MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
10845 /* Type of command/response */
10846 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
10847 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
10848 /* enum: MCDI command directed to or response originating from the MC. */
10849 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
10850 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type
10851  * are not defined.
10852  */
10853 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
10854 
10855 
10856 /***********************************/
10857 /* MC_CMD_TCM_BUCKET_ALLOC
10858  * Allocate a pacer bucket (for qau rp or a snapper test)
10859  */
10860 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
10861 
10862 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10863 
10864 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
10865 #define    MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
10866 
10867 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
10868 #define    MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
10869 /* the bucket id */
10870 #define       MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
10871 #define       MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
10872 
10873 
10874 /***********************************/
10875 /* MC_CMD_TCM_BUCKET_FREE
10876  * Free a pacer bucket
10877  */
10878 #define MC_CMD_TCM_BUCKET_FREE 0xb3
10879 
10880 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10881 
10882 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
10883 #define    MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
10884 /* the bucket id */
10885 #define       MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
10886 #define       MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
10887 
10888 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
10889 #define    MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
10890 
10891 
10892 /***********************************/
10893 /* MC_CMD_TCM_BUCKET_INIT
10894  * Initialise pacer bucket with a given rate
10895  */
10896 #define MC_CMD_TCM_BUCKET_INIT 0xb4
10897 
10898 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10899 
10900 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
10901 #define    MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
10902 /* the bucket id */
10903 #define       MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
10904 #define       MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
10905 /* the rate in mbps */
10906 #define       MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
10907 #define       MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
10908 
10909 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */
10910 #define    MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12
10911 /* the bucket id */
10912 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
10913 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
10914 /* the rate in mbps */
10915 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
10916 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
10917 /* the desired maximum fill level */
10918 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8
10919 #define       MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
10920 
10921 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
10922 #define    MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
10923 
10924 
10925 /***********************************/
10926 /* MC_CMD_TCM_TXQ_INIT
10927  * Initialise txq in pacer with given options or set options
10928  */
10929 #define MC_CMD_TCM_TXQ_INIT 0xb5
10930 
10931 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10932 
10933 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
10934 #define    MC_CMD_TCM_TXQ_INIT_IN_LEN 28
10935 /* the txq id */
10936 #define       MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
10937 #define       MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
10938 /* the static priority associated with the txq */
10939 #define       MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
10940 #define       MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
10941 /* bitmask of the priority queues this txq is inserted into when inserted. */
10942 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
10943 #define       MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
10944 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
10945 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10946 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
10947 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
10948 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
10949 #define        MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
10950 /* the reaction point (RP) bucket */
10951 #define       MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
10952 #define       MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
10953 /* an already reserved bucket (typically set to bucket associated with outer
10954  * vswitch)
10955  */
10956 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
10957 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
10958 /* an already reserved bucket (typically set to bucket associated with inner
10959  * vswitch)
10960  */
10961 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
10962 #define       MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
10963 /* the min bucket (typically for ETS/minimum bandwidth) */
10964 #define       MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
10965 #define       MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
10966 
10967 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */
10968 #define    MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32
10969 /* the txq id */
10970 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
10971 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
10972 /* the static priority associated with the txq */
10973 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
10974 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
10975 /* bitmask of the priority queues this txq is inserted into when inserted. */
10976 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
10977 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
10978 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
10979 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10980 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
10981 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
10982 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
10983 #define        MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
10984 /* the reaction point (RP) bucket */
10985 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12
10986 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
10987 /* an already reserved bucket (typically set to bucket associated with outer
10988  * vswitch)
10989  */
10990 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16
10991 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
10992 /* an already reserved bucket (typically set to bucket associated with inner
10993  * vswitch)
10994  */
10995 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20
10996 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
10997 /* the min bucket (typically for ETS/minimum bandwidth) */
10998 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24
10999 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
11000 /* the static priority associated with the txq */
11001 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28
11002 #define       MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
11003 
11004 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
11005 #define    MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
11006 
11007 
11008 /***********************************/
11009 /* MC_CMD_LINK_PIOBUF
11010  * Link a push I/O buffer to a TxQ
11011  */
11012 #define MC_CMD_LINK_PIOBUF 0x92
11013 
11014 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11015 
11016 /* MC_CMD_LINK_PIOBUF_IN msgrequest */
11017 #define    MC_CMD_LINK_PIOBUF_IN_LEN 8
11018 /* Handle for allocated push I/O buffer. */
11019 #define       MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
11020 #define       MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
11021 /* Function Local Instance (VI) number. */
11022 #define       MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
11023 #define       MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
11024 
11025 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */
11026 #define    MC_CMD_LINK_PIOBUF_OUT_LEN 0
11027 
11028 
11029 /***********************************/
11030 /* MC_CMD_UNLINK_PIOBUF
11031  * Unlink a push I/O buffer from a TxQ
11032  */
11033 #define MC_CMD_UNLINK_PIOBUF 0x93
11034 
11035 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11036 
11037 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
11038 #define    MC_CMD_UNLINK_PIOBUF_IN_LEN 4
11039 /* Function Local Instance (VI) number. */
11040 #define       MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
11041 #define       MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
11042 
11043 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
11044 #define    MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
11045 
11046 
11047 /***********************************/
11048 /* MC_CMD_VSWITCH_ALLOC
11049  * allocate and initialise a v-switch.
11050  */
11051 #define MC_CMD_VSWITCH_ALLOC 0x94
11052 
11053 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11054 
11055 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
11056 #define    MC_CMD_VSWITCH_ALLOC_IN_LEN 16
11057 /* The port to connect to the v-switch's upstream port. */
11058 #define       MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11059 #define       MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11060 /* The type of v-switch to create. */
11061 #define       MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
11062 #define       MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
11063 /* enum: VLAN */
11064 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
11065 /* enum: VEB */
11066 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
11067 /* enum: VEPA (obsolete) */
11068 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
11069 /* enum: MUX */
11070 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
11071 /* enum: Snapper specific; semantics TBD */
11072 #define          MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
11073 /* Flags controlling v-port creation */
11074 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
11075 #define       MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
11076 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11077 #define        MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
11078 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
11079  * this must be one or greated, and the attached v-ports must have exactly this
11080  * number of tags. For other v-switch types, this must be zero of greater, and
11081  * is an upper limit on the number of VLAN tags for attached v-ports. An error
11082  * will be returned if existing configuration means we can't support attached
11083  * v-ports with this number of tags.
11084  */
11085 #define       MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
11086 #define       MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11087 
11088 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
11089 #define    MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
11090 
11091 
11092 /***********************************/
11093 /* MC_CMD_VSWITCH_FREE
11094  * de-allocate a v-switch.
11095  */
11096 #define MC_CMD_VSWITCH_FREE 0x95
11097 
11098 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11099 
11100 /* MC_CMD_VSWITCH_FREE_IN msgrequest */
11101 #define    MC_CMD_VSWITCH_FREE_IN_LEN 4
11102 /* The port to which the v-switch is connected. */
11103 #define       MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11104 #define       MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
11105 
11106 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */
11107 #define    MC_CMD_VSWITCH_FREE_OUT_LEN 0
11108 
11109 
11110 /***********************************/
11111 /* MC_CMD_VSWITCH_QUERY
11112  * read some config of v-switch. For now this command is an empty placeholder.
11113  * It may be used to check if a v-switch is connected to a given EVB port (if
11114  * not, then the command returns ENOENT).
11115  */
11116 #define MC_CMD_VSWITCH_QUERY 0x63
11117 
11118 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11119 
11120 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */
11121 #define    MC_CMD_VSWITCH_QUERY_IN_LEN 4
11122 /* The port to which the v-switch is connected. */
11123 #define       MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11124 #define       MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
11125 
11126 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
11127 #define    MC_CMD_VSWITCH_QUERY_OUT_LEN 0
11128 
11129 
11130 /***********************************/
11131 /* MC_CMD_VPORT_ALLOC
11132  * allocate a v-port.
11133  */
11134 #define MC_CMD_VPORT_ALLOC 0x96
11135 
11136 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11137 
11138 /* MC_CMD_VPORT_ALLOC_IN msgrequest */
11139 #define    MC_CMD_VPORT_ALLOC_IN_LEN 20
11140 /* The port to which the v-switch is connected. */
11141 #define       MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11142 #define       MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11143 /* The type of the new v-port. */
11144 #define       MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
11145 #define       MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
11146 /* enum: VLAN (obsolete) */
11147 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
11148 /* enum: VEB (obsolete) */
11149 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
11150 /* enum: VEPA (obsolete) */
11151 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
11152 /* enum: A normal v-port receives packets which match a specified MAC and/or
11153  * VLAN.
11154  */
11155 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
11156 /* enum: An expansion v-port packets traffic which don't match any other
11157  * v-port.
11158  */
11159 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
11160 /* enum: An test v-port receives packets which match any filters installed by
11161  * its downstream components.
11162  */
11163 #define          MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
11164 /* Flags controlling v-port creation */
11165 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
11166 #define       MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
11167 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11168 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
11169 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
11170 #define        MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
11171 /* The number of VLAN tags to insert/remove. An error will be returned if
11172  * incompatible with the number of VLAN tags specified for the upstream
11173  * v-switch.
11174  */
11175 #define       MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
11176 #define       MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11177 /* The actual VLAN tags to insert/remove */
11178 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
11179 #define       MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
11180 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
11181 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
11182 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
11183 #define        MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
11184 
11185 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */
11186 #define    MC_CMD_VPORT_ALLOC_OUT_LEN 4
11187 /* The handle of the new v-port */
11188 #define       MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
11189 #define       MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
11190 
11191 
11192 /***********************************/
11193 /* MC_CMD_VPORT_FREE
11194  * de-allocate a v-port.
11195  */
11196 #define MC_CMD_VPORT_FREE 0x97
11197 
11198 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11199 
11200 /* MC_CMD_VPORT_FREE_IN msgrequest */
11201 #define    MC_CMD_VPORT_FREE_IN_LEN 4
11202 /* The handle of the v-port */
11203 #define       MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
11204 #define       MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
11205 
11206 /* MC_CMD_VPORT_FREE_OUT msgresponse */
11207 #define    MC_CMD_VPORT_FREE_OUT_LEN 0
11208 
11209 
11210 /***********************************/
11211 /* MC_CMD_VADAPTOR_ALLOC
11212  * allocate a v-adaptor.
11213  */
11214 #define MC_CMD_VADAPTOR_ALLOC 0x98
11215 
11216 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11217 
11218 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
11219 #define    MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
11220 /* The port to connect to the v-adaptor's port. */
11221 #define       MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11222 #define       MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11223 /* Flags controlling v-adaptor creation */
11224 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
11225 #define       MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
11226 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
11227 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
11228 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
11229 #define        MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11230 /* The number of VLAN tags to strip on receive */
11231 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
11232 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
11233 /* The number of VLAN tags to transparently insert/remove. */
11234 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
11235 #define       MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
11236 /* The actual VLAN tags to insert/remove */
11237 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
11238 #define       MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
11239 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
11240 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
11241 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
11242 #define        MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
11243 /* The MAC address to assign to this v-adaptor */
11244 #define       MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
11245 #define       MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
11246 /* enum: Derive the MAC address from the upstream port */
11247 #define          MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
11248 
11249 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
11250 #define    MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
11251 
11252 
11253 /***********************************/
11254 /* MC_CMD_VADAPTOR_FREE
11255  * de-allocate a v-adaptor.
11256  */
11257 #define MC_CMD_VADAPTOR_FREE 0x99
11258 
11259 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11260 
11261 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */
11262 #define    MC_CMD_VADAPTOR_FREE_IN_LEN 4
11263 /* The port to which the v-adaptor is connected. */
11264 #define       MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11265 #define       MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
11266 
11267 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
11268 #define    MC_CMD_VADAPTOR_FREE_OUT_LEN 0
11269 
11270 
11271 /***********************************/
11272 /* MC_CMD_VADAPTOR_SET_MAC
11273  * assign a new MAC address to a v-adaptor.
11274  */
11275 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
11276 
11277 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11278 
11279 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
11280 #define    MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
11281 /* The port to which the v-adaptor is connected. */
11282 #define       MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11283 #define       MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
11284 /* The new MAC address to assign to this v-adaptor */
11285 #define       MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
11286 #define       MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
11287 
11288 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
11289 #define    MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
11290 
11291 
11292 /***********************************/
11293 /* MC_CMD_VADAPTOR_GET_MAC
11294  * read the MAC address assigned to a v-adaptor.
11295  */
11296 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
11297 
11298 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11299 
11300 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
11301 #define    MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
11302 /* The port to which the v-adaptor is connected. */
11303 #define       MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11304 #define       MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
11305 
11306 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
11307 #define    MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
11308 /* The MAC address assigned to this v-adaptor */
11309 #define       MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
11310 #define       MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
11311 
11312 
11313 /***********************************/
11314 /* MC_CMD_VADAPTOR_QUERY
11315  * read some config of v-adaptor.
11316  */
11317 #define MC_CMD_VADAPTOR_QUERY 0x61
11318 
11319 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11320 
11321 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
11322 #define    MC_CMD_VADAPTOR_QUERY_IN_LEN 4
11323 /* The port to which the v-adaptor is connected. */
11324 #define       MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11325 #define       MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
11326 
11327 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
11328 #define    MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
11329 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11330 #define       MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
11331 #define       MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
11332 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
11333 #define       MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
11334 #define       MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
11335 /* The number of VLAN tags that may still be added */
11336 #define       MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
11337 #define       MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
11338 
11339 
11340 /***********************************/
11341 /* MC_CMD_EVB_PORT_ASSIGN
11342  * assign a port to a PCI function.
11343  */
11344 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
11345 
11346 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11347 
11348 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
11349 #define    MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
11350 /* The port to assign. */
11351 #define       MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
11352 #define       MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
11353 /* The target function to modify. */
11354 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
11355 #define       MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
11356 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
11357 #define        MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
11358 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
11359 #define        MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
11360 
11361 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
11362 #define    MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
11363 
11364 
11365 /***********************************/
11366 /* MC_CMD_RDWR_A64_REGIONS
11367  * Assign the 64 bit region addresses.
11368  */
11369 #define MC_CMD_RDWR_A64_REGIONS 0x9b
11370 
11371 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11372 
11373 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
11374 #define    MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
11375 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
11376 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
11377 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
11378 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
11379 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
11380 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
11381 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
11382 #define       MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
11383 /* Write enable bits 0-3, set to write, clear to read. */
11384 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
11385 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
11386 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
11387 #define       MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
11388 
11389 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
11390  * regardless of state of write bits in the request.
11391  */
11392 #define    MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
11393 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
11394 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
11395 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
11396 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
11397 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
11398 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
11399 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
11400 #define       MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
11401 
11402 
11403 /***********************************/
11404 /* MC_CMD_ONLOAD_STACK_ALLOC
11405  * Allocate an Onload stack ID.
11406  */
11407 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
11408 
11409 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11410 
11411 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
11412 #define    MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
11413 /* The handle of the owning upstream port */
11414 #define       MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11415 #define       MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11416 
11417 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
11418 #define    MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
11419 /* The handle of the new Onload stack */
11420 #define       MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
11421 #define       MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
11422 
11423 
11424 /***********************************/
11425 /* MC_CMD_ONLOAD_STACK_FREE
11426  * Free an Onload stack ID.
11427  */
11428 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
11429 
11430 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11431 
11432 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
11433 #define    MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
11434 /* The handle of the Onload stack */
11435 #define       MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
11436 #define       MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
11437 
11438 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
11439 #define    MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
11440 
11441 
11442 /***********************************/
11443 /* MC_CMD_RSS_CONTEXT_ALLOC
11444  * Allocate an RSS context.
11445  */
11446 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
11447 
11448 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11449 
11450 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
11451 #define    MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
11452 /* The handle of the owning upstream port */
11453 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11454 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11455 /* The type of context to allocate */
11456 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
11457 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
11458 /* enum: Allocate a context for exclusive use. The key and indirection table
11459  * must be explicitly configured.
11460  */
11461 #define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
11462 /* enum: Allocate a context for shared use; this will spread across a range of
11463  * queues, but the key and indirection table are pre-configured and may not be
11464  * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
11465  */
11466 #define          MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
11467 /* Number of queues spanned by this context, in the range 1-64; valid offsets
11468  * in the indirection table will be in the range 0 to NUM_QUEUES-1.
11469  */
11470 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
11471 #define       MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
11472 
11473 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
11474 #define    MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
11475 /* The handle of the new RSS context. This should be considered opaque to the
11476  * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11477  * handle.
11478  */
11479 #define       MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
11480 #define       MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
11481 /* enum: guaranteed invalid RSS context handle value */
11482 #define          MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
11483 
11484 
11485 /***********************************/
11486 /* MC_CMD_RSS_CONTEXT_FREE
11487  * Free an RSS context.
11488  */
11489 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
11490 
11491 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11492 
11493 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
11494 #define    MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
11495 /* The handle of the RSS context */
11496 #define       MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
11497 #define       MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
11498 
11499 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
11500 #define    MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
11501 
11502 
11503 /***********************************/
11504 /* MC_CMD_RSS_CONTEXT_SET_KEY
11505  * Set the Toeplitz hash key for an RSS context.
11506  */
11507 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
11508 
11509 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11510 
11511 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
11512 #define    MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
11513 /* The handle of the RSS context */
11514 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11515 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
11516 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11517 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
11518 #define       MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
11519 
11520 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
11521 #define    MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
11522 
11523 
11524 /***********************************/
11525 /* MC_CMD_RSS_CONTEXT_GET_KEY
11526  * Get the Toeplitz hash key for an RSS context.
11527  */
11528 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
11529 
11530 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11531 
11532 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
11533 #define    MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
11534 /* The handle of the RSS context */
11535 #define       MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
11536 #define       MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
11537 
11538 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
11539 #define    MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
11540 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
11541 #define       MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
11542 #define       MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
11543 
11544 
11545 /***********************************/
11546 /* MC_CMD_RSS_CONTEXT_SET_TABLE
11547  * Set the indirection table for an RSS context.
11548  */
11549 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
11550 
11551 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11552 
11553 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
11554 #define    MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
11555 /* The handle of the RSS context */
11556 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11557 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
11558 /* The 128-byte indirection table (1 byte per entry) */
11559 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
11560 #define       MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
11561 
11562 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
11563 #define    MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
11564 
11565 
11566 /***********************************/
11567 /* MC_CMD_RSS_CONTEXT_GET_TABLE
11568  * Get the indirection table for an RSS context.
11569  */
11570 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
11571 
11572 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11573 
11574 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
11575 #define    MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
11576 /* The handle of the RSS context */
11577 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
11578 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
11579 
11580 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
11581 #define    MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
11582 /* The 128-byte indirection table (1 byte per entry) */
11583 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
11584 #define       MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
11585 
11586 
11587 /***********************************/
11588 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
11589  * Set various control flags for an RSS context.
11590  */
11591 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
11592 
11593 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11594 
11595 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
11596 #define    MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
11597 /* The handle of the RSS context */
11598 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11599 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
11600 /* Hash control flags. The _EN bits are always supported, but new modes are
11601  * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
11602  * in this case, the MODE fields may be set to non-zero values, and will take
11603  * effect regardless of the settings of the _EN flags. See the RSS_MODE
11604  * structure for the meaning of the mode bits. Drivers must check the
11605  * capability before trying to set any _MODE fields, as older firmware will
11606  * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
11607  * the case where all the _MODE flags are zero, the _EN flags take effect,
11608  * providing backward compatibility for existing drivers. (Setting all _MODE
11609  * *and* all _EN flags to zero is valid, to disable RSS spreading for that
11610  * particular packet type.)
11611  */
11612 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
11613 #define       MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
11614 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
11615 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
11616 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
11617 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
11618 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
11619 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
11620 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
11621 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
11622 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
11623 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
11624 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
11625 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
11626 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
11627 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
11628 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
11629 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
11630 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
11631 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
11632 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
11633 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
11634 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
11635 #define        MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
11636 
11637 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
11638 #define    MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
11639 
11640 
11641 /***********************************/
11642 /* MC_CMD_RSS_CONTEXT_GET_FLAGS
11643  * Get various control flags for an RSS context.
11644  */
11645 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
11646 
11647 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11648 
11649 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
11650 #define    MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
11651 /* The handle of the RSS context */
11652 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11653 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
11654 
11655 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
11656 #define    MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
11657 /* Hash control flags. If all _MODE bits are zero (which will always be true
11658  * for older firmware which does not report the ADDITIONAL_RSS_MODES
11659  * capability), the _EN bits report the state. If any _MODE bits are non-zero
11660  * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
11661  * then the _EN bits should be disregarded, although the _MODE flags are
11662  * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
11663  * context and in the case where the _EN flags were used in the SET. This
11664  * provides backward compatibility: old drivers will not be attempting to
11665  * derive any meaning from the _MODE bits (and can never set them to any value
11666  * not representable by the _EN bits); new drivers can always determine the
11667  * mode by looking only at the _MODE bits; the value returned by a GET can
11668  * always be used for a SET regardless of old/new driver vs. old/new firmware.
11669  */
11670 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
11671 #define       MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
11672 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
11673 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
11674 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
11675 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
11676 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
11677 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
11678 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
11679 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
11680 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
11681 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
11682 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
11683 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
11684 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
11685 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
11686 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
11687 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
11688 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
11689 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
11690 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
11691 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
11692 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
11693 #define        MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
11694 
11695 
11696 /***********************************/
11697 /* MC_CMD_DOT1P_MAPPING_ALLOC
11698  * Allocate a .1p mapping.
11699  */
11700 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
11701 
11702 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11703 
11704 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
11705 #define    MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
11706 /* The handle of the owning upstream port */
11707 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11708 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11709 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
11710  * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
11711  * referenced RSS contexts must span no more than this number.
11712  */
11713 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
11714 #define       MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
11715 
11716 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
11717 #define    MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
11718 /* The handle of the new .1p mapping. This should be considered opaque to the
11719  * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11720  * handle.
11721  */
11722 #define       MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
11723 #define       MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
11724 /* enum: guaranteed invalid .1p mapping handle value */
11725 #define          MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
11726 
11727 
11728 /***********************************/
11729 /* MC_CMD_DOT1P_MAPPING_FREE
11730  * Free a .1p mapping.
11731  */
11732 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
11733 
11734 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11735 
11736 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
11737 #define    MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
11738 /* The handle of the .1p mapping */
11739 #define       MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
11740 #define       MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
11741 
11742 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
11743 #define    MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
11744 
11745 
11746 /***********************************/
11747 /* MC_CMD_DOT1P_MAPPING_SET_TABLE
11748  * Set the mapping table for a .1p mapping.
11749  */
11750 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
11751 
11752 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11753 
11754 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
11755 #define    MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
11756 /* The handle of the .1p mapping */
11757 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11758 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11759 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11760  * handle)
11761  */
11762 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
11763 #define       MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
11764 
11765 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
11766 #define    MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
11767 
11768 
11769 /***********************************/
11770 /* MC_CMD_DOT1P_MAPPING_GET_TABLE
11771  * Get the mapping table for a .1p mapping.
11772  */
11773 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
11774 
11775 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11776 
11777 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
11778 #define    MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
11779 /* The handle of the .1p mapping */
11780 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11781 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11782 
11783 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
11784 #define    MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
11785 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11786  * handle)
11787  */
11788 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
11789 #define       MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
11790 
11791 
11792 /***********************************/
11793 /* MC_CMD_GET_VECTOR_CFG
11794  * Get Interrupt Vector config for this PF.
11795  */
11796 #define MC_CMD_GET_VECTOR_CFG 0xbf
11797 
11798 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11799 
11800 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
11801 #define    MC_CMD_GET_VECTOR_CFG_IN_LEN 0
11802 
11803 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
11804 #define    MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
11805 /* Base absolute interrupt vector number. */
11806 #define       MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
11807 #define       MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
11808 /* Number of interrupt vectors allocate to this PF. */
11809 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
11810 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
11811 /* Number of interrupt vectors to allocate per VF. */
11812 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
11813 #define       MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
11814 
11815 
11816 /***********************************/
11817 /* MC_CMD_SET_VECTOR_CFG
11818  * Set Interrupt Vector config for this PF.
11819  */
11820 #define MC_CMD_SET_VECTOR_CFG 0xc0
11821 
11822 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11823 
11824 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
11825 #define    MC_CMD_SET_VECTOR_CFG_IN_LEN 12
11826 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
11827  * let the system find a suitable base.
11828  */
11829 #define       MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
11830 #define       MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
11831 /* Number of interrupt vectors allocate to this PF. */
11832 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
11833 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
11834 /* Number of interrupt vectors to allocate per VF. */
11835 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
11836 #define       MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
11837 
11838 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
11839 #define    MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
11840 
11841 
11842 /***********************************/
11843 /* MC_CMD_VPORT_ADD_MAC_ADDRESS
11844  * Add a MAC address to a v-port
11845  */
11846 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
11847 
11848 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11849 
11850 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
11851 #define    MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
11852 /* The handle of the v-port */
11853 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11854 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11855 /* MAC address to add */
11856 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
11857 #define       MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
11858 
11859 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
11860 #define    MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
11861 
11862 
11863 /***********************************/
11864 /* MC_CMD_VPORT_DEL_MAC_ADDRESS
11865  * Delete a MAC address from a v-port
11866  */
11867 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
11868 
11869 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11870 
11871 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
11872 #define    MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
11873 /* The handle of the v-port */
11874 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11875 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11876 /* MAC address to add */
11877 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
11878 #define       MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
11879 
11880 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
11881 #define    MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
11882 
11883 
11884 /***********************************/
11885 /* MC_CMD_VPORT_GET_MAC_ADDRESSES
11886  * Delete a MAC address from a v-port
11887  */
11888 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
11889 
11890 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11891 
11892 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
11893 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
11894 /* The handle of the v-port */
11895 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
11896 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
11897 
11898 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
11899 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
11900 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
11901 #define    MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
11902 /* The number of MAC addresses returned */
11903 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
11904 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
11905 /* Array of MAC addresses */
11906 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
11907 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
11908 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
11909 #define       MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
11910 
11911 
11912 /***********************************/
11913 /* MC_CMD_VPORT_RECONFIGURE
11914  * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
11915  * has already been passed to another function (v-port's user), then that
11916  * function will be reset before applying the changes.
11917  */
11918 #define MC_CMD_VPORT_RECONFIGURE 0xeb
11919 
11920 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11921 
11922 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
11923 #define    MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
11924 /* The handle of the v-port */
11925 #define       MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
11926 #define       MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
11927 /* Flags requesting what should be changed. */
11928 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
11929 #define       MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
11930 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
11931 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
11932 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
11933 #define        MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
11934 /* The number of VLAN tags to insert/remove. An error will be returned if
11935  * incompatible with the number of VLAN tags specified for the upstream
11936  * v-switch.
11937  */
11938 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
11939 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
11940 /* The actual VLAN tags to insert/remove */
11941 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
11942 #define       MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
11943 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
11944 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
11945 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
11946 #define        MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
11947 /* The number of MAC addresses to add */
11948 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
11949 #define       MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
11950 /* MAC addresses to add */
11951 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
11952 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
11953 #define       MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
11954 
11955 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
11956 #define    MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
11957 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
11958 #define       MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
11959 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
11960 #define        MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
11961 
11962 
11963 /***********************************/
11964 /* MC_CMD_EVB_PORT_QUERY
11965  * read some config of v-port.
11966  */
11967 #define MC_CMD_EVB_PORT_QUERY 0x62
11968 
11969 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11970 
11971 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
11972 #define    MC_CMD_EVB_PORT_QUERY_IN_LEN 4
11973 /* The handle of the v-port */
11974 #define       MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
11975 #define       MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
11976 
11977 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
11978 #define    MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
11979 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11980 #define       MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
11981 #define       MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
11982 /* The number of VLAN tags that may be used on a v-adaptor connected to this
11983  * EVB port.
11984  */
11985 #define       MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
11986 #define       MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
11987 
11988 
11989 /***********************************/
11990 /* MC_CMD_DUMP_BUFTBL_ENTRIES
11991  * Dump buffer table entries, mainly for command client debug use. Dumps
11992  * absolute entries, and does not use chunk handles. All entries must be in
11993  * range, and used for q page mapping, Although the latter restriction may be
11994  * lifted in future.
11995  */
11996 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
11997 
11998 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11999 
12000 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
12001 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
12002 /* Index of the first buffer table entry. */
12003 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
12004 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
12005 /* Number of buffer table entries to dump. */
12006 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
12007 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
12008 
12009 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
12010 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
12011 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
12012 #define    MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
12013 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
12014 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
12015 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
12016 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
12017 #define       MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
12018 
12019 
12020 /***********************************/
12021 /* MC_CMD_SET_RXDP_CONFIG
12022  * Set global RXDP configuration settings
12023  */
12024 #define MC_CMD_SET_RXDP_CONFIG 0xc1
12025 
12026 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12027 
12028 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
12029 #define    MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
12030 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
12031 #define       MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
12032 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
12033 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
12034 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
12035 #define        MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
12036 /* enum: pad to 64 bytes */
12037 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
12038 /* enum: pad to 128 bytes (Medford only) */
12039 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
12040 /* enum: pad to 256 bytes (Medford only) */
12041 #define          MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
12042 
12043 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
12044 #define    MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
12045 
12046 
12047 /***********************************/
12048 /* MC_CMD_GET_RXDP_CONFIG
12049  * Get global RXDP configuration settings
12050  */
12051 #define MC_CMD_GET_RXDP_CONFIG 0xc2
12052 
12053 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12054 
12055 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
12056 #define    MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
12057 
12058 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
12059 #define    MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
12060 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
12061 #define       MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
12062 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
12063 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
12064 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
12065 #define        MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
12066 /*             Enum values, see field(s): */
12067 /*                MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */
12068 
12069 
12070 /***********************************/
12071 /* MC_CMD_GET_CLOCK
12072  * Return the system and PDCPU clock frequencies.
12073  */
12074 #define MC_CMD_GET_CLOCK 0xac
12075 
12076 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12077 
12078 /* MC_CMD_GET_CLOCK_IN msgrequest */
12079 #define    MC_CMD_GET_CLOCK_IN_LEN 0
12080 
12081 /* MC_CMD_GET_CLOCK_OUT msgresponse */
12082 #define    MC_CMD_GET_CLOCK_OUT_LEN 8
12083 /* System frequency, MHz */
12084 #define       MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
12085 #define       MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
12086 /* DPCPU frequency, MHz */
12087 #define       MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
12088 #define       MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
12089 
12090 
12091 /***********************************/
12092 /* MC_CMD_SET_CLOCK
12093  * Control the system and DPCPU clock frequencies. Changes are lost reboot.
12094  */
12095 #define MC_CMD_SET_CLOCK 0xad
12096 
12097 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12098 
12099 /* MC_CMD_SET_CLOCK_IN msgrequest */
12100 #define    MC_CMD_SET_CLOCK_IN_LEN 28
12101 /* Requested frequency in MHz for system clock domain */
12102 #define       MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
12103 #define       MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
12104 /* enum: Leave the system clock domain frequency unchanged */
12105 #define          MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
12106 /* Requested frequency in MHz for inter-core clock domain */
12107 #define       MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
12108 #define       MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
12109 /* enum: Leave the inter-core clock domain frequency unchanged */
12110 #define          MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
12111 /* Requested frequency in MHz for DPCPU clock domain */
12112 #define       MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
12113 #define       MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
12114 /* enum: Leave the DPCPU clock domain frequency unchanged */
12115 #define          MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
12116 /* Requested frequency in MHz for PCS clock domain */
12117 #define       MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
12118 #define       MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
12119 /* enum: Leave the PCS clock domain frequency unchanged */
12120 #define          MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
12121 /* Requested frequency in MHz for MC clock domain */
12122 #define       MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
12123 #define       MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
12124 /* enum: Leave the MC clock domain frequency unchanged */
12125 #define          MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
12126 /* Requested frequency in MHz for rmon clock domain */
12127 #define       MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
12128 #define       MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
12129 /* enum: Leave the rmon clock domain frequency unchanged */
12130 #define          MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
12131 /* Requested frequency in MHz for vswitch clock domain */
12132 #define       MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
12133 #define       MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
12134 /* enum: Leave the vswitch clock domain frequency unchanged */
12135 #define          MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
12136 
12137 /* MC_CMD_SET_CLOCK_OUT msgresponse */
12138 #define    MC_CMD_SET_CLOCK_OUT_LEN 28
12139 /* Resulting system frequency in MHz */
12140 #define       MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
12141 #define       MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
12142 /* enum: The system clock domain doesn't exist */
12143 #define          MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
12144 /* Resulting inter-core frequency in MHz */
12145 #define       MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
12146 #define       MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
12147 /* enum: The inter-core clock domain doesn't exist / isn't used */
12148 #define          MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
12149 /* Resulting DPCPU frequency in MHz */
12150 #define       MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
12151 #define       MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
12152 /* enum: The dpcpu clock domain doesn't exist */
12153 #define          MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
12154 /* Resulting PCS frequency in MHz */
12155 #define       MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
12156 #define       MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
12157 /* enum: The PCS clock domain doesn't exist / isn't controlled */
12158 #define          MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
12159 /* Resulting MC frequency in MHz */
12160 #define       MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
12161 #define       MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
12162 /* enum: The MC clock domain doesn't exist / isn't controlled */
12163 #define          MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
12164 /* Resulting rmon frequency in MHz */
12165 #define       MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
12166 #define       MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
12167 /* enum: The rmon clock domain doesn't exist / isn't controlled */
12168 #define          MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
12169 /* Resulting vswitch frequency in MHz */
12170 #define       MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
12171 #define       MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
12172 /* enum: The vswitch clock domain doesn't exist / isn't controlled */
12173 #define          MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
12174 
12175 
12176 /***********************************/
12177 /* MC_CMD_DPCPU_RPC
12178  * Send an arbitrary DPCPU message.
12179  */
12180 #define MC_CMD_DPCPU_RPC 0xae
12181 
12182 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12183 
12184 /* MC_CMD_DPCPU_RPC_IN msgrequest */
12185 #define    MC_CMD_DPCPU_RPC_IN_LEN 36
12186 #define       MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
12187 #define       MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
12188 /* enum: RxDPCPU0 */
12189 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
12190 /* enum: TxDPCPU0 */
12191 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
12192 /* enum: TxDPCPU1 */
12193 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
12194 /* enum: RxDPCPU1 (Medford only) */
12195 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
12196 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of
12197  * DPCPU_RX0)
12198  */
12199 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
12200 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of
12201  * DPCPU_TX0)
12202  */
12203 #define          MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
12204 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
12205  * initialised to zero
12206  */
12207 #define       MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
12208 #define       MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
12209 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
12210 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
12211 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
12212 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
12213 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
12214 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
12215 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
12216 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
12217 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
12218 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
12219 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
12220 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
12221 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
12222 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
12223 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
12224 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
12225 #define        MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
12226 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
12227 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
12228 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
12229 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
12230 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
12231 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
12232 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
12233 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
12234 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
12235 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
12236 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
12237 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
12238 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
12239 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
12240 #define        MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
12241 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
12242 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
12243 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
12244 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
12245 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
12246 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
12247 #define        MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
12248 #define       MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
12249 #define       MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
12250 /* Register data to write. Only valid in write/write-read. */
12251 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
12252 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
12253 /* Register address. */
12254 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
12255 #define       MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
12256 
12257 /* MC_CMD_DPCPU_RPC_OUT msgresponse */
12258 #define    MC_CMD_DPCPU_RPC_OUT_LEN 36
12259 #define       MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
12260 #define       MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
12261 /* DATA */
12262 #define       MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
12263 #define       MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
12264 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
12265 #define        MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
12266 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
12267 #define        MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
12268 #define       MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
12269 #define       MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
12270 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
12271 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
12272 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
12273 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
12274 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
12275 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
12276 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
12277 #define       MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
12278 
12279 
12280 /***********************************/
12281 /* MC_CMD_TRIGGER_INTERRUPT
12282  * Trigger an interrupt by prodding the BIU.
12283  */
12284 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
12285 
12286 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12287 
12288 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
12289 #define    MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
12290 /* Interrupt level relative to base for function. */
12291 #define       MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
12292 #define       MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
12293 
12294 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
12295 #define    MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
12296 
12297 
12298 /***********************************/
12299 /* MC_CMD_SHMBOOT_OP
12300  * Special operations to support (for now) shmboot.
12301  */
12302 #define MC_CMD_SHMBOOT_OP 0xe6
12303 
12304 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12305 
12306 /* MC_CMD_SHMBOOT_OP_IN msgrequest */
12307 #define    MC_CMD_SHMBOOT_OP_IN_LEN 4
12308 /* Identifies the operation to perform */
12309 #define       MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
12310 #define       MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
12311 /* enum: Copy slave_data section to the slave core. (Greenport only) */
12312 #define          MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
12313 
12314 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */
12315 #define    MC_CMD_SHMBOOT_OP_OUT_LEN 0
12316 
12317 
12318 /***********************************/
12319 /* MC_CMD_CAP_BLK_READ
12320  * Read multiple 64bit words from capture block memory
12321  */
12322 #define MC_CMD_CAP_BLK_READ 0xe7
12323 
12324 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12325 
12326 /* MC_CMD_CAP_BLK_READ_IN msgrequest */
12327 #define    MC_CMD_CAP_BLK_READ_IN_LEN 12
12328 #define       MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
12329 #define       MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
12330 #define       MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
12331 #define       MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
12332 #define       MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
12333 #define       MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
12334 
12335 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */
12336 #define    MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
12337 #define    MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
12338 #define    MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
12339 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
12340 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
12341 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
12342 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
12343 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
12344 #define       MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
12345 
12346 
12347 /***********************************/
12348 /* MC_CMD_DUMP_DO
12349  * Take a dump of the DUT state
12350  */
12351 #define MC_CMD_DUMP_DO 0xe8
12352 
12353 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12354 
12355 /* MC_CMD_DUMP_DO_IN msgrequest */
12356 #define    MC_CMD_DUMP_DO_IN_LEN 52
12357 #define       MC_CMD_DUMP_DO_IN_PADDING_OFST 0
12358 #define       MC_CMD_DUMP_DO_IN_PADDING_LEN 4
12359 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
12360 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
12361 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
12362 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
12363 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12364 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
12365 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
12366 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
12367 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
12368 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
12369 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12370 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12371 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12372 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
12373 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12374 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12375 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12376 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12377 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12378 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12379 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
12380 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12381 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12382 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12383 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12384 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
12385 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12386 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
12387 /* enum: The uart port this command was received over (if using a uart
12388  * transport)
12389  */
12390 #define          MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
12391 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12392 #define       MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
12393 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
12394 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
12395 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
12396 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
12397 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12398 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
12399 /*            Enum values, see field(s): */
12400 /*               MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12401 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12402 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12403 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12404 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
12405 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12406 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12407 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12408 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12409 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12410 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12411 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12412 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12413 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12414 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12415 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12416 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
12417 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12418 #define       MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
12419 
12420 /* MC_CMD_DUMP_DO_OUT msgresponse */
12421 #define    MC_CMD_DUMP_DO_OUT_LEN 4
12422 #define       MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
12423 #define       MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
12424 
12425 
12426 /***********************************/
12427 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
12428  * Configure unsolicited dumps
12429  */
12430 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
12431 
12432 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12433 
12434 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
12435 #define    MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
12436 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
12437 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
12438 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
12439 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
12440 /*            Enum values, see field(s): */
12441 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
12442 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
12443 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
12444 /*            Enum values, see field(s): */
12445 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12446 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
12447 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12448 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
12449 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
12450 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
12451 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12452 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
12453 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12454 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
12455 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12456 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
12457 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12458 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
12459 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12460 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
12461 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
12462 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
12463 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
12464 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
12465 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
12466 /*            Enum values, see field(s): */
12467 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
12468 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
12469 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
12470 /*            Enum values, see field(s): */
12471 /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
12472 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
12473 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
12474 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
12475 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
12476 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
12477 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
12478 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
12479 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
12480 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
12481 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
12482 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
12483 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
12484 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
12485 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
12486 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
12487 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
12488 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
12489 #define       MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
12490 
12491 
12492 /***********************************/
12493 /* MC_CMD_SET_PSU
12494  * Adjusts power supply parameters. This is a warranty-voiding operation.
12495  * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
12496  * the parameter is out of range.
12497  */
12498 #define MC_CMD_SET_PSU 0xea
12499 
12500 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12501 
12502 /* MC_CMD_SET_PSU_IN msgrequest */
12503 #define    MC_CMD_SET_PSU_IN_LEN 12
12504 #define       MC_CMD_SET_PSU_IN_PARAM_OFST 0
12505 #define       MC_CMD_SET_PSU_IN_PARAM_LEN 4
12506 #define          MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
12507 #define       MC_CMD_SET_PSU_IN_RAIL_OFST 4
12508 #define       MC_CMD_SET_PSU_IN_RAIL_LEN 4
12509 #define          MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
12510 #define          MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
12511 /* desired value, eg voltage in mV */
12512 #define       MC_CMD_SET_PSU_IN_VALUE_OFST 8
12513 #define       MC_CMD_SET_PSU_IN_VALUE_LEN 4
12514 
12515 /* MC_CMD_SET_PSU_OUT msgresponse */
12516 #define    MC_CMD_SET_PSU_OUT_LEN 0
12517 
12518 
12519 /***********************************/
12520 /* MC_CMD_GET_FUNCTION_INFO
12521  * Get function information. PF and VF number.
12522  */
12523 #define MC_CMD_GET_FUNCTION_INFO 0xec
12524 
12525 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12526 
12527 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
12528 #define    MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
12529 
12530 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
12531 #define    MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
12532 #define       MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
12533 #define       MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
12534 #define       MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
12535 #define       MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
12536 
12537 
12538 /***********************************/
12539 /* MC_CMD_ENABLE_OFFLINE_BIST
12540  * Enters offline BIST mode. All queues are torn down, chip enters quiescent
12541  * mode, calling function gets exclusive MCDI ownership. The only way out is
12542  * reboot.
12543  */
12544 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
12545 
12546 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12547 
12548 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
12549 #define    MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
12550 
12551 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
12552 #define    MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
12553 
12554 
12555 /***********************************/
12556 /* MC_CMD_UART_SEND_DATA
12557  * Send checksummed[sic] block of data over the uart. Response is a placeholder
12558  * should we wish to make this reliable; currently requests are fire-and-
12559  * forget.
12560  */
12561 #define MC_CMD_UART_SEND_DATA 0xee
12562 
12563 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12564 
12565 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */
12566 #define    MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
12567 #define    MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
12568 #define    MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
12569 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
12570 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
12571 #define       MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
12572 /* Offset at which to write the data */
12573 #define       MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
12574 #define       MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
12575 /* Length of data */
12576 #define       MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
12577 #define       MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
12578 /* Reserved for future use */
12579 #define       MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
12580 #define       MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
12581 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
12582 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
12583 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
12584 #define       MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
12585 
12586 /* MC_CMD_UART_SEND_DATA_IN msgresponse */
12587 #define    MC_CMD_UART_SEND_DATA_IN_LEN 0
12588 
12589 
12590 /***********************************/
12591 /* MC_CMD_UART_RECV_DATA
12592  * Request checksummed[sic] block of data over the uart. Only a placeholder,
12593  * subject to change and not currently implemented.
12594  */
12595 #define MC_CMD_UART_RECV_DATA 0xef
12596 
12597 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12598 
12599 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */
12600 #define    MC_CMD_UART_RECV_DATA_OUT_LEN 16
12601 /* CRC32 over OFFSET, LENGTH, RESERVED */
12602 #define       MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
12603 #define       MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
12604 /* Offset from which to read the data */
12605 #define       MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
12606 #define       MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
12607 /* Length of data */
12608 #define       MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
12609 #define       MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
12610 /* Reserved for future use */
12611 #define       MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
12612 #define       MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
12613 
12614 /* MC_CMD_UART_RECV_DATA_IN msgresponse */
12615 #define    MC_CMD_UART_RECV_DATA_IN_LENMIN 16
12616 #define    MC_CMD_UART_RECV_DATA_IN_LENMAX 252
12617 #define    MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
12618 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
12619 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
12620 #define       MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
12621 /* Offset at which to write the data */
12622 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
12623 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
12624 /* Length of data */
12625 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
12626 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
12627 /* Reserved for future use */
12628 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
12629 #define       MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
12630 #define       MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
12631 #define       MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
12632 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
12633 #define       MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
12634 
12635 
12636 /***********************************/
12637 /* MC_CMD_READ_FUSES
12638  * Read data programmed into the device One-Time-Programmable (OTP) Fuses
12639  */
12640 #define MC_CMD_READ_FUSES 0xf0
12641 
12642 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12643 
12644 /* MC_CMD_READ_FUSES_IN msgrequest */
12645 #define    MC_CMD_READ_FUSES_IN_LEN 8
12646 /* Offset in OTP to read */
12647 #define       MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
12648 #define       MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
12649 /* Length of data to read in bytes */
12650 #define       MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
12651 #define       MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
12652 
12653 /* MC_CMD_READ_FUSES_OUT msgresponse */
12654 #define    MC_CMD_READ_FUSES_OUT_LENMIN 4
12655 #define    MC_CMD_READ_FUSES_OUT_LENMAX 252
12656 #define    MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
12657 /* Length of returned OTP data in bytes */
12658 #define       MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
12659 #define       MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
12660 /* Returned data */
12661 #define       MC_CMD_READ_FUSES_OUT_DATA_OFST 4
12662 #define       MC_CMD_READ_FUSES_OUT_DATA_LEN 1
12663 #define       MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
12664 #define       MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
12665 
12666 
12667 /***********************************/
12668 /* MC_CMD_KR_TUNE
12669  * Get or set KR Serdes RXEQ and TX Driver settings
12670  */
12671 #define MC_CMD_KR_TUNE 0xf1
12672 
12673 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12674 
12675 /* MC_CMD_KR_TUNE_IN msgrequest */
12676 #define    MC_CMD_KR_TUNE_IN_LENMIN 4
12677 #define    MC_CMD_KR_TUNE_IN_LENMAX 252
12678 #define    MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
12679 /* Requested operation */
12680 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
12681 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
12682 /* enum: Get current RXEQ settings */
12683 #define          MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
12684 /* enum: Override RXEQ settings */
12685 #define          MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
12686 /* enum: Get current TX Driver settings */
12687 #define          MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
12688 /* enum: Override TX Driver settings */
12689 #define          MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
12690 /* enum: Force KR Serdes reset / recalibration */
12691 #define          MC_CMD_KR_TUNE_IN_RECAL 0x4
12692 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
12693  * signal.
12694  */
12695 #define          MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
12696 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
12697  * caller should call this command repeatedly after starting eye plot, until no
12698  * more data is returned.
12699  */
12700 #define          MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
12701 /* enum: Read Figure Of Merit (eye quality, higher is better). */
12702 #define          MC_CMD_KR_TUNE_IN_READ_FOM 0x7
12703 /* enum: Start/stop link training frames */
12704 #define          MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
12705 /* enum: Issue KR link training command (control training coefficients) */
12706 #define          MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
12707 /* Align the arguments to 32 bits */
12708 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
12709 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
12710 /* Arguments specific to the operation */
12711 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
12712 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
12713 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
12714 #define       MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
12715 
12716 /* MC_CMD_KR_TUNE_OUT msgresponse */
12717 #define    MC_CMD_KR_TUNE_OUT_LEN 0
12718 
12719 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
12720 #define    MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
12721 /* Requested operation */
12722 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
12723 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
12724 /* Align the arguments to 32 bits */
12725 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12726 #define       MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12727 
12728 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
12729 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
12730 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
12731 #define    MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12732 /* RXEQ Parameter */
12733 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12734 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12735 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12736 #define       MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12737 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12738 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12739 /* enum: Attenuation (0-15, Huntington) */
12740 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
12741 /* enum: CTLE Boost (0-15, Huntington) */
12742 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
12743 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
12744  * positive, Medford - 0-31)
12745  */
12746 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
12747 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
12748  * positive, Medford - 0-31)
12749  */
12750 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
12751 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
12752  * positive, Medford - 0-16)
12753  */
12754 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
12755 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
12756  * positive, Medford - 0-16)
12757  */
12758 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
12759 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
12760  * positive, Medford - 0-16)
12761  */
12762 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
12763 /* enum: Edge DFE DLEV (0-128 for Medford) */
12764 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
12765 /* enum: Variable Gain Amplifier (0-15, Medford) */
12766 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
12767 /* enum: CTLE EQ Capacitor (0-15, Medford) */
12768 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12769 /* enum: CTLE EQ Resistor (0-7, Medford) */
12770 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12771 /* enum: CTLE gain (0-31, Medford2) */
12772 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
12773 /* enum: CTLE pole (0-31, Medford2) */
12774 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
12775 /* enum: CTLE peaking (0-31, Medford2) */
12776 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
12777 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
12778 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
12779 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
12780 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
12781 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
12782 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
12783 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
12784 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
12785 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
12786 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
12787 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
12788 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
12789 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
12790 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
12791 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
12792 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
12793 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
12794 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
12795 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
12796 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
12797 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
12798 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
12799 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
12800 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
12801 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
12802 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
12803 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
12804 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
12805 /* enum: Negative h1 polarity data sampler offset calibration code, even path
12806  * (Medford2 - 6 bit signed (-29 - +29)))
12807  */
12808 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
12809 /* enum: Negative h1 polarity data sampler offset calibration code, odd path
12810  * (Medford2 - 6 bit signed (-29 - +29)))
12811  */
12812 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
12813 /* enum: Positive h1 polarity data sampler offset calibration code, even path
12814  * (Medford2 - 6 bit signed (-29 - +29)))
12815  */
12816 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
12817 /* enum: Positive h1 polarity data sampler offset calibration code, odd path
12818  * (Medford2 - 6 bit signed (-29 - +29)))
12819  */
12820 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
12821 /* enum: CDR calibration loop code (Medford2) */
12822 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
12823 /* enum: CDR integral loop code (Medford2) */
12824 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
12825 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12826 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12827 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12828 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12829 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12830 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12831 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12832 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
12833 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12834 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
12835 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
12836 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12837 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12838 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12839 #define        MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12840 
12841 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
12842 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
12843 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
12844 #define    MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12845 /* Requested operation */
12846 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
12847 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
12848 /* Align the arguments to 32 bits */
12849 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12850 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12851 /* RXEQ Parameter */
12852 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12853 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12854 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12855 #define       MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12856 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12857 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12858 /*             Enum values, see field(s): */
12859 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
12860 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12861 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
12862 /*             Enum values, see field(s): */
12863 /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12864 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
12865 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12866 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
12867 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
12868 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12869 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12870 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12871 #define        MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12872 
12873 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
12874 #define    MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
12875 
12876 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
12877 #define    MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
12878 /* Requested operation */
12879 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
12880 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
12881 /* Align the arguments to 32 bits */
12882 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12883 #define       MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12884 
12885 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
12886 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
12887 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
12888 #define    MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12889 /* TXEQ Parameter */
12890 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12891 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12892 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12893 #define       MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12894 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12895 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12896 /* enum: TX Amplitude (Huntington, Medford, Medford2) */
12897 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
12898 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
12899 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
12900 /* enum: De-Emphasis Tap1 Fine */
12901 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
12902 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
12903 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
12904 /* enum: De-Emphasis Tap2 Fine (Huntington) */
12905 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
12906 /* enum: Pre-Emphasis Magnitude (Huntington) */
12907 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
12908 /* enum: Pre-Emphasis Fine (Huntington) */
12909 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
12910 /* enum: TX Slew Rate Coarse control (Huntington) */
12911 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
12912 /* enum: TX Slew Rate Fine control (Huntington) */
12913 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
12914 /* enum: TX Termination Impedance control (Huntington) */
12915 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
12916 /* enum: TX Amplitude Fine control (Medford) */
12917 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
12918 /* enum: Pre-shoot Tap (Medford, Medford2) */
12919 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
12920 /* enum: De-emphasis Tap (Medford, Medford2) */
12921 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
12922 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12923 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12924 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
12925 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
12926 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
12927 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
12928 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12929 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
12930 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
12931 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12932 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12933 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
12934 #define        MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
12935 
12936 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
12937 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
12938 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
12939 #define    MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
12940 /* Requested operation */
12941 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
12942 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
12943 /* Align the arguments to 32 bits */
12944 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12945 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12946 /* TXEQ Parameter */
12947 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
12948 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
12949 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
12950 #define       MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
12951 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
12952 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
12953 /*             Enum values, see field(s): */
12954 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
12955 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
12956 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
12957 /*             Enum values, see field(s): */
12958 /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
12959 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
12960 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
12961 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
12962 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12963 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
12964 #define        MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
12965 
12966 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
12967 #define    MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
12968 
12969 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
12970 #define    MC_CMD_KR_TUNE_RECAL_IN_LEN 4
12971 /* Requested operation */
12972 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
12973 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
12974 /* Align the arguments to 32 bits */
12975 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
12976 #define       MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
12977 
12978 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
12979 #define    MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
12980 
12981 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
12982 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
12983 /* Requested operation */
12984 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12985 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12986 /* Align the arguments to 32 bits */
12987 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12988 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12989 /* Port-relative lane to scan eye on */
12990 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12991 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
12992 
12993 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */
12994 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12
12995 /* Requested operation */
12996 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
12997 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
12998 /* Align the arguments to 32 bits */
12999 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
13000 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
13001 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
13002 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
13003 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
13004 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
13005 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
13006 #define        MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
13007 /* Scan duration / cycle count */
13008 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
13009 #define       MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
13010 
13011 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
13012 #define    MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
13013 
13014 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
13015 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
13016 /* Requested operation */
13017 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
13018 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
13019 /* Align the arguments to 32 bits */
13020 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
13021 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
13022 
13023 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
13024 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13025 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
13026 #define    MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13027 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13028 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
13029 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13030 #define       MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
13031 
13032 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
13033 #define    MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
13034 /* Requested operation */
13035 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
13036 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
13037 /* Align the arguments to 32 bits */
13038 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
13039 #define       MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
13040 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
13041 #define       MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
13042 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
13043 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
13044 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
13045 #define        MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
13046 
13047 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
13048 #define    MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
13049 #define       MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
13050 #define       MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
13051 
13052 /* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */
13053 #define    MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8
13054 /* Requested operation */
13055 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
13056 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
13057 /* Align the arguments to 32 bits */
13058 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
13059 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
13060 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
13061 #define       MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
13062 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
13063 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
13064 
13065 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
13066 #define    MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
13067 /* Requested operation */
13068 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
13069 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
13070 /* Align the arguments to 32 bits */
13071 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
13072 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3
13073 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
13074 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
13075 /* Set INITIALIZE state */
13076 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8
13077 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
13078 /* Set PRESET state */
13079 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12
13080 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
13081 /* C(-1) request */
13082 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
13083 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
13084 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
13085 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
13086 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
13087 /* C(0) request */
13088 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
13089 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
13090 /*            Enum values, see field(s): */
13091 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13092 /* C(+1) request */
13093 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24
13094 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
13095 /*            Enum values, see field(s): */
13096 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13097 
13098 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */
13099 #define    MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24
13100 /* C(-1) status */
13101 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
13102 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
13103 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
13104 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
13105 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
13106 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
13107 /* C(0) status */
13108 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
13109 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
13110 /*            Enum values, see field(s): */
13111 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13112 /* C(+1) status */
13113 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8
13114 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
13115 /*            Enum values, see field(s): */
13116 /*               MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
13117 /* C(-1) value */
13118 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12
13119 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
13120 /* C(0) value */
13121 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16
13122 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
13123 /* C(+1) status */
13124 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20
13125 #define       MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
13126 
13127 
13128 /***********************************/
13129 /* MC_CMD_PCIE_TUNE
13130  * Get or set PCIE Serdes RXEQ and TX Driver settings
13131  */
13132 #define MC_CMD_PCIE_TUNE 0xf2
13133 
13134 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13135 
13136 /* MC_CMD_PCIE_TUNE_IN msgrequest */
13137 #define    MC_CMD_PCIE_TUNE_IN_LENMIN 4
13138 #define    MC_CMD_PCIE_TUNE_IN_LENMAX 252
13139 #define    MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
13140 /* Requested operation */
13141 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
13142 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
13143 /* enum: Get current RXEQ settings */
13144 #define          MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
13145 /* enum: Override RXEQ settings */
13146 #define          MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
13147 /* enum: Get current TX Driver settings */
13148 #define          MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
13149 /* enum: Override TX Driver settings */
13150 #define          MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
13151 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
13152 #define          MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
13153 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
13154  * caller should call this command repeatedly after starting eye plot, until no
13155  * more data is returned.
13156  */
13157 #define          MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
13158 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
13159 #define          MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
13160 /* Align the arguments to 32 bits */
13161 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
13162 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
13163 /* Arguments specific to the operation */
13164 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
13165 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
13166 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
13167 #define       MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
13168 
13169 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
13170 #define    MC_CMD_PCIE_TUNE_OUT_LEN 0
13171 
13172 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
13173 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
13174 /* Requested operation */
13175 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13176 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
13177 /* Align the arguments to 32 bits */
13178 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
13179 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
13180 
13181 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
13182 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
13183 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
13184 #define    MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
13185 /* RXEQ Parameter */
13186 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
13187 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
13188 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
13189 #define       MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
13190 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
13191 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
13192 /* enum: Attenuation (0-15) */
13193 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
13194 /* enum: CTLE Boost (0-15) */
13195 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
13196 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
13197 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
13198 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
13199 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
13200 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
13201 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
13202 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
13203 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
13204 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
13205 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
13206 /* enum: DFE DLev */
13207 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
13208 /* enum: Figure of Merit */
13209 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
13210 /* enum: CTLE EQ Capacitor (HF Gain) */
13211 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
13212 /* enum: CTLE EQ Resistor (DC Gain) */
13213 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
13214 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
13215 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
13216 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
13217 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
13218 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
13219 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
13220 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
13221 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
13222 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
13223 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
13224 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
13225 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
13226 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
13227 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
13228 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
13229 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
13230 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
13231 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
13232 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
13233 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
13234 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
13235 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
13236 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
13237 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
13238 #define        MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
13239 
13240 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
13241 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
13242 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
13243 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
13244 /* Requested operation */
13245 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
13246 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
13247 /* Align the arguments to 32 bits */
13248 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
13249 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3
13250 /* RXEQ Parameter */
13251 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
13252 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
13253 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
13254 #define       MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
13255 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
13256 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
13257 /*             Enum values, see field(s): */
13258 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
13259 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
13260 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
13261 /*             Enum values, see field(s): */
13262 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
13263 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
13264 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
13265 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
13266 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
13267 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
13268 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
13269 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
13270 #define        MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
13271 
13272 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */
13273 #define    MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
13274 
13275 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
13276 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
13277 /* Requested operation */
13278 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13279 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
13280 /* Align the arguments to 32 bits */
13281 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
13282 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
13283 
13284 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
13285 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
13286 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
13287 #define    MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
13288 /* RXEQ Parameter */
13289 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
13290 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
13291 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
13292 #define       MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
13293 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
13294 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
13295 /* enum: TxMargin (PIPE) */
13296 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
13297 /* enum: TxSwing (PIPE) */
13298 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
13299 /* enum: De-emphasis coefficient C(-1) (PIPE) */
13300 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
13301 /* enum: De-emphasis coefficient C(0) (PIPE) */
13302 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
13303 /* enum: De-emphasis coefficient C(+1) (PIPE) */
13304 #define          MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
13305 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
13306 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
13307 /*             Enum values, see field(s): */
13308 /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
13309 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
13310 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
13311 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
13312 #define        MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
13313 
13314 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
13315 #define    MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
13316 /* Requested operation */
13317 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13318 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
13319 /* Align the arguments to 32 bits */
13320 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
13321 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
13322 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
13323 #define       MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
13324 
13325 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
13326 #define    MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
13327 
13328 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
13329 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
13330 /* Requested operation */
13331 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13332 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
13333 /* Align the arguments to 32 bits */
13334 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
13335 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
13336 
13337 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
13338 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13339 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
13340 #define    MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13341 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13342 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
13343 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13344 #define       MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
13345 
13346 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */
13347 #define    MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
13348 
13349 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */
13350 #define    MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
13351 
13352 
13353 /***********************************/
13354 /* MC_CMD_LICENSING
13355  * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
13356  * - not used for V3 licensing
13357  */
13358 #define MC_CMD_LICENSING 0xf3
13359 
13360 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13361 
13362 /* MC_CMD_LICENSING_IN msgrequest */
13363 #define    MC_CMD_LICENSING_IN_LEN 4
13364 /* identifies the type of operation requested */
13365 #define       MC_CMD_LICENSING_IN_OP_OFST 0
13366 #define       MC_CMD_LICENSING_IN_OP_LEN 4
13367 /* enum: re-read and apply licenses after a license key partition update; note
13368  * that this operation returns a zero-length response
13369  */
13370 #define          MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
13371 /* enum: report counts of installed licenses */
13372 #define          MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
13373 
13374 /* MC_CMD_LICENSING_OUT msgresponse */
13375 #define    MC_CMD_LICENSING_OUT_LEN 28
13376 /* count of application keys which are valid */
13377 #define       MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
13378 #define       MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
13379 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
13380  * MC_CMD_FC_OP_LICENSE)
13381  */
13382 #define       MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
13383 #define       MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
13384 /* count of application keys which are invalid due to being blacklisted */
13385 #define       MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
13386 #define       MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
13387 /* count of application keys which are invalid due to being unverifiable */
13388 #define       MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
13389 #define       MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
13390 /* count of application keys which are invalid due to being for the wrong node
13391  */
13392 #define       MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
13393 #define       MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
13394 /* licensing state (for diagnostics; the exact meaning of the bits in this
13395  * field are private to the firmware)
13396  */
13397 #define       MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
13398 #define       MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
13399 /* licensing subsystem self-test report (for manftest) */
13400 #define       MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
13401 #define       MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
13402 /* enum: licensing subsystem self-test failed */
13403 #define          MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
13404 /* enum: licensing subsystem self-test passed */
13405 #define          MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
13406 
13407 
13408 /***********************************/
13409 /* MC_CMD_LICENSING_V3
13410  * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
13411  * - V3 licensing (Medford)
13412  */
13413 #define MC_CMD_LICENSING_V3 0xd0
13414 
13415 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13416 
13417 /* MC_CMD_LICENSING_V3_IN msgrequest */
13418 #define    MC_CMD_LICENSING_V3_IN_LEN 4
13419 /* identifies the type of operation requested */
13420 #define       MC_CMD_LICENSING_V3_IN_OP_OFST 0
13421 #define       MC_CMD_LICENSING_V3_IN_OP_LEN 4
13422 /* enum: re-read and apply licenses after a license key partition update; note
13423  * that this operation returns a zero-length response
13424  */
13425 #define          MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
13426 /* enum: report counts of installed licenses Returns EAGAIN if license
13427  * processing (updating) has been started but not yet completed.
13428  */
13429 #define          MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
13430 
13431 /* MC_CMD_LICENSING_V3_OUT msgresponse */
13432 #define    MC_CMD_LICENSING_V3_OUT_LEN 88
13433 /* count of keys which are valid */
13434 #define       MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
13435 #define       MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
13436 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
13437  * MC_CMD_FC_OP_LICENSE)
13438  */
13439 #define       MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
13440 #define       MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
13441 /* count of keys which are invalid due to being unverifiable */
13442 #define       MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
13443 #define       MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
13444 /* count of keys which are invalid due to being for the wrong node */
13445 #define       MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
13446 #define       MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
13447 /* licensing state (for diagnostics; the exact meaning of the bits in this
13448  * field are private to the firmware)
13449  */
13450 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
13451 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
13452 /* licensing subsystem self-test report (for manftest) */
13453 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
13454 #define       MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
13455 /* enum: licensing subsystem self-test failed */
13456 #define          MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
13457 /* enum: licensing subsystem self-test passed */
13458 #define          MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
13459 /* bitmask of licensed applications */
13460 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
13461 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
13462 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
13463 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
13464 /* reserved for future use */
13465 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
13466 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
13467 /* bitmask of licensed features */
13468 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
13469 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
13470 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
13471 #define       MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
13472 /* reserved for future use */
13473 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
13474 #define       MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
13475 
13476 
13477 /***********************************/
13478 /* MC_CMD_LICENSING_GET_ID_V3
13479  * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
13480  * partition - V3 licensing (Medford)
13481  */
13482 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
13483 
13484 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13485 
13486 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
13487 #define    MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
13488 
13489 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
13490 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
13491 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
13492 #define    MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
13493 /* type of license (eg 3) */
13494 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
13495 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
13496 /* length of the license ID (in bytes) */
13497 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
13498 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
13499 /* the unique license ID of the adapter */
13500 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
13501 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
13502 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
13503 #define       MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
13504 
13505 
13506 /***********************************/
13507 /* MC_CMD_MC2MC_PROXY
13508  * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
13509  * This will fail on a single-core system.
13510  */
13511 #define MC_CMD_MC2MC_PROXY 0xf4
13512 
13513 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13514 
13515 /* MC_CMD_MC2MC_PROXY_IN msgrequest */
13516 #define    MC_CMD_MC2MC_PROXY_IN_LEN 0
13517 
13518 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */
13519 #define    MC_CMD_MC2MC_PROXY_OUT_LEN 0
13520 
13521 
13522 /***********************************/
13523 /* MC_CMD_GET_LICENSED_APP_STATE
13524  * Query the state of an individual licensed application. (Note that the actual
13525  * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
13526  * or a reboot of the MC.) Not used for V3 licensing
13527  */
13528 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
13529 
13530 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13531 
13532 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
13533 #define    MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
13534 /* application ID to query (LICENSED_APP_ID_xxx) */
13535 #define       MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
13536 #define       MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
13537 
13538 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
13539 #define    MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
13540 /* state of this application */
13541 #define       MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
13542 #define       MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
13543 /* enum: no (or invalid) license is present for the application */
13544 #define          MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
13545 /* enum: a valid license is present for the application */
13546 #define          MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
13547 
13548 
13549 /***********************************/
13550 /* MC_CMD_GET_LICENSED_V3_APP_STATE
13551  * Query the state of an individual licensed application. (Note that the actual
13552  * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13553  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13554  */
13555 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
13556 
13557 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13558 
13559 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
13560 #define    MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
13561 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
13562  * mask
13563  */
13564 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
13565 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
13566 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
13567 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
13568 
13569 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
13570 #define    MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
13571 /* state of this application */
13572 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
13573 #define       MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
13574 /* enum: no (or invalid) license is present for the application */
13575 #define          MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
13576 /* enum: a valid license is present for the application */
13577 #define          MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
13578 
13579 
13580 /***********************************/
13581 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
13582  * Query the state of one or more licensed features. (Note that the actual
13583  * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
13584  * operation or a reboot of the MC.) Used for V3 licensing (Medford)
13585  */
13586 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
13587 
13588 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13589 
13590 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
13591 #define    MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
13592 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
13593  * more bits set
13594  */
13595 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
13596 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
13597 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
13598 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
13599 
13600 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
13601 #define    MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
13602 /* states of these features - bit set for licensed, clear for not licensed */
13603 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
13604 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
13605 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
13606 #define       MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
13607 
13608 
13609 /***********************************/
13610 /* MC_CMD_LICENSED_APP_OP
13611  * Perform an action for an individual licensed application - not used for V3
13612  * licensing.
13613  */
13614 #define MC_CMD_LICENSED_APP_OP 0xf6
13615 
13616 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13617 
13618 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */
13619 #define    MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
13620 #define    MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
13621 #define    MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
13622 /* application ID */
13623 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
13624 #define       MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
13625 /* the type of operation requested */
13626 #define       MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
13627 #define       MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
13628 /* enum: validate application */
13629 #define          MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
13630 /* enum: mask application */
13631 #define          MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
13632 /* arguments specific to this particular operation */
13633 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
13634 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
13635 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
13636 #define       MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
13637 
13638 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
13639 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
13640 #define    MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
13641 #define    MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
13642 /* result specific to this particular operation */
13643 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
13644 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
13645 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
13646 #define       MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
13647 
13648 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
13649 #define    MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
13650 /* application ID */
13651 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
13652 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
13653 /* the type of operation requested */
13654 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
13655 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
13656 /* validation challenge */
13657 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
13658 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
13659 
13660 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
13661 #define    MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
13662 /* feature expiry (time_t) */
13663 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
13664 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
13665 /* validation response */
13666 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
13667 #define       MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
13668 
13669 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
13670 #define    MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
13671 /* application ID */
13672 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
13673 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
13674 /* the type of operation requested */
13675 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
13676 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
13677 /* flag */
13678 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
13679 #define       MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
13680 
13681 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
13682 #define    MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
13683 
13684 
13685 /***********************************/
13686 /* MC_CMD_LICENSED_V3_VALIDATE_APP
13687  * Perform validation for an individual licensed application - V3 licensing
13688  * (Medford)
13689  */
13690 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
13691 
13692 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13693 
13694 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
13695 #define    MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56
13696 /* challenge for validation (384 bits) */
13697 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
13698 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
13699 /* application ID expressed as a single bit mask */
13700 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
13701 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
13702 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
13703 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
13704 
13705 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
13706 #define    MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
13707 /* validation response to challenge in the form of ECDSA signature consisting
13708  * of two 384-bit integers, r and s, in big-endian order. The signature signs a
13709  * SHA-384 digest of a message constructed from the concatenation of the input
13710  * message and the remaining fields of this output message, e.g. challenge[48
13711  * bytes] ... expiry_time[4 bytes] ...
13712  */
13713 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
13714 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
13715 /* application expiry time */
13716 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
13717 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
13718 /* application expiry units */
13719 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
13720 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
13721 /* enum: expiry units are accounting units */
13722 #define          MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
13723 /* enum: expiry units are calendar days */
13724 #define          MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
13725 /* base MAC address of the NIC stored in NVRAM (note that this is a constant
13726  * value for a given NIC regardless which function is calling, effectively this
13727  * is PF0 base MAC address)
13728  */
13729 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104
13730 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6
13731 /* MAC address of v-adaptor associated with the client. If no such v-adapator
13732  * exists, then the field is filled with 0xFF.
13733  */
13734 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110
13735 #define       MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6
13736 
13737 
13738 /***********************************/
13739 /* MC_CMD_LICENSED_V3_MASK_FEATURES
13740  * Mask features - V3 licensing (Medford)
13741  */
13742 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
13743 
13744 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13745 
13746 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
13747 #define    MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
13748 /* mask to be applied to features to be changed */
13749 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
13750 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
13751 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
13752 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
13753 /* whether to turn on or turn off the masked features */
13754 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
13755 #define       MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
13756 /* enum: turn the features off */
13757 #define          MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
13758 /* enum: turn the features back on */
13759 #define          MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
13760 
13761 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
13762 #define    MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
13763 
13764 
13765 /***********************************/
13766 /* MC_CMD_LICENSING_V3_TEMPORARY
13767  * Perform operations to support installation of a single temporary license in
13768  * the adapter, in addition to those found in the licensing partition. See
13769  * SF-116124-SW for an overview of how this could be used. The license is
13770  * stored in MC persistent data and so will survive a MC reboot, but will be
13771  * erased when the adapter is power cycled
13772  */
13773 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
13774 
13775 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13776 
13777 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
13778 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
13779 /* operation code */
13780 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
13781 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
13782 /* enum: install a new license, overwriting any existing temporary license.
13783  * This is an asynchronous operation owing to the time taken to validate an
13784  * ECDSA license
13785  */
13786 #define          MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
13787 /* enum: clear the license immediately rather than waiting for the next power
13788  * cycle
13789  */
13790 #define          MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
13791 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
13792  * operation
13793  */
13794 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
13795 
13796 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
13797 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
13798 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
13799 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
13800 /* ECDSA license and signature */
13801 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
13802 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
13803 
13804 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
13805 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
13806 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
13807 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
13808 
13809 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
13810 #define    MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
13811 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
13812 #define       MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
13813 
13814 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
13815 #define    MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
13816 /* status code */
13817 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
13818 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
13819 /* enum: finished validating and installing license */
13820 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
13821 /* enum: license validation and installation in progress */
13822 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
13823 /* enum: licensing error. More specific error messages are not provided to
13824  * avoid exposing details of the licensing system to the client
13825  */
13826 #define          MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
13827 /* bitmask of licensed features */
13828 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
13829 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
13830 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
13831 #define       MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
13832 
13833 
13834 /***********************************/
13835 /* MC_CMD_SET_PORT_SNIFF_CONFIG
13836  * Configure RX port sniffing for the physical port associated with the calling
13837  * function. Only a privileged function may change the port sniffing
13838  * configuration. A copy of all traffic delivered to the host (non-promiscuous
13839  * mode) or all traffic arriving at the port (promiscuous mode) may be
13840  * delivered to a specific queue, or a set of queues with RSS.
13841  */
13842 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
13843 
13844 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13845 
13846 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
13847 #define    MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
13848 /* configuration flags */
13849 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13850 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
13851 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13852 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13853 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
13854 #define        MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
13855 /* receive queue handle (for RSS mode, this is the base queue) */
13856 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13857 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
13858 /* receive mode */
13859 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13860 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
13861 /* enum: receive to just the specified queue */
13862 #define          MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13863 /* enum: receive to multiple queues using RSS context */
13864 #define          MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13865 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13866  * that these handles should be considered opaque to the host, although a value
13867  * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13868  */
13869 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13870 #define       MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
13871 
13872 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
13873 #define    MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
13874 
13875 
13876 /***********************************/
13877 /* MC_CMD_GET_PORT_SNIFF_CONFIG
13878  * Obtain the current RX port sniffing configuration for the physical port
13879  * associated with the calling function. Only a privileged function may read
13880  * the configuration.
13881  */
13882 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
13883 
13884 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13885 
13886 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
13887 #define    MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
13888 
13889 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
13890 #define    MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
13891 /* configuration flags */
13892 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13893 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
13894 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13895 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13896 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
13897 #define        MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
13898 /* receiving queue handle (for RSS mode, this is the base queue) */
13899 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13900 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
13901 /* receive mode */
13902 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13903 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
13904 /* enum: receiving to just the specified queue */
13905 #define          MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13906 /* enum: receiving to multiple queues using RSS context */
13907 #define          MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13908 /* RSS context (for RX_MODE_RSS) */
13909 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13910 #define       MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
13911 
13912 
13913 /***********************************/
13914 /* MC_CMD_SET_PARSER_DISP_CONFIG
13915  * Change configuration related to the parser-dispatcher subsystem.
13916  */
13917 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
13918 
13919 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13920 
13921 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
13922 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
13923 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
13924 #define    MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
13925 /* the type of configuration setting to change */
13926 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13927 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13928 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
13929  * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
13930  */
13931 #define          MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
13932 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
13933  * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
13934  * boolean.)
13935  */
13936 #define          MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
13937 /* handle for the entity to update: queue handle, EVB port ID, etc. depending
13938  * on the type of configuration setting being changed
13939  */
13940 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13941 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13942 /* new value: the details depend on the type of configuration setting being
13943  * changed
13944  */
13945 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
13946 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
13947 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
13948 #define       MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
13949 
13950 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
13951 #define    MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
13952 
13953 
13954 /***********************************/
13955 /* MC_CMD_GET_PARSER_DISP_CONFIG
13956  * Read configuration related to the parser-dispatcher subsystem.
13957  */
13958 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
13959 
13960 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13961 
13962 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
13963 #define    MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
13964 /* the type of configuration setting to read */
13965 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13966 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13967 /*            Enum values, see field(s): */
13968 /*               MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
13969 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on
13970  * the type of configuration setting being read
13971  */
13972 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13973 #define       MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13974 
13975 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
13976 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
13977 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
13978 #define    MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
13979 /* current value: the details depend on the type of configuration setting being
13980  * read
13981  */
13982 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
13983 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
13984 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
13985 #define       MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
13986 
13987 
13988 /***********************************/
13989 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG
13990  * Configure TX port sniffing for the physical port associated with the calling
13991  * function. Only a privileged function may change the port sniffing
13992  * configuration. A copy of all traffic transmitted through the port may be
13993  * delivered to a specific queue, or a set of queues with RSS. Note that these
13994  * packets are delivered with transmit timestamps in the packet prefix, not
13995  * receive timestamps, so it is likely that the queue(s) will need to be
13996  * dedicated as TX sniff receivers.
13997  */
13998 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
13999 
14000 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14001 
14002 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
14003 #define    MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16
14004 /* configuration flags */
14005 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
14006 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
14007 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
14008 #define        MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
14009 /* receive queue handle (for RSS mode, this is the base queue) */
14010 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
14011 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
14012 /* receive mode */
14013 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
14014 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
14015 /* enum: receive to just the specified queue */
14016 #define          MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
14017 /* enum: receive to multiple queues using RSS context */
14018 #define          MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
14019 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
14020  * that these handles should be considered opaque to the host, although a value
14021  * of 0xFFFFFFFF is guaranteed never to be a valid handle.
14022  */
14023 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
14024 #define       MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
14025 
14026 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
14027 #define    MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
14028 
14029 
14030 /***********************************/
14031 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG
14032  * Obtain the current TX port sniffing configuration for the physical port
14033  * associated with the calling function. Only a privileged function may read
14034  * the configuration.
14035  */
14036 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
14037 
14038 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14039 
14040 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
14041 #define    MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
14042 
14043 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
14044 #define    MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16
14045 /* configuration flags */
14046 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
14047 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
14048 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
14049 #define        MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
14050 /* receiving queue handle (for RSS mode, this is the base queue) */
14051 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
14052 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
14053 /* receive mode */
14054 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
14055 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
14056 /* enum: receiving to just the specified queue */
14057 #define          MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
14058 /* enum: receiving to multiple queues using RSS context */
14059 #define          MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
14060 /* RSS context (for RX_MODE_RSS) */
14061 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
14062 #define       MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
14063 
14064 
14065 /***********************************/
14066 /* MC_CMD_RMON_STATS_RX_ERRORS
14067  * Per queue rx error stats.
14068  */
14069 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
14070 
14071 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14072 
14073 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */
14074 #define    MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8
14075 /* The rx queue to get stats for. */
14076 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
14077 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
14078 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
14079 #define       MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
14080 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
14081 #define        MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
14082 
14083 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */
14084 #define    MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16
14085 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
14086 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
14087 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
14088 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
14089 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8
14090 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
14091 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12
14092 #define       MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
14093 
14094 
14095 /***********************************/
14096 /* MC_CMD_GET_PCIE_RESOURCE_INFO
14097  * Find out about available PCIE resources
14098  */
14099 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
14100 
14101 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14102 
14103 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */
14104 #define    MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
14105 
14106 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */
14107 #define    MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28
14108 /* The maximum number of PFs the device can expose */
14109 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
14110 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
14111 /* The maximum number of VFs the device can expose in total */
14112 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
14113 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
14114 /* The maximum number of MSI-X vectors the device can provide in total */
14115 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8
14116 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
14117 /* the number of MSI-X vectors the device will allocate by default to each PF
14118  */
14119 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12
14120 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
14121 /* the number of MSI-X vectors the device will allocate by default to each VF
14122  */
14123 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16
14124 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
14125 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
14126 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20
14127 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
14128 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
14129 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24
14130 #define       MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
14131 
14132 
14133 /***********************************/
14134 /* MC_CMD_GET_PORT_MODES
14135  * Find out about available port modes
14136  */
14137 #define MC_CMD_GET_PORT_MODES 0xff
14138 
14139 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14140 
14141 /* MC_CMD_GET_PORT_MODES_IN msgrequest */
14142 #define    MC_CMD_GET_PORT_MODES_IN_LEN 0
14143 
14144 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */
14145 #define    MC_CMD_GET_PORT_MODES_OUT_LEN 12
14146 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */
14147 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
14148 #define       MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
14149 /* Default (canonical) board mode */
14150 #define       MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
14151 #define       MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
14152 /* Current board mode */
14153 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
14154 #define       MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
14155 
14156 
14157 /***********************************/
14158 /* MC_CMD_READ_ATB
14159  * Sample voltages on the ATB
14160  */
14161 #define MC_CMD_READ_ATB 0x100
14162 
14163 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14164 
14165 /* MC_CMD_READ_ATB_IN msgrequest */
14166 #define    MC_CMD_READ_ATB_IN_LEN 16
14167 #define       MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
14168 #define       MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
14169 #define          MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
14170 #define          MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
14171 #define          MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
14172 #define       MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
14173 #define       MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
14174 #define       MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
14175 #define       MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
14176 #define       MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12
14177 #define       MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
14178 
14179 /* MC_CMD_READ_ATB_OUT msgresponse */
14180 #define    MC_CMD_READ_ATB_OUT_LEN 4
14181 #define       MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
14182 #define       MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
14183 
14184 
14185 /***********************************/
14186 /* MC_CMD_GET_WORKAROUNDS
14187  * Read the list of all implemented and all currently enabled workarounds. The
14188  * enums here must correspond with those in MC_CMD_WORKAROUND.
14189  */
14190 #define MC_CMD_GET_WORKAROUNDS 0x59
14191 
14192 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14193 
14194 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
14195 #define    MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
14196 /* Each workaround is represented by a single bit according to the enums below.
14197  */
14198 #define       MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
14199 #define       MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
14200 #define       MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
14201 #define       MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
14202 /* enum: Bug 17230 work around. */
14203 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
14204 /* enum: Bug 35388 work around (unsafe EVQ writes). */
14205 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
14206 /* enum: Bug35017 workaround (A64 tables must be identity map) */
14207 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
14208 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
14209 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
14210 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
14211  * - before adding code that queries this workaround, remember that there's
14212  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
14213  * and will hence (incorrectly) report that the bug doesn't exist.
14214  */
14215 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
14216 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
14217 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
14218 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
14219 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
14220 
14221 
14222 /***********************************/
14223 /* MC_CMD_PRIVILEGE_MASK
14224  * Read/set privileges of an arbitrary PCIe function
14225  */
14226 #define MC_CMD_PRIVILEGE_MASK 0x5a
14227 
14228 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14229 
14230 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
14231 #define    MC_CMD_PRIVILEGE_MASK_IN_LEN 8
14232 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
14233  * 1,3 = 0x00030001
14234  */
14235 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
14236 #define       MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
14237 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
14238 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
14239 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
14240 #define        MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
14241 #define          MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
14242 /* New privilege mask to be set. The mask will only be changed if the MSB is
14243  * set to 1.
14244  */
14245 #define       MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
14246 #define       MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
14247 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
14248 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
14249 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
14250 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
14251 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
14252 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
14253 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
14254 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
14255 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
14256 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
14257 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
14258 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
14259 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
14260  * adress.
14261  */
14262 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
14263 /* enum: Privilege that allows a Function to change the MAC address configured
14264  * in its associated vAdapter/vPort.
14265  */
14266 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
14267 /* enum: Privilege that allows a Function to install filters that specify VLANs
14268  * that are not in the permit list for the associated vPort. This privilege is
14269  * primarily to support ESX where vPorts are created that restrict traffic to
14270  * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
14271  */
14272 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
14273 /* enum: Privilege for insecure commands. Commands that belong to this group
14274  * are not permitted on secure adapters regardless of the privilege mask.
14275  */
14276 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
14277 /* enum: Set this bit to indicate that a new privilege mask is to be set,
14278  * otherwise the command will only read the existing mask.
14279  */
14280 #define          MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
14281 
14282 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
14283 #define    MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
14284 /* For an admin function, always all the privileges are reported. */
14285 #define       MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
14286 #define       MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
14287 
14288 
14289 /***********************************/
14290 /* MC_CMD_LINK_STATE_MODE
14291  * Read/set link state mode of a VF
14292  */
14293 #define MC_CMD_LINK_STATE_MODE 0x5c
14294 
14295 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14296 
14297 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */
14298 #define    MC_CMD_LINK_STATE_MODE_IN_LEN 8
14299 /* The target function to have its link state mode read or set, must be a VF
14300  * e.g. VF 1,3 = 0x00030001
14301  */
14302 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
14303 #define       MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
14304 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
14305 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
14306 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
14307 #define        MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
14308 /* New link state mode to be set */
14309 #define       MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
14310 #define       MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
14311 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
14312 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
14313 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
14314 /* enum: Use this value to just read the existing setting without modifying it.
14315  */
14316 #define          MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
14317 
14318 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
14319 #define    MC_CMD_LINK_STATE_MODE_OUT_LEN 4
14320 #define       MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
14321 #define       MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
14322 
14323 
14324 /***********************************/
14325 /* MC_CMD_GET_SNAPSHOT_LENGTH
14326  * Obtain the current range of allowable values for the SNAPSHOT_LENGTH
14327  * parameter to MC_CMD_INIT_RXQ.
14328  */
14329 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
14330 
14331 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14332 
14333 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */
14334 #define    MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
14335 
14336 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */
14337 #define    MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8
14338 /* Minimum acceptable snapshot length. */
14339 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
14340 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
14341 /* Maximum acceptable snapshot length. */
14342 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
14343 #define       MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
14344 
14345 
14346 /***********************************/
14347 /* MC_CMD_FUSE_DIAGS
14348  * Additional fuse diagnostics
14349  */
14350 #define MC_CMD_FUSE_DIAGS 0x102
14351 
14352 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14353 
14354 /* MC_CMD_FUSE_DIAGS_IN msgrequest */
14355 #define    MC_CMD_FUSE_DIAGS_IN_LEN 0
14356 
14357 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */
14358 #define    MC_CMD_FUSE_DIAGS_OUT_LEN 48
14359 /* Total number of mismatched bits between pairs in area 0 */
14360 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
14361 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
14362 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
14363 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
14364 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
14365 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
14366 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
14367 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
14368 /* Checksum of data after logical OR of pairs in area 0 */
14369 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
14370 #define       MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
14371 /* Total number of mismatched bits between pairs in area 1 */
14372 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
14373 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
14374 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
14375 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
14376 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
14377 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
14378 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
14379 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
14380 /* Checksum of data after logical OR of pairs in area 1 */
14381 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
14382 #define       MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
14383 /* Total number of mismatched bits between pairs in area 2 */
14384 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
14385 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
14386 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
14387 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
14388 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
14389 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
14390 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
14391 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
14392 /* Checksum of data after logical OR of pairs in area 2 */
14393 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
14394 #define       MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
14395 
14396 
14397 /***********************************/
14398 /* MC_CMD_PRIVILEGE_MODIFY
14399  * Modify the privileges of a set of PCIe functions. Note that this operation
14400  * only effects non-admin functions unless the admin privilege itself is
14401  * included in one of the masks provided.
14402  */
14403 #define MC_CMD_PRIVILEGE_MODIFY 0x60
14404 
14405 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14406 
14407 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
14408 #define    MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
14409 /* The groups of functions to have their privilege masks modified. */
14410 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
14411 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
14412 #define          MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
14413 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
14414 #define          MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
14415 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
14416 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
14417 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
14418 /* For VFS_OF_PF specify the PF, for ONE specify the target function */
14419 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
14420 #define       MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
14421 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
14422 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
14423 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
14424 #define        MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
14425 /* Privileges to be added to the target functions. For privilege definitions
14426  * refer to the command MC_CMD_PRIVILEGE_MASK
14427  */
14428 #define       MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
14429 #define       MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
14430 /* Privileges to be removed from the target functions. For privilege
14431  * definitions refer to the command MC_CMD_PRIVILEGE_MASK
14432  */
14433 #define       MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
14434 #define       MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
14435 
14436 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
14437 #define    MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
14438 
14439 
14440 /***********************************/
14441 /* MC_CMD_XPM_READ_BYTES
14442  * Read XPM memory
14443  */
14444 #define MC_CMD_XPM_READ_BYTES 0x103
14445 
14446 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14447 
14448 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */
14449 #define    MC_CMD_XPM_READ_BYTES_IN_LEN 8
14450 /* Start address (byte) */
14451 #define       MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
14452 #define       MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
14453 /* Count (bytes) */
14454 #define       MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
14455 #define       MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
14456 
14457 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
14458 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
14459 #define    MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
14460 #define    MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
14461 /* Data */
14462 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
14463 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
14464 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
14465 #define       MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
14466 
14467 
14468 /***********************************/
14469 /* MC_CMD_XPM_WRITE_BYTES
14470  * Write XPM memory
14471  */
14472 #define MC_CMD_XPM_WRITE_BYTES 0x104
14473 
14474 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14475 
14476 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
14477 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
14478 #define    MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
14479 #define    MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
14480 /* Start address (byte) */
14481 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
14482 #define       MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
14483 /* Count (bytes) */
14484 #define       MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
14485 #define       MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
14486 /* Data */
14487 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8
14488 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
14489 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
14490 #define       MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
14491 
14492 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
14493 #define    MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
14494 
14495 
14496 /***********************************/
14497 /* MC_CMD_XPM_READ_SECTOR
14498  * Read XPM sector
14499  */
14500 #define MC_CMD_XPM_READ_SECTOR 0x105
14501 
14502 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14503 
14504 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */
14505 #define    MC_CMD_XPM_READ_SECTOR_IN_LEN 8
14506 /* Sector index */
14507 #define       MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
14508 #define       MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
14509 /* Sector size */
14510 #define       MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
14511 #define       MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
14512 
14513 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
14514 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
14515 #define    MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
14516 #define    MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
14517 /* Sector type */
14518 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
14519 #define       MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
14520 #define          MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
14521 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
14522 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
14523 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
14524 #define          MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
14525 /* Sector data */
14526 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
14527 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
14528 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
14529 #define       MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
14530 
14531 
14532 /***********************************/
14533 /* MC_CMD_XPM_WRITE_SECTOR
14534  * Write XPM sector
14535  */
14536 #define MC_CMD_XPM_WRITE_SECTOR 0x106
14537 
14538 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14539 
14540 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
14541 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
14542 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
14543 #define    MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
14544 /* If writing fails due to an uncorrectable error, try up to RETRIES following
14545  * sectors (or until no more space available). If 0, only one write attempt is
14546  * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
14547  * mechanism.
14548  */
14549 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
14550 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
14551 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
14552 #define       MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3
14553 /* Sector type */
14554 #define       MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
14555 #define       MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
14556 /*            Enum values, see field(s): */
14557 /*               MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */
14558 /* Sector size */
14559 #define       MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8
14560 #define       MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
14561 /* Sector data */
14562 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12
14563 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
14564 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
14565 #define       MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
14566 
14567 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
14568 #define    MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
14569 /* New sector index */
14570 #define       MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
14571 #define       MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
14572 
14573 
14574 /***********************************/
14575 /* MC_CMD_XPM_INVALIDATE_SECTOR
14576  * Invalidate XPM sector
14577  */
14578 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
14579 
14580 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14581 
14582 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */
14583 #define    MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
14584 /* Sector index */
14585 #define       MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
14586 #define       MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
14587 
14588 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */
14589 #define    MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
14590 
14591 
14592 /***********************************/
14593 /* MC_CMD_XPM_BLANK_CHECK
14594  * Blank-check XPM memory and report bad locations
14595  */
14596 #define MC_CMD_XPM_BLANK_CHECK 0x108
14597 
14598 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14599 
14600 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */
14601 #define    MC_CMD_XPM_BLANK_CHECK_IN_LEN 8
14602 /* Start address (byte) */
14603 #define       MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
14604 #define       MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
14605 /* Count (bytes) */
14606 #define       MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
14607 #define       MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
14608 
14609 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
14610 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
14611 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
14612 #define    MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
14613 /* Total number of bad (non-blank) locations */
14614 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
14615 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
14616 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit
14617  * into MCDI response)
14618  */
14619 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
14620 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
14621 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
14622 #define       MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
14623 
14624 
14625 /***********************************/
14626 /* MC_CMD_XPM_REPAIR
14627  * Blank-check and repair XPM memory
14628  */
14629 #define MC_CMD_XPM_REPAIR 0x109
14630 
14631 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14632 
14633 /* MC_CMD_XPM_REPAIR_IN msgrequest */
14634 #define    MC_CMD_XPM_REPAIR_IN_LEN 8
14635 /* Start address (byte) */
14636 #define       MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
14637 #define       MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
14638 /* Count (bytes) */
14639 #define       MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
14640 #define       MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
14641 
14642 /* MC_CMD_XPM_REPAIR_OUT msgresponse */
14643 #define    MC_CMD_XPM_REPAIR_OUT_LEN 0
14644 
14645 
14646 /***********************************/
14647 /* MC_CMD_XPM_DECODER_TEST
14648  * Test XPM memory address decoders for gross manufacturing defects. Can only
14649  * be performed on an unprogrammed part.
14650  */
14651 #define MC_CMD_XPM_DECODER_TEST 0x10a
14652 
14653 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14654 
14655 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */
14656 #define    MC_CMD_XPM_DECODER_TEST_IN_LEN 0
14657 
14658 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */
14659 #define    MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
14660 
14661 
14662 /***********************************/
14663 /* MC_CMD_XPM_WRITE_TEST
14664  * XPM memory write test. Test XPM write logic for gross manufacturing defects
14665  * by writing to a dedicated test row. There are 16 locations in the test row
14666  * and the test can only be performed on locations that have not been
14667  * previously used (i.e. can be run at most 16 times). The test will pick the
14668  * first available location to use, or fail with ENOSPC if none left.
14669  */
14670 #define MC_CMD_XPM_WRITE_TEST 0x10b
14671 
14672 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14673 
14674 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */
14675 #define    MC_CMD_XPM_WRITE_TEST_IN_LEN 0
14676 
14677 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */
14678 #define    MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
14679 
14680 
14681 /***********************************/
14682 /* MC_CMD_EXEC_SIGNED
14683  * Check the CMAC of the contents of IMEM and DMEM against the value supplied
14684  * and if correct begin execution from the start of IMEM. The caller supplies a
14685  * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC
14686  * computation runs from the start of IMEM, and from the start of DMEM + 16k,
14687  * to match flash booting. The command will respond with EINVAL if the CMAC
14688  * does match, otherwise it will respond with success before it jumps to IMEM.
14689  */
14690 #define MC_CMD_EXEC_SIGNED 0x10c
14691 
14692 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14693 
14694 /* MC_CMD_EXEC_SIGNED_IN msgrequest */
14695 #define    MC_CMD_EXEC_SIGNED_IN_LEN 28
14696 /* the length of code to include in the CMAC */
14697 #define       MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
14698 #define       MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
14699 /* the length of date to include in the CMAC */
14700 #define       MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
14701 #define       MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
14702 /* the XPM sector containing the key to use */
14703 #define       MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8
14704 #define       MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
14705 /* the expected CMAC value */
14706 #define       MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12
14707 #define       MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16
14708 
14709 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */
14710 #define    MC_CMD_EXEC_SIGNED_OUT_LEN 0
14711 
14712 
14713 /***********************************/
14714 /* MC_CMD_PREPARE_SIGNED
14715  * Prepare to upload a signed image. This will scrub the specified length of
14716  * the data region, which must be at least as large as the DATALEN supplied to
14717  * MC_CMD_EXEC_SIGNED.
14718  */
14719 #define MC_CMD_PREPARE_SIGNED 0x10d
14720 
14721 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14722 
14723 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */
14724 #define    MC_CMD_PREPARE_SIGNED_IN_LEN 4
14725 /* the length of data area to clear */
14726 #define       MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
14727 #define       MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
14728 
14729 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */
14730 #define    MC_CMD_PREPARE_SIGNED_OUT_LEN 0
14731 
14732 
14733 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
14734 #define    TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
14735 /* UDP port (the standard ports are named below but any port may be used) */
14736 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
14737 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
14738 /* enum: the IANA allocated UDP port for VXLAN */
14739 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
14740 /* enum: the IANA allocated UDP port for Geneve */
14741 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
14742 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
14743 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
14744 /* tunnel encapsulation protocol (only those named below are supported) */
14745 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
14746 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
14747 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
14748 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
14749 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */
14750 #define          TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
14751 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
14752 #define       TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
14753 
14754 
14755 /***********************************/
14756 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
14757  * Configure UDP ports for tunnel encapsulation hardware acceleration. The
14758  * parser-dispatcher will attempt to parse traffic on these ports as tunnel
14759  * encapsulation PDUs and filter them using the tunnel encapsulation filter
14760  * chain rather than the standard filter chain. Note that this command can
14761  * cause all functions to see a reset. (Available on Medford only.)
14762  */
14763 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
14764 
14765 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14766 
14767 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
14768 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
14769 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
14770 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
14771 /* Flags */
14772 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
14773 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
14774 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
14775 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
14776 /* The number of entries in the ENTRIES array */
14777 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
14778 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
14779 /* Entries defining the UDP port to protocol mapping, each laid out as a
14780  * TUNNEL_ENCAP_UDP_PORT_ENTRY
14781  */
14782 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
14783 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
14784 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
14785 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
14786 
14787 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
14788 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
14789 /* Flags */
14790 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
14791 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
14792 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
14793 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
14794 
14795 
14796 /***********************************/
14797 /* MC_CMD_RX_BALANCING
14798  * Configure a port upconverter to distribute the packets on both RX engines.
14799  * Packets are distributed based on a table with the destination vFIFO. The
14800  * index of the table is a hash of source and destination of IPV4 and VLAN
14801  * priority.
14802  */
14803 #define MC_CMD_RX_BALANCING 0x118
14804 
14805 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14806 
14807 /* MC_CMD_RX_BALANCING_IN msgrequest */
14808 #define    MC_CMD_RX_BALANCING_IN_LEN 16
14809 /* The RX port whose upconverter table will be modified */
14810 #define       MC_CMD_RX_BALANCING_IN_PORT_OFST 0
14811 #define       MC_CMD_RX_BALANCING_IN_PORT_LEN 4
14812 /* The VLAN priority associated to the table index and vFIFO */
14813 #define       MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
14814 #define       MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
14815 /* The resulting bit of SRC^DST for indexing the table */
14816 #define       MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8
14817 #define       MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
14818 /* The RX engine to which the vFIFO in the table entry will point to */
14819 #define       MC_CMD_RX_BALANCING_IN_ENG_OFST 12
14820 #define       MC_CMD_RX_BALANCING_IN_ENG_LEN 4
14821 
14822 /* MC_CMD_RX_BALANCING_OUT msgresponse */
14823 #define    MC_CMD_RX_BALANCING_OUT_LEN 0
14824 
14825 
14826 /***********************************/
14827 /* MC_CMD_NVRAM_PRIVATE_APPEND
14828  * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST
14829  * if the tag is already present.
14830  */
14831 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
14832 
14833 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14834 
14835 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
14836 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
14837 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
14838 #define    MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
14839 /* The tag to be appended */
14840 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
14841 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
14842 /* The length of the data */
14843 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
14844 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
14845 /* The data to be contained in the TLV structure */
14846 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8
14847 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
14848 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
14849 #define       MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
14850 
14851 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
14852 #define    MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
14853 
14854 
14855 /***********************************/
14856 /* MC_CMD_XPM_VERIFY_CONTENTS
14857  * Verify that the contents of the XPM memory is correct (Medford only). This
14858  * is used during manufacture to check that the XPM memory has been programmed
14859  * correctly at ATE.
14860  */
14861 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
14862 
14863 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14864 
14865 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */
14866 #define    MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
14867 /* Data type to be checked */
14868 #define       MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
14869 #define       MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
14870 
14871 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
14872 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
14873 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
14874 #define    MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
14875 /* Number of sectors found (test builds only) */
14876 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
14877 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
14878 /* Number of bytes found (test builds only) */
14879 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
14880 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
14881 /* Length of signature */
14882 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8
14883 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
14884 /* Signature */
14885 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12
14886 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
14887 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
14888 #define       MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
14889 
14890 
14891 /***********************************/
14892 /* MC_CMD_SET_EVQ_TMR
14893  * Update the timer load, timer reload and timer mode values for a given EVQ.
14894  * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
14895  * be rounded up to the granularity supported by the hardware, then truncated
14896  * to the range supported by the hardware. The resulting value after the
14897  * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
14898  * and TMR_RELOAD_ACT_NS).
14899  */
14900 #define MC_CMD_SET_EVQ_TMR 0x120
14901 
14902 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14903 
14904 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */
14905 #define    MC_CMD_SET_EVQ_TMR_IN_LEN 16
14906 /* Function-relative queue instance */
14907 #define       MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
14908 #define       MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
14909 /* Requested value for timer load (in nanoseconds) */
14910 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
14911 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
14912 /* Requested value for timer reload (in nanoseconds) */
14913 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
14914 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
14915 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
14916 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
14917 #define       MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
14918 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
14919 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
14920 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
14921 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
14922 
14923 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
14924 #define    MC_CMD_SET_EVQ_TMR_OUT_LEN 8
14925 /* Actual value for timer load (in nanoseconds) */
14926 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
14927 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
14928 /* Actual value for timer reload (in nanoseconds) */
14929 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
14930 #define       MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
14931 
14932 
14933 /***********************************/
14934 /* MC_CMD_GET_EVQ_TMR_PROPERTIES
14935  * Query properties about the event queue timers.
14936  */
14937 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
14938 
14939 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14940 
14941 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
14942 #define    MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
14943 
14944 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
14945 #define    MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
14946 /* Reserved for future use. */
14947 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
14948 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
14949 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
14950  * nanoseconds) for each increment of the timer load/reload count. The
14951  * requested duration of a timer is this value multiplied by the timer
14952  * load/reload count.
14953  */
14954 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
14955 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
14956 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
14957  * allowed for timer load/reload counts.
14958  */
14959 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
14960 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
14961 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
14962  * multiple of this step size will be rounded in an implementation defined
14963  * manner.
14964  */
14965 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
14966 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
14967 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
14968  * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14969  */
14970 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
14971 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
14972 /* Timer durations requested via MCDI that are not a multiple of this step size
14973  * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
14974  */
14975 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
14976 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
14977 /* For timers updated using the bug35388 workaround, this is the time interval
14978  * (in nanoseconds) for each increment of the timer load/reload count. The
14979  * requested duration of a timer is this value multiplied by the timer
14980  * load/reload count. This field is only meaningful if the bug35388 workaround
14981  * is enabled.
14982  */
14983 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
14984 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
14985 /* For timers updated using the bug35388 workaround, this is the maximum value
14986  * allowed for timer load/reload counts. This field is only meaningful if the
14987  * bug35388 workaround is enabled.
14988  */
14989 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
14990 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
14991 /* For timers updated using the bug35388 workaround, timer load/reload counts
14992  * not a multiple of this step size will be rounded in an implementation
14993  * defined manner. This field is only meaningful if the bug35388 workaround is
14994  * enabled.
14995  */
14996 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
14997 #define       MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
14998 
14999 
15000 /***********************************/
15001 /* MC_CMD_ALLOCATE_TX_VFIFO_CP
15002  * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the
15003  * non used switch buffers.
15004  */
15005 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
15006 
15007 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15008 
15009 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
15010 #define    MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
15011 /* Desired instance. Must be set to a specific instance, which is a function
15012  * local queue index.
15013  */
15014 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
15015 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
15016 /* Will the common pool be used as TX_vFIFO_ULL (1) */
15017 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
15018 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
15019 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
15020 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
15021 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
15022 /* Number of buffers to reserve for the common pool */
15023 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
15024 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
15025 /* TX datapath to which the Common Pool is connected to. */
15026 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
15027 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
15028 /* enum: Extracts information from function */
15029 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
15030 /* Network port or RX Engine to which the common pool connects. */
15031 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
15032 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
15033 /* enum: Extracts information from function */
15034 /*               MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
15035 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
15036 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
15037 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
15038 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
15039 /* enum: To enable Switch loopback with Rx engine 0 */
15040 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
15041 /* enum: To enable Switch loopback with Rx engine 1 */
15042 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
15043 
15044 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15045 #define    MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
15046 /* ID of the common pool allocated */
15047 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
15048 #define       MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
15049 
15050 
15051 /***********************************/
15052 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO
15053  * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the
15054  * previously allocated common pools.
15055  */
15056 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
15057 
15058 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15059 
15060 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
15061 #define    MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
15062 /* Common pool previously allocated to which the new vFIFO will be associated
15063  */
15064 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
15065 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
15066 /* Port or RX engine to associate the vFIFO egress */
15067 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
15068 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
15069 /* enum: Extracts information from common pool */
15070 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
15071 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
15072 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
15073 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
15074 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
15075 /* enum: To enable Switch loopback with Rx engine 0 */
15076 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
15077 /* enum: To enable Switch loopback with Rx engine 1 */
15078 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
15079 /* Minimum number of buffers that the pool must have */
15080 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
15081 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
15082 /* enum: Do not check the space available */
15083 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
15084 /* Will the vFIFO be used as TX_vFIFO_ULL */
15085 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
15086 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
15087 /* Network priority of the vFIFO,if applicable */
15088 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
15089 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
15090 /* enum: Search for the lowest unused priority */
15091 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
15092 
15093 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
15094 #define    MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
15095 /* Short vFIFO ID */
15096 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
15097 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
15098 /* Network priority of the vFIFO */
15099 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
15100 #define       MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
15101 
15102 
15103 /***********************************/
15104 /* MC_CMD_TEARDOWN_TX_VFIFO_VF
15105  * This interface clears the configuration of the given vFIFO and leaves it
15106  * ready to be re-used.
15107  */
15108 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
15109 
15110 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15111 
15112 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
15113 #define    MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
15114 /* Short vFIFO ID */
15115 #define       MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
15116 #define       MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
15117 
15118 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */
15119 #define    MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
15120 
15121 
15122 /***********************************/
15123 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP
15124  * This interface clears the configuration of the given common pool and leaves
15125  * it ready to be re-used.
15126  */
15127 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
15128 
15129 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15130 
15131 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
15132 #define    MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
15133 /* Common pool ID given when pool allocated */
15134 #define       MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
15135 #define       MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
15136 
15137 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15138 #define    MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
15139 
15140 
15141 /***********************************/
15142 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS
15143  * This interface allows the host to find out how many common pool buffers are
15144  * not yet assigned.
15145  */
15146 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
15147 
15148 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15149 
15150 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
15151 #define    MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
15152 
15153 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */
15154 #define    MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8
15155 /* Available buffers for the ENG to NET vFIFOs. */
15156 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
15157 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
15158 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */
15159 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
15160 #define       MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
15161 
15162 
15163 #endif /* MCDI_PCOL_H */