1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
6 */
7
8 /* Common definitions for all Efx net driver code */
9
10 #ifndef EFX_NET_DRIVER_H
11 #define EFX_NET_DRIVER_H
12
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/timer.h>
18 #include <linux/mdio.h>
19 #include <linux/list.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/highmem.h>
23 #include <linux/workqueue.h>
24 #include <linux/mutex.h>
25 #include <linux/rwsem.h>
26 #include <linux/vmalloc.h>
27 #include <linux/i2c.h>
28 #include <linux/mtd/mtd.h>
29 #include <net/busy_poll.h>
30
31 #include "enum.h"
32 #include "bitfield.h"
33 #include "filter.h"
34
35 /**************************************************************************
36 *
37 * Build definitions
38 *
39 **************************************************************************/
40
41 #define EFX_DRIVER_VERSION "4.1"
42
43 #ifdef DEBUG
44 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
45 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
46 #else
47 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
48 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
49 #endif
50
51 /**************************************************************************
52 *
53 * Efx data structures
54 *
55 **************************************************************************/
56
57 #define EFX_MAX_CHANNELS 32U
58 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
59 #define EFX_EXTRA_CHANNEL_IOV 0
60 #define EFX_EXTRA_CHANNEL_PTP 1
61 #define EFX_MAX_EXTRA_CHANNELS 2U
62
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
65 * queues. */
66 #define EFX_MAX_TX_TC 2
67 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
68 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
69 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
70 #define EFX_TXQ_TYPES 4
71 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
72
73 /* Maximum possible MTU the driver supports */
74 #define EFX_MAX_MTU (9 * 1024)
75
76 /* Minimum MTU, from RFC791 (IP) */
77 #define EFX_MIN_MTU 68
78
79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
80 * and should be a multiple of the cache line size.
81 */
82 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
83
84 /* If possible, we should ensure cache line alignment at start and end
85 * of every buffer. Otherwise, we just need to ensure 4-byte
86 * alignment of the network header.
87 */
88 #if NET_IP_ALIGN == 0
89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
90 #else
91 #define EFX_RX_BUF_ALIGNMENT 4
92 #endif
93
94 /* Forward declare Precision Time Protocol (PTP) support structure. */
95 struct efx_ptp_data;
96 struct hwtstamp_config;
97
98 struct efx_self_tests;
99
100 /**
101 * struct efx_buffer - A general-purpose DMA buffer
102 * @addr: host base address of the buffer
103 * @dma_addr: DMA base address of the buffer
104 * @len: Buffer length, in bytes
105 *
106 * The NIC uses these buffers for its interrupt status registers and
107 * MAC stats dumps.
108 */
109 struct efx_buffer {
110 void *addr;
111 dma_addr_t dma_addr;
112 unsigned int len;
113 };
114
115 /**
116 * struct efx_special_buffer - DMA buffer entered into buffer table
117 * @buf: Standard &struct efx_buffer
118 * @index: Buffer index within controller;s buffer table
119 * @entries: Number of buffer table entries
120 *
121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
122 * Event and descriptor rings are addressed via one or more buffer
123 * table entries (and so can be physically non-contiguous, although we
124 * currently do not take advantage of that). On Falcon and Siena we
125 * have to take care of allocating and initialising the entries
126 * ourselves. On later hardware this is managed by the firmware and
127 * @index and @entries are left as 0.
128 */
129 struct efx_special_buffer {
130 struct efx_buffer buf;
131 unsigned int index;
132 unsigned int entries;
133 };
134
135 /**
136 * struct efx_tx_buffer - buffer state for a TX descriptor
137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
138 * freed when descriptor completes
139 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
140 * @dma_addr: DMA address of the fragment.
141 * @flags: Flags for allocation and DMA mapping type
142 * @len: Length of this fragment.
143 * This field is zero when the queue slot is empty.
144 * @unmap_len: Length of this fragment to unmap
145 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
146 * Only valid if @unmap_len != 0.
147 */
148 struct efx_tx_buffer {
149 const struct sk_buff *skb;
150 union {
151 efx_qword_t option;
152 dma_addr_t dma_addr;
153 };
154 unsigned short flags;
155 unsigned short len;
156 unsigned short unmap_len;
157 unsigned short dma_offset;
158 };
159 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
160 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
161 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
162 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
163
164 /**
165 * struct efx_tx_queue - An Efx TX queue
166 *
167 * This is a ring buffer of TX fragments.
168 * Since the TX completion path always executes on the same
169 * CPU and the xmit path can operate on different CPUs,
170 * performance is increased by ensuring that the completion
171 * path and the xmit path operate on different cache lines.
172 * This is particularly important if the xmit path is always
173 * executing on one CPU which is different from the completion
174 * path. There is also a cache line for members which are
175 * read but not written on the fast path.
176 *
177 * @efx: The associated Efx NIC
178 * @queue: DMA queue number
179 * @tso_version: Version of TSO in use for this queue.
180 * @channel: The associated channel
181 * @core_txq: The networking core TX queue structure
182 * @buffer: The software buffer ring
183 * @cb_page: Array of pages of copy buffers. Carved up according to
184 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
185 * @txd: The hardware descriptor ring
186 * @ptr_mask: The size of the ring minus 1.
187 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
188 * Size of the region is efx_piobuf_size.
189 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
190 * @initialised: Has hardware queue been initialised?
191 * @timestamping: Is timestamping enabled for this channel?
192 * @handle_tso: TSO xmit preparation handler. Sets up the TSO metadata and
193 * may also map tx data, depending on the nature of the TSO implementation.
194 * @read_count: Current read pointer.
195 * This is the number of buffers that have been removed from both rings.
196 * @old_write_count: The value of @write_count when last checked.
197 * This is here for performance reasons. The xmit path will
198 * only get the up-to-date value of @write_count if this
199 * variable indicates that the queue is empty. This is to
200 * avoid cache-line ping-pong between the xmit path and the
201 * completion path.
202 * @merge_events: Number of TX merged completion events
203 * @completed_desc_ptr: Most recent completed pointer - only used with
204 * timestamping.
205 * @completed_timestamp_major: Top part of the most recent tx timestamp.
206 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
207 * @insert_count: Current insert pointer
208 * This is the number of buffers that have been added to the
209 * software ring.
210 * @write_count: Current write pointer
211 * This is the number of buffers that have been added to the
212 * hardware ring.
213 * @packet_write_count: Completable write pointer
214 * This is the write pointer of the last packet written.
215 * Normally this will equal @write_count, but as option descriptors
216 * don't produce completion events, they won't update this.
217 * Filled in iff @efx->type->option_descriptors; only used for PIO.
218 * Thus, this is written and used on EF10, and neither on farch.
219 * @old_read_count: The value of read_count when last checked.
220 * This is here for performance reasons. The xmit path will
221 * only get the up-to-date value of read_count if this
222 * variable indicates that the queue is full. This is to
223 * avoid cache-line ping-pong between the xmit path and the
224 * completion path.
225 * @tso_bursts: Number of times TSO xmit invoked by kernel
226 * @tso_long_headers: Number of packets with headers too long for standard
227 * blocks
228 * @tso_packets: Number of packets via the TSO xmit path
229 * @tso_fallbacks: Number of times TSO fallback used
230 * @pushes: Number of times the TX push feature has been used
231 * @pio_packets: Number of times the TX PIO feature has been used
232 * @xmit_more_available: Are any packets waiting to be pushed to the NIC
233 * @cb_packets: Number of times the TX copybreak feature has been used
234 * @empty_read_count: If the completion path has seen the queue as empty
235 * and the transmission path has not yet checked this, the value of
236 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
237 */
238 struct efx_tx_queue {
239 /* Members which don't change on the fast path */
240 struct efx_nic *efx ____cacheline_aligned_in_smp;
241 unsigned queue;
242 unsigned int tso_version;
243 struct efx_channel *channel;
244 struct netdev_queue *core_txq;
245 struct efx_tx_buffer *buffer;
246 struct efx_buffer *cb_page;
247 struct efx_special_buffer txd;
248 unsigned int ptr_mask;
249 void __iomem *piobuf;
250 unsigned int piobuf_offset;
251 bool initialised;
252 bool timestamping;
253
254 /* Function pointers used in the fast path. */
255 int (*handle_tso)(struct efx_tx_queue*, struct sk_buff*, bool *);
256
257 /* Members used mainly on the completion path */
258 unsigned int read_count ____cacheline_aligned_in_smp;
259 unsigned int old_write_count;
260 unsigned int merge_events;
261 unsigned int bytes_compl;
262 unsigned int pkts_compl;
263 unsigned int completed_desc_ptr;
264 u32 completed_timestamp_major;
265 u32 completed_timestamp_minor;
266
267 /* Members used only on the xmit path */
268 unsigned int insert_count ____cacheline_aligned_in_smp;
269 unsigned int write_count;
270 unsigned int packet_write_count;
271 unsigned int old_read_count;
272 unsigned int tso_bursts;
273 unsigned int tso_long_headers;
274 unsigned int tso_packets;
275 unsigned int tso_fallbacks;
276 unsigned int pushes;
277 unsigned int pio_packets;
278 bool xmit_more_available;
279 unsigned int cb_packets;
280 /* Statistics to supplement MAC stats */
281 unsigned long tx_packets;
282
283 /* Members shared between paths and sometimes updated */
284 unsigned int empty_read_count ____cacheline_aligned_in_smp;
285 #define EFX_EMPTY_COUNT_VALID 0x80000000
286 atomic_t flush_outstanding;
287 };
288
289 #define EFX_TX_CB_ORDER 7
290 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
291
292 /**
293 * struct efx_rx_buffer - An Efx RX data buffer
294 * @dma_addr: DMA base address of the buffer
295 * @page: The associated page buffer.
296 * Will be %NULL if the buffer slot is currently free.
297 * @page_offset: If pending: offset in @page of DMA base address.
298 * If completed: offset in @page of Ethernet header.
299 * @len: If pending: length for DMA descriptor.
300 * If completed: received length, excluding hash prefix.
301 * @flags: Flags for buffer and packet state. These are only set on the
302 * first buffer of a scattered packet.
303 */
304 struct efx_rx_buffer {
305 dma_addr_t dma_addr;
306 struct page *page;
307 u16 page_offset;
308 u16 len;
309 u16 flags;
310 };
311 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
312 #define EFX_RX_PKT_CSUMMED 0x0002
313 #define EFX_RX_PKT_DISCARD 0x0004
314 #define EFX_RX_PKT_TCP 0x0040
315 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
316 #define EFX_RX_PKT_CSUM_LEVEL 0x0200
317
318 /**
319 * struct efx_rx_page_state - Page-based rx buffer state
320 *
321 * Inserted at the start of every page allocated for receive buffers.
322 * Used to facilitate sharing dma mappings between recycled rx buffers
323 * and those passed up to the kernel.
324 *
325 * @dma_addr: The dma address of this page.
326 */
327 struct efx_rx_page_state {
328 dma_addr_t dma_addr;
329
330 unsigned int __pad[0] ____cacheline_aligned;
331 };
332
333 /**
334 * struct efx_rx_queue - An Efx RX queue
335 * @efx: The associated Efx NIC
336 * @core_index: Index of network core RX queue. Will be >= 0 iff this
337 * is associated with a real RX queue.
338 * @buffer: The software buffer ring
339 * @rxd: The hardware descriptor ring
340 * @ptr_mask: The size of the ring minus 1.
341 * @refill_enabled: Enable refill whenever fill level is low
342 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
343 * @rxq_flush_pending.
344 * @added_count: Number of buffers added to the receive queue.
345 * @notified_count: Number of buffers given to NIC (<= @added_count).
346 * @removed_count: Number of buffers removed from the receive queue.
347 * @scatter_n: Used by NIC specific receive code.
348 * @scatter_len: Used by NIC specific receive code.
349 * @page_ring: The ring to store DMA mapped pages for reuse.
350 * @page_add: Counter to calculate the write pointer for the recycle ring.
351 * @page_remove: Counter to calculate the read pointer for the recycle ring.
352 * @page_recycle_count: The number of pages that have been recycled.
353 * @page_recycle_failed: The number of pages that couldn't be recycled because
354 * the kernel still held a reference to them.
355 * @page_recycle_full: The number of pages that were released because the
356 * recycle ring was full.
357 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
358 * @max_fill: RX descriptor maximum fill level (<= ring size)
359 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
360 * (<= @max_fill)
361 * @min_fill: RX descriptor minimum non-zero fill level.
362 * This records the minimum fill level observed when a ring
363 * refill was triggered.
364 * @recycle_count: RX buffer recycle counter.
365 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
366 */
367 struct efx_rx_queue {
368 struct efx_nic *efx;
369 int core_index;
370 struct efx_rx_buffer *buffer;
371 struct efx_special_buffer rxd;
372 unsigned int ptr_mask;
373 bool refill_enabled;
374 bool flush_pending;
375
376 unsigned int added_count;
377 unsigned int notified_count;
378 unsigned int removed_count;
379 unsigned int scatter_n;
380 unsigned int scatter_len;
381 struct page **page_ring;
382 unsigned int page_add;
383 unsigned int page_remove;
384 unsigned int page_recycle_count;
385 unsigned int page_recycle_failed;
386 unsigned int page_recycle_full;
387 unsigned int page_ptr_mask;
388 unsigned int max_fill;
389 unsigned int fast_fill_trigger;
390 unsigned int min_fill;
391 unsigned int min_overfill;
392 unsigned int recycle_count;
393 struct timer_list slow_fill;
394 unsigned int slow_fill_count;
395 /* Statistics to supplement MAC stats */
396 unsigned long rx_packets;
397 };
398
399 enum efx_sync_events_state {
400 SYNC_EVENTS_DISABLED = 0,
401 SYNC_EVENTS_QUIESCENT,
402 SYNC_EVENTS_REQUESTED,
403 SYNC_EVENTS_VALID,
404 };
405
406 /**
407 * struct efx_channel - An Efx channel
408 *
409 * A channel comprises an event queue, at least one TX queue, at least
410 * one RX queue, and an associated tasklet for processing the event
411 * queue.
412 *
413 * @efx: Associated Efx NIC
414 * @channel: Channel instance number
415 * @type: Channel type definition
416 * @eventq_init: Event queue initialised flag
417 * @enabled: Channel enabled indicator
418 * @irq: IRQ number (MSI and MSI-X only)
419 * @irq_moderation_us: IRQ moderation value (in microseconds)
420 * @napi_dev: Net device used with NAPI
421 * @napi_str: NAPI control structure
422 * @state: state for NAPI vs busy polling
423 * @state_lock: lock protecting @state
424 * @eventq: Event queue buffer
425 * @eventq_mask: Event queue pointer mask
426 * @eventq_read_ptr: Event queue read pointer
427 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
428 * @irq_count: Number of IRQs since last adaptive moderation decision
429 * @irq_mod_score: IRQ moderation score
430 * @filter_work: Work item for efx_filter_rfs_expire()
431 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
432 * indexed by filter ID
433 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
434 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
435 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
436 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
437 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
438 * @n_rx_overlength: Count of RX_OVERLENGTH errors
439 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
440 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
441 * lack of descriptors
442 * @n_rx_merge_events: Number of RX merged completion events
443 * @n_rx_merge_packets: Number of RX packets completed by merged events
444 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
445 * __efx_rx_packet(), or zero if there is none
446 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
447 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
448 * @rx_list: list of SKBs from current RX, awaiting processing
449 * @rx_queue: RX queue for this channel
450 * @tx_queue: TX queues for this channel
451 * @sync_events_state: Current state of sync events on this channel
452 * @sync_timestamp_major: Major part of the last ptp sync event
453 * @sync_timestamp_minor: Minor part of the last ptp sync event
454 */
455 struct efx_channel {
456 struct efx_nic *efx;
457 int channel;
458 const struct efx_channel_type *type;
459 bool eventq_init;
460 bool enabled;
461 int irq;
462 unsigned int irq_moderation_us;
463 struct net_device *napi_dev;
464 struct napi_struct napi_str;
465 #ifdef CONFIG_NET_RX_BUSY_POLL
466 unsigned long busy_poll_state;
467 #endif
468 struct efx_special_buffer eventq;
469 unsigned int eventq_mask;
470 unsigned int eventq_read_ptr;
471 int event_test_cpu;
472
473 unsigned int irq_count;
474 unsigned int irq_mod_score;
475 #ifdef CONFIG_RFS_ACCEL
476 unsigned int rfs_filters_added;
477 struct work_struct filter_work;
478 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
479 u32 *rps_flow_id;
480 #endif
481
482 unsigned int n_rx_tobe_disc;
483 unsigned int n_rx_ip_hdr_chksum_err;
484 unsigned int n_rx_tcp_udp_chksum_err;
485 unsigned int n_rx_outer_ip_hdr_chksum_err;
486 unsigned int n_rx_outer_tcp_udp_chksum_err;
487 unsigned int n_rx_inner_ip_hdr_chksum_err;
488 unsigned int n_rx_inner_tcp_udp_chksum_err;
489 unsigned int n_rx_eth_crc_err;
490 unsigned int n_rx_mcast_mismatch;
491 unsigned int n_rx_frm_trunc;
492 unsigned int n_rx_overlength;
493 unsigned int n_skbuff_leaks;
494 unsigned int n_rx_nodesc_trunc;
495 unsigned int n_rx_merge_events;
496 unsigned int n_rx_merge_packets;
497
498 unsigned int rx_pkt_n_frags;
499 unsigned int rx_pkt_index;
500
501 struct list_head *rx_list;
502
503 struct efx_rx_queue rx_queue;
504 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
505
506 enum efx_sync_events_state sync_events_state;
507 u32 sync_timestamp_major;
508 u32 sync_timestamp_minor;
509 };
510
511 /**
512 * struct efx_msi_context - Context for each MSI
513 * @efx: The associated NIC
514 * @index: Index of the channel/IRQ
515 * @name: Name of the channel/IRQ
516 *
517 * Unlike &struct efx_channel, this is never reallocated and is always
518 * safe for the IRQ handler to access.
519 */
520 struct efx_msi_context {
521 struct efx_nic *efx;
522 unsigned int index;
523 char name[IFNAMSIZ + 6];
524 };
525
526 /**
527 * struct efx_channel_type - distinguishes traffic and extra channels
528 * @handle_no_channel: Handle failure to allocate an extra channel
529 * @pre_probe: Set up extra state prior to initialisation
530 * @post_remove: Tear down extra state after finalisation, if allocated.
531 * May be called on channels that have not been probed.
532 * @get_name: Generate the channel's name (used for its IRQ handler)
533 * @copy: Copy the channel state prior to reallocation. May be %NULL if
534 * reallocation is not supported.
535 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
536 * @want_txqs: Determine whether this channel should have TX queues
537 * created. If %NULL, TX queues are not created.
538 * @keep_eventq: Flag for whether event queue should be kept initialised
539 * while the device is stopped
540 * @want_pio: Flag for whether PIO buffers should be linked to this
541 * channel's TX queues.
542 */
543 struct efx_channel_type {
544 void (*handle_no_channel)(struct efx_nic *);
545 int (*pre_probe)(struct efx_channel *);
546 void (*post_remove)(struct efx_channel *);
547 void (*get_name)(struct efx_channel *, char *buf, size_t len);
548 struct efx_channel *(*copy)(const struct efx_channel *);
549 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
550 bool (*want_txqs)(struct efx_channel *);
551 bool keep_eventq;
552 bool want_pio;
553 };
554
555 enum efx_led_mode {
556 EFX_LED_OFF = 0,
557 EFX_LED_ON = 1,
558 EFX_LED_DEFAULT = 2
559 };
560
561 #define STRING_TABLE_LOOKUP(val, member) \
562 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
563
564 extern const char *const efx_loopback_mode_names[];
565 extern const unsigned int efx_loopback_mode_max;
566 #define LOOPBACK_MODE(efx) \
567 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
568
569 extern const char *const efx_reset_type_names[];
570 extern const unsigned int efx_reset_type_max;
571 #define RESET_TYPE(type) \
572 STRING_TABLE_LOOKUP(type, efx_reset_type)
573
574 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen);
575
576 enum efx_int_mode {
577 /* Be careful if altering to correct macro below */
578 EFX_INT_MODE_MSIX = 0,
579 EFX_INT_MODE_MSI = 1,
580 EFX_INT_MODE_LEGACY = 2,
581 EFX_INT_MODE_MAX /* Insert any new items before this */
582 };
583 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
584
585 enum nic_state {
586 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
587 STATE_READY = 1, /* hardware ready and netdev registered */
588 STATE_DISABLED = 2, /* device disabled due to hardware errors */
589 STATE_RECOVERY = 3, /* device recovering from PCI error */
590 };
591
592 /* Forward declaration */
593 struct efx_nic;
594
595 /* Pseudo bit-mask flow control field */
596 #define EFX_FC_RX FLOW_CTRL_RX
597 #define EFX_FC_TX FLOW_CTRL_TX
598 #define EFX_FC_AUTO 4
599
600 /**
601 * struct efx_link_state - Current state of the link
602 * @up: Link is up
603 * @fd: Link is full-duplex
604 * @fc: Actual flow control flags
605 * @speed: Link speed (Mbps)
606 */
607 struct efx_link_state {
608 bool up;
609 bool fd;
610 u8 fc;
611 unsigned int speed;
612 };
613
614 static inline bool efx_link_state_equal(const struct efx_link_state *left,
615 const struct efx_link_state *right)
616 {
617 return left->up == right->up && left->fd == right->fd &&
618 left->fc == right->fc && left->speed == right->speed;
619 }
620
621 /**
622 * struct efx_phy_operations - Efx PHY operations table
623 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
624 * efx->loopback_modes.
625 * @init: Initialise PHY
626 * @fini: Shut down PHY
627 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
628 * @poll: Update @link_state and report whether it changed.
629 * Serialised by the mac_lock.
630 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock.
631 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock.
632 * @get_fecparam: Get Forward Error Correction settings. Serialised by mac_lock.
633 * @set_fecparam: Set Forward Error Correction settings. Serialised by mac_lock.
634 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
635 * (only needed where AN bit is set in mmds)
636 * @test_alive: Test that PHY is 'alive' (online)
637 * @test_name: Get the name of a PHY-specific test/result
638 * @run_tests: Run tests and record results as appropriate (offline).
639 * Flags are the ethtool tests flags.
640 */
641 struct efx_phy_operations {
642 int (*probe) (struct efx_nic *efx);
643 int (*init) (struct efx_nic *efx);
644 void (*fini) (struct efx_nic *efx);
645 void (*remove) (struct efx_nic *efx);
646 int (*reconfigure) (struct efx_nic *efx);
647 bool (*poll) (struct efx_nic *efx);
648 void (*get_link_ksettings)(struct efx_nic *efx,
649 struct ethtool_link_ksettings *cmd);
650 int (*set_link_ksettings)(struct efx_nic *efx,
651 const struct ethtool_link_ksettings *cmd);
652 int (*get_fecparam)(struct efx_nic *efx, struct ethtool_fecparam *fec);
653 int (*set_fecparam)(struct efx_nic *efx,
654 const struct ethtool_fecparam *fec);
655 void (*set_npage_adv) (struct efx_nic *efx, u32);
656 int (*test_alive) (struct efx_nic *efx);
657 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
658 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
659 int (*get_module_eeprom) (struct efx_nic *efx,
660 struct ethtool_eeprom *ee,
661 u8 *data);
662 int (*get_module_info) (struct efx_nic *efx,
663 struct ethtool_modinfo *modinfo);
664 };
665
666 /**
667 * enum efx_phy_mode - PHY operating mode flags
668 * @PHY_MODE_NORMAL: on and should pass traffic
669 * @PHY_MODE_TX_DISABLED: on with TX disabled
670 * @PHY_MODE_LOW_POWER: set to low power through MDIO
671 * @PHY_MODE_OFF: switched off through external control
672 * @PHY_MODE_SPECIAL: on but will not pass traffic
673 */
674 enum efx_phy_mode {
675 PHY_MODE_NORMAL = 0,
676 PHY_MODE_TX_DISABLED = 1,
677 PHY_MODE_LOW_POWER = 2,
678 PHY_MODE_OFF = 4,
679 PHY_MODE_SPECIAL = 8,
680 };
681
682 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
683 {
684 return !!(mode & ~PHY_MODE_TX_DISABLED);
685 }
686
687 /**
688 * struct efx_hw_stat_desc - Description of a hardware statistic
689 * @name: Name of the statistic as visible through ethtool, or %NULL if
690 * it should not be exposed
691 * @dma_width: Width in bits (0 for non-DMA statistics)
692 * @offset: Offset within stats (ignored for non-DMA statistics)
693 */
694 struct efx_hw_stat_desc {
695 const char *name;
696 u16 dma_width;
697 u16 offset;
698 };
699
700 /* Number of bits used in a multicast filter hash address */
701 #define EFX_MCAST_HASH_BITS 8
702
703 /* Number of (single-bit) entries in a multicast filter hash */
704 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
705
706 /* An Efx multicast filter hash */
707 union efx_multicast_hash {
708 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
709 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
710 };
711
712 struct vfdi_status;
713
714 /* The reserved RSS context value */
715 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
716 /**
717 * struct efx_rss_context - A user-defined RSS context for filtering
718 * @list: node of linked list on which this struct is stored
719 * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
720 * %EFX_EF10_RSS_CONTEXT_INVALID if this context is not present on the NIC.
721 * For Siena, 0 if RSS is active, else %EFX_EF10_RSS_CONTEXT_INVALID.
722 * @user_id: the rss_context ID exposed to userspace over ethtool.
723 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
724 * @rx_hash_key: Toeplitz hash key for this RSS context
725 * @indir_table: Indirection table for this RSS context
726 */
727 struct efx_rss_context {
728 struct list_head list;
729 u32 context_id;
730 u32 user_id;
731 bool rx_hash_udp_4tuple;
732 u8 rx_hash_key[40];
733 u32 rx_indir_table[128];
734 };
735
736 #ifdef CONFIG_RFS_ACCEL
737 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
738 * is used to test if filter does or will exist.
739 */
740 #define EFX_ARFS_FILTER_ID_PENDING -1
741 #define EFX_ARFS_FILTER_ID_ERROR -2
742 #define EFX_ARFS_FILTER_ID_REMOVING -3
743 /**
744 * struct efx_arfs_rule - record of an ARFS filter and its IDs
745 * @node: linkage into hash table
746 * @spec: details of the filter (used as key for hash table). Use efx->type to
747 * determine which member to use.
748 * @rxq_index: channel to which the filter will steer traffic.
749 * @arfs_id: filter ID which was returned to ARFS
750 * @filter_id: index in software filter table. May be
751 * %EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
752 * %EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
753 * %EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
754 */
755 struct efx_arfs_rule {
756 struct hlist_node node;
757 struct efx_filter_spec spec;
758 u16 rxq_index;
759 u16 arfs_id;
760 s32 filter_id;
761 };
762
763 /* Size chosen so that the table is one page (4kB) */
764 #define EFX_ARFS_HASH_TABLE_SIZE 512
765
766 /**
767 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
768 * @net_dev: Reference to the netdevice
769 * @spec: The filter to insert
770 * @work: Workitem for this request
771 * @rxq_index: Identifies the channel for which this request was made
772 * @flow_id: Identifies the kernel-side flow for which this request was made
773 */
774 struct efx_async_filter_insertion {
775 struct net_device *net_dev;
776 struct efx_filter_spec spec;
777 struct work_struct work;
778 u16 rxq_index;
779 u32 flow_id;
780 };
781
782 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */
783 #define EFX_RPS_MAX_IN_FLIGHT 8
784 #endif /* CONFIG_RFS_ACCEL */
785
786 /**
787 * struct efx_nic - an Efx NIC
788 * @name: Device name (net device name or bus id before net device registered)
789 * @pci_dev: The PCI device
790 * @node: List node for maintaning primary/secondary function lists
791 * @primary: &struct efx_nic instance for the primary function of this
792 * controller. May be the same structure, and may be %NULL if no
793 * primary function is bound. Serialised by rtnl_lock.
794 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
795 * functions of the controller, if this is for the primary function.
796 * Serialised by rtnl_lock.
797 * @type: Controller type attributes
798 * @legacy_irq: IRQ number
799 * @workqueue: Workqueue for port reconfigures and the HW monitor.
800 * Work items do not hold and must not acquire RTNL.
801 * @workqueue_name: Name of workqueue
802 * @reset_work: Scheduled reset workitem
803 * @membase_phys: Memory BAR value as physical address
804 * @membase: Memory BAR value
805 * @vi_stride: step between per-VI registers / memory regions
806 * @interrupt_mode: Interrupt mode
807 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
808 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
809 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
810 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
811 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
812 * @msg_enable: Log message enable flags
813 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
814 * @reset_pending: Bitmask for pending resets
815 * @tx_queue: TX DMA queues
816 * @rx_queue: RX DMA queues
817 * @channel: Channels
818 * @msi_context: Context for each MSI
819 * @extra_channel_types: Types of extra (non-traffic) channels that
820 * should be allocated for this NIC
821 * @rxq_entries: Size of receive queues requested by user.
822 * @txq_entries: Size of transmit queues requested by user.
823 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
824 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
825 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
826 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
827 * @sram_lim_qw: Qword address limit of SRAM
828 * @next_buffer_table: First available buffer table id
829 * @n_channels: Number of channels in use
830 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
831 * @n_tx_channels: Number of channels used for TX
832 * @n_extra_tx_channels: Number of extra channels with TX queues
833 * @rx_ip_align: RX DMA address offset to have IP header aligned in
834 * in accordance with NET_IP_ALIGN
835 * @rx_dma_len: Current maximum RX DMA length
836 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
837 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
838 * for use in sk_buff::truesize
839 * @rx_prefix_size: Size of RX prefix before packet data
840 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
841 * (valid only if @rx_prefix_size != 0; always negative)
842 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
843 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
844 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
845 * (valid only if channel->sync_timestamps_enabled; always negative)
846 * @rx_scatter: Scatter mode enabled for receives
847 * @rss_context: Main RSS context. Its @list member is the head of the list of
848 * RSS contexts created by user requests
849 * @rss_lock: Protects custom RSS context software state in @rss_context.list
850 * @int_error_count: Number of internal errors seen recently
851 * @int_error_expire: Time at which error count will be expired
852 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
853 * acknowledge but do nothing else.
854 * @irq_status: Interrupt status buffer
855 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
856 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
857 * @selftest_work: Work item for asynchronous self-test
858 * @mtd_list: List of MTDs attached to the NIC
859 * @nic_data: Hardware dependent state
860 * @mcdi: Management-Controller-to-Driver Interface state
861 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
862 * efx_monitor() and efx_reconfigure_port()
863 * @port_enabled: Port enabled indicator.
864 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
865 * efx_mac_work() with kernel interfaces. Safe to read under any
866 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
867 * be held to modify it.
868 * @port_initialized: Port initialized?
869 * @net_dev: Operating system network device. Consider holding the rtnl lock
870 * @fixed_features: Features which cannot be turned off
871 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
872 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
873 * @stats_buffer: DMA buffer for statistics
874 * @phy_type: PHY type
875 * @phy_op: PHY interface
876 * @phy_data: PHY private data (including PHY-specific stats)
877 * @mdio: PHY MDIO interface
878 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
879 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
880 * @link_advertising: Autonegotiation advertising flags
881 * @fec_config: Forward Error Correction configuration flags. For bit positions
882 * see &enum ethtool_fec_config_bits.
883 * @link_state: Current state of the link
884 * @n_link_state_changes: Number of times the link has changed state
885 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
886 * Protected by @mac_lock.
887 * @multicast_hash: Multicast hash table for Falcon-arch.
888 * Protected by @mac_lock.
889 * @wanted_fc: Wanted flow control flags
890 * @fc_disable: When non-zero flow control is disabled. Typically used to
891 * ensure that network back pressure doesn't delay dma queue flushes.
892 * Serialised by the rtnl lock.
893 * @mac_work: Work item for changing MAC promiscuity and multicast hash
894 * @loopback_mode: Loopback status
895 * @loopback_modes: Supported loopback mode bitmask
896 * @loopback_selftest: Offline self-test private state
897 * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
898 * @filter_state: Architecture-dependent filter table state
899 * @rps_mutex: Protects RPS state of all channels
900 * @rps_expire_channel: Next channel to check for expiry
901 * @rps_expire_index: Next index to check for expiry in
902 * @rps_expire_channel's @rps_flow_id
903 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
904 * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
905 * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
906 * @rps_next_id).
907 * @rps_hash_table: Mapping between ARFS filters and their various IDs
908 * @rps_next_id: next arfs_id for an ARFS filter
909 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
910 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
911 * Decremented when the efx_flush_rx_queue() is called.
912 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
913 * completed (either success or failure). Not used when MCDI is used to
914 * flush receive queues.
915 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
916 * @vf_count: Number of VFs intended to be enabled.
917 * @vf_init_count: Number of VFs that have been fully initialised.
918 * @vi_scale: log2 number of vnics per VF.
919 * @ptp_data: PTP state data
920 * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
921 * @vpd_sn: Serial number read from VPD
922 * @monitor_work: Hardware monitor workitem
923 * @biu_lock: BIU (bus interface unit) lock
924 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
925 * field is used by efx_test_interrupts() to verify that an
926 * interrupt has occurred.
927 * @stats_lock: Statistics update lock. Must be held when calling
928 * efx_nic_type::{update,start,stop}_stats.
929 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
930 *
931 * This is stored in the private area of the &struct net_device.
932 */
933 struct efx_nic {
934 /* The following fields should be written very rarely */
935
936 char name[IFNAMSIZ];
937 struct list_head node;
938 struct efx_nic *primary;
939 struct list_head secondary_list;
940 struct pci_dev *pci_dev;
941 unsigned int port_num;
942 const struct efx_nic_type *type;
943 int legacy_irq;
944 bool eeh_disabled_legacy_irq;
945 struct workqueue_struct *workqueue;
946 char workqueue_name[16];
947 struct work_struct reset_work;
948 resource_size_t membase_phys;
949 void __iomem *membase;
950
951 unsigned int vi_stride;
952
953 enum efx_int_mode interrupt_mode;
954 unsigned int timer_quantum_ns;
955 unsigned int timer_max_ns;
956 bool irq_rx_adaptive;
957 unsigned int irq_mod_step_us;
958 unsigned int irq_rx_moderation_us;
959 u32 msg_enable;
960
961 enum nic_state state;
962 unsigned long reset_pending;
963
964 struct efx_channel *channel[EFX_MAX_CHANNELS];
965 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
966 const struct efx_channel_type *
967 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
968
969 unsigned rxq_entries;
970 unsigned txq_entries;
971 unsigned int txq_stop_thresh;
972 unsigned int txq_wake_thresh;
973
974 unsigned tx_dc_base;
975 unsigned rx_dc_base;
976 unsigned sram_lim_qw;
977 unsigned next_buffer_table;
978
979 unsigned int max_channels;
980 unsigned int max_tx_channels;
981 unsigned n_channels;
982 unsigned n_rx_channels;
983 unsigned rss_spread;
984 unsigned tx_channel_offset;
985 unsigned n_tx_channels;
986 unsigned n_extra_tx_channels;
987 unsigned int rx_ip_align;
988 unsigned int rx_dma_len;
989 unsigned int rx_buffer_order;
990 unsigned int rx_buffer_truesize;
991 unsigned int rx_page_buf_step;
992 unsigned int rx_bufs_per_page;
993 unsigned int rx_pages_per_batch;
994 unsigned int rx_prefix_size;
995 int rx_packet_hash_offset;
996 int rx_packet_len_offset;
997 int rx_packet_ts_offset;
998 bool rx_scatter;
999 struct efx_rss_context rss_context;
1000 struct mutex rss_lock;
1001
1002 unsigned int_error_count;
1003 unsigned long int_error_expire;
1004
1005 bool irq_soft_enabled;
1006 struct efx_buffer irq_status;
1007 unsigned irq_zero_count;
1008 unsigned irq_level;
1009 struct delayed_work selftest_work;
1010
1011 #ifdef CONFIG_SFC_MTD
1012 struct list_head mtd_list;
1013 #endif
1014
1015 void *nic_data;
1016 struct efx_mcdi_data *mcdi;
1017
1018 struct mutex mac_lock;
1019 struct work_struct mac_work;
1020 bool port_enabled;
1021
1022 bool mc_bist_for_other_fn;
1023 bool port_initialized;
1024 struct net_device *net_dev;
1025
1026 netdev_features_t fixed_features;
1027
1028 u16 num_mac_stats;
1029 struct efx_buffer stats_buffer;
1030 u64 rx_nodesc_drops_total;
1031 u64 rx_nodesc_drops_while_down;
1032 bool rx_nodesc_drops_prev_state;
1033
1034 unsigned int phy_type;
1035 const struct efx_phy_operations *phy_op;
1036 void *phy_data;
1037 struct mdio_if_info mdio;
1038 unsigned int mdio_bus;
1039 enum efx_phy_mode phy_mode;
1040
1041 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1042 u32 fec_config;
1043 struct efx_link_state link_state;
1044 unsigned int n_link_state_changes;
1045
1046 bool unicast_filter;
1047 union efx_multicast_hash multicast_hash;
1048 u8 wanted_fc;
1049 unsigned fc_disable;
1050
1051 atomic_t rx_reset;
1052 enum efx_loopback_mode loopback_mode;
1053 u64 loopback_modes;
1054
1055 void *loopback_selftest;
1056
1057 struct rw_semaphore filter_sem;
1058 void *filter_state;
1059 #ifdef CONFIG_RFS_ACCEL
1060 struct mutex rps_mutex;
1061 unsigned int rps_expire_channel;
1062 unsigned int rps_expire_index;
1063 unsigned long rps_slot_map;
1064 struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1065 spinlock_t rps_hash_lock;
1066 struct hlist_head *rps_hash_table;
1067 u32 rps_next_id;
1068 #endif
1069
1070 atomic_t active_queues;
1071 atomic_t rxq_flush_pending;
1072 atomic_t rxq_flush_outstanding;
1073 wait_queue_head_t flush_wq;
1074
1075 #ifdef CONFIG_SFC_SRIOV
1076 unsigned vf_count;
1077 unsigned vf_init_count;
1078 unsigned vi_scale;
1079 #endif
1080
1081 struct efx_ptp_data *ptp_data;
1082 bool ptp_warned;
1083
1084 char *vpd_sn;
1085
1086 /* The following fields may be written more often */
1087
1088 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1089 spinlock_t biu_lock;
1090 int last_irq_cpu;
1091 spinlock_t stats_lock;
1092 atomic_t n_rx_noskb_drops;
1093 };
1094
1095 static inline int efx_dev_registered(struct efx_nic *efx)
1096 {
1097 return efx->net_dev->reg_state == NETREG_REGISTERED;
1098 }
1099
1100 static inline unsigned int efx_port_num(struct efx_nic *efx)
1101 {
1102 return efx->port_num;
1103 }
1104
1105 struct efx_mtd_partition {
1106 struct list_head node;
1107 struct mtd_info mtd;
1108 const char *dev_type_name;
1109 const char *type_name;
1110 char name[IFNAMSIZ + 20];
1111 };
1112
1113 struct efx_udp_tunnel {
1114 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1115 __be16 port;
1116 /* Count of repeated adds of the same port. Used only inside the list,
1117 * not in request arguments.
1118 */
1119 u16 count;
1120 };
1121
1122 /**
1123 * struct efx_nic_type - Efx device type definition
1124 * @mem_bar: Get the memory BAR
1125 * @mem_map_size: Get memory BAR mapped size
1126 * @probe: Probe the controller
1127 * @remove: Free resources allocated by probe()
1128 * @init: Initialise the controller
1129 * @dimension_resources: Dimension controller resources (buffer table,
1130 * and VIs once the available interrupt resources are clear)
1131 * @fini: Shut down the controller
1132 * @monitor: Periodic function for polling link state and hardware monitor
1133 * @map_reset_reason: Map ethtool reset reason to a reset method
1134 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1135 * @reset: Reset the controller hardware and possibly the PHY. This will
1136 * be called while the controller is uninitialised.
1137 * @probe_port: Probe the MAC and PHY
1138 * @remove_port: Free resources allocated by probe_port()
1139 * @handle_global_event: Handle a "global" event (may be %NULL)
1140 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1141 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1142 * (for Falcon architecture)
1143 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1144 * architecture)
1145 * @prepare_flr: Prepare for an FLR
1146 * @finish_flr: Clean up after an FLR
1147 * @describe_stats: Describe statistics for ethtool
1148 * @update_stats: Update statistics not provided by event handling.
1149 * Either argument may be %NULL.
1150 * @start_stats: Start the regular fetching of statistics
1151 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1152 * @stop_stats: Stop the regular fetching of statistics
1153 * @set_id_led: Set state of identifying LED or revert to automatic function
1154 * @push_irq_moderation: Apply interrupt moderation value
1155 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1156 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1157 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1158 * to the hardware. Serialised by the mac_lock.
1159 * @check_mac_fault: Check MAC fault state. True if fault present.
1160 * @get_wol: Get WoL configuration from driver state
1161 * @set_wol: Push WoL configuration to the NIC
1162 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1163 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1164 * expected to reset the NIC.
1165 * @test_nvram: Test validity of NVRAM contents
1166 * @mcdi_request: Send an MCDI request with the given header and SDU.
1167 * The SDU length may be any value from 0 up to the protocol-
1168 * defined maximum, but its buffer will be padded to a multiple
1169 * of 4 bytes.
1170 * @mcdi_poll_response: Test whether an MCDI response is available.
1171 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1172 * be a multiple of 4. The length may not be, but the buffer
1173 * will be padded so it is safe to round up.
1174 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1175 * return an appropriate error code for aborting any current
1176 * request; otherwise return 0.
1177 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1178 * be separately enabled after this.
1179 * @irq_test_generate: Generate a test IRQ
1180 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1181 * queue must be separately disabled before this.
1182 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1183 * a pointer to the &struct efx_msi_context for the channel.
1184 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1185 * is a pointer to the &struct efx_nic.
1186 * @tx_probe: Allocate resources for TX queue
1187 * @tx_init: Initialise TX queue on the NIC
1188 * @tx_remove: Free resources for TX queue
1189 * @tx_write: Write TX descriptors and doorbell
1190 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1191 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1192 * @rx_push_rss_context_config: Write RSS hash key and indirection table for
1193 * user RSS context to the NIC
1194 * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user
1195 * RSS context back from the NIC
1196 * @rx_probe: Allocate resources for RX queue
1197 * @rx_init: Initialise RX queue on the NIC
1198 * @rx_remove: Free resources for RX queue
1199 * @rx_write: Write RX descriptors and doorbell
1200 * @rx_defer_refill: Generate a refill reminder event
1201 * @ev_probe: Allocate resources for event queue
1202 * @ev_init: Initialise event queue on the NIC
1203 * @ev_fini: Deinitialise event queue on the NIC
1204 * @ev_remove: Free resources for event queue
1205 * @ev_process: Process events for a queue, up to the given NAPI quota
1206 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1207 * @ev_test_generate: Generate a test event
1208 * @filter_table_probe: Probe filter capabilities and set up filter software state
1209 * @filter_table_restore: Restore filters removed from hardware
1210 * @filter_table_remove: Remove filters from hardware and tear down software state
1211 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1212 * @filter_insert: add or replace a filter
1213 * @filter_remove_safe: remove a filter by ID, carefully
1214 * @filter_get_safe: retrieve a filter by ID, carefully
1215 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1216 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1217 * @filter_count_rx_used: Get the number of filters in use at a given priority
1218 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1219 * @filter_get_rx_ids: Get list of RX filters at a given priority
1220 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1221 * This must check whether the specified table entry is used by RFS
1222 * and that rps_may_expire_flow() returns true for it.
1223 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1224 * using efx_mtd_add()
1225 * @mtd_rename: Set an MTD partition name using the net device name
1226 * @mtd_read: Read from an MTD partition
1227 * @mtd_erase: Erase part of an MTD partition
1228 * @mtd_write: Write to an MTD partition
1229 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1230 * also notifies the driver that a writer has finished using this
1231 * partition.
1232 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1233 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1234 * timestamping, possibly only temporarily for the purposes of a reset.
1235 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1236 * and tx_type will already have been validated but this operation
1237 * must validate and update rx_filter.
1238 * @get_phys_port_id: Get the underlying physical port id.
1239 * @set_mac_address: Set the MAC address of the device
1240 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1241 * If %NULL, then device does not support any TSO version.
1242 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1243 * @udp_tnl_add_port: Add a UDP tunnel port
1244 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1245 * @udp_tnl_del_port: Remove a UDP tunnel port
1246 * @revision: Hardware architecture revision
1247 * @txd_ptr_tbl_base: TX descriptor ring base address
1248 * @rxd_ptr_tbl_base: RX descriptor ring base address
1249 * @buf_tbl_base: Buffer table base address
1250 * @evq_ptr_tbl_base: Event queue pointer table base address
1251 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1252 * @max_dma_mask: Maximum possible DMA mask
1253 * @rx_prefix_size: Size of RX prefix before packet data
1254 * @rx_hash_offset: Offset of RX flow hash within prefix
1255 * @rx_ts_offset: Offset of timestamp within prefix
1256 * @rx_buffer_padding: Size of padding at end of RX packet
1257 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1258 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1259 * @option_descriptors: NIC supports TX option descriptors
1260 * @min_interrupt_mode: Lowest capability interrupt mode supported
1261 * from &enum efx_int_mode.
1262 * @max_interrupt_mode: Highest capability interrupt mode supported
1263 * from &enum efx_int_mode.
1264 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1265 * @offload_features: net_device feature flags for protocol offload
1266 * features implemented in hardware
1267 * @mcdi_max_ver: Maximum MCDI version supported
1268 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1269 */
1270 struct efx_nic_type {
1271 bool is_vf;
1272 unsigned int (*mem_bar)(struct efx_nic *efx);
1273 unsigned int (*mem_map_size)(struct efx_nic *efx);
1274 int (*probe)(struct efx_nic *efx);
1275 void (*remove)(struct efx_nic *efx);
1276 int (*init)(struct efx_nic *efx);
1277 int (*dimension_resources)(struct efx_nic *efx);
1278 void (*fini)(struct efx_nic *efx);
1279 void (*monitor)(struct efx_nic *efx);
1280 enum reset_type (*map_reset_reason)(enum reset_type reason);
1281 int (*map_reset_flags)(u32 *flags);
1282 int (*reset)(struct efx_nic *efx, enum reset_type method);
1283 int (*probe_port)(struct efx_nic *efx);
1284 void (*remove_port)(struct efx_nic *efx);
1285 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1286 int (*fini_dmaq)(struct efx_nic *efx);
1287 void (*prepare_flush)(struct efx_nic *efx);
1288 void (*finish_flush)(struct efx_nic *efx);
1289 void (*prepare_flr)(struct efx_nic *efx);
1290 void (*finish_flr)(struct efx_nic *efx);
1291 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1292 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1293 struct rtnl_link_stats64 *core_stats);
1294 void (*start_stats)(struct efx_nic *efx);
1295 void (*pull_stats)(struct efx_nic *efx);
1296 void (*stop_stats)(struct efx_nic *efx);
1297 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1298 void (*push_irq_moderation)(struct efx_channel *channel);
1299 int (*reconfigure_port)(struct efx_nic *efx);
1300 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1301 int (*reconfigure_mac)(struct efx_nic *efx);
1302 bool (*check_mac_fault)(struct efx_nic *efx);
1303 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1304 int (*set_wol)(struct efx_nic *efx, u32 type);
1305 void (*resume_wol)(struct efx_nic *efx);
1306 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1307 int (*test_nvram)(struct efx_nic *efx);
1308 void (*mcdi_request)(struct efx_nic *efx,
1309 const efx_dword_t *hdr, size_t hdr_len,
1310 const efx_dword_t *sdu, size_t sdu_len);
1311 bool (*mcdi_poll_response)(struct efx_nic *efx);
1312 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1313 size_t pdu_offset, size_t pdu_len);
1314 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1315 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1316 void (*irq_enable_master)(struct efx_nic *efx);
1317 int (*irq_test_generate)(struct efx_nic *efx);
1318 void (*irq_disable_non_ev)(struct efx_nic *efx);
1319 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1320 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1321 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1322 void (*tx_init)(struct efx_tx_queue *tx_queue);
1323 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1324 void (*tx_write)(struct efx_tx_queue *tx_queue);
1325 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1326 dma_addr_t dma_addr, unsigned int len);
1327 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1328 const u32 *rx_indir_table, const u8 *key);
1329 int (*rx_pull_rss_config)(struct efx_nic *efx);
1330 int (*rx_push_rss_context_config)(struct efx_nic *efx,
1331 struct efx_rss_context *ctx,
1332 const u32 *rx_indir_table,
1333 const u8 *key);
1334 int (*rx_pull_rss_context_config)(struct efx_nic *efx,
1335 struct efx_rss_context *ctx);
1336 void (*rx_restore_rss_contexts)(struct efx_nic *efx);
1337 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1338 void (*rx_init)(struct efx_rx_queue *rx_queue);
1339 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1340 void (*rx_write)(struct efx_rx_queue *rx_queue);
1341 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1342 int (*ev_probe)(struct efx_channel *channel);
1343 int (*ev_init)(struct efx_channel *channel);
1344 void (*ev_fini)(struct efx_channel *channel);
1345 void (*ev_remove)(struct efx_channel *channel);
1346 int (*ev_process)(struct efx_channel *channel, int quota);
1347 void (*ev_read_ack)(struct efx_channel *channel);
1348 void (*ev_test_generate)(struct efx_channel *channel);
1349 int (*filter_table_probe)(struct efx_nic *efx);
1350 void (*filter_table_restore)(struct efx_nic *efx);
1351 void (*filter_table_remove)(struct efx_nic *efx);
1352 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1353 s32 (*filter_insert)(struct efx_nic *efx,
1354 struct efx_filter_spec *spec, bool replace);
1355 int (*filter_remove_safe)(struct efx_nic *efx,
1356 enum efx_filter_priority priority,
1357 u32 filter_id);
1358 int (*filter_get_safe)(struct efx_nic *efx,
1359 enum efx_filter_priority priority,
1360 u32 filter_id, struct efx_filter_spec *);
1361 int (*filter_clear_rx)(struct efx_nic *efx,
1362 enum efx_filter_priority priority);
1363 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1364 enum efx_filter_priority priority);
1365 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1366 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1367 enum efx_filter_priority priority,
1368 u32 *buf, u32 size);
1369 #ifdef CONFIG_RFS_ACCEL
1370 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1371 unsigned int index);
1372 #endif
1373 #ifdef CONFIG_SFC_MTD
1374 int (*mtd_probe)(struct efx_nic *efx);
1375 void (*mtd_rename)(struct efx_mtd_partition *part);
1376 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1377 size_t *retlen, u8 *buffer);
1378 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1379 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1380 size_t *retlen, const u8 *buffer);
1381 int (*mtd_sync)(struct mtd_info *mtd);
1382 #endif
1383 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1384 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1385 int (*ptp_set_ts_config)(struct efx_nic *efx,
1386 struct hwtstamp_config *init);
1387 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1388 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1389 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1390 int (*get_phys_port_id)(struct efx_nic *efx,
1391 struct netdev_phys_item_id *ppid);
1392 int (*sriov_init)(struct efx_nic *efx);
1393 void (*sriov_fini)(struct efx_nic *efx);
1394 bool (*sriov_wanted)(struct efx_nic *efx);
1395 void (*sriov_reset)(struct efx_nic *efx);
1396 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1397 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1398 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1399 u8 qos);
1400 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1401 bool spoofchk);
1402 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1403 struct ifla_vf_info *ivi);
1404 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1405 int link_state);
1406 int (*vswitching_probe)(struct efx_nic *efx);
1407 int (*vswitching_restore)(struct efx_nic *efx);
1408 void (*vswitching_remove)(struct efx_nic *efx);
1409 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1410 int (*set_mac_address)(struct efx_nic *efx);
1411 u32 (*tso_versions)(struct efx_nic *efx);
1412 int (*udp_tnl_push_ports)(struct efx_nic *efx);
1413 int (*udp_tnl_add_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl);
1414 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1415 int (*udp_tnl_del_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl);
1416
1417 int revision;
1418 unsigned int txd_ptr_tbl_base;
1419 unsigned int rxd_ptr_tbl_base;
1420 unsigned int buf_tbl_base;
1421 unsigned int evq_ptr_tbl_base;
1422 unsigned int evq_rptr_tbl_base;
1423 u64 max_dma_mask;
1424 unsigned int rx_prefix_size;
1425 unsigned int rx_hash_offset;
1426 unsigned int rx_ts_offset;
1427 unsigned int rx_buffer_padding;
1428 bool can_rx_scatter;
1429 bool always_rx_scatter;
1430 bool option_descriptors;
1431 unsigned int min_interrupt_mode;
1432 unsigned int max_interrupt_mode;
1433 unsigned int timer_period_max;
1434 netdev_features_t offload_features;
1435 int mcdi_max_ver;
1436 unsigned int max_rx_ip_filters;
1437 u32 hwtstamp_filters;
1438 unsigned int rx_hash_key_size;
1439 };
1440
1441 /**************************************************************************
1442 *
1443 * Prototypes and inline functions
1444 *
1445 *************************************************************************/
1446
1447 static inline struct efx_channel *
1448 efx_get_channel(struct efx_nic *efx, unsigned index)
1449 {
1450 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1451 return efx->channel[index];
1452 }
1453
1454 /* Iterate over all used channels */
1455 #define efx_for_each_channel(_channel, _efx) \
1456 for (_channel = (_efx)->channel[0]; \
1457 _channel; \
1458 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1459 (_efx)->channel[_channel->channel + 1] : NULL)
1460
1461 /* Iterate over all used channels in reverse */
1462 #define efx_for_each_channel_rev(_channel, _efx) \
1463 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1464 _channel; \
1465 _channel = _channel->channel ? \
1466 (_efx)->channel[_channel->channel - 1] : NULL)
1467
1468 static inline struct efx_tx_queue *
1469 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1470 {
1471 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels ||
1472 type >= EFX_TXQ_TYPES);
1473 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1474 }
1475
1476 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1477 {
1478 return channel->type && channel->type->want_txqs &&
1479 channel->type->want_txqs(channel);
1480 }
1481
1482 static inline struct efx_tx_queue *
1483 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1484 {
1485 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_tx_queues(channel) ||
1486 type >= EFX_TXQ_TYPES);
1487 return &channel->tx_queue[type];
1488 }
1489
1490 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1491 {
1492 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1493 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1494 }
1495
1496 /* Iterate over all TX queues belonging to a channel */
1497 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1498 if (!efx_channel_has_tx_queues(_channel)) \
1499 ; \
1500 else \
1501 for (_tx_queue = (_channel)->tx_queue; \
1502 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1503 efx_tx_queue_used(_tx_queue); \
1504 _tx_queue++)
1505
1506 /* Iterate over all possible TX queues belonging to a channel */
1507 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1508 if (!efx_channel_has_tx_queues(_channel)) \
1509 ; \
1510 else \
1511 for (_tx_queue = (_channel)->tx_queue; \
1512 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1513 _tx_queue++)
1514
1515 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1516 {
1517 return channel->rx_queue.core_index >= 0;
1518 }
1519
1520 static inline struct efx_rx_queue *
1521 efx_channel_get_rx_queue(struct efx_channel *channel)
1522 {
1523 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1524 return &channel->rx_queue;
1525 }
1526
1527 /* Iterate over all RX queues belonging to a channel */
1528 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1529 if (!efx_channel_has_rx_queue(_channel)) \
1530 ; \
1531 else \
1532 for (_rx_queue = &(_channel)->rx_queue; \
1533 _rx_queue; \
1534 _rx_queue = NULL)
1535
1536 static inline struct efx_channel *
1537 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1538 {
1539 return container_of(rx_queue, struct efx_channel, rx_queue);
1540 }
1541
1542 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1543 {
1544 return efx_rx_queue_channel(rx_queue)->channel;
1545 }
1546
1547 /* Returns a pointer to the specified receive buffer in the RX
1548 * descriptor queue.
1549 */
1550 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1551 unsigned int index)
1552 {
1553 return &rx_queue->buffer[index];
1554 }
1555
1556 /**
1557 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1558 *
1559 * This calculates the maximum frame length that will be used for a
1560 * given MTU. The frame length will be equal to the MTU plus a
1561 * constant amount of header space and padding. This is the quantity
1562 * that the net driver will program into the MAC as the maximum frame
1563 * length.
1564 *
1565 * The 10G MAC requires 8-byte alignment on the frame
1566 * length, so we round up to the nearest 8.
1567 *
1568 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1569 * XGMII cycle). If the frame length reaches the maximum value in the
1570 * same cycle, the XMAC can miss the IPG altogether. We work around
1571 * this by adding a further 16 bytes.
1572 */
1573 #define EFX_FRAME_PAD 16
1574 #define EFX_MAX_FRAME_LEN(mtu) \
1575 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1576
1577 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1578 {
1579 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1580 }
1581 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1582 {
1583 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1584 }
1585
1586 /* Get all supported features.
1587 * If a feature is not fixed, it is present in hw_features.
1588 * If a feature is fixed, it does not present in hw_features, but
1589 * always in features.
1590 */
1591 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1592 {
1593 const struct net_device *net_dev = efx->net_dev;
1594
1595 return net_dev->features | net_dev->hw_features;
1596 }
1597
1598 /* Get the current TX queue insert index. */
1599 static inline unsigned int
1600 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1601 {
1602 return tx_queue->insert_count & tx_queue->ptr_mask;
1603 }
1604
1605 /* Get a TX buffer. */
1606 static inline struct efx_tx_buffer *
1607 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1608 {
1609 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1610 }
1611
1612 /* Get a TX buffer, checking it's not currently in use. */
1613 static inline struct efx_tx_buffer *
1614 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1615 {
1616 struct efx_tx_buffer *buffer =
1617 __efx_tx_queue_get_insert_buffer(tx_queue);
1618
1619 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1620 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1621 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1622
1623 return buffer;
1624 }
1625
1626 #endif /* EFX_NET_DRIVER_H */