root/drivers/net/ethernet/sfc/falcon/farch_regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2012 Solarflare Communications Inc.
   6  */
   7 
   8 #ifndef EF4_FARCH_REGS_H
   9 #define EF4_FARCH_REGS_H
  10 
  11 /*
  12  * Falcon hardware architecture definitions have a name prefix following
  13  * the format:
  14  *
  15  *     F<type>_<min-rev><max-rev>_
  16  *
  17  * The following <type> strings are used:
  18  *
  19  *             MMIO register  MC register  Host memory structure
  20  * -------------------------------------------------------------
  21  * Address     R              MCR
  22  * Bitfield    RF             MCRF         SF
  23  * Enumerator  FE             MCFE         SE
  24  *
  25  * <min-rev> is the first revision to which the definition applies:
  26  *
  27  *     A: Falcon A1 (SFC4000AB)
  28  *     B: Falcon B0 (SFC4000BA)
  29  *     C: Siena A0 (SFL9021AA)
  30  *
  31  * If the definition has been changed or removed in later revisions
  32  * then <max-rev> is the last revision to which the definition applies;
  33  * otherwise it is "Z".
  34  */
  35 
  36 /**************************************************************************
  37  *
  38  * Falcon/Siena registers and descriptors
  39  *
  40  **************************************************************************
  41  */
  42 
  43 /* ADR_REGION_REG: Address region register */
  44 #define FR_AZ_ADR_REGION 0x00000000
  45 #define FRF_AZ_ADR_REGION3_LBN 96
  46 #define FRF_AZ_ADR_REGION3_WIDTH 18
  47 #define FRF_AZ_ADR_REGION2_LBN 64
  48 #define FRF_AZ_ADR_REGION2_WIDTH 18
  49 #define FRF_AZ_ADR_REGION1_LBN 32
  50 #define FRF_AZ_ADR_REGION1_WIDTH 18
  51 #define FRF_AZ_ADR_REGION0_LBN 0
  52 #define FRF_AZ_ADR_REGION0_WIDTH 18
  53 
  54 /* INT_EN_REG_KER: Kernel driver Interrupt enable register */
  55 #define FR_AZ_INT_EN_KER 0x00000010
  56 #define FRF_AZ_KER_INT_LEVE_SEL_LBN 8
  57 #define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
  58 #define FRF_AZ_KER_INT_CHAR_LBN 4
  59 #define FRF_AZ_KER_INT_CHAR_WIDTH 1
  60 #define FRF_AZ_KER_INT_KER_LBN 3
  61 #define FRF_AZ_KER_INT_KER_WIDTH 1
  62 #define FRF_AZ_DRV_INT_EN_KER_LBN 0
  63 #define FRF_AZ_DRV_INT_EN_KER_WIDTH 1
  64 
  65 /* INT_EN_REG_CHAR: Char Driver interrupt enable register */
  66 #define FR_BZ_INT_EN_CHAR 0x00000020
  67 #define FRF_BZ_CHAR_INT_LEVE_SEL_LBN 8
  68 #define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 6
  69 #define FRF_BZ_CHAR_INT_CHAR_LBN 4
  70 #define FRF_BZ_CHAR_INT_CHAR_WIDTH 1
  71 #define FRF_BZ_CHAR_INT_KER_LBN 3
  72 #define FRF_BZ_CHAR_INT_KER_WIDTH 1
  73 #define FRF_BZ_DRV_INT_EN_CHAR_LBN 0
  74 #define FRF_BZ_DRV_INT_EN_CHAR_WIDTH 1
  75 
  76 /* INT_ADR_REG_KER: Interrupt host address for Kernel driver */
  77 #define FR_AZ_INT_ADR_KER 0x00000030
  78 #define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
  79 #define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
  80 #define FRF_AZ_INT_ADR_KER_LBN 0
  81 #define FRF_AZ_INT_ADR_KER_WIDTH 64
  82 
  83 /* INT_ADR_REG_CHAR: Interrupt host address for Char driver */
  84 #define FR_BZ_INT_ADR_CHAR 0x00000040
  85 #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 64
  86 #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
  87 #define FRF_BZ_INT_ADR_CHAR_LBN 0
  88 #define FRF_BZ_INT_ADR_CHAR_WIDTH 64
  89 
  90 /* INT_ACK_KER: Kernel interrupt acknowledge register */
  91 #define FR_AA_INT_ACK_KER 0x00000050
  92 #define FRF_AA_INT_ACK_KER_FIELD_LBN 0
  93 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
  94 
  95 /* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */
  96 #define FR_BZ_INT_ISR0 0x00000090
  97 #define FRF_BZ_INT_ISR_REG_LBN 0
  98 #define FRF_BZ_INT_ISR_REG_WIDTH 64
  99 
 100 /* HW_INIT_REG: Hardware initialization register */
 101 #define FR_AZ_HW_INIT 0x000000c0
 102 #define FRF_BB_BDMRD_CPLF_FULL_LBN 124
 103 #define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
 104 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
 105 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
 106 #define FRF_CZ_TX_MRG_TAGS_LBN 120
 107 #define FRF_CZ_TX_MRG_TAGS_WIDTH 1
 108 #define FRF_AB_TRGT_MASK_ALL_LBN 100
 109 #define FRF_AB_TRGT_MASK_ALL_WIDTH 1
 110 #define FRF_AZ_DOORBELL_DROP_LBN 92
 111 #define FRF_AZ_DOORBELL_DROP_WIDTH 8
 112 #define FRF_AB_TX_RREQ_MASK_EN_LBN 76
 113 #define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
 114 #define FRF_AB_PE_EIDLE_DIS_LBN 75
 115 #define FRF_AB_PE_EIDLE_DIS_WIDTH 1
 116 #define FRF_AA_FC_BLOCKING_EN_LBN 45
 117 #define FRF_AA_FC_BLOCKING_EN_WIDTH 1
 118 #define FRF_BZ_B2B_REQ_EN_LBN 45
 119 #define FRF_BZ_B2B_REQ_EN_WIDTH 1
 120 #define FRF_AA_B2B_REQ_EN_LBN 44
 121 #define FRF_AA_B2B_REQ_EN_WIDTH 1
 122 #define FRF_BB_FC_BLOCKING_EN_LBN 44
 123 #define FRF_BB_FC_BLOCKING_EN_WIDTH 1
 124 #define FRF_AZ_POST_WR_MASK_LBN 40
 125 #define FRF_AZ_POST_WR_MASK_WIDTH 4
 126 #define FRF_AZ_TLP_TC_LBN 34
 127 #define FRF_AZ_TLP_TC_WIDTH 3
 128 #define FRF_AZ_TLP_ATTR_LBN 32
 129 #define FRF_AZ_TLP_ATTR_WIDTH 2
 130 #define FRF_AB_INTB_VEC_LBN 24
 131 #define FRF_AB_INTB_VEC_WIDTH 5
 132 #define FRF_AB_INTA_VEC_LBN 16
 133 #define FRF_AB_INTA_VEC_WIDTH 5
 134 #define FRF_AZ_WD_TIMER_LBN 8
 135 #define FRF_AZ_WD_TIMER_WIDTH 8
 136 #define FRF_AZ_US_DISABLE_LBN 5
 137 #define FRF_AZ_US_DISABLE_WIDTH 1
 138 #define FRF_AZ_TLP_EP_LBN 4
 139 #define FRF_AZ_TLP_EP_WIDTH 1
 140 #define FRF_AZ_ATTR_SEL_LBN 3
 141 #define FRF_AZ_ATTR_SEL_WIDTH 1
 142 #define FRF_AZ_TD_SEL_LBN 1
 143 #define FRF_AZ_TD_SEL_WIDTH 1
 144 #define FRF_AZ_TLP_TD_LBN 0
 145 #define FRF_AZ_TLP_TD_WIDTH 1
 146 
 147 /* EE_SPI_HCMD_REG: SPI host command register */
 148 #define FR_AB_EE_SPI_HCMD 0x00000100
 149 #define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
 150 #define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
 151 #define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
 152 #define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
 153 #define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
 154 #define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
 155 #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
 156 #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
 157 #define FRF_AB_EE_SPI_HCMD_READ_LBN 15
 158 #define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
 159 #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
 160 #define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
 161 #define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
 162 #define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
 163 #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
 164 #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
 165 
 166 /* USR_EV_CFG: User Level Event Configuration register */
 167 #define FR_CZ_USR_EV_CFG 0x00000100
 168 #define FRF_CZ_USREV_DIS_LBN 16
 169 #define FRF_CZ_USREV_DIS_WIDTH 1
 170 #define FRF_CZ_DFLT_EVQ_LBN 0
 171 #define FRF_CZ_DFLT_EVQ_WIDTH 10
 172 
 173 /* EE_SPI_HADR_REG: SPI host address register */
 174 #define FR_AB_EE_SPI_HADR 0x00000110
 175 #define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
 176 #define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
 177 #define FRF_AB_EE_SPI_HADR_ADR_LBN 0
 178 #define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
 179 
 180 /* EE_SPI_HDATA_REG: SPI host data register */
 181 #define FR_AB_EE_SPI_HDATA 0x00000120
 182 #define FRF_AB_EE_SPI_HDATA3_LBN 96
 183 #define FRF_AB_EE_SPI_HDATA3_WIDTH 32
 184 #define FRF_AB_EE_SPI_HDATA2_LBN 64
 185 #define FRF_AB_EE_SPI_HDATA2_WIDTH 32
 186 #define FRF_AB_EE_SPI_HDATA1_LBN 32
 187 #define FRF_AB_EE_SPI_HDATA1_WIDTH 32
 188 #define FRF_AB_EE_SPI_HDATA0_LBN 0
 189 #define FRF_AB_EE_SPI_HDATA0_WIDTH 32
 190 
 191 /* EE_BASE_PAGE_REG: Expansion ROM base mirror register */
 192 #define FR_AB_EE_BASE_PAGE 0x00000130
 193 #define FRF_AB_EE_EXPROM_MASK_LBN 16
 194 #define FRF_AB_EE_EXPROM_MASK_WIDTH 13
 195 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
 196 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
 197 
 198 /* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */
 199 #define FR_AB_EE_VPD_CFG0 0x00000140
 200 #define FRF_AB_EE_SF_FASTRD_EN_LBN 127
 201 #define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
 202 #define FRF_AB_EE_SF_CLOCK_DIV_LBN 120
 203 #define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
 204 #define FRF_AB_EE_VPD_WIP_POLL_LBN 119
 205 #define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
 206 #define FRF_AB_EE_EE_CLOCK_DIV_LBN 112
 207 #define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
 208 #define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
 209 #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
 210 #define FRF_AB_EE_VPDW_LENGTH_LBN 80
 211 #define FRF_AB_EE_VPDW_LENGTH_WIDTH 15
 212 #define FRF_AB_EE_VPDW_BASE_LBN 64
 213 #define FRF_AB_EE_VPDW_BASE_WIDTH 15
 214 #define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
 215 #define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
 216 #define FRF_AB_EE_VPD_BASE_LBN 32
 217 #define FRF_AB_EE_VPD_BASE_WIDTH 24
 218 #define FRF_AB_EE_VPD_LENGTH_LBN 16
 219 #define FRF_AB_EE_VPD_LENGTH_WIDTH 15
 220 #define FRF_AB_EE_VPD_AD_SIZE_LBN 8
 221 #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
 222 #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
 223 #define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
 224 #define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
 225 #define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
 226 #define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
 227 #define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
 228 #define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
 229 #define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
 230 #define FRF_AB_EE_VPD_EN_LBN 0
 231 #define FRF_AB_EE_VPD_EN_WIDTH 1
 232 
 233 /* EE_VPD_SW_CNTL_REG: VPD access SW control register */
 234 #define FR_AB_EE_VPD_SW_CNTL 0x00000150
 235 #define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
 236 #define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
 237 #define FRF_AB_EE_VPD_CYC_WRITE_LBN 28
 238 #define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
 239 #define FRF_AB_EE_VPD_CYC_ADR_LBN 0
 240 #define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
 241 
 242 /* EE_VPD_SW_DATA_REG: VPD access SW data register */
 243 #define FR_AB_EE_VPD_SW_DATA 0x00000160
 244 #define FRF_AB_EE_VPD_CYC_DAT_LBN 0
 245 #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
 246 
 247 /* PBMX_DBG_IADDR_REG: Capture Module address register */
 248 #define FR_CZ_PBMX_DBG_IADDR 0x000001f0
 249 #define FRF_CZ_PBMX_DBG_IADDR_LBN 0
 250 #define FRF_CZ_PBMX_DBG_IADDR_WIDTH 32
 251 
 252 /* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */
 253 #define FR_BB_PCIE_CORE_INDIRECT 0x000001f0
 254 #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
 255 #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
 256 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
 257 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
 258 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
 259 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
 260 
 261 /* PBMX_DBG_IDATA_REG: Capture Module data register */
 262 #define FR_CZ_PBMX_DBG_IDATA 0x000001f8
 263 #define FRF_CZ_PBMX_DBG_IDATA_LBN 0
 264 #define FRF_CZ_PBMX_DBG_IDATA_WIDTH 64
 265 
 266 /* NIC_STAT_REG: NIC status register */
 267 #define FR_AB_NIC_STAT 0x00000200
 268 #define FRF_BB_AER_DIS_LBN 34
 269 #define FRF_BB_AER_DIS_WIDTH 1
 270 #define FRF_BB_EE_STRAP_EN_LBN 31
 271 #define FRF_BB_EE_STRAP_EN_WIDTH 1
 272 #define FRF_BB_EE_STRAP_LBN 24
 273 #define FRF_BB_EE_STRAP_WIDTH 4
 274 #define FRF_BB_REVISION_ID_LBN 17
 275 #define FRF_BB_REVISION_ID_WIDTH 7
 276 #define FRF_AB_ONCHIP_SRAM_LBN 16
 277 #define FRF_AB_ONCHIP_SRAM_WIDTH 1
 278 #define FRF_AB_SF_PRST_LBN 9
 279 #define FRF_AB_SF_PRST_WIDTH 1
 280 #define FRF_AB_EE_PRST_LBN 8
 281 #define FRF_AB_EE_PRST_WIDTH 1
 282 #define FRF_AB_ATE_MODE_LBN 3
 283 #define FRF_AB_ATE_MODE_WIDTH 1
 284 #define FRF_AB_STRAP_PINS_LBN 0
 285 #define FRF_AB_STRAP_PINS_WIDTH 3
 286 
 287 /* GPIO_CTL_REG: GPIO control register */
 288 #define FR_AB_GPIO_CTL 0x00000210
 289 #define FRF_AB_GPIO_OUT3_LBN 112
 290 #define FRF_AB_GPIO_OUT3_WIDTH 16
 291 #define FRF_AB_GPIO_IN3_LBN 104
 292 #define FRF_AB_GPIO_IN3_WIDTH 8
 293 #define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96
 294 #define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8
 295 #define FRF_AB_GPIO_OUT2_LBN 80
 296 #define FRF_AB_GPIO_OUT2_WIDTH 16
 297 #define FRF_AB_GPIO_IN2_LBN 72
 298 #define FRF_AB_GPIO_IN2_WIDTH 8
 299 #define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64
 300 #define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8
 301 #define FRF_AB_GPIO15_OEN_LBN 63
 302 #define FRF_AB_GPIO15_OEN_WIDTH 1
 303 #define FRF_AB_GPIO14_OEN_LBN 62
 304 #define FRF_AB_GPIO14_OEN_WIDTH 1
 305 #define FRF_AB_GPIO13_OEN_LBN 61
 306 #define FRF_AB_GPIO13_OEN_WIDTH 1
 307 #define FRF_AB_GPIO12_OEN_LBN 60
 308 #define FRF_AB_GPIO12_OEN_WIDTH 1
 309 #define FRF_AB_GPIO11_OEN_LBN 59
 310 #define FRF_AB_GPIO11_OEN_WIDTH 1
 311 #define FRF_AB_GPIO10_OEN_LBN 58
 312 #define FRF_AB_GPIO10_OEN_WIDTH 1
 313 #define FRF_AB_GPIO9_OEN_LBN 57
 314 #define FRF_AB_GPIO9_OEN_WIDTH 1
 315 #define FRF_AB_GPIO8_OEN_LBN 56
 316 #define FRF_AB_GPIO8_OEN_WIDTH 1
 317 #define FRF_AB_GPIO15_OUT_LBN 55
 318 #define FRF_AB_GPIO15_OUT_WIDTH 1
 319 #define FRF_AB_GPIO14_OUT_LBN 54
 320 #define FRF_AB_GPIO14_OUT_WIDTH 1
 321 #define FRF_AB_GPIO13_OUT_LBN 53
 322 #define FRF_AB_GPIO13_OUT_WIDTH 1
 323 #define FRF_AB_GPIO12_OUT_LBN 52
 324 #define FRF_AB_GPIO12_OUT_WIDTH 1
 325 #define FRF_AB_GPIO11_OUT_LBN 51
 326 #define FRF_AB_GPIO11_OUT_WIDTH 1
 327 #define FRF_AB_GPIO10_OUT_LBN 50
 328 #define FRF_AB_GPIO10_OUT_WIDTH 1
 329 #define FRF_AB_GPIO9_OUT_LBN 49
 330 #define FRF_AB_GPIO9_OUT_WIDTH 1
 331 #define FRF_AB_GPIO8_OUT_LBN 48
 332 #define FRF_AB_GPIO8_OUT_WIDTH 1
 333 #define FRF_AB_GPIO15_IN_LBN 47
 334 #define FRF_AB_GPIO15_IN_WIDTH 1
 335 #define FRF_AB_GPIO14_IN_LBN 46
 336 #define FRF_AB_GPIO14_IN_WIDTH 1
 337 #define FRF_AB_GPIO13_IN_LBN 45
 338 #define FRF_AB_GPIO13_IN_WIDTH 1
 339 #define FRF_AB_GPIO12_IN_LBN 44
 340 #define FRF_AB_GPIO12_IN_WIDTH 1
 341 #define FRF_AB_GPIO11_IN_LBN 43
 342 #define FRF_AB_GPIO11_IN_WIDTH 1
 343 #define FRF_AB_GPIO10_IN_LBN 42
 344 #define FRF_AB_GPIO10_IN_WIDTH 1
 345 #define FRF_AB_GPIO9_IN_LBN 41
 346 #define FRF_AB_GPIO9_IN_WIDTH 1
 347 #define FRF_AB_GPIO8_IN_LBN 40
 348 #define FRF_AB_GPIO8_IN_WIDTH 1
 349 #define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
 350 #define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
 351 #define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
 352 #define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
 353 #define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
 354 #define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
 355 #define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
 356 #define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
 357 #define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
 358 #define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
 359 #define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
 360 #define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
 361 #define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
 362 #define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
 363 #define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
 364 #define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
 365 #define FRF_AB_CLK156_OUT_EN_LBN 31
 366 #define FRF_AB_CLK156_OUT_EN_WIDTH 1
 367 #define FRF_AB_USE_NIC_CLK_LBN 30
 368 #define FRF_AB_USE_NIC_CLK_WIDTH 1
 369 #define FRF_AB_GPIO5_OEN_LBN 29
 370 #define FRF_AB_GPIO5_OEN_WIDTH 1
 371 #define FRF_AB_GPIO4_OEN_LBN 28
 372 #define FRF_AB_GPIO4_OEN_WIDTH 1
 373 #define FRF_AB_GPIO3_OEN_LBN 27
 374 #define FRF_AB_GPIO3_OEN_WIDTH 1
 375 #define FRF_AB_GPIO2_OEN_LBN 26
 376 #define FRF_AB_GPIO2_OEN_WIDTH 1
 377 #define FRF_AB_GPIO1_OEN_LBN 25
 378 #define FRF_AB_GPIO1_OEN_WIDTH 1
 379 #define FRF_AB_GPIO0_OEN_LBN 24
 380 #define FRF_AB_GPIO0_OEN_WIDTH 1
 381 #define FRF_AB_GPIO7_OUT_LBN 23
 382 #define FRF_AB_GPIO7_OUT_WIDTH 1
 383 #define FRF_AB_GPIO6_OUT_LBN 22
 384 #define FRF_AB_GPIO6_OUT_WIDTH 1
 385 #define FRF_AB_GPIO5_OUT_LBN 21
 386 #define FRF_AB_GPIO5_OUT_WIDTH 1
 387 #define FRF_AB_GPIO4_OUT_LBN 20
 388 #define FRF_AB_GPIO4_OUT_WIDTH 1
 389 #define FRF_AB_GPIO3_OUT_LBN 19
 390 #define FRF_AB_GPIO3_OUT_WIDTH 1
 391 #define FRF_AB_GPIO2_OUT_LBN 18
 392 #define FRF_AB_GPIO2_OUT_WIDTH 1
 393 #define FRF_AB_GPIO1_OUT_LBN 17
 394 #define FRF_AB_GPIO1_OUT_WIDTH 1
 395 #define FRF_AB_GPIO0_OUT_LBN 16
 396 #define FRF_AB_GPIO0_OUT_WIDTH 1
 397 #define FRF_AB_GPIO7_IN_LBN 15
 398 #define FRF_AB_GPIO7_IN_WIDTH 1
 399 #define FRF_AB_GPIO6_IN_LBN 14
 400 #define FRF_AB_GPIO6_IN_WIDTH 1
 401 #define FRF_AB_GPIO5_IN_LBN 13
 402 #define FRF_AB_GPIO5_IN_WIDTH 1
 403 #define FRF_AB_GPIO4_IN_LBN 12
 404 #define FRF_AB_GPIO4_IN_WIDTH 1
 405 #define FRF_AB_GPIO3_IN_LBN 11
 406 #define FRF_AB_GPIO3_IN_WIDTH 1
 407 #define FRF_AB_GPIO2_IN_LBN 10
 408 #define FRF_AB_GPIO2_IN_WIDTH 1
 409 #define FRF_AB_GPIO1_IN_LBN 9
 410 #define FRF_AB_GPIO1_IN_WIDTH 1
 411 #define FRF_AB_GPIO0_IN_LBN 8
 412 #define FRF_AB_GPIO0_IN_WIDTH 1
 413 #define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7
 414 #define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1
 415 #define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6
 416 #define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1
 417 #define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
 418 #define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
 419 #define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
 420 #define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
 421 #define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
 422 #define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
 423 #define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
 424 #define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
 425 #define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
 426 #define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
 427 #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
 428 #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
 429 
 430 /* GLB_CTL_REG: Global control register */
 431 #define FR_AB_GLB_CTL 0x00000220
 432 #define FRF_AB_EXT_PHY_RST_CTL_LBN 63
 433 #define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
 434 #define FRF_AB_XAUI_SD_RST_CTL_LBN 62
 435 #define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
 436 #define FRF_AB_PCIE_SD_RST_CTL_LBN 61
 437 #define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
 438 #define FRF_AA_PCIX_RST_CTL_LBN 60
 439 #define FRF_AA_PCIX_RST_CTL_WIDTH 1
 440 #define FRF_BB_BIU_RST_CTL_LBN 60
 441 #define FRF_BB_BIU_RST_CTL_WIDTH 1
 442 #define FRF_AB_PCIE_STKY_RST_CTL_LBN 59
 443 #define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
 444 #define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
 445 #define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
 446 #define FRF_AB_PCIE_CORE_RST_CTL_LBN 57
 447 #define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
 448 #define FRF_AB_XGRX_RST_CTL_LBN 56
 449 #define FRF_AB_XGRX_RST_CTL_WIDTH 1
 450 #define FRF_AB_XGTX_RST_CTL_LBN 55
 451 #define FRF_AB_XGTX_RST_CTL_WIDTH 1
 452 #define FRF_AB_EM_RST_CTL_LBN 54
 453 #define FRF_AB_EM_RST_CTL_WIDTH 1
 454 #define FRF_AB_EV_RST_CTL_LBN 53
 455 #define FRF_AB_EV_RST_CTL_WIDTH 1
 456 #define FRF_AB_SR_RST_CTL_LBN 52
 457 #define FRF_AB_SR_RST_CTL_WIDTH 1
 458 #define FRF_AB_RX_RST_CTL_LBN 51
 459 #define FRF_AB_RX_RST_CTL_WIDTH 1
 460 #define FRF_AB_TX_RST_CTL_LBN 50
 461 #define FRF_AB_TX_RST_CTL_WIDTH 1
 462 #define FRF_AB_EE_RST_CTL_LBN 49
 463 #define FRF_AB_EE_RST_CTL_WIDTH 1
 464 #define FRF_AB_CS_RST_CTL_LBN 48
 465 #define FRF_AB_CS_RST_CTL_WIDTH 1
 466 #define FRF_AB_HOT_RST_CTL_LBN 40
 467 #define FRF_AB_HOT_RST_CTL_WIDTH 2
 468 #define FRF_AB_RST_EXT_PHY_LBN 31
 469 #define FRF_AB_RST_EXT_PHY_WIDTH 1
 470 #define FRF_AB_RST_XAUI_SD_LBN 30
 471 #define FRF_AB_RST_XAUI_SD_WIDTH 1
 472 #define FRF_AB_RST_PCIE_SD_LBN 29
 473 #define FRF_AB_RST_PCIE_SD_WIDTH 1
 474 #define FRF_AA_RST_PCIX_LBN 28
 475 #define FRF_AA_RST_PCIX_WIDTH 1
 476 #define FRF_BB_RST_BIU_LBN 28
 477 #define FRF_BB_RST_BIU_WIDTH 1
 478 #define FRF_AB_RST_PCIE_STKY_LBN 27
 479 #define FRF_AB_RST_PCIE_STKY_WIDTH 1
 480 #define FRF_AB_RST_PCIE_NSTKY_LBN 26
 481 #define FRF_AB_RST_PCIE_NSTKY_WIDTH 1
 482 #define FRF_AB_RST_PCIE_CORE_LBN 25
 483 #define FRF_AB_RST_PCIE_CORE_WIDTH 1
 484 #define FRF_AB_RST_XGRX_LBN 24
 485 #define FRF_AB_RST_XGRX_WIDTH 1
 486 #define FRF_AB_RST_XGTX_LBN 23
 487 #define FRF_AB_RST_XGTX_WIDTH 1
 488 #define FRF_AB_RST_EM_LBN 22
 489 #define FRF_AB_RST_EM_WIDTH 1
 490 #define FRF_AB_RST_EV_LBN 21
 491 #define FRF_AB_RST_EV_WIDTH 1
 492 #define FRF_AB_RST_SR_LBN 20
 493 #define FRF_AB_RST_SR_WIDTH 1
 494 #define FRF_AB_RST_RX_LBN 19
 495 #define FRF_AB_RST_RX_WIDTH 1
 496 #define FRF_AB_RST_TX_LBN 18
 497 #define FRF_AB_RST_TX_WIDTH 1
 498 #define FRF_AB_RST_SF_LBN 17
 499 #define FRF_AB_RST_SF_WIDTH 1
 500 #define FRF_AB_RST_CS_LBN 16
 501 #define FRF_AB_RST_CS_WIDTH 1
 502 #define FRF_AB_INT_RST_DUR_LBN 4
 503 #define FRF_AB_INT_RST_DUR_WIDTH 3
 504 #define FRF_AB_EXT_PHY_RST_DUR_LBN 1
 505 #define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
 506 #define FFE_AB_EXT_PHY_RST_DUR_10240US 7
 507 #define FFE_AB_EXT_PHY_RST_DUR_5120US 6
 508 #define FFE_AB_EXT_PHY_RST_DUR_2560US 5
 509 #define FFE_AB_EXT_PHY_RST_DUR_1280US 4
 510 #define FFE_AB_EXT_PHY_RST_DUR_640US 3
 511 #define FFE_AB_EXT_PHY_RST_DUR_320US 2
 512 #define FFE_AB_EXT_PHY_RST_DUR_160US 1
 513 #define FFE_AB_EXT_PHY_RST_DUR_80US 0
 514 #define FRF_AB_SWRST_LBN 0
 515 #define FRF_AB_SWRST_WIDTH 1
 516 
 517 /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
 518 #define FR_AZ_FATAL_INTR_KER 0x00000230
 519 #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
 520 #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
 521 #define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
 522 #define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
 523 #define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
 524 #define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
 525 #define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
 526 #define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
 527 #define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
 528 #define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
 529 #define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
 530 #define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
 531 #define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
 532 #define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
 533 #define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
 534 #define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
 535 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
 536 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
 537 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
 538 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
 539 #define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
 540 #define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
 541 #define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
 542 #define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
 543 #define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
 544 #define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
 545 #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
 546 #define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
 547 #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
 548 #define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
 549 #define FRF_AB_PCI_BUSERR_INT_KER_LBN 11
 550 #define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
 551 #define FRF_CZ_MBU_PERR_INT_KER_LBN 11
 552 #define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
 553 #define FRF_AZ_SRAM_OOB_INT_KER_LBN 10
 554 #define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
 555 #define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
 556 #define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
 557 #define FRF_AZ_MEM_PERR_INT_KER_LBN 8
 558 #define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
 559 #define FRF_AZ_RBUF_OWN_INT_KER_LBN 7
 560 #define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
 561 #define FRF_AZ_TBUF_OWN_INT_KER_LBN 6
 562 #define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
 563 #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
 564 #define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
 565 #define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
 566 #define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
 567 #define FRF_AZ_EVQ_OWN_INT_KER_LBN 3
 568 #define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
 569 #define FRF_AZ_EVF_OFLO_INT_KER_LBN 2
 570 #define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
 571 #define FRF_AZ_ILL_ADR_INT_KER_LBN 1
 572 #define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
 573 #define FRF_AZ_SRM_PERR_INT_KER_LBN 0
 574 #define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
 575 
 576 /* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */
 577 #define FR_BZ_FATAL_INTR_CHAR 0x00000240
 578 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
 579 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
 580 #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43
 581 #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
 582 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
 583 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
 584 #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42
 585 #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
 586 #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41
 587 #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
 588 #define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40
 589 #define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
 590 #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39
 591 #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
 592 #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38
 593 #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
 594 #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
 595 #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
 596 #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
 597 #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
 598 #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35
 599 #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
 600 #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34
 601 #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
 602 #define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33
 603 #define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
 604 #define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32
 605 #define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
 606 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
 607 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
 608 #define FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11
 609 #define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1
 610 #define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
 611 #define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
 612 #define FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10
 613 #define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1
 614 #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9
 615 #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
 616 #define FRF_BZ_MEM_PERR_INT_CHAR_LBN 8
 617 #define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1
 618 #define FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7
 619 #define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1
 620 #define FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6
 621 #define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1
 622 #define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5
 623 #define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
 624 #define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4
 625 #define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
 626 #define FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3
 627 #define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1
 628 #define FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2
 629 #define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1
 630 #define FRF_BZ_ILL_ADR_INT_CHAR_LBN 1
 631 #define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1
 632 #define FRF_BZ_SRM_PERR_INT_CHAR_LBN 0
 633 #define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1
 634 
 635 /* DP_CTRL_REG: Datapath control register */
 636 #define FR_BZ_DP_CTRL 0x00000250
 637 #define FRF_BZ_FLS_EVQ_ID_LBN 0
 638 #define FRF_BZ_FLS_EVQ_ID_WIDTH 12
 639 
 640 /* MEM_STAT_REG: Memory status register */
 641 #define FR_AZ_MEM_STAT 0x00000260
 642 #define FRF_AB_MEM_PERR_VEC_LBN 53
 643 #define FRF_AB_MEM_PERR_VEC_WIDTH 38
 644 #define FRF_AB_MBIST_CORR_LBN 38
 645 #define FRF_AB_MBIST_CORR_WIDTH 15
 646 #define FRF_AB_MBIST_ERR_LBN 0
 647 #define FRF_AB_MBIST_ERR_WIDTH 40
 648 #define FRF_CZ_MEM_PERR_VEC_LBN 0
 649 #define FRF_CZ_MEM_PERR_VEC_WIDTH 35
 650 
 651 /* CS_DEBUG_REG: Debug register */
 652 #define FR_AZ_CS_DEBUG 0x00000270
 653 #define FRF_AB_GLB_DEBUG2_SEL_LBN 50
 654 #define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
 655 #define FRF_AB_DEBUG_BLK_SEL2_LBN 47
 656 #define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
 657 #define FRF_AB_DEBUG_BLK_SEL1_LBN 44
 658 #define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
 659 #define FRF_AB_DEBUG_BLK_SEL0_LBN 41
 660 #define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
 661 #define FRF_CZ_CS_PORT_NUM_LBN 40
 662 #define FRF_CZ_CS_PORT_NUM_WIDTH 2
 663 #define FRF_AB_MISC_DEBUG_ADDR_LBN 36
 664 #define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
 665 #define FRF_AB_SERDES_DEBUG_ADDR_LBN 31
 666 #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
 667 #define FRF_CZ_CS_PORT_FPE_LBN 1
 668 #define FRF_CZ_CS_PORT_FPE_WIDTH 35
 669 #define FRF_AB_EM_DEBUG_ADDR_LBN 26
 670 #define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
 671 #define FRF_AB_SR_DEBUG_ADDR_LBN 21
 672 #define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
 673 #define FRF_AB_EV_DEBUG_ADDR_LBN 16
 674 #define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
 675 #define FRF_AB_RX_DEBUG_ADDR_LBN 11
 676 #define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
 677 #define FRF_AB_TX_DEBUG_ADDR_LBN 6
 678 #define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
 679 #define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
 680 #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
 681 #define FRF_AZ_CS_DEBUG_EN_LBN 0
 682 #define FRF_AZ_CS_DEBUG_EN_WIDTH 1
 683 
 684 /* DRIVER_REG: Driver scratch register [0-7] */
 685 #define FR_AZ_DRIVER 0x00000280
 686 #define FR_AZ_DRIVER_STEP 16
 687 #define FR_AZ_DRIVER_ROWS 8
 688 #define FRF_AZ_DRIVER_DW0_LBN 0
 689 #define FRF_AZ_DRIVER_DW0_WIDTH 32
 690 
 691 /* ALTERA_BUILD_REG: Altera build register */
 692 #define FR_AZ_ALTERA_BUILD 0x00000300
 693 #define FRF_AZ_ALTERA_BUILD_VER_LBN 0
 694 #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
 695 
 696 /* CSR_SPARE_REG: Spare register */
 697 #define FR_AZ_CSR_SPARE 0x00000310
 698 #define FRF_AB_MEM_PERR_EN_LBN 64
 699 #define FRF_AB_MEM_PERR_EN_WIDTH 38
 700 #define FRF_CZ_MEM_PERR_EN_LBN 64
 701 #define FRF_CZ_MEM_PERR_EN_WIDTH 35
 702 #define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72
 703 #define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2
 704 #define FRF_AZ_CSR_SPARE_BITS_LBN 0
 705 #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
 706 
 707 /* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */
 708 #define FR_AB_PCIE_SD_CTL0123 0x00000320
 709 #define FRF_AB_PCIE_TESTSIG_H_LBN 96
 710 #define FRF_AB_PCIE_TESTSIG_H_WIDTH 19
 711 #define FRF_AB_PCIE_TESTSIG_L_LBN 64
 712 #define FRF_AB_PCIE_TESTSIG_L_WIDTH 19
 713 #define FRF_AB_PCIE_OFFSET_LBN 56
 714 #define FRF_AB_PCIE_OFFSET_WIDTH 8
 715 #define FRF_AB_PCIE_OFFSETEN_H_LBN 55
 716 #define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
 717 #define FRF_AB_PCIE_OFFSETEN_L_LBN 54
 718 #define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
 719 #define FRF_AB_PCIE_HIVMODE_H_LBN 53
 720 #define FRF_AB_PCIE_HIVMODE_H_WIDTH 1
 721 #define FRF_AB_PCIE_HIVMODE_L_LBN 52
 722 #define FRF_AB_PCIE_HIVMODE_L_WIDTH 1
 723 #define FRF_AB_PCIE_PARRESET_H_LBN 51
 724 #define FRF_AB_PCIE_PARRESET_H_WIDTH 1
 725 #define FRF_AB_PCIE_PARRESET_L_LBN 50
 726 #define FRF_AB_PCIE_PARRESET_L_WIDTH 1
 727 #define FRF_AB_PCIE_LPBKWDRV_H_LBN 49
 728 #define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
 729 #define FRF_AB_PCIE_LPBKWDRV_L_LBN 48
 730 #define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
 731 #define FRF_AB_PCIE_LPBK_LBN 40
 732 #define FRF_AB_PCIE_LPBK_WIDTH 8
 733 #define FRF_AB_PCIE_PARLPBK_LBN 32
 734 #define FRF_AB_PCIE_PARLPBK_WIDTH 8
 735 #define FRF_AB_PCIE_RXTERMADJ_H_LBN 30
 736 #define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
 737 #define FRF_AB_PCIE_RXTERMADJ_L_LBN 28
 738 #define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
 739 #define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
 740 #define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
 741 #define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
 742 #define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
 743 #define FRF_AB_PCIE_TXTERMADJ_H_LBN 26
 744 #define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
 745 #define FRF_AB_PCIE_TXTERMADJ_L_LBN 24
 746 #define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
 747 #define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
 748 #define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
 749 #define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
 750 #define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
 751 #define FRF_AB_PCIE_RXEQCTL_H_LBN 18
 752 #define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
 753 #define FRF_AB_PCIE_RXEQCTL_L_LBN 16
 754 #define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
 755 #define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
 756 #define FFE_AB_PCIE_RXEQCTL_OFF 2
 757 #define FFE_AB_PCIE_RXEQCTL_MIN 1
 758 #define FFE_AB_PCIE_RXEQCTL_MAX 0
 759 #define FRF_AB_PCIE_HIDRV_LBN 8
 760 #define FRF_AB_PCIE_HIDRV_WIDTH 8
 761 #define FRF_AB_PCIE_LODRV_LBN 0
 762 #define FRF_AB_PCIE_LODRV_WIDTH 8
 763 
 764 /* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */
 765 #define FR_AB_PCIE_SD_CTL45 0x00000330
 766 #define FRF_AB_PCIE_DTX7_LBN 60
 767 #define FRF_AB_PCIE_DTX7_WIDTH 4
 768 #define FRF_AB_PCIE_DTX6_LBN 56
 769 #define FRF_AB_PCIE_DTX6_WIDTH 4
 770 #define FRF_AB_PCIE_DTX5_LBN 52
 771 #define FRF_AB_PCIE_DTX5_WIDTH 4
 772 #define FRF_AB_PCIE_DTX4_LBN 48
 773 #define FRF_AB_PCIE_DTX4_WIDTH 4
 774 #define FRF_AB_PCIE_DTX3_LBN 44
 775 #define FRF_AB_PCIE_DTX3_WIDTH 4
 776 #define FRF_AB_PCIE_DTX2_LBN 40
 777 #define FRF_AB_PCIE_DTX2_WIDTH 4
 778 #define FRF_AB_PCIE_DTX1_LBN 36
 779 #define FRF_AB_PCIE_DTX1_WIDTH 4
 780 #define FRF_AB_PCIE_DTX0_LBN 32
 781 #define FRF_AB_PCIE_DTX0_WIDTH 4
 782 #define FRF_AB_PCIE_DEQ7_LBN 28
 783 #define FRF_AB_PCIE_DEQ7_WIDTH 4
 784 #define FRF_AB_PCIE_DEQ6_LBN 24
 785 #define FRF_AB_PCIE_DEQ6_WIDTH 4
 786 #define FRF_AB_PCIE_DEQ5_LBN 20
 787 #define FRF_AB_PCIE_DEQ5_WIDTH 4
 788 #define FRF_AB_PCIE_DEQ4_LBN 16
 789 #define FRF_AB_PCIE_DEQ4_WIDTH 4
 790 #define FRF_AB_PCIE_DEQ3_LBN 12
 791 #define FRF_AB_PCIE_DEQ3_WIDTH 4
 792 #define FRF_AB_PCIE_DEQ2_LBN 8
 793 #define FRF_AB_PCIE_DEQ2_WIDTH 4
 794 #define FRF_AB_PCIE_DEQ1_LBN 4
 795 #define FRF_AB_PCIE_DEQ1_WIDTH 4
 796 #define FRF_AB_PCIE_DEQ0_LBN 0
 797 #define FRF_AB_PCIE_DEQ0_WIDTH 4
 798 
 799 /* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */
 800 #define FR_AB_PCIE_PCS_CTL_STAT 0x00000340
 801 #define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
 802 #define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
 803 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
 804 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
 805 #define FRF_AB_PCIE_PRBSERR_LBN 40
 806 #define FRF_AB_PCIE_PRBSERR_WIDTH 8
 807 #define FRF_AB_PCIE_PRBSERRH0_LBN 32
 808 #define FRF_AB_PCIE_PRBSERRH0_WIDTH 8
 809 #define FRF_AB_PCIE_FASTINIT_H_LBN 15
 810 #define FRF_AB_PCIE_FASTINIT_H_WIDTH 1
 811 #define FRF_AB_PCIE_FASTINIT_L_LBN 14
 812 #define FRF_AB_PCIE_FASTINIT_L_WIDTH 1
 813 #define FRF_AB_PCIE_CTCDISABLE_H_LBN 13
 814 #define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
 815 #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
 816 #define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
 817 #define FRF_AB_PCIE_PRBSSYNC_H_LBN 11
 818 #define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
 819 #define FRF_AB_PCIE_PRBSSYNC_L_LBN 10
 820 #define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
 821 #define FRF_AB_PCIE_PRBSERRACK_H_LBN 9
 822 #define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
 823 #define FRF_AB_PCIE_PRBSERRACK_L_LBN 8
 824 #define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
 825 #define FRF_AB_PCIE_PRBSSEL_LBN 0
 826 #define FRF_AB_PCIE_PRBSSEL_WIDTH 8
 827 
 828 /* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */
 829 #define FR_BB_DEBUG_DATA_OUT 0x00000350
 830 #define FRF_BB_DEBUG2_PORT_LBN 25
 831 #define FRF_BB_DEBUG2_PORT_WIDTH 15
 832 #define FRF_BB_DEBUG1_PORT_LBN 0
 833 #define FRF_BB_DEBUG1_PORT_WIDTH 25
 834 
 835 /* EVQ_RPTR_REGP0: Event queue read pointer register */
 836 #define FR_BZ_EVQ_RPTR_P0 0x00000400
 837 #define FR_BZ_EVQ_RPTR_P0_STEP 8192
 838 #define FR_BZ_EVQ_RPTR_P0_ROWS 1024
 839 /* EVQ_RPTR_REG_KER: Event queue read pointer register */
 840 #define FR_AA_EVQ_RPTR_KER 0x00011b00
 841 #define FR_AA_EVQ_RPTR_KER_STEP 4
 842 #define FR_AA_EVQ_RPTR_KER_ROWS 4
 843 /* EVQ_RPTR_REG: Event queue read pointer register */
 844 #define FR_BZ_EVQ_RPTR 0x00fa0000
 845 #define FR_BZ_EVQ_RPTR_STEP 16
 846 #define FR_BB_EVQ_RPTR_ROWS 4096
 847 #define FR_CZ_EVQ_RPTR_ROWS 1024
 848 /* EVQ_RPTR_REGP123: Event queue read pointer register */
 849 #define FR_BB_EVQ_RPTR_P123 0x01000400
 850 #define FR_BB_EVQ_RPTR_P123_STEP 8192
 851 #define FR_BB_EVQ_RPTR_P123_ROWS 3072
 852 #define FRF_AZ_EVQ_RPTR_VLD_LBN 15
 853 #define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
 854 #define FRF_AZ_EVQ_RPTR_LBN 0
 855 #define FRF_AZ_EVQ_RPTR_WIDTH 15
 856 
 857 /* TIMER_COMMAND_REGP0: Timer Command Registers */
 858 #define FR_BZ_TIMER_COMMAND_P0 0x00000420
 859 #define FR_BZ_TIMER_COMMAND_P0_STEP 8192
 860 #define FR_BZ_TIMER_COMMAND_P0_ROWS 1024
 861 /* TIMER_COMMAND_REG_KER: Timer Command Registers */
 862 #define FR_AA_TIMER_COMMAND_KER 0x00000420
 863 #define FR_AA_TIMER_COMMAND_KER_STEP 8192
 864 #define FR_AA_TIMER_COMMAND_KER_ROWS 4
 865 /* TIMER_COMMAND_REGP123: Timer Command Registers */
 866 #define FR_BB_TIMER_COMMAND_P123 0x01000420
 867 #define FR_BB_TIMER_COMMAND_P123_STEP 8192
 868 #define FR_BB_TIMER_COMMAND_P123_ROWS 3072
 869 #define FRF_CZ_TC_TIMER_MODE_LBN 14
 870 #define FRF_CZ_TC_TIMER_MODE_WIDTH 2
 871 #define FRF_AB_TC_TIMER_MODE_LBN 12
 872 #define FRF_AB_TC_TIMER_MODE_WIDTH 2
 873 #define FRF_CZ_TC_TIMER_VAL_LBN 0
 874 #define FRF_CZ_TC_TIMER_VAL_WIDTH 14
 875 #define FRF_AB_TC_TIMER_VAL_LBN 0
 876 #define FRF_AB_TC_TIMER_VAL_WIDTH 12
 877 
 878 /* DRV_EV_REG: Driver generated event register */
 879 #define FR_AZ_DRV_EV 0x00000440
 880 #define FRF_AZ_DRV_EV_QID_LBN 64
 881 #define FRF_AZ_DRV_EV_QID_WIDTH 12
 882 #define FRF_AZ_DRV_EV_DATA_LBN 0
 883 #define FRF_AZ_DRV_EV_DATA_WIDTH 64
 884 
 885 /* EVQ_CTL_REG: Event queue control register */
 886 #define FR_AZ_EVQ_CTL 0x00000450
 887 #define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
 888 #define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
 889 #define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
 890 #define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
 891 #define FRF_AZ_EVQ_OWNERR_CTL_LBN 14
 892 #define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
 893 #define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
 894 #define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
 895 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
 896 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
 897 
 898 /* EVQ_CNT1_REG: Event counter 1 register */
 899 #define FR_AZ_EVQ_CNT1 0x00000460
 900 #define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
 901 #define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
 902 #define FRF_AZ_EVQ_CNT_TOBIU_LBN 100
 903 #define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
 904 #define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
 905 #define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
 906 #define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
 907 #define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
 908 #define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
 909 #define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
 910 #define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
 911 #define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
 912 #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
 913 #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
 914 
 915 /* EVQ_CNT2_REG: Event counter 2 register */
 916 #define FR_AZ_EVQ_CNT2 0x00000470
 917 #define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
 918 #define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
 919 #define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
 920 #define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
 921 #define FRF_AZ_EVQ_RDY_CNT_LBN 80
 922 #define FRF_AZ_EVQ_RDY_CNT_WIDTH 4
 923 #define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
 924 #define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
 925 #define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
 926 #define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
 927 #define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
 928 #define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
 929 #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
 930 #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
 931 
 932 /* USR_EV_REG: Event mailbox register */
 933 #define FR_CZ_USR_EV 0x00000540
 934 #define FR_CZ_USR_EV_STEP 8192
 935 #define FR_CZ_USR_EV_ROWS 1024
 936 #define FRF_CZ_USR_EV_DATA_LBN 0
 937 #define FRF_CZ_USR_EV_DATA_WIDTH 32
 938 
 939 /* BUF_TBL_CFG_REG: Buffer table configuration register */
 940 #define FR_AZ_BUF_TBL_CFG 0x00000600
 941 #define FRF_AZ_BUF_TBL_MODE_LBN 3
 942 #define FRF_AZ_BUF_TBL_MODE_WIDTH 1
 943 
 944 /* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */
 945 #define FR_AZ_SRM_RX_DC_CFG 0x00000610
 946 #define FRF_AZ_SRM_CLK_TMP_EN_LBN 21
 947 #define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
 948 #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
 949 #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
 950 
 951 /* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */
 952 #define FR_AZ_SRM_TX_DC_CFG 0x00000620
 953 #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
 954 #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
 955 
 956 /* SRM_CFG_REG: SRAM configuration register */
 957 #define FR_AZ_SRM_CFG 0x00000630
 958 #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
 959 #define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
 960 #define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
 961 #define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
 962 #define FRF_AZ_SRM_INIT_EN_LBN 3
 963 #define FRF_AZ_SRM_INIT_EN_WIDTH 1
 964 #define FRF_AZ_SRM_NUM_BANK_LBN 2
 965 #define FRF_AZ_SRM_NUM_BANK_WIDTH 1
 966 #define FRF_AZ_SRM_BANK_SIZE_LBN 0
 967 #define FRF_AZ_SRM_BANK_SIZE_WIDTH 2
 968 
 969 /* BUF_TBL_UPD_REG: Buffer table update register */
 970 #define FR_AZ_BUF_TBL_UPD 0x00000650
 971 #define FRF_AZ_BUF_UPD_CMD_LBN 63
 972 #define FRF_AZ_BUF_UPD_CMD_WIDTH 1
 973 #define FRF_AZ_BUF_CLR_CMD_LBN 62
 974 #define FRF_AZ_BUF_CLR_CMD_WIDTH 1
 975 #define FRF_AZ_BUF_CLR_END_ID_LBN 32
 976 #define FRF_AZ_BUF_CLR_END_ID_WIDTH 20
 977 #define FRF_AZ_BUF_CLR_START_ID_LBN 0
 978 #define FRF_AZ_BUF_CLR_START_ID_WIDTH 20
 979 
 980 /* SRM_UPD_EVQ_REG: Buffer table update register */
 981 #define FR_AZ_SRM_UPD_EVQ 0x00000660
 982 #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
 983 #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
 984 
 985 /* SRAM_PARITY_REG: SRAM parity register. */
 986 #define FR_AZ_SRAM_PARITY 0x00000670
 987 #define FRF_CZ_BYPASS_ECC_LBN 3
 988 #define FRF_CZ_BYPASS_ECC_WIDTH 1
 989 #define FRF_CZ_SEC_INT_LBN 2
 990 #define FRF_CZ_SEC_INT_WIDTH 1
 991 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
 992 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
 993 #define FRF_AB_FORCE_SRAM_PERR_LBN 0
 994 #define FRF_AB_FORCE_SRAM_PERR_WIDTH 1
 995 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
 996 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
 997 
 998 /* RX_CFG_REG: Receive configuration register */
 999 #define FR_AZ_RX_CFG 0x00000800
1000 #define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72
1001 #define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14
1002 #define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
1003 #define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
1004 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
1005 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
1006 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
1007 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
1008 #define FRF_CZ_RX_PRE_RFF_IPG_LBN 49
1009 #define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
1010 #define FRF_BZ_RX_TCP_SUP_LBN 48
1011 #define FRF_BZ_RX_TCP_SUP_WIDTH 1
1012 #define FRF_BZ_RX_INGR_EN_LBN 47
1013 #define FRF_BZ_RX_INGR_EN_WIDTH 1
1014 #define FRF_BZ_RX_IP_HASH_LBN 46
1015 #define FRF_BZ_RX_IP_HASH_WIDTH 1
1016 #define FRF_BZ_RX_HASH_ALG_LBN 45
1017 #define FRF_BZ_RX_HASH_ALG_WIDTH 1
1018 #define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
1019 #define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
1020 #define FRF_BZ_RX_DESC_PUSH_EN_LBN 43
1021 #define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
1022 #define FRF_BZ_RX_RDW_PATCH_EN_LBN 42
1023 #define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
1024 #define FRF_BB_RX_PCI_BURST_SIZE_LBN 39
1025 #define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
1026 #define FRF_BZ_RX_OWNERR_CTL_LBN 38
1027 #define FRF_BZ_RX_OWNERR_CTL_WIDTH 1
1028 #define FRF_BZ_RX_XON_TX_TH_LBN 33
1029 #define FRF_BZ_RX_XON_TX_TH_WIDTH 5
1030 #define FRF_AA_RX_DESC_PUSH_EN_LBN 35
1031 #define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
1032 #define FRF_AA_RX_RDW_PATCH_EN_LBN 34
1033 #define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
1034 #define FRF_AA_RX_PCI_BURST_SIZE_LBN 31
1035 #define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
1036 #define FRF_BZ_RX_XOFF_TX_TH_LBN 28
1037 #define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1038 #define FRF_AA_RX_OWNERR_CTL_LBN 30
1039 #define FRF_AA_RX_OWNERR_CTL_WIDTH 1
1040 #define FRF_AA_RX_XON_TX_TH_LBN 25
1041 #define FRF_AA_RX_XON_TX_TH_WIDTH 5
1042 #define FRF_BZ_RX_USR_BUF_SIZE_LBN 19
1043 #define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
1044 #define FRF_AA_RX_XOFF_TX_TH_LBN 20
1045 #define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1046 #define FRF_AA_RX_USR_BUF_SIZE_LBN 11
1047 #define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
1048 #define FRF_BZ_RX_XON_MAC_TH_LBN 10
1049 #define FRF_BZ_RX_XON_MAC_TH_WIDTH 9
1050 #define FRF_AA_RX_XON_MAC_TH_LBN 6
1051 #define FRF_AA_RX_XON_MAC_TH_WIDTH 5
1052 #define FRF_BZ_RX_XOFF_MAC_TH_LBN 1
1053 #define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
1054 #define FRF_AA_RX_XOFF_MAC_TH_LBN 1
1055 #define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1056 #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1057 #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
1058 
1059 /* RX_FILTER_CTL_REG: Receive filter control registers */
1060 #define FR_BZ_RX_FILTER_CTL 0x00000810
1061 #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
1062 #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
1063 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
1064 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
1065 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
1066 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
1067 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
1068 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1069 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
1070 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1071 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
1072 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1073 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
1074 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1075 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
1076 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1077 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
1078 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1079 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
1080 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1081 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
1082 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
1083 #define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 32
1084 #define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
1085 #define FRF_BZ_NUM_KER_LBN 24
1086 #define FRF_BZ_NUM_KER_WIDTH 2
1087 #define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 16
1088 #define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
1089 #define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 8
1090 #define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
1091 #define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 0
1092 #define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
1093 
1094 /* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */
1095 #define FR_AZ_RX_FLUSH_DESCQ 0x00000820
1096 #define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
1097 #define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
1098 #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1099 #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1100 
1101 /* RX_DESC_UPD_REGP0: Receive descriptor update register. */
1102 #define FR_BZ_RX_DESC_UPD_P0 0x00000830
1103 #define FR_BZ_RX_DESC_UPD_P0_STEP 8192
1104 #define FR_BZ_RX_DESC_UPD_P0_ROWS 1024
1105 /* RX_DESC_UPD_REG_KER: Receive descriptor update register. */
1106 #define FR_AA_RX_DESC_UPD_KER 0x00000830
1107 #define FR_AA_RX_DESC_UPD_KER_STEP 8192
1108 #define FR_AA_RX_DESC_UPD_KER_ROWS 4
1109 /* RX_DESC_UPD_REGP123: Receive descriptor update register. */
1110 #define FR_BB_RX_DESC_UPD_P123 0x01000830
1111 #define FR_BB_RX_DESC_UPD_P123_STEP 8192
1112 #define FR_BB_RX_DESC_UPD_P123_ROWS 3072
1113 #define FRF_AZ_RX_DESC_WPTR_LBN 96
1114 #define FRF_AZ_RX_DESC_WPTR_WIDTH 12
1115 #define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
1116 #define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
1117 #define FRF_AZ_RX_DESC_LBN 0
1118 #define FRF_AZ_RX_DESC_WIDTH 64
1119 
1120 /* RX_DC_CFG_REG: Receive descriptor cache configuration register */
1121 #define FR_AZ_RX_DC_CFG 0x00000840
1122 #define FRF_AB_RX_MAX_PF_LBN 2
1123 #define FRF_AB_RX_MAX_PF_WIDTH 2
1124 #define FRF_AZ_RX_DC_SIZE_LBN 0
1125 #define FRF_AZ_RX_DC_SIZE_WIDTH 2
1126 #define FFE_AZ_RX_DC_SIZE_64 3
1127 #define FFE_AZ_RX_DC_SIZE_32 2
1128 #define FFE_AZ_RX_DC_SIZE_16 1
1129 #define FFE_AZ_RX_DC_SIZE_8 0
1130 
1131 /* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */
1132 #define FR_AZ_RX_DC_PF_WM 0x00000850
1133 #define FRF_AZ_RX_DC_PF_HWM_LBN 6
1134 #define FRF_AZ_RX_DC_PF_HWM_WIDTH 6
1135 #define FRF_AZ_RX_DC_PF_LWM_LBN 0
1136 #define FRF_AZ_RX_DC_PF_LWM_WIDTH 6
1137 
1138 /* RX_RSS_TKEY_REG: RSS Toeplitz hash key */
1139 #define FR_BZ_RX_RSS_TKEY 0x00000860
1140 #define FRF_BZ_RX_RSS_TKEY_HI_LBN 64
1141 #define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64
1142 #define FRF_BZ_RX_RSS_TKEY_LO_LBN 0
1143 #define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64
1144 
1145 /* RX_NODESC_DROP_REG: Receive dropped packet counter register */
1146 #define FR_AZ_RX_NODESC_DROP 0x00000880
1147 #define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0
1148 #define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32
1149 #define FRF_AB_RX_NODESC_DROP_CNT_LBN 0
1150 #define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16
1151 
1152 /* RX_SELF_RST_REG: Receive self reset register */
1153 #define FR_AA_RX_SELF_RST 0x00000890
1154 #define FRF_AA_RX_ISCSI_DIS_LBN 17
1155 #define FRF_AA_RX_ISCSI_DIS_WIDTH 1
1156 #define FRF_AA_RX_SW_RST_REG_LBN 16
1157 #define FRF_AA_RX_SW_RST_REG_WIDTH 1
1158 #define FRF_AA_RX_NODESC_WAIT_DIS_LBN 9
1159 #define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 1
1160 #define FRF_AA_RX_SELF_RST_EN_LBN 8
1161 #define FRF_AA_RX_SELF_RST_EN_WIDTH 1
1162 #define FRF_AA_RX_MAX_PF_LAT_LBN 4
1163 #define FRF_AA_RX_MAX_PF_LAT_WIDTH 4
1164 #define FRF_AA_RX_MAX_LU_LAT_LBN 0
1165 #define FRF_AA_RX_MAX_LU_LAT_WIDTH 4
1166 
1167 /* RX_DEBUG_REG: undocumented register */
1168 #define FR_AZ_RX_DEBUG 0x000008a0
1169 #define FRF_AZ_RX_DEBUG_LBN 0
1170 #define FRF_AZ_RX_DEBUG_WIDTH 64
1171 
1172 /* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */
1173 #define FR_AZ_RX_PUSH_DROP 0x000008b0
1174 #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1175 #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1176 
1177 /* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */
1178 #define FR_CZ_RX_RSS_IPV6_REG1 0x000008d0
1179 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1180 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
1181 
1182 /* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */
1183 #define FR_CZ_RX_RSS_IPV6_REG2 0x000008e0
1184 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1185 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
1186 
1187 /* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */
1188 #define FR_CZ_RX_RSS_IPV6_REG3 0x000008f0
1189 #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
1190 #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
1191 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
1192 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
1193 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
1194 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
1195 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1196 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
1197 
1198 /* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */
1199 #define FR_AZ_TX_FLUSH_DESCQ 0x00000a00
1200 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1201 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
1202 #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1203 #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1204 
1205 /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
1206 #define FR_BZ_TX_DESC_UPD_P0 0x00000a10
1207 #define FR_BZ_TX_DESC_UPD_P0_STEP 8192
1208 #define FR_BZ_TX_DESC_UPD_P0_ROWS 1024
1209 /* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */
1210 #define FR_AA_TX_DESC_UPD_KER 0x00000a10
1211 #define FR_AA_TX_DESC_UPD_KER_STEP 8192
1212 #define FR_AA_TX_DESC_UPD_KER_ROWS 8
1213 /* TX_DESC_UPD_REGP123: Transmit descriptor update register. */
1214 #define FR_BB_TX_DESC_UPD_P123 0x01000a10
1215 #define FR_BB_TX_DESC_UPD_P123_STEP 8192
1216 #define FR_BB_TX_DESC_UPD_P123_ROWS 3072
1217 #define FRF_AZ_TX_DESC_WPTR_LBN 96
1218 #define FRF_AZ_TX_DESC_WPTR_WIDTH 12
1219 #define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
1220 #define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
1221 #define FRF_AZ_TX_DESC_LBN 0
1222 #define FRF_AZ_TX_DESC_WIDTH 95
1223 
1224 /* TX_DC_CFG_REG: Transmit descriptor cache configuration register */
1225 #define FR_AZ_TX_DC_CFG 0x00000a20
1226 #define FRF_AZ_TX_DC_SIZE_LBN 0
1227 #define FRF_AZ_TX_DC_SIZE_WIDTH 2
1228 #define FFE_AZ_TX_DC_SIZE_32 2
1229 #define FFE_AZ_TX_DC_SIZE_16 1
1230 #define FFE_AZ_TX_DC_SIZE_8 0
1231 
1232 /* TX_CHKSM_CFG_REG: Transmit checksum configuration register */
1233 #define FR_AA_TX_CHKSM_CFG 0x00000a30
1234 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
1235 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1236 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
1237 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1238 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1239 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1240 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1241 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1242 
1243 /* TX_CFG_REG: Transmit configuration register */
1244 #define FR_AZ_TX_CFG 0x00000a50
1245 #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
1246 #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
1247 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
1248 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
1249 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
1250 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1251 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
1252 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1253 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
1254 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1255 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
1256 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1257 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
1258 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1259 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
1260 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1261 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
1262 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
1263 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
1264 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1265 #define FRF_CZ_TX_FILTER_EN_BIT_LBN 47
1266 #define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
1267 #define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1268 #define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
1269 #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1270 #define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
1271 #define FRF_AZ_TX_P1_PRI_EN_LBN 4
1272 #define FRF_AZ_TX_P1_PRI_EN_WIDTH 1
1273 #define FRF_AZ_TX_OWNERR_CTL_LBN 2
1274 #define FRF_AZ_TX_OWNERR_CTL_WIDTH 1
1275 #define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
1276 #define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
1277 #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1278 #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
1279 
1280 /* TX_PUSH_DROP_REG: Transmit push dropped register */
1281 #define FR_AZ_TX_PUSH_DROP 0x00000a60
1282 #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1283 #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1284 
1285 /* TX_RESERVED_REG: Transmit configuration register */
1286 #define FR_AZ_TX_RESERVED 0x00000a80
1287 #define FRF_AZ_TX_EVT_CNT_LBN 121
1288 #define FRF_AZ_TX_EVT_CNT_WIDTH 7
1289 #define FRF_AZ_TX_PREF_AGE_CNT_LBN 119
1290 #define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
1291 #define FRF_AZ_TX_RD_COMP_TMR_LBN 96
1292 #define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
1293 #define FRF_AZ_TX_PUSH_EN_LBN 89
1294 #define FRF_AZ_TX_PUSH_EN_WIDTH 1
1295 #define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
1296 #define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
1297 #define FRF_AZ_TX_D_FF_FULL_P0_LBN 85
1298 #define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
1299 #define FRF_AZ_TX_DMAR_ST_P0_LBN 81
1300 #define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
1301 #define FRF_AZ_TX_DMAQ_ST_LBN 78
1302 #define FRF_AZ_TX_DMAQ_ST_WIDTH 1
1303 #define FRF_AZ_TX_RX_SPACER_LBN 64
1304 #define FRF_AZ_TX_RX_SPACER_WIDTH 8
1305 #define FRF_AZ_TX_DROP_ABORT_EN_LBN 60
1306 #define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
1307 #define FRF_AZ_TX_SOFT_EVT_EN_LBN 59
1308 #define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
1309 #define FRF_AZ_TX_PS_EVT_DIS_LBN 58
1310 #define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
1311 #define FRF_AZ_TX_RX_SPACER_EN_LBN 57
1312 #define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
1313 #define FRF_AZ_TX_XP_TIMER_LBN 52
1314 #define FRF_AZ_TX_XP_TIMER_WIDTH 5
1315 #define FRF_AZ_TX_PREF_SPACER_LBN 44
1316 #define FRF_AZ_TX_PREF_SPACER_WIDTH 8
1317 #define FRF_AZ_TX_PREF_WD_TMR_LBN 22
1318 #define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
1319 #define FRF_AZ_TX_ONLY1TAG_LBN 21
1320 #define FRF_AZ_TX_ONLY1TAG_WIDTH 1
1321 #define FRF_AZ_TX_PREF_THRESHOLD_LBN 19
1322 #define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
1323 #define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
1324 #define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
1325 #define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
1326 #define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
1327 #define FRF_AA_TX_DMA_FF_THR_LBN 16
1328 #define FRF_AA_TX_DMA_FF_THR_WIDTH 1
1329 #define FRF_AZ_TX_DMA_SPACER_LBN 8
1330 #define FRF_AZ_TX_DMA_SPACER_WIDTH 8
1331 #define FRF_AA_TX_TCP_DIS_LBN 7
1332 #define FRF_AA_TX_TCP_DIS_WIDTH 1
1333 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
1334 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
1335 #define FRF_AA_TX_IP_DIS_LBN 6
1336 #define FRF_AA_TX_IP_DIS_WIDTH 1
1337 #define FRF_AZ_TX_MAX_CPL_LBN 2
1338 #define FRF_AZ_TX_MAX_CPL_WIDTH 2
1339 #define FFE_AZ_TX_MAX_CPL_16 3
1340 #define FFE_AZ_TX_MAX_CPL_8 2
1341 #define FFE_AZ_TX_MAX_CPL_4 1
1342 #define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1343 #define FRF_AZ_TX_MAX_PREF_LBN 0
1344 #define FRF_AZ_TX_MAX_PREF_WIDTH 2
1345 #define FFE_AZ_TX_MAX_PREF_32 3
1346 #define FFE_AZ_TX_MAX_PREF_16 2
1347 #define FFE_AZ_TX_MAX_PREF_8 1
1348 #define FFE_AZ_TX_MAX_PREF_OFF 0
1349 
1350 /* TX_PACE_REG: Transmit pace control register */
1351 #define FR_BZ_TX_PACE 0x00000a90
1352 #define FRF_BZ_TX_PACE_SB_NOT_AF_LBN 19
1353 #define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 10
1354 #define FRF_BZ_TX_PACE_SB_AF_LBN 9
1355 #define FRF_BZ_TX_PACE_SB_AF_WIDTH 10
1356 #define FRF_BZ_TX_PACE_FB_BASE_LBN 5
1357 #define FRF_BZ_TX_PACE_FB_BASE_WIDTH 4
1358 #define FRF_BZ_TX_PACE_BIN_TH_LBN 0
1359 #define FRF_BZ_TX_PACE_BIN_TH_WIDTH 5
1360 
1361 /* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */
1362 #define FR_BZ_TX_PACE_DROP_QID 0x00000aa0
1363 #define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 0
1364 #define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1365 
1366 /* TX_VLAN_REG: Transmit VLAN tag register */
1367 #define FR_BB_TX_VLAN 0x00000ae0
1368 #define FRF_BB_TX_VLAN_EN_LBN 127
1369 #define FRF_BB_TX_VLAN_EN_WIDTH 1
1370 #define FRF_BB_TX_VLAN7_PORT1_EN_LBN 125
1371 #define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 1
1372 #define FRF_BB_TX_VLAN7_PORT0_EN_LBN 124
1373 #define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 1
1374 #define FRF_BB_TX_VLAN7_LBN 112
1375 #define FRF_BB_TX_VLAN7_WIDTH 12
1376 #define FRF_BB_TX_VLAN6_PORT1_EN_LBN 109
1377 #define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 1
1378 #define FRF_BB_TX_VLAN6_PORT0_EN_LBN 108
1379 #define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 1
1380 #define FRF_BB_TX_VLAN6_LBN 96
1381 #define FRF_BB_TX_VLAN6_WIDTH 12
1382 #define FRF_BB_TX_VLAN5_PORT1_EN_LBN 93
1383 #define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 1
1384 #define FRF_BB_TX_VLAN5_PORT0_EN_LBN 92
1385 #define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 1
1386 #define FRF_BB_TX_VLAN5_LBN 80
1387 #define FRF_BB_TX_VLAN5_WIDTH 12
1388 #define FRF_BB_TX_VLAN4_PORT1_EN_LBN 77
1389 #define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 1
1390 #define FRF_BB_TX_VLAN4_PORT0_EN_LBN 76
1391 #define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 1
1392 #define FRF_BB_TX_VLAN4_LBN 64
1393 #define FRF_BB_TX_VLAN4_WIDTH 12
1394 #define FRF_BB_TX_VLAN3_PORT1_EN_LBN 61
1395 #define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 1
1396 #define FRF_BB_TX_VLAN3_PORT0_EN_LBN 60
1397 #define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 1
1398 #define FRF_BB_TX_VLAN3_LBN 48
1399 #define FRF_BB_TX_VLAN3_WIDTH 12
1400 #define FRF_BB_TX_VLAN2_PORT1_EN_LBN 45
1401 #define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 1
1402 #define FRF_BB_TX_VLAN2_PORT0_EN_LBN 44
1403 #define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 1
1404 #define FRF_BB_TX_VLAN2_LBN 32
1405 #define FRF_BB_TX_VLAN2_WIDTH 12
1406 #define FRF_BB_TX_VLAN1_PORT1_EN_LBN 29
1407 #define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 1
1408 #define FRF_BB_TX_VLAN1_PORT0_EN_LBN 28
1409 #define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 1
1410 #define FRF_BB_TX_VLAN1_LBN 16
1411 #define FRF_BB_TX_VLAN1_WIDTH 12
1412 #define FRF_BB_TX_VLAN0_PORT1_EN_LBN 13
1413 #define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 1
1414 #define FRF_BB_TX_VLAN0_PORT0_EN_LBN 12
1415 #define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 1
1416 #define FRF_BB_TX_VLAN0_LBN 0
1417 #define FRF_BB_TX_VLAN0_WIDTH 12
1418 
1419 /* TX_IPFIL_PORTEN_REG: Transmit filter control register */
1420 #define FR_BZ_TX_IPFIL_PORTEN 0x00000af0
1421 #define FRF_BZ_TX_MADR0_FIL_EN_LBN 64
1422 #define FRF_BZ_TX_MADR0_FIL_EN_WIDTH 1
1423 #define FRF_BB_TX_IPFIL31_PORT_EN_LBN 62
1424 #define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 1
1425 #define FRF_BB_TX_IPFIL30_PORT_EN_LBN 60
1426 #define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 1
1427 #define FRF_BB_TX_IPFIL29_PORT_EN_LBN 58
1428 #define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 1
1429 #define FRF_BB_TX_IPFIL28_PORT_EN_LBN 56
1430 #define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 1
1431 #define FRF_BB_TX_IPFIL27_PORT_EN_LBN 54
1432 #define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 1
1433 #define FRF_BB_TX_IPFIL26_PORT_EN_LBN 52
1434 #define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 1
1435 #define FRF_BB_TX_IPFIL25_PORT_EN_LBN 50
1436 #define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 1
1437 #define FRF_BB_TX_IPFIL24_PORT_EN_LBN 48
1438 #define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 1
1439 #define FRF_BB_TX_IPFIL23_PORT_EN_LBN 46
1440 #define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 1
1441 #define FRF_BB_TX_IPFIL22_PORT_EN_LBN 44
1442 #define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 1
1443 #define FRF_BB_TX_IPFIL21_PORT_EN_LBN 42
1444 #define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 1
1445 #define FRF_BB_TX_IPFIL20_PORT_EN_LBN 40
1446 #define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 1
1447 #define FRF_BB_TX_IPFIL19_PORT_EN_LBN 38
1448 #define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 1
1449 #define FRF_BB_TX_IPFIL18_PORT_EN_LBN 36
1450 #define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 1
1451 #define FRF_BB_TX_IPFIL17_PORT_EN_LBN 34
1452 #define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 1
1453 #define FRF_BB_TX_IPFIL16_PORT_EN_LBN 32
1454 #define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 1
1455 #define FRF_BB_TX_IPFIL15_PORT_EN_LBN 30
1456 #define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 1
1457 #define FRF_BB_TX_IPFIL14_PORT_EN_LBN 28
1458 #define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 1
1459 #define FRF_BB_TX_IPFIL13_PORT_EN_LBN 26
1460 #define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 1
1461 #define FRF_BB_TX_IPFIL12_PORT_EN_LBN 24
1462 #define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 1
1463 #define FRF_BB_TX_IPFIL11_PORT_EN_LBN 22
1464 #define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 1
1465 #define FRF_BB_TX_IPFIL10_PORT_EN_LBN 20
1466 #define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 1
1467 #define FRF_BB_TX_IPFIL9_PORT_EN_LBN 18
1468 #define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 1
1469 #define FRF_BB_TX_IPFIL8_PORT_EN_LBN 16
1470 #define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 1
1471 #define FRF_BB_TX_IPFIL7_PORT_EN_LBN 14
1472 #define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 1
1473 #define FRF_BB_TX_IPFIL6_PORT_EN_LBN 12
1474 #define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 1
1475 #define FRF_BB_TX_IPFIL5_PORT_EN_LBN 10
1476 #define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 1
1477 #define FRF_BB_TX_IPFIL4_PORT_EN_LBN 8
1478 #define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 1
1479 #define FRF_BB_TX_IPFIL3_PORT_EN_LBN 6
1480 #define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 1
1481 #define FRF_BB_TX_IPFIL2_PORT_EN_LBN 4
1482 #define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 1
1483 #define FRF_BB_TX_IPFIL1_PORT_EN_LBN 2
1484 #define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 1
1485 #define FRF_BB_TX_IPFIL0_PORT_EN_LBN 0
1486 #define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 1
1487 
1488 /* TX_IPFIL_TBL: Transmit IP source address filter table */
1489 #define FR_BB_TX_IPFIL_TBL 0x00000b00
1490 #define FR_BB_TX_IPFIL_TBL_STEP 16
1491 #define FR_BB_TX_IPFIL_TBL_ROWS 16
1492 #define FRF_BB_TX_IPFIL_MASK_1_LBN 96
1493 #define FRF_BB_TX_IPFIL_MASK_1_WIDTH 32
1494 #define FRF_BB_TX_IP_SRC_ADR_1_LBN 64
1495 #define FRF_BB_TX_IP_SRC_ADR_1_WIDTH 32
1496 #define FRF_BB_TX_IPFIL_MASK_0_LBN 32
1497 #define FRF_BB_TX_IPFIL_MASK_0_WIDTH 32
1498 #define FRF_BB_TX_IP_SRC_ADR_0_LBN 0
1499 #define FRF_BB_TX_IP_SRC_ADR_0_WIDTH 32
1500 
1501 /* MD_TXD_REG: PHY management transmit data register */
1502 #define FR_AB_MD_TXD 0x00000c00
1503 #define FRF_AB_MD_TXD_LBN 0
1504 #define FRF_AB_MD_TXD_WIDTH 16
1505 
1506 /* MD_RXD_REG: PHY management receive data register */
1507 #define FR_AB_MD_RXD 0x00000c10
1508 #define FRF_AB_MD_RXD_LBN 0
1509 #define FRF_AB_MD_RXD_WIDTH 16
1510 
1511 /* MD_CS_REG: PHY management configuration & status register */
1512 #define FR_AB_MD_CS 0x00000c20
1513 #define FRF_AB_MD_RD_EN_CMD_LBN 15
1514 #define FRF_AB_MD_RD_EN_CMD_WIDTH 1
1515 #define FRF_AB_MD_WR_EN_CMD_LBN 14
1516 #define FRF_AB_MD_WR_EN_CMD_WIDTH 1
1517 #define FRF_AB_MD_ADDR_CMD_LBN 13
1518 #define FRF_AB_MD_ADDR_CMD_WIDTH 1
1519 #define FRF_AB_MD_PT_LBN 7
1520 #define FRF_AB_MD_PT_WIDTH 3
1521 #define FRF_AB_MD_PL_LBN 6
1522 #define FRF_AB_MD_PL_WIDTH 1
1523 #define FRF_AB_MD_INT_CLR_LBN 5
1524 #define FRF_AB_MD_INT_CLR_WIDTH 1
1525 #define FRF_AB_MD_GC_LBN 4
1526 #define FRF_AB_MD_GC_WIDTH 1
1527 #define FRF_AB_MD_PRSP_LBN 3
1528 #define FRF_AB_MD_PRSP_WIDTH 1
1529 #define FRF_AB_MD_RIC_LBN 2
1530 #define FRF_AB_MD_RIC_WIDTH 1
1531 #define FRF_AB_MD_RDC_LBN 1
1532 #define FRF_AB_MD_RDC_WIDTH 1
1533 #define FRF_AB_MD_WRC_LBN 0
1534 #define FRF_AB_MD_WRC_WIDTH 1
1535 
1536 /* MD_PHY_ADR_REG: PHY management PHY address register */
1537 #define FR_AB_MD_PHY_ADR 0x00000c30
1538 #define FRF_AB_MD_PHY_ADR_LBN 0
1539 #define FRF_AB_MD_PHY_ADR_WIDTH 16
1540 
1541 /* MD_ID_REG: PHY management ID register */
1542 #define FR_AB_MD_ID 0x00000c40
1543 #define FRF_AB_MD_PRT_ADR_LBN 11
1544 #define FRF_AB_MD_PRT_ADR_WIDTH 5
1545 #define FRF_AB_MD_DEV_ADR_LBN 6
1546 #define FRF_AB_MD_DEV_ADR_WIDTH 5
1547 
1548 /* MD_STAT_REG: PHY management status & mask register */
1549 #define FR_AB_MD_STAT 0x00000c50
1550 #define FRF_AB_MD_PINT_LBN 4
1551 #define FRF_AB_MD_PINT_WIDTH 1
1552 #define FRF_AB_MD_DONE_LBN 3
1553 #define FRF_AB_MD_DONE_WIDTH 1
1554 #define FRF_AB_MD_BSERR_LBN 2
1555 #define FRF_AB_MD_BSERR_WIDTH 1
1556 #define FRF_AB_MD_LNFL_LBN 1
1557 #define FRF_AB_MD_LNFL_WIDTH 1
1558 #define FRF_AB_MD_BSY_LBN 0
1559 #define FRF_AB_MD_BSY_WIDTH 1
1560 
1561 /* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */
1562 #define FR_AB_MAC_STAT_DMA 0x00000c60
1563 #define FRF_AB_MAC_STAT_DMA_CMD_LBN 48
1564 #define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
1565 #define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
1566 #define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
1567 
1568 /* MAC_CTRL_REG: Port MAC control register */
1569 #define FR_AB_MAC_CTRL 0x00000c80
1570 #define FRF_AB_MAC_XOFF_VAL_LBN 16
1571 #define FRF_AB_MAC_XOFF_VAL_WIDTH 16
1572 #define FRF_BB_TXFIFO_DRAIN_EN_LBN 7
1573 #define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
1574 #define FRF_AB_MAC_XG_DISTXCRC_LBN 5
1575 #define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
1576 #define FRF_AB_MAC_BCAD_ACPT_LBN 4
1577 #define FRF_AB_MAC_BCAD_ACPT_WIDTH 1
1578 #define FRF_AB_MAC_UC_PROM_LBN 3
1579 #define FRF_AB_MAC_UC_PROM_WIDTH 1
1580 #define FRF_AB_MAC_LINK_STATUS_LBN 2
1581 #define FRF_AB_MAC_LINK_STATUS_WIDTH 1
1582 #define FRF_AB_MAC_SPEED_LBN 0
1583 #define FRF_AB_MAC_SPEED_WIDTH 2
1584 #define FFE_AB_MAC_SPEED_10G 3
1585 #define FFE_AB_MAC_SPEED_1G 2
1586 #define FFE_AB_MAC_SPEED_100M 1
1587 #define FFE_AB_MAC_SPEED_10M 0
1588 
1589 /* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */
1590 #define FR_BB_GEN_MODE 0x00000c90
1591 #define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
1592 #define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
1593 #define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
1594 #define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
1595 #define FRF_BB_XFP_PHY_INT_MASK_LBN 1
1596 #define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
1597 #define FRF_BB_XG_PHY_INT_MASK_LBN 0
1598 #define FRF_BB_XG_PHY_INT_MASK_WIDTH 1
1599 
1600 /* MAC_MC_HASH_REG0: Multicast address hash table */
1601 #define FR_AB_MAC_MC_HASH_REG0 0x00000ca0
1602 #define FRF_AB_MAC_MCAST_HASH0_LBN 0
1603 #define FRF_AB_MAC_MCAST_HASH0_WIDTH 128
1604 
1605 /* MAC_MC_HASH_REG1: Multicast address hash table */
1606 #define FR_AB_MAC_MC_HASH_REG1 0x00000cb0
1607 #define FRF_AB_MAC_MCAST_HASH1_LBN 0
1608 #define FRF_AB_MAC_MCAST_HASH1_WIDTH 128
1609 
1610 /* GM_CFG1_REG: GMAC configuration register 1 */
1611 #define FR_AB_GM_CFG1 0x00000e00
1612 #define FRF_AB_GM_SW_RST_LBN 31
1613 #define FRF_AB_GM_SW_RST_WIDTH 1
1614 #define FRF_AB_GM_SIM_RST_LBN 30
1615 #define FRF_AB_GM_SIM_RST_WIDTH 1
1616 #define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
1617 #define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
1618 #define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
1619 #define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
1620 #define FRF_AB_GM_RST_RX_FUNC_LBN 17
1621 #define FRF_AB_GM_RST_RX_FUNC_WIDTH 1
1622 #define FRF_AB_GM_RST_TX_FUNC_LBN 16
1623 #define FRF_AB_GM_RST_TX_FUNC_WIDTH 1
1624 #define FRF_AB_GM_LOOP_LBN 8
1625 #define FRF_AB_GM_LOOP_WIDTH 1
1626 #define FRF_AB_GM_RX_FC_EN_LBN 5
1627 #define FRF_AB_GM_RX_FC_EN_WIDTH 1
1628 #define FRF_AB_GM_TX_FC_EN_LBN 4
1629 #define FRF_AB_GM_TX_FC_EN_WIDTH 1
1630 #define FRF_AB_GM_SYNC_RXEN_LBN 3
1631 #define FRF_AB_GM_SYNC_RXEN_WIDTH 1
1632 #define FRF_AB_GM_RX_EN_LBN 2
1633 #define FRF_AB_GM_RX_EN_WIDTH 1
1634 #define FRF_AB_GM_SYNC_TXEN_LBN 1
1635 #define FRF_AB_GM_SYNC_TXEN_WIDTH 1
1636 #define FRF_AB_GM_TX_EN_LBN 0
1637 #define FRF_AB_GM_TX_EN_WIDTH 1
1638 
1639 /* GM_CFG2_REG: GMAC configuration register 2 */
1640 #define FR_AB_GM_CFG2 0x00000e10
1641 #define FRF_AB_GM_PAMBL_LEN_LBN 12
1642 #define FRF_AB_GM_PAMBL_LEN_WIDTH 4
1643 #define FRF_AB_GM_IF_MODE_LBN 8
1644 #define FRF_AB_GM_IF_MODE_WIDTH 2
1645 #define FFE_AB_IF_MODE_BYTE_MODE 2
1646 #define FFE_AB_IF_MODE_NIBBLE_MODE 1
1647 #define FRF_AB_GM_HUGE_FRM_EN_LBN 5
1648 #define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
1649 #define FRF_AB_GM_LEN_CHK_LBN 4
1650 #define FRF_AB_GM_LEN_CHK_WIDTH 1
1651 #define FRF_AB_GM_PAD_CRC_EN_LBN 2
1652 #define FRF_AB_GM_PAD_CRC_EN_WIDTH 1
1653 #define FRF_AB_GM_CRC_EN_LBN 1
1654 #define FRF_AB_GM_CRC_EN_WIDTH 1
1655 #define FRF_AB_GM_FD_LBN 0
1656 #define FRF_AB_GM_FD_WIDTH 1
1657 
1658 /* GM_IPG_REG: GMAC IPG register */
1659 #define FR_AB_GM_IPG 0x00000e20
1660 #define FRF_AB_GM_NONB2B_IPG1_LBN 24
1661 #define FRF_AB_GM_NONB2B_IPG1_WIDTH 7
1662 #define FRF_AB_GM_NONB2B_IPG2_LBN 16
1663 #define FRF_AB_GM_NONB2B_IPG2_WIDTH 7
1664 #define FRF_AB_GM_MIN_IPG_ENF_LBN 8
1665 #define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
1666 #define FRF_AB_GM_B2B_IPG_LBN 0
1667 #define FRF_AB_GM_B2B_IPG_WIDTH 7
1668 
1669 /* GM_HD_REG: GMAC half duplex register */
1670 #define FR_AB_GM_HD 0x00000e30
1671 #define FRF_AB_GM_ALT_BOFF_VAL_LBN 20
1672 #define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
1673 #define FRF_AB_GM_ALT_BOFF_EN_LBN 19
1674 #define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
1675 #define FRF_AB_GM_BP_NO_BOFF_LBN 18
1676 #define FRF_AB_GM_BP_NO_BOFF_WIDTH 1
1677 #define FRF_AB_GM_DIS_BOFF_LBN 17
1678 #define FRF_AB_GM_DIS_BOFF_WIDTH 1
1679 #define FRF_AB_GM_EXDEF_TX_EN_LBN 16
1680 #define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
1681 #define FRF_AB_GM_RTRY_LIMIT_LBN 12
1682 #define FRF_AB_GM_RTRY_LIMIT_WIDTH 4
1683 #define FRF_AB_GM_COL_WIN_LBN 0
1684 #define FRF_AB_GM_COL_WIN_WIDTH 10
1685 
1686 /* GM_MAX_FLEN_REG: GMAC maximum frame length register */
1687 #define FR_AB_GM_MAX_FLEN 0x00000e40
1688 #define FRF_AB_GM_MAX_FLEN_LBN 0
1689 #define FRF_AB_GM_MAX_FLEN_WIDTH 16
1690 
1691 /* GM_TEST_REG: GMAC test register */
1692 #define FR_AB_GM_TEST 0x00000e70
1693 #define FRF_AB_GM_MAX_BOFF_LBN 3
1694 #define FRF_AB_GM_MAX_BOFF_WIDTH 1
1695 #define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
1696 #define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
1697 #define FRF_AB_GM_TEST_PAUSE_LBN 1
1698 #define FRF_AB_GM_TEST_PAUSE_WIDTH 1
1699 #define FRF_AB_GM_SHORT_SLOT_LBN 0
1700 #define FRF_AB_GM_SHORT_SLOT_WIDTH 1
1701 
1702 /* GM_ADR1_REG: GMAC station address register 1 */
1703 #define FR_AB_GM_ADR1 0x00000f00
1704 #define FRF_AB_GM_ADR_B0_LBN 24
1705 #define FRF_AB_GM_ADR_B0_WIDTH 8
1706 #define FRF_AB_GM_ADR_B1_LBN 16
1707 #define FRF_AB_GM_ADR_B1_WIDTH 8
1708 #define FRF_AB_GM_ADR_B2_LBN 8
1709 #define FRF_AB_GM_ADR_B2_WIDTH 8
1710 #define FRF_AB_GM_ADR_B3_LBN 0
1711 #define FRF_AB_GM_ADR_B3_WIDTH 8
1712 
1713 /* GM_ADR2_REG: GMAC station address register 2 */
1714 #define FR_AB_GM_ADR2 0x00000f10
1715 #define FRF_AB_GM_ADR_B4_LBN 24
1716 #define FRF_AB_GM_ADR_B4_WIDTH 8
1717 #define FRF_AB_GM_ADR_B5_LBN 16
1718 #define FRF_AB_GM_ADR_B5_WIDTH 8
1719 
1720 /* GMF_CFG0_REG: GMAC FIFO configuration register 0 */
1721 #define FR_AB_GMF_CFG0 0x00000f20
1722 #define FRF_AB_GMF_FTFENRPLY_LBN 20
1723 #define FRF_AB_GMF_FTFENRPLY_WIDTH 1
1724 #define FRF_AB_GMF_STFENRPLY_LBN 19
1725 #define FRF_AB_GMF_STFENRPLY_WIDTH 1
1726 #define FRF_AB_GMF_FRFENRPLY_LBN 18
1727 #define FRF_AB_GMF_FRFENRPLY_WIDTH 1
1728 #define FRF_AB_GMF_SRFENRPLY_LBN 17
1729 #define FRF_AB_GMF_SRFENRPLY_WIDTH 1
1730 #define FRF_AB_GMF_WTMENRPLY_LBN 16
1731 #define FRF_AB_GMF_WTMENRPLY_WIDTH 1
1732 #define FRF_AB_GMF_FTFENREQ_LBN 12
1733 #define FRF_AB_GMF_FTFENREQ_WIDTH 1
1734 #define FRF_AB_GMF_STFENREQ_LBN 11
1735 #define FRF_AB_GMF_STFENREQ_WIDTH 1
1736 #define FRF_AB_GMF_FRFENREQ_LBN 10
1737 #define FRF_AB_GMF_FRFENREQ_WIDTH 1
1738 #define FRF_AB_GMF_SRFENREQ_LBN 9
1739 #define FRF_AB_GMF_SRFENREQ_WIDTH 1
1740 #define FRF_AB_GMF_WTMENREQ_LBN 8
1741 #define FRF_AB_GMF_WTMENREQ_WIDTH 1
1742 #define FRF_AB_GMF_HSTRSTFT_LBN 4
1743 #define FRF_AB_GMF_HSTRSTFT_WIDTH 1
1744 #define FRF_AB_GMF_HSTRSTST_LBN 3
1745 #define FRF_AB_GMF_HSTRSTST_WIDTH 1
1746 #define FRF_AB_GMF_HSTRSTFR_LBN 2
1747 #define FRF_AB_GMF_HSTRSTFR_WIDTH 1
1748 #define FRF_AB_GMF_HSTRSTSR_LBN 1
1749 #define FRF_AB_GMF_HSTRSTSR_WIDTH 1
1750 #define FRF_AB_GMF_HSTRSTWT_LBN 0
1751 #define FRF_AB_GMF_HSTRSTWT_WIDTH 1
1752 
1753 /* GMF_CFG1_REG: GMAC FIFO configuration register 1 */
1754 #define FR_AB_GMF_CFG1 0x00000f30
1755 #define FRF_AB_GMF_CFGFRTH_LBN 16
1756 #define FRF_AB_GMF_CFGFRTH_WIDTH 5
1757 #define FRF_AB_GMF_CFGXOFFRTX_LBN 0
1758 #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
1759 
1760 /* GMF_CFG2_REG: GMAC FIFO configuration register 2 */
1761 #define FR_AB_GMF_CFG2 0x00000f40
1762 #define FRF_AB_GMF_CFGHWM_LBN 16
1763 #define FRF_AB_GMF_CFGHWM_WIDTH 6
1764 #define FRF_AB_GMF_CFGLWM_LBN 0
1765 #define FRF_AB_GMF_CFGLWM_WIDTH 6
1766 
1767 /* GMF_CFG3_REG: GMAC FIFO configuration register 3 */
1768 #define FR_AB_GMF_CFG3 0x00000f50
1769 #define FRF_AB_GMF_CFGHWMFT_LBN 16
1770 #define FRF_AB_GMF_CFGHWMFT_WIDTH 6
1771 #define FRF_AB_GMF_CFGFTTH_LBN 0
1772 #define FRF_AB_GMF_CFGFTTH_WIDTH 6
1773 
1774 /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
1775 #define FR_AB_GMF_CFG4 0x00000f60
1776 #define FRF_AB_GMF_HSTFLTRFRM_LBN 0
1777 #define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
1778 
1779 /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
1780 #define FR_AB_GMF_CFG5 0x00000f70
1781 #define FRF_AB_GMF_CFGHDPLX_LBN 22
1782 #define FRF_AB_GMF_CFGHDPLX_WIDTH 1
1783 #define FRF_AB_GMF_SRFULL_LBN 21
1784 #define FRF_AB_GMF_SRFULL_WIDTH 1
1785 #define FRF_AB_GMF_HSTSRFULLCLR_LBN 20
1786 #define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
1787 #define FRF_AB_GMF_CFGBYTMODE_LBN 19
1788 #define FRF_AB_GMF_CFGBYTMODE_WIDTH 1
1789 #define FRF_AB_GMF_HSTDRPLT64_LBN 18
1790 #define FRF_AB_GMF_HSTDRPLT64_WIDTH 1
1791 #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
1792 #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
1793 
1794 /* TX_SRC_MAC_TBL: Transmit IP source address filter table */
1795 #define FR_BB_TX_SRC_MAC_TBL 0x00001000
1796 #define FR_BB_TX_SRC_MAC_TBL_STEP 16
1797 #define FR_BB_TX_SRC_MAC_TBL_ROWS 16
1798 #define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
1799 #define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
1800 #define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
1801 #define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
1802 
1803 /* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */
1804 #define FR_BB_TX_SRC_MAC_CTL 0x00001100
1805 #define FRF_BB_TX_SRC_DROP_CTR_LBN 16
1806 #define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
1807 #define FRF_BB_TX_SRC_FLTR_EN_LBN 15
1808 #define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
1809 #define FRF_BB_TX_DROP_CTR_CLR_LBN 12
1810 #define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
1811 #define FRF_BB_TX_MAC_QID_SEL_LBN 0
1812 #define FRF_BB_TX_MAC_QID_SEL_WIDTH 3
1813 
1814 /* XM_ADR_LO_REG: XGMAC address register low */
1815 #define FR_AB_XM_ADR_LO 0x00001200
1816 #define FRF_AB_XM_ADR_LO_LBN 0
1817 #define FRF_AB_XM_ADR_LO_WIDTH 32
1818 
1819 /* XM_ADR_HI_REG: XGMAC address register high */
1820 #define FR_AB_XM_ADR_HI 0x00001210
1821 #define FRF_AB_XM_ADR_HI_LBN 0
1822 #define FRF_AB_XM_ADR_HI_WIDTH 16
1823 
1824 /* XM_GLB_CFG_REG: XGMAC global configuration */
1825 #define FR_AB_XM_GLB_CFG 0x00001220
1826 #define FRF_AB_XM_RMTFLT_GEN_LBN 17
1827 #define FRF_AB_XM_RMTFLT_GEN_WIDTH 1
1828 #define FRF_AB_XM_DEBUG_MODE_LBN 16
1829 #define FRF_AB_XM_DEBUG_MODE_WIDTH 1
1830 #define FRF_AB_XM_RX_STAT_EN_LBN 11
1831 #define FRF_AB_XM_RX_STAT_EN_WIDTH 1
1832 #define FRF_AB_XM_TX_STAT_EN_LBN 10
1833 #define FRF_AB_XM_TX_STAT_EN_WIDTH 1
1834 #define FRF_AB_XM_RX_JUMBO_MODE_LBN 6
1835 #define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
1836 #define FRF_AB_XM_WAN_MODE_LBN 5
1837 #define FRF_AB_XM_WAN_MODE_WIDTH 1
1838 #define FRF_AB_XM_INTCLR_MODE_LBN 3
1839 #define FRF_AB_XM_INTCLR_MODE_WIDTH 1
1840 #define FRF_AB_XM_CORE_RST_LBN 0
1841 #define FRF_AB_XM_CORE_RST_WIDTH 1
1842 
1843 /* XM_TX_CFG_REG: XGMAC transmit configuration */
1844 #define FR_AB_XM_TX_CFG 0x00001230
1845 #define FRF_AB_XM_TX_PROG_LBN 24
1846 #define FRF_AB_XM_TX_PROG_WIDTH 1
1847 #define FRF_AB_XM_IPG_LBN 16
1848 #define FRF_AB_XM_IPG_WIDTH 4
1849 #define FRF_AB_XM_FCNTL_LBN 10
1850 #define FRF_AB_XM_FCNTL_WIDTH 1
1851 #define FRF_AB_XM_TXCRC_LBN 8
1852 #define FRF_AB_XM_TXCRC_WIDTH 1
1853 #define FRF_AB_XM_EDRC_LBN 6
1854 #define FRF_AB_XM_EDRC_WIDTH 1
1855 #define FRF_AB_XM_AUTO_PAD_LBN 5
1856 #define FRF_AB_XM_AUTO_PAD_WIDTH 1
1857 #define FRF_AB_XM_TX_PRMBL_LBN 2
1858 #define FRF_AB_XM_TX_PRMBL_WIDTH 1
1859 #define FRF_AB_XM_TXEN_LBN 1
1860 #define FRF_AB_XM_TXEN_WIDTH 1
1861 #define FRF_AB_XM_TX_RST_LBN 0
1862 #define FRF_AB_XM_TX_RST_WIDTH 1
1863 
1864 /* XM_RX_CFG_REG: XGMAC receive configuration */
1865 #define FR_AB_XM_RX_CFG 0x00001240
1866 #define FRF_AB_XM_PASS_LENERR_LBN 26
1867 #define FRF_AB_XM_PASS_LENERR_WIDTH 1
1868 #define FRF_AB_XM_PASS_CRC_ERR_LBN 25
1869 #define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
1870 #define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
1871 #define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
1872 #define FRF_AB_XM_REJ_BCAST_LBN 20
1873 #define FRF_AB_XM_REJ_BCAST_WIDTH 1
1874 #define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
1875 #define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
1876 #define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
1877 #define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
1878 #define FRF_AB_XM_AUTO_DEPAD_LBN 8
1879 #define FRF_AB_XM_AUTO_DEPAD_WIDTH 1
1880 #define FRF_AB_XM_RXCRC_LBN 3
1881 #define FRF_AB_XM_RXCRC_WIDTH 1
1882 #define FRF_AB_XM_RX_PRMBL_LBN 2
1883 #define FRF_AB_XM_RX_PRMBL_WIDTH 1
1884 #define FRF_AB_XM_RXEN_LBN 1
1885 #define FRF_AB_XM_RXEN_WIDTH 1
1886 #define FRF_AB_XM_RX_RST_LBN 0
1887 #define FRF_AB_XM_RX_RST_WIDTH 1
1888 
1889 /* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */
1890 #define FR_AB_XM_MGT_INT_MASK 0x00001250
1891 #define FRF_AB_XM_MSK_STA_INTR_LBN 16
1892 #define FRF_AB_XM_MSK_STA_INTR_WIDTH 1
1893 #define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
1894 #define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
1895 #define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
1896 #define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
1897 #define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
1898 #define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
1899 #define FRF_AB_XM_MSK_RMTFLT_LBN 1
1900 #define FRF_AB_XM_MSK_RMTFLT_WIDTH 1
1901 #define FRF_AB_XM_MSK_LCLFLT_LBN 0
1902 #define FRF_AB_XM_MSK_LCLFLT_WIDTH 1
1903 
1904 /* XM_FC_REG: XGMAC flow control register */
1905 #define FR_AB_XM_FC 0x00001270
1906 #define FRF_AB_XM_PAUSE_TIME_LBN 16
1907 #define FRF_AB_XM_PAUSE_TIME_WIDTH 16
1908 #define FRF_AB_XM_RX_MAC_STAT_LBN 11
1909 #define FRF_AB_XM_RX_MAC_STAT_WIDTH 1
1910 #define FRF_AB_XM_TX_MAC_STAT_LBN 10
1911 #define FRF_AB_XM_TX_MAC_STAT_WIDTH 1
1912 #define FRF_AB_XM_MCNTL_PASS_LBN 8
1913 #define FRF_AB_XM_MCNTL_PASS_WIDTH 2
1914 #define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
1915 #define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
1916 #define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
1917 #define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
1918 #define FRF_AB_XM_ZPAUSE_LBN 2
1919 #define FRF_AB_XM_ZPAUSE_WIDTH 1
1920 #define FRF_AB_XM_XMIT_PAUSE_LBN 1
1921 #define FRF_AB_XM_XMIT_PAUSE_WIDTH 1
1922 #define FRF_AB_XM_DIS_FCNTL_LBN 0
1923 #define FRF_AB_XM_DIS_FCNTL_WIDTH 1
1924 
1925 /* XM_PAUSE_TIME_REG: XGMAC pause time register */
1926 #define FR_AB_XM_PAUSE_TIME 0x00001290
1927 #define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
1928 #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
1929 #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
1930 #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
1931 
1932 /* XM_TX_PARAM_REG: XGMAC transmit parameter register */
1933 #define FR_AB_XM_TX_PARAM 0x000012d0
1934 #define FRF_AB_XM_TX_JUMBO_MODE_LBN 31
1935 #define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
1936 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
1937 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
1938 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
1939 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
1940 #define FRF_AB_XM_PAD_CHAR_LBN 0
1941 #define FRF_AB_XM_PAD_CHAR_WIDTH 8
1942 
1943 /* XM_RX_PARAM_REG: XGMAC receive parameter register */
1944 #define FR_AB_XM_RX_PARAM 0x000012e0
1945 #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
1946 #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
1947 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
1948 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
1949 
1950 /* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */
1951 #define FR_AB_XM_MGT_INT_MSK 0x000012f0
1952 #define FRF_AB_XM_STAT_CNTR_OF_LBN 9
1953 #define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
1954 #define FRF_AB_XM_STAT_CNTR_HF_LBN 8
1955 #define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
1956 #define FRF_AB_XM_PRMBLE_ERR_LBN 2
1957 #define FRF_AB_XM_PRMBLE_ERR_WIDTH 1
1958 #define FRF_AB_XM_RMTFLT_LBN 1
1959 #define FRF_AB_XM_RMTFLT_WIDTH 1
1960 #define FRF_AB_XM_LCLFLT_LBN 0
1961 #define FRF_AB_XM_LCLFLT_WIDTH 1
1962 
1963 /* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */
1964 #define FR_AB_XX_PWR_RST 0x00001300
1965 #define FRF_AB_XX_PWRDND_SIG_LBN 31
1966 #define FRF_AB_XX_PWRDND_SIG_WIDTH 1
1967 #define FRF_AB_XX_PWRDNC_SIG_LBN 30
1968 #define FRF_AB_XX_PWRDNC_SIG_WIDTH 1
1969 #define FRF_AB_XX_PWRDNB_SIG_LBN 29
1970 #define FRF_AB_XX_PWRDNB_SIG_WIDTH 1
1971 #define FRF_AB_XX_PWRDNA_SIG_LBN 28
1972 #define FRF_AB_XX_PWRDNA_SIG_WIDTH 1
1973 #define FRF_AB_XX_SIM_MODE_LBN 27
1974 #define FRF_AB_XX_SIM_MODE_WIDTH 1
1975 #define FRF_AB_XX_RSTPLLCD_SIG_LBN 25
1976 #define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1
1977 #define FRF_AB_XX_RSTPLLAB_SIG_LBN 24
1978 #define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1
1979 #define FRF_AB_XX_RESETD_SIG_LBN 23
1980 #define FRF_AB_XX_RESETD_SIG_WIDTH 1
1981 #define FRF_AB_XX_RESETC_SIG_LBN 22
1982 #define FRF_AB_XX_RESETC_SIG_WIDTH 1
1983 #define FRF_AB_XX_RESETB_SIG_LBN 21
1984 #define FRF_AB_XX_RESETB_SIG_WIDTH 1
1985 #define FRF_AB_XX_RESETA_SIG_LBN 20
1986 #define FRF_AB_XX_RESETA_SIG_WIDTH 1
1987 #define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18
1988 #define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1
1989 #define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17
1990 #define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1
1991 #define FRF_AB_XX_SD_RST_ACT_LBN 16
1992 #define FRF_AB_XX_SD_RST_ACT_WIDTH 1
1993 #define FRF_AB_XX_PWRDND_EN_LBN 15
1994 #define FRF_AB_XX_PWRDND_EN_WIDTH 1
1995 #define FRF_AB_XX_PWRDNC_EN_LBN 14
1996 #define FRF_AB_XX_PWRDNC_EN_WIDTH 1
1997 #define FRF_AB_XX_PWRDNB_EN_LBN 13
1998 #define FRF_AB_XX_PWRDNB_EN_WIDTH 1
1999 #define FRF_AB_XX_PWRDNA_EN_LBN 12
2000 #define FRF_AB_XX_PWRDNA_EN_WIDTH 1
2001 #define FRF_AB_XX_RSTPLLCD_EN_LBN 9
2002 #define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1
2003 #define FRF_AB_XX_RSTPLLAB_EN_LBN 8
2004 #define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1
2005 #define FRF_AB_XX_RESETD_EN_LBN 7
2006 #define FRF_AB_XX_RESETD_EN_WIDTH 1
2007 #define FRF_AB_XX_RESETC_EN_LBN 6
2008 #define FRF_AB_XX_RESETC_EN_WIDTH 1
2009 #define FRF_AB_XX_RESETB_EN_LBN 5
2010 #define FRF_AB_XX_RESETB_EN_WIDTH 1
2011 #define FRF_AB_XX_RESETA_EN_LBN 4
2012 #define FRF_AB_XX_RESETA_EN_WIDTH 1
2013 #define FRF_AB_XX_RSTXGXSRX_EN_LBN 2
2014 #define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1
2015 #define FRF_AB_XX_RSTXGXSTX_EN_LBN 1
2016 #define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1
2017 #define FRF_AB_XX_RST_XX_EN_LBN 0
2018 #define FRF_AB_XX_RST_XX_EN_WIDTH 1
2019 
2020 /* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */
2021 #define FR_AB_XX_SD_CTL 0x00001310
2022 #define FRF_AB_XX_TERMADJ1_LBN 17
2023 #define FRF_AB_XX_TERMADJ1_WIDTH 1
2024 #define FRF_AB_XX_TERMADJ0_LBN 16
2025 #define FRF_AB_XX_TERMADJ0_WIDTH 1
2026 #define FRF_AB_XX_HIDRVD_LBN 15
2027 #define FRF_AB_XX_HIDRVD_WIDTH 1
2028 #define FRF_AB_XX_LODRVD_LBN 14
2029 #define FRF_AB_XX_LODRVD_WIDTH 1
2030 #define FRF_AB_XX_HIDRVC_LBN 13
2031 #define FRF_AB_XX_HIDRVC_WIDTH 1
2032 #define FRF_AB_XX_LODRVC_LBN 12
2033 #define FRF_AB_XX_LODRVC_WIDTH 1
2034 #define FRF_AB_XX_HIDRVB_LBN 11
2035 #define FRF_AB_XX_HIDRVB_WIDTH 1
2036 #define FRF_AB_XX_LODRVB_LBN 10
2037 #define FRF_AB_XX_LODRVB_WIDTH 1
2038 #define FRF_AB_XX_HIDRVA_LBN 9
2039 #define FRF_AB_XX_HIDRVA_WIDTH 1
2040 #define FRF_AB_XX_LODRVA_LBN 8
2041 #define FRF_AB_XX_LODRVA_WIDTH 1
2042 #define FRF_AB_XX_LPBKD_LBN 3
2043 #define FRF_AB_XX_LPBKD_WIDTH 1
2044 #define FRF_AB_XX_LPBKC_LBN 2
2045 #define FRF_AB_XX_LPBKC_WIDTH 1
2046 #define FRF_AB_XX_LPBKB_LBN 1
2047 #define FRF_AB_XX_LPBKB_WIDTH 1
2048 #define FRF_AB_XX_LPBKA_LBN 0
2049 #define FRF_AB_XX_LPBKA_WIDTH 1
2050 
2051 /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2052 #define FR_AB_XX_TXDRV_CTL 0x00001320
2053 #define FRF_AB_XX_DEQD_LBN 28
2054 #define FRF_AB_XX_DEQD_WIDTH 4
2055 #define FRF_AB_XX_DEQC_LBN 24
2056 #define FRF_AB_XX_DEQC_WIDTH 4
2057 #define FRF_AB_XX_DEQB_LBN 20
2058 #define FRF_AB_XX_DEQB_WIDTH 4
2059 #define FRF_AB_XX_DEQA_LBN 16
2060 #define FRF_AB_XX_DEQA_WIDTH 4
2061 #define FRF_AB_XX_DTXD_LBN 12
2062 #define FRF_AB_XX_DTXD_WIDTH 4
2063 #define FRF_AB_XX_DTXC_LBN 8
2064 #define FRF_AB_XX_DTXC_WIDTH 4
2065 #define FRF_AB_XX_DTXB_LBN 4
2066 #define FRF_AB_XX_DTXB_WIDTH 4
2067 #define FRF_AB_XX_DTXA_LBN 0
2068 #define FRF_AB_XX_DTXA_WIDTH 4
2069 
2070 /* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */
2071 #define FR_AB_XX_PRBS_CTL 0x00001330
2072 #define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30
2073 #define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2
2074 #define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29
2075 #define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1
2076 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28
2077 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1
2078 #define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26
2079 #define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2
2080 #define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25
2081 #define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1
2082 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24
2083 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1
2084 #define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22
2085 #define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2
2086 #define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21
2087 #define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1
2088 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20
2089 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1
2090 #define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18
2091 #define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2
2092 #define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17
2093 #define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1
2094 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2095 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1
2096 #define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14
2097 #define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2
2098 #define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13
2099 #define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1
2100 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2101 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1
2102 #define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10
2103 #define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2
2104 #define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9
2105 #define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1
2106 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8
2107 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1
2108 #define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6
2109 #define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2
2110 #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2111 #define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1
2112 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4
2113 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1
2114 #define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2
2115 #define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2
2116 #define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1
2117 #define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1
2118 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
2119 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1
2120 
2121 /* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */
2122 #define FR_AB_XX_PRBS_CHK 0x00001340
2123 #define FRF_AB_XX_REV_LB_EN_LBN 16
2124 #define FRF_AB_XX_REV_LB_EN_WIDTH 1
2125 #define FRF_AB_XX_CH3_DEG_DET_LBN 15
2126 #define FRF_AB_XX_CH3_DEG_DET_WIDTH 1
2127 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14
2128 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1
2129 #define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13
2130 #define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1
2131 #define FRF_AB_XX_CH3_ERR_CHK_LBN 12
2132 #define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1
2133 #define FRF_AB_XX_CH2_DEG_DET_LBN 11
2134 #define FRF_AB_XX_CH2_DEG_DET_WIDTH 1
2135 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10
2136 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1
2137 #define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9
2138 #define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1
2139 #define FRF_AB_XX_CH2_ERR_CHK_LBN 8
2140 #define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1
2141 #define FRF_AB_XX_CH1_DEG_DET_LBN 7
2142 #define FRF_AB_XX_CH1_DEG_DET_WIDTH 1
2143 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6
2144 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1
2145 #define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
2146 #define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1
2147 #define FRF_AB_XX_CH1_ERR_CHK_LBN 4
2148 #define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1
2149 #define FRF_AB_XX_CH0_DEG_DET_LBN 3
2150 #define FRF_AB_XX_CH0_DEG_DET_WIDTH 1
2151 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2
2152 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1
2153 #define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1
2154 #define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1
2155 #define FRF_AB_XX_CH0_ERR_CHK_LBN 0
2156 #define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1
2157 
2158 /* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */
2159 #define FR_AB_XX_PRBS_ERR 0x00001350
2160 #define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24
2161 #define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8
2162 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
2163 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8
2164 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8
2165 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8
2166 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
2167 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8
2168 
2169 /* XX_CORE_STAT_REG: XAUI XGXS core status register */
2170 #define FR_AB_XX_CORE_STAT 0x00001360
2171 #define FRF_AB_XX_FORCE_SIG3_LBN 31
2172 #define FRF_AB_XX_FORCE_SIG3_WIDTH 1
2173 #define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30
2174 #define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1
2175 #define FRF_AB_XX_FORCE_SIG2_LBN 29
2176 #define FRF_AB_XX_FORCE_SIG2_WIDTH 1
2177 #define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28
2178 #define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1
2179 #define FRF_AB_XX_FORCE_SIG1_LBN 27
2180 #define FRF_AB_XX_FORCE_SIG1_WIDTH 1
2181 #define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26
2182 #define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1
2183 #define FRF_AB_XX_FORCE_SIG0_LBN 25
2184 #define FRF_AB_XX_FORCE_SIG0_WIDTH 1
2185 #define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24
2186 #define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1
2187 #define FRF_AB_XX_XGXS_LB_EN_LBN 23
2188 #define FRF_AB_XX_XGXS_LB_EN_WIDTH 1
2189 #define FRF_AB_XX_XGMII_LB_EN_LBN 22
2190 #define FRF_AB_XX_XGMII_LB_EN_WIDTH 1
2191 #define FRF_AB_XX_MATCH_FAULT_LBN 21
2192 #define FRF_AB_XX_MATCH_FAULT_WIDTH 1
2193 #define FRF_AB_XX_ALIGN_DONE_LBN 20
2194 #define FRF_AB_XX_ALIGN_DONE_WIDTH 1
2195 #define FRF_AB_XX_SYNC_STAT3_LBN 19
2196 #define FRF_AB_XX_SYNC_STAT3_WIDTH 1
2197 #define FRF_AB_XX_SYNC_STAT2_LBN 18
2198 #define FRF_AB_XX_SYNC_STAT2_WIDTH 1
2199 #define FRF_AB_XX_SYNC_STAT1_LBN 17
2200 #define FRF_AB_XX_SYNC_STAT1_WIDTH 1
2201 #define FRF_AB_XX_SYNC_STAT0_LBN 16
2202 #define FRF_AB_XX_SYNC_STAT0_WIDTH 1
2203 #define FRF_AB_XX_COMMA_DET_CH3_LBN 15
2204 #define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1
2205 #define FRF_AB_XX_COMMA_DET_CH2_LBN 14
2206 #define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1
2207 #define FRF_AB_XX_COMMA_DET_CH1_LBN 13
2208 #define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1
2209 #define FRF_AB_XX_COMMA_DET_CH0_LBN 12
2210 #define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1
2211 #define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11
2212 #define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1
2213 #define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10
2214 #define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1
2215 #define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9
2216 #define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1
2217 #define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8
2218 #define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1
2219 #define FRF_AB_XX_CHAR_ERR_CH3_LBN 7
2220 #define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1
2221 #define FRF_AB_XX_CHAR_ERR_CH2_LBN 6
2222 #define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1
2223 #define FRF_AB_XX_CHAR_ERR_CH1_LBN 5
2224 #define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1
2225 #define FRF_AB_XX_CHAR_ERR_CH0_LBN 4
2226 #define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1
2227 #define FRF_AB_XX_DISPERR_CH3_LBN 3
2228 #define FRF_AB_XX_DISPERR_CH3_WIDTH 1
2229 #define FRF_AB_XX_DISPERR_CH2_LBN 2
2230 #define FRF_AB_XX_DISPERR_CH2_WIDTH 1
2231 #define FRF_AB_XX_DISPERR_CH1_LBN 1
2232 #define FRF_AB_XX_DISPERR_CH1_WIDTH 1
2233 #define FRF_AB_XX_DISPERR_CH0_LBN 0
2234 #define FRF_AB_XX_DISPERR_CH0_WIDTH 1
2235 
2236 /* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */
2237 #define FR_AA_RX_DESC_PTR_TBL_KER 0x00011800
2238 #define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
2239 #define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
2240 /* RX_DESC_PTR_TBL: Receive descriptor pointer table */
2241 #define FR_BZ_RX_DESC_PTR_TBL 0x00f40000
2242 #define FR_BZ_RX_DESC_PTR_TBL_STEP 16
2243 #define FR_BB_RX_DESC_PTR_TBL_ROWS 4096
2244 #define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
2245 #define FRF_CZ_RX_HDR_SPLIT_LBN 90
2246 #define FRF_CZ_RX_HDR_SPLIT_WIDTH 1
2247 #define FRF_AA_RX_RESET_LBN 89
2248 #define FRF_AA_RX_RESET_WIDTH 1
2249 #define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
2250 #define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
2251 #define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
2252 #define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
2253 #define FRF_AZ_RX_DESC_PREF_ACT_LBN 86
2254 #define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
2255 #define FRF_AZ_RX_DC_HW_RPTR_LBN 80
2256 #define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
2257 #define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
2258 #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
2259 #define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
2260 #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
2261 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
2262 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
2263 #define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
2264 #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
2265 #define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
2266 #define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
2267 #define FRF_AZ_RX_DESCQ_LABEL_LBN 5
2268 #define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
2269 #define FRF_AZ_RX_DESCQ_SIZE_LBN 3
2270 #define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
2271 #define FFE_AZ_RX_DESCQ_SIZE_4K 3
2272 #define FFE_AZ_RX_DESCQ_SIZE_2K 2
2273 #define FFE_AZ_RX_DESCQ_SIZE_1K 1
2274 #define FFE_AZ_RX_DESCQ_SIZE_512 0
2275 #define FRF_AZ_RX_DESCQ_TYPE_LBN 2
2276 #define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
2277 #define FRF_AZ_RX_DESCQ_JUMBO_LBN 1
2278 #define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
2279 #define FRF_AZ_RX_DESCQ_EN_LBN 0
2280 #define FRF_AZ_RX_DESCQ_EN_WIDTH 1
2281 
2282 /* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */
2283 #define FR_AA_TX_DESC_PTR_TBL_KER 0x00011900
2284 #define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
2285 #define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
2286 /* TX_DESC_PTR_TBL: Transmit descriptor pointer */
2287 #define FR_BZ_TX_DESC_PTR_TBL 0x00f50000
2288 #define FR_BZ_TX_DESC_PTR_TBL_STEP 16
2289 #define FR_BB_TX_DESC_PTR_TBL_ROWS 4096
2290 #define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
2291 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
2292 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
2293 #define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
2294 #define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
2295 #define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
2296 #define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
2297 #define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
2298 #define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
2299 #define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
2300 #define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
2301 #define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
2302 #define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
2303 #define FRF_AZ_TX_DESCQ_EN_LBN 88
2304 #define FRF_AZ_TX_DESCQ_EN_WIDTH 1
2305 #define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
2306 #define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
2307 #define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
2308 #define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
2309 #define FRF_AZ_TX_DC_HW_RPTR_LBN 80
2310 #define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
2311 #define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
2312 #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
2313 #define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
2314 #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
2315 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
2316 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
2317 #define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
2318 #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
2319 #define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
2320 #define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
2321 #define FRF_AZ_TX_DESCQ_LABEL_LBN 5
2322 #define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
2323 #define FRF_AZ_TX_DESCQ_SIZE_LBN 3
2324 #define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
2325 #define FFE_AZ_TX_DESCQ_SIZE_4K 3
2326 #define FFE_AZ_TX_DESCQ_SIZE_2K 2
2327 #define FFE_AZ_TX_DESCQ_SIZE_1K 1
2328 #define FFE_AZ_TX_DESCQ_SIZE_512 0
2329 #define FRF_AZ_TX_DESCQ_TYPE_LBN 1
2330 #define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
2331 #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
2332 #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
2333 
2334 /* EVQ_PTR_TBL_KER: Event queue pointer table */
2335 #define FR_AA_EVQ_PTR_TBL_KER 0x00011a00
2336 #define FR_AA_EVQ_PTR_TBL_KER_STEP 16
2337 #define FR_AA_EVQ_PTR_TBL_KER_ROWS 4
2338 /* EVQ_PTR_TBL: Event queue pointer table */
2339 #define FR_BZ_EVQ_PTR_TBL 0x00f60000
2340 #define FR_BZ_EVQ_PTR_TBL_STEP 16
2341 #define FR_CZ_EVQ_PTR_TBL_ROWS 1024
2342 #define FR_BB_EVQ_PTR_TBL_ROWS 4096
2343 #define FRF_BZ_EVQ_RPTR_IGN_LBN 40
2344 #define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
2345 #define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39
2346 #define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1
2347 #define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39
2348 #define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1
2349 #define FRF_AZ_EVQ_NXT_WPTR_LBN 24
2350 #define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
2351 #define FRF_AZ_EVQ_EN_LBN 23
2352 #define FRF_AZ_EVQ_EN_WIDTH 1
2353 #define FRF_AZ_EVQ_SIZE_LBN 20
2354 #define FRF_AZ_EVQ_SIZE_WIDTH 3
2355 #define FFE_AZ_EVQ_SIZE_32K 6
2356 #define FFE_AZ_EVQ_SIZE_16K 5
2357 #define FFE_AZ_EVQ_SIZE_8K 4
2358 #define FFE_AZ_EVQ_SIZE_4K 3
2359 #define FFE_AZ_EVQ_SIZE_2K 2
2360 #define FFE_AZ_EVQ_SIZE_1K 1
2361 #define FFE_AZ_EVQ_SIZE_512 0
2362 #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
2363 #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
2364 
2365 /* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */
2366 #define FR_AA_BUF_HALF_TBL_KER 0x00018000
2367 #define FR_AA_BUF_HALF_TBL_KER_STEP 8
2368 #define FR_AA_BUF_HALF_TBL_KER_ROWS 4096
2369 /* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */
2370 #define FR_BZ_BUF_HALF_TBL 0x00800000
2371 #define FR_BZ_BUF_HALF_TBL_STEP 8
2372 #define FR_CZ_BUF_HALF_TBL_ROWS 147456
2373 #define FR_BB_BUF_HALF_TBL_ROWS 524288
2374 #define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
2375 #define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
2376 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
2377 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
2378 #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
2379 #define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
2380 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
2381 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
2382 
2383 /* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */
2384 #define FR_AA_BUF_FULL_TBL_KER 0x00018000
2385 #define FR_AA_BUF_FULL_TBL_KER_STEP 8
2386 #define FR_AA_BUF_FULL_TBL_KER_ROWS 4096
2387 /* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */
2388 #define FR_BZ_BUF_FULL_TBL 0x00800000
2389 #define FR_BZ_BUF_FULL_TBL_STEP 8
2390 #define FR_CZ_BUF_FULL_TBL_ROWS 147456
2391 #define FR_BB_BUF_FULL_TBL_ROWS 917504
2392 #define FRF_AZ_BUF_FULL_UNUSED_LBN 51
2393 #define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
2394 #define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
2395 #define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
2396 #define FRF_AZ_BUF_ADR_REGION_LBN 48
2397 #define FRF_AZ_BUF_ADR_REGION_WIDTH 2
2398 #define FFE_AZ_BUF_ADR_REGN3 3
2399 #define FFE_AZ_BUF_ADR_REGN2 2
2400 #define FFE_AZ_BUF_ADR_REGN1 1
2401 #define FFE_AZ_BUF_ADR_REGN0 0
2402 #define FRF_AZ_BUF_ADR_FBUF_LBN 14
2403 #define FRF_AZ_BUF_ADR_FBUF_WIDTH 34
2404 #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
2405 #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
2406 
2407 /* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */
2408 #define FR_BZ_RX_FILTER_TBL0 0x00f00000
2409 #define FR_BZ_RX_FILTER_TBL0_STEP 32
2410 #define FR_BZ_RX_FILTER_TBL0_ROWS 8192
2411 /* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */
2412 #define FR_BB_RX_FILTER_TBL1 0x00f00010
2413 #define FR_BB_RX_FILTER_TBL1_STEP 32
2414 #define FR_BB_RX_FILTER_TBL1_ROWS 8192
2415 #define FRF_BZ_RSS_EN_LBN 110
2416 #define FRF_BZ_RSS_EN_WIDTH 1
2417 #define FRF_BZ_SCATTER_EN_LBN 109
2418 #define FRF_BZ_SCATTER_EN_WIDTH 1
2419 #define FRF_BZ_TCP_UDP_LBN 108
2420 #define FRF_BZ_TCP_UDP_WIDTH 1
2421 #define FRF_BZ_RXQ_ID_LBN 96
2422 #define FRF_BZ_RXQ_ID_WIDTH 12
2423 #define FRF_BZ_DEST_IP_LBN 64
2424 #define FRF_BZ_DEST_IP_WIDTH 32
2425 #define FRF_BZ_DEST_PORT_TCP_LBN 48
2426 #define FRF_BZ_DEST_PORT_TCP_WIDTH 16
2427 #define FRF_BZ_SRC_IP_LBN 16
2428 #define FRF_BZ_SRC_IP_WIDTH 32
2429 #define FRF_BZ_SRC_TCP_DEST_UDP_LBN 0
2430 #define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 16
2431 
2432 /* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */
2433 #define FR_CZ_RX_MAC_FILTER_TBL0 0x00f00010
2434 #define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
2435 #define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
2436 #define FRF_CZ_RMFT_RSS_EN_LBN 75
2437 #define FRF_CZ_RMFT_RSS_EN_WIDTH 1
2438 #define FRF_CZ_RMFT_SCATTER_EN_LBN 74
2439 #define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
2440 #define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
2441 #define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
2442 #define FRF_CZ_RMFT_RXQ_ID_LBN 61
2443 #define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
2444 #define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
2445 #define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
2446 #define FRF_CZ_RMFT_DEST_MAC_LBN 12
2447 #define FRF_CZ_RMFT_DEST_MAC_WIDTH 48
2448 #define FRF_CZ_RMFT_VLAN_ID_LBN 0
2449 #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
2450 
2451 /* TIMER_TBL: Timer table */
2452 #define FR_BZ_TIMER_TBL 0x00f70000
2453 #define FR_BZ_TIMER_TBL_STEP 16
2454 #define FR_CZ_TIMER_TBL_ROWS 1024
2455 #define FR_BB_TIMER_TBL_ROWS 4096
2456 #define FRF_CZ_TIMER_Q_EN_LBN 33
2457 #define FRF_CZ_TIMER_Q_EN_WIDTH 1
2458 #define FRF_CZ_INT_ARMD_LBN 32
2459 #define FRF_CZ_INT_ARMD_WIDTH 1
2460 #define FRF_CZ_INT_PEND_LBN 31
2461 #define FRF_CZ_INT_PEND_WIDTH 1
2462 #define FRF_CZ_HOST_NOTIFY_MODE_LBN 30
2463 #define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
2464 #define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
2465 #define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
2466 #define FRF_CZ_TIMER_MODE_LBN 14
2467 #define FRF_CZ_TIMER_MODE_WIDTH 2
2468 #define FFE_CZ_TIMER_MODE_INT_HLDOFF 3
2469 #define FFE_CZ_TIMER_MODE_TRIG_START 2
2470 #define FFE_CZ_TIMER_MODE_IMMED_START 1
2471 #define FFE_CZ_TIMER_MODE_DIS 0
2472 #define FRF_BB_TIMER_MODE_LBN 12
2473 #define FRF_BB_TIMER_MODE_WIDTH 2
2474 #define FFE_BB_TIMER_MODE_INT_HLDOFF 2
2475 #define FFE_BB_TIMER_MODE_TRIG_START 2
2476 #define FFE_BB_TIMER_MODE_IMMED_START 1
2477 #define FFE_BB_TIMER_MODE_DIS 0
2478 #define FRF_CZ_TIMER_VAL_LBN 0
2479 #define FRF_CZ_TIMER_VAL_WIDTH 14
2480 #define FRF_BB_TIMER_VAL_LBN 0
2481 #define FRF_BB_TIMER_VAL_WIDTH 12
2482 
2483 /* TX_PACE_TBL: Transmit pacing table */
2484 #define FR_BZ_TX_PACE_TBL 0x00f80000
2485 #define FR_BZ_TX_PACE_TBL_STEP 16
2486 #define FR_CZ_TX_PACE_TBL_ROWS 1024
2487 #define FR_BB_TX_PACE_TBL_ROWS 4096
2488 #define FRF_BZ_TX_PACE_LBN 0
2489 #define FRF_BZ_TX_PACE_WIDTH 5
2490 
2491 /* RX_INDIRECTION_TBL: RX Indirection Table */
2492 #define FR_BZ_RX_INDIRECTION_TBL 0x00fb0000
2493 #define FR_BZ_RX_INDIRECTION_TBL_STEP 16
2494 #define FR_BZ_RX_INDIRECTION_TBL_ROWS 128
2495 #define FRF_BZ_IT_QUEUE_LBN 0
2496 #define FRF_BZ_IT_QUEUE_WIDTH 6
2497 
2498 /* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */
2499 #define FR_CZ_TX_FILTER_TBL0 0x00fc0000
2500 #define FR_CZ_TX_FILTER_TBL0_STEP 16
2501 #define FR_CZ_TX_FILTER_TBL0_ROWS 8192
2502 #define FRF_CZ_TIFT_TCP_UDP_LBN 108
2503 #define FRF_CZ_TIFT_TCP_UDP_WIDTH 1
2504 #define FRF_CZ_TIFT_TXQ_ID_LBN 96
2505 #define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
2506 #define FRF_CZ_TIFT_DEST_IP_LBN 64
2507 #define FRF_CZ_TIFT_DEST_IP_WIDTH 32
2508 #define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
2509 #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
2510 #define FRF_CZ_TIFT_SRC_IP_LBN 16
2511 #define FRF_CZ_TIFT_SRC_IP_WIDTH 32
2512 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
2513 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
2514 
2515 /* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */
2516 #define FR_CZ_TX_MAC_FILTER_TBL0 0x00fe0000
2517 #define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
2518 #define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
2519 #define FRF_CZ_TMFT_TXQ_ID_LBN 61
2520 #define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
2521 #define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
2522 #define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
2523 #define FRF_CZ_TMFT_SRC_MAC_LBN 12
2524 #define FRF_CZ_TMFT_SRC_MAC_WIDTH 48
2525 #define FRF_CZ_TMFT_VLAN_ID_LBN 0
2526 #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
2527 
2528 /* MC_TREG_SMEM: MC Shared Memory */
2529 #define FR_CZ_MC_TREG_SMEM 0x00ff0000
2530 #define FR_CZ_MC_TREG_SMEM_STEP 4
2531 #define FR_CZ_MC_TREG_SMEM_ROWS 512
2532 #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
2533 #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
2534 
2535 /* MSIX_VECTOR_TABLE: MSIX Vector Table */
2536 #define FR_BB_MSIX_VECTOR_TABLE 0x00ff0000
2537 #define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
2538 #define FR_BB_MSIX_VECTOR_TABLE_ROWS 64
2539 /* MSIX_VECTOR_TABLE: MSIX Vector Table */
2540 #define FR_CZ_MSIX_VECTOR_TABLE 0x00000000
2541 /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
2542 #define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
2543 #define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
2544 #define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
2545 #define FRF_BZ_MSIX_VECTOR_MASK_LBN 96
2546 #define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
2547 #define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
2548 #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
2549 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
2550 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
2551 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
2552 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
2553 
2554 /* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2555 #define FR_BB_MSIX_PBA_TABLE 0x00ff2000
2556 #define FR_BZ_MSIX_PBA_TABLE_STEP 4
2557 #define FR_BB_MSIX_PBA_TABLE_ROWS 2
2558 /* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2559 #define FR_CZ_MSIX_PBA_TABLE 0x00008000
2560 /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
2561 #define FR_CZ_MSIX_PBA_TABLE_ROWS 32
2562 #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
2563 #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
2564 
2565 /* SRM_DBG_REG: SRAM debug access */
2566 #define FR_BZ_SRM_DBG 0x03000000
2567 #define FR_BZ_SRM_DBG_STEP 8
2568 #define FR_CZ_SRM_DBG_ROWS 262144
2569 #define FR_BB_SRM_DBG_ROWS 2097152
2570 #define FRF_BZ_SRM_DBG_LBN 0
2571 #define FRF_BZ_SRM_DBG_WIDTH 64
2572 
2573 /* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */
2574 #define FR_CZ_TB_MSIX_PBA_TABLE 0x00008000
2575 #define FR_CZ_TB_MSIX_PBA_TABLE_STEP 4
2576 #define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024
2577 #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0
2578 #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32
2579 
2580 /* DRIVER_EV */
2581 #define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
2582 #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
2583 #define FSE_BZ_TX_DSC_ERROR_EV 15
2584 #define FSE_BZ_RX_DSC_ERROR_EV 14
2585 #define FSE_AA_RX_RECOVER_EV 11
2586 #define FSE_AZ_TIMER_EV 10
2587 #define FSE_AZ_TX_PKT_NON_TCP_UDP 9
2588 #define FSE_AZ_WAKE_UP_EV 6
2589 #define FSE_AZ_SRM_UPD_DONE_EV 5
2590 #define FSE_AB_EVQ_NOT_EN_EV 3
2591 #define FSE_AZ_EVQ_INIT_DONE_EV 2
2592 #define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
2593 #define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
2594 #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
2595 #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
2596 
2597 /* EVENT_ENTRY */
2598 #define FSF_AZ_EV_CODE_LBN 60
2599 #define FSF_AZ_EV_CODE_WIDTH 4
2600 #define FSE_CZ_EV_CODE_MCDI_EV 12
2601 #define FSE_CZ_EV_CODE_USER_EV 8
2602 #define FSE_AZ_EV_CODE_DRV_GEN_EV 7
2603 #define FSE_AZ_EV_CODE_GLOBAL_EV 6
2604 #define FSE_AZ_EV_CODE_DRIVER_EV 5
2605 #define FSE_AZ_EV_CODE_TX_EV 2
2606 #define FSE_AZ_EV_CODE_RX_EV 0
2607 #define FSF_AZ_EV_DATA_LBN 0
2608 #define FSF_AZ_EV_DATA_WIDTH 60
2609 
2610 /* GLOBAL_EV */
2611 #define FSF_BB_GLB_EV_RX_RECOVERY_LBN 12
2612 #define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1
2613 #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 11
2614 #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
2615 #define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11
2616 #define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1
2617 #define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10
2618 #define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1
2619 #define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9
2620 #define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1
2621 #define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7
2622 #define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1
2623 
2624 /* LEGACY_INT_VEC */
2625 #define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
2626 #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
2627 #define FSF_AZ_NET_IVEC_INT_Q_LBN 40
2628 #define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
2629 #define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
2630 #define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
2631 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
2632 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
2633 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
2634 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
2635 
2636 /* MC_XGMAC_FLTR_RULE_DEF */
2637 #define FSF_CZ_MC_XFRC_MODE_LBN 416
2638 #define FSF_CZ_MC_XFRC_MODE_WIDTH 1
2639 #define FSE_CZ_MC_XFRC_MODE_LAYERED 1
2640 #define FSE_CZ_MC_XFRC_MODE_SIMPLE 0
2641 #define FSF_CZ_MC_XFRC_HASH_LBN 384
2642 #define FSF_CZ_MC_XFRC_HASH_WIDTH 32
2643 #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256
2644 #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128
2645 #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128
2646 #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128
2647 #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0
2648 #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128
2649 
2650 /* RX_EV */
2651 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
2652 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
2653 #define FSF_CZ_RX_EV_IPV6_PKT_LBN 57
2654 #define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
2655 #define FSF_AZ_RX_EV_PKT_OK_LBN 56
2656 #define FSF_AZ_RX_EV_PKT_OK_WIDTH 1
2657 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
2658 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
2659 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
2660 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2661 #define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
2662 #define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
2663 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
2664 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
2665 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
2666 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
2667 #define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
2668 #define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
2669 #define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
2670 #define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
2671 #define FSF_AA_RX_EV_DRIB_NIB_LBN 49
2672 #define FSF_AA_RX_EV_DRIB_NIB_WIDTH 1
2673 #define FSF_AZ_RX_EV_TOBE_DISC_LBN 47
2674 #define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
2675 #define FSF_AZ_RX_EV_PKT_TYPE_LBN 44
2676 #define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
2677 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
2678 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
2679 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
2680 #define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
2681 #define FSE_AZ_RX_EV_PKT_TYPE_LLC 1
2682 #define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
2683 #define FSF_AZ_RX_EV_HDR_TYPE_LBN 42
2684 #define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
2685 #define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
2686 #define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2
2687 #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
2688 #define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1
2689 #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
2690 #define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0
2691 #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
2692 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
2693 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
2694 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
2695 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
2696 #define FSF_AZ_RX_EV_MCAST_PKT_LBN 39
2697 #define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
2698 #define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
2699 #define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
2700 #define FSF_AZ_RX_EV_Q_LABEL_LBN 32
2701 #define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
2702 #define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
2703 #define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
2704 #define FSF_AZ_RX_EV_PORT_LBN 30
2705 #define FSF_AZ_RX_EV_PORT_WIDTH 1
2706 #define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
2707 #define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
2708 #define FSF_AZ_RX_EV_SOP_LBN 15
2709 #define FSF_AZ_RX_EV_SOP_WIDTH 1
2710 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
2711 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
2712 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
2713 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
2714 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
2715 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
2716 #define FSF_AZ_RX_EV_DESC_PTR_LBN 0
2717 #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
2718 
2719 /* RX_KER_DESC */
2720 #define FSF_AZ_RX_KER_BUF_SIZE_LBN 48
2721 #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
2722 #define FSF_AZ_RX_KER_BUF_REGION_LBN 46
2723 #define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
2724 #define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
2725 #define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
2726 
2727 /* RX_USER_DESC */
2728 #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
2729 #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
2730 #define FSF_AZ_RX_USER_BUF_ID_LBN 0
2731 #define FSF_AZ_RX_USER_BUF_ID_WIDTH 20
2732 
2733 /* TX_EV */
2734 #define FSF_AZ_TX_EV_PKT_ERR_LBN 38
2735 #define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
2736 #define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
2737 #define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
2738 #define FSF_AZ_TX_EV_Q_LABEL_LBN 32
2739 #define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
2740 #define FSF_AZ_TX_EV_PORT_LBN 16
2741 #define FSF_AZ_TX_EV_PORT_WIDTH 1
2742 #define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
2743 #define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
2744 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
2745 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2746 #define FSF_AZ_TX_EV_COMP_LBN 12
2747 #define FSF_AZ_TX_EV_COMP_WIDTH 1
2748 #define FSF_AZ_TX_EV_DESC_PTR_LBN 0
2749 #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
2750 
2751 /* TX_KER_DESC */
2752 #define FSF_AZ_TX_KER_CONT_LBN 62
2753 #define FSF_AZ_TX_KER_CONT_WIDTH 1
2754 #define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
2755 #define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
2756 #define FSF_AZ_TX_KER_BUF_REGION_LBN 46
2757 #define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
2758 #define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
2759 #define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
2760 
2761 /* TX_USER_DESC */
2762 #define FSF_AZ_TX_USER_SW_EV_EN_LBN 48
2763 #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
2764 #define FSF_AZ_TX_USER_CONT_LBN 46
2765 #define FSF_AZ_TX_USER_CONT_WIDTH 1
2766 #define FSF_AZ_TX_USER_BYTE_CNT_LBN 33
2767 #define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
2768 #define FSF_AZ_TX_USER_BUF_ID_LBN 13
2769 #define FSF_AZ_TX_USER_BUF_ID_WIDTH 20
2770 #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
2771 #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
2772 
2773 /* USER_EV */
2774 #define FSF_CZ_USER_QID_LBN 32
2775 #define FSF_CZ_USER_QID_WIDTH 10
2776 #define FSF_CZ_USER_EV_REG_VALUE_LBN 0
2777 #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
2778 
2779 /**************************************************************************
2780  *
2781  * Falcon B0 PCIe core indirect registers
2782  *
2783  **************************************************************************
2784  */
2785 
2786 #define FPCR_BB_PCIE_DEVICE_CTRL_STAT 0x68
2787 
2788 #define FPCR_BB_PCIE_LINK_CTRL_STAT 0x70
2789 
2790 #define FPCR_BB_ACK_RPL_TIMER 0x700
2791 #define FPCRF_BB_ACK_TL_LBN 0
2792 #define FPCRF_BB_ACK_TL_WIDTH 16
2793 #define FPCRF_BB_RPL_TL_LBN 16
2794 #define FPCRF_BB_RPL_TL_WIDTH 16
2795 
2796 #define FPCR_BB_ACK_FREQ 0x70C
2797 #define FPCRF_BB_ACK_FREQ_LBN 0
2798 #define FPCRF_BB_ACK_FREQ_WIDTH 7
2799 
2800 /**************************************************************************
2801  *
2802  * Pseudo-registers and fields
2803  *
2804  **************************************************************************
2805  */
2806 
2807 /* Interrupt acknowledge work-around register (A0/A1 only) */
2808 #define FR_AA_WORK_AROUND_BROKEN_PCI_READS 0x0070
2809 
2810 /* EE_SPI_HCMD_REG: SPI host command register */
2811 /* Values for the EE_SPI_HCMD_SF_SEL register field */
2812 #define FFE_AB_SPI_DEVICE_EEPROM 0
2813 #define FFE_AB_SPI_DEVICE_FLASH 1
2814 
2815 /* NIC_STAT_REG: NIC status register */
2816 #define FRF_AB_STRAP_10G_LBN 2
2817 #define FRF_AB_STRAP_10G_WIDTH 1
2818 #define FRF_AA_STRAP_PCIE_LBN 0
2819 #define FRF_AA_STRAP_PCIE_WIDTH 1
2820 
2821 /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
2822 #define FRF_AZ_FATAL_INTR_LBN 0
2823 #define FRF_AZ_FATAL_INTR_WIDTH 12
2824 
2825 /* SRM_CFG_REG: SRAM configuration register */
2826 /* We treat the number of SRAM banks and bank size as a single field */
2827 #define FRF_AZ_SRM_NB_SZ_LBN FRF_AZ_SRM_BANK_SIZE_LBN
2828 #define FRF_AZ_SRM_NB_SZ_WIDTH \
2829         (FRF_AZ_SRM_BANK_SIZE_WIDTH + FRF_AZ_SRM_NUM_BANK_WIDTH)
2830 #define FFE_AB_SRM_NB1_SZ2M 0
2831 #define FFE_AB_SRM_NB1_SZ4M 1
2832 #define FFE_AB_SRM_NB1_SZ8M 2
2833 #define FFE_AB_SRM_NB_SZ_DEF 3
2834 #define FFE_AB_SRM_NB2_SZ4M 4
2835 #define FFE_AB_SRM_NB2_SZ8M 5
2836 #define FFE_AB_SRM_NB2_SZ16M 6
2837 #define FFE_AB_SRM_NB_SZ_RES 7
2838 
2839 /* RX_DESC_UPD_REGP0: Receive descriptor update register. */
2840 /* We write just the last dword of these registers */
2841 #define FR_AZ_RX_DESC_UPD_DWORD_P0 \
2842         (BUILD_BUG_ON_ZERO(FR_AA_RX_DESC_UPD_KER != FR_BZ_RX_DESC_UPD_P0) + \
2843          FR_BZ_RX_DESC_UPD_P0 + 3 * 4)
2844 #define FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32)
2845 #define FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH FRF_AZ_RX_DESC_WPTR_WIDTH
2846 
2847 /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
2848 #define FR_AZ_TX_DESC_UPD_DWORD_P0 \
2849         (BUILD_BUG_ON_ZERO(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0) + \
2850          FR_BZ_TX_DESC_UPD_P0 + 3 * 4)
2851 #define FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32)
2852 #define FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH FRF_AZ_TX_DESC_WPTR_WIDTH
2853 
2854 /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
2855 #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN 12
2856 #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH 1
2857 
2858 /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
2859 #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN 12
2860 #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
2861 
2862 /* XM_TX_PARAM_REG: XGMAC transmit parameter register */
2863 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LBN FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN
2864 #define FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH + \
2865                                          FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH)
2866 
2867 /* XM_RX_PARAM_REG: XGMAC receive parameter register */
2868 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LBN FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN
2869 #define FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH + \
2870                                          FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH)
2871 
2872 /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2873 /* Default values */
2874 #define FFE_AB_XX_TXDRV_DEQ_DEF 0xe /* deq=.6 */
2875 #define FFE_AB_XX_TXDRV_DTX_DEF 0x5 /* 1.25 */
2876 #define FFE_AB_XX_SD_CTL_DRV_DEF 0  /* 20mA */
2877 
2878 /* XX_CORE_STAT_REG: XAUI XGXS core status register */
2879 /* XGXS all-lanes status fields */
2880 #define FRF_AB_XX_SYNC_STAT_LBN FRF_AB_XX_SYNC_STAT0_LBN
2881 #define FRF_AB_XX_SYNC_STAT_WIDTH 4
2882 #define FRF_AB_XX_COMMA_DET_LBN FRF_AB_XX_COMMA_DET_CH0_LBN
2883 #define FRF_AB_XX_COMMA_DET_WIDTH 4
2884 #define FRF_AB_XX_CHAR_ERR_LBN FRF_AB_XX_CHAR_ERR_CH0_LBN
2885 #define FRF_AB_XX_CHAR_ERR_WIDTH 4
2886 #define FRF_AB_XX_DISPERR_LBN FRF_AB_XX_DISPERR_CH0_LBN
2887 #define FRF_AB_XX_DISPERR_WIDTH 4
2888 #define FFE_AB_XX_STAT_ALL_LANES 0xf
2889 #define FRF_AB_XX_FORCE_SIG_LBN FRF_AB_XX_FORCE_SIG0_VAL_LBN
2890 #define FRF_AB_XX_FORCE_SIG_WIDTH 8
2891 #define FFE_AB_XX_FORCE_SIG_ALL_LANES 0xff
2892 
2893 /* RX_MAC_FILTER_TBL0 */
2894 /* RMFT_DEST_MAC is wider than 32 bits */
2895 #define FRF_CZ_RMFT_DEST_MAC_LO_LBN FRF_CZ_RMFT_DEST_MAC_LBN
2896 #define FRF_CZ_RMFT_DEST_MAC_LO_WIDTH 32
2897 #define FRF_CZ_RMFT_DEST_MAC_HI_LBN (FRF_CZ_RMFT_DEST_MAC_LBN + 32)
2898 #define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH (FRF_CZ_RMFT_DEST_MAC_WIDTH - 32)
2899 
2900 /* TX_MAC_FILTER_TBL0 */
2901 /* TMFT_SRC_MAC is wider than 32 bits */
2902 #define FRF_CZ_TMFT_SRC_MAC_LO_LBN FRF_CZ_TMFT_SRC_MAC_LBN
2903 #define FRF_CZ_TMFT_SRC_MAC_LO_WIDTH 32
2904 #define FRF_CZ_TMFT_SRC_MAC_HI_LBN (FRF_CZ_TMFT_SRC_MAC_LBN + 32)
2905 #define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH (FRF_CZ_TMFT_SRC_MAC_WIDTH - 32)
2906 
2907 /* TX_PACE_TBL */
2908 /* Values >20 are documented as reserved, but will result in a queue going
2909  * into the fast bin with a pace value of zero. */
2910 #define FFE_BZ_TX_PACE_OFF 0
2911 #define FFE_BZ_TX_PACE_RESERVED 21
2912 
2913 /* DRIVER_EV */
2914 /* Sub-fields of an RX flush completion event */
2915 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
2916 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
2917 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0
2918 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12
2919 
2920 /* EVENT_ENTRY */
2921 /* Magic number field for event test */
2922 #define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0
2923 #define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32
2924 
2925 /* RX packet prefix */
2926 #define FS_BZ_RX_PREFIX_HASH_OFST 12
2927 #define FS_BZ_RX_PREFIX_SIZE 16
2928 
2929 #endif /* EF4_FARCH_REGS_H */