This source file includes following definitions.
- ixgbe_write_reg
- ixgbe_write_reg_array
- ixgbe_read_reg_array
1
2
3
4 #ifndef __IXGBE_VF_H__
5 #define __IXGBE_VF_H__
6
7 #include <linux/pci.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/if_ether.h>
11 #include <linux/netdevice.h>
12
13 #include "defines.h"
14 #include "regs.h"
15 #include "mbx.h"
16
17 struct ixgbe_hw;
18
19
20 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
21 u32 *vmdq);
22 struct ixgbe_mac_operations {
23 s32 (*init_hw)(struct ixgbe_hw *);
24 s32 (*reset_hw)(struct ixgbe_hw *);
25 s32 (*start_hw)(struct ixgbe_hw *);
26 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
27 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
28 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
29 s32 (*stop_adapter)(struct ixgbe_hw *);
30 s32 (*get_bus_info)(struct ixgbe_hw *);
31 s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
32
33
34 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
35 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
36 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
37 bool *);
38
39
40 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32);
41 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
42 s32 (*init_rx_addrs)(struct ixgbe_hw *);
43 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
44 s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
45 s32 (*enable_mc)(struct ixgbe_hw *);
46 s32 (*disable_mc)(struct ixgbe_hw *);
47 s32 (*clear_vfta)(struct ixgbe_hw *);
48 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
49 s32 (*set_rlpml)(struct ixgbe_hw *, u16);
50 };
51
52 enum ixgbe_mac_type {
53 ixgbe_mac_unknown = 0,
54 ixgbe_mac_82599_vf,
55 ixgbe_mac_X540_vf,
56 ixgbe_mac_X550_vf,
57 ixgbe_mac_X550EM_x_vf,
58 ixgbe_mac_x550em_a_vf,
59 ixgbe_num_macs
60 };
61
62 struct ixgbe_mac_info {
63 struct ixgbe_mac_operations ops;
64 u8 addr[6];
65 u8 perm_addr[6];
66
67 enum ixgbe_mac_type type;
68
69 s32 mc_filter_type;
70
71 bool get_link_status;
72 u32 max_tx_queues;
73 u32 max_rx_queues;
74 u32 max_msix_vectors;
75 };
76
77 struct ixgbe_mbx_operations {
78 s32 (*init_params)(struct ixgbe_hw *hw);
79 s32 (*read)(struct ixgbe_hw *, u32 *, u16);
80 s32 (*write)(struct ixgbe_hw *, u32 *, u16);
81 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16);
82 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16);
83 s32 (*check_for_msg)(struct ixgbe_hw *);
84 s32 (*check_for_ack)(struct ixgbe_hw *);
85 s32 (*check_for_rst)(struct ixgbe_hw *);
86 };
87
88 struct ixgbe_mbx_stats {
89 u32 msgs_tx;
90 u32 msgs_rx;
91
92 u32 acks;
93 u32 reqs;
94 u32 rsts;
95 };
96
97 struct ixgbe_mbx_info {
98 struct ixgbe_mbx_operations ops;
99 struct ixgbe_mbx_stats stats;
100 u32 timeout;
101 u32 udelay;
102 u32 v2p_mailbox;
103 u16 size;
104 };
105
106 struct ixgbe_hw {
107 void *back;
108
109 u8 __iomem *hw_addr;
110
111 struct ixgbe_mac_info mac;
112 struct ixgbe_mbx_info mbx;
113
114 u16 device_id;
115 u16 subsystem_vendor_id;
116 u16 subsystem_device_id;
117 u16 vendor_id;
118
119 u8 revision_id;
120 bool adapter_stopped;
121
122 int api_version;
123 };
124
125 struct ixgbevf_hw_stats {
126 u64 base_vfgprc;
127 u64 base_vfgptc;
128 u64 base_vfgorc;
129 u64 base_vfgotc;
130 u64 base_vfmprc;
131
132 u64 last_vfgprc;
133 u64 last_vfgptc;
134 u64 last_vfgorc;
135 u64 last_vfgotc;
136 u64 last_vfmprc;
137
138 u64 vfgprc;
139 u64 vfgptc;
140 u64 vfgorc;
141 u64 vfgotc;
142 u64 vfmprc;
143
144 u64 saved_reset_vfgprc;
145 u64 saved_reset_vfgptc;
146 u64 saved_reset_vfgorc;
147 u64 saved_reset_vfgotc;
148 u64 saved_reset_vfmprc;
149 };
150
151 struct ixgbevf_info {
152 enum ixgbe_mac_type mac;
153 const struct ixgbe_mac_operations *mac_ops;
154 };
155
156 #define IXGBE_FAILED_READ_REG 0xffffffffU
157
158 #define IXGBE_REMOVED(a) unlikely(!(a))
159
160 static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value)
161 {
162 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
163
164 if (IXGBE_REMOVED(reg_addr))
165 return;
166 writel(value, reg_addr + reg);
167 }
168
169 #define IXGBE_WRITE_REG(h, r, v) ixgbe_write_reg(h, r, v)
170
171 u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg);
172 #define IXGBE_READ_REG(h, r) ixgbevf_read_reg(h, r)
173
174 static inline void ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg,
175 u32 offset, u32 value)
176 {
177 ixgbe_write_reg(hw, reg + (offset << 2), value);
178 }
179
180 #define IXGBE_WRITE_REG_ARRAY(h, r, o, v) ixgbe_write_reg_array(h, r, o, v)
181
182 static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg,
183 u32 offset)
184 {
185 return ixgbevf_read_reg(hw, reg + (offset << 2));
186 }
187
188 #define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o)
189
190 int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
191 unsigned int *default_tc);
192 int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues);
193 int ixgbevf_get_rss_key_locked(struct ixgbe_hw *hw, u8 *rss_key);
194 #endif