This source file includes following definitions.
- ice_setup_rx_ctx
- ice_setup_tx_ctx
- ice_pf_rxq_wait
- ice_vsi_ctrl_rx_ring
- ice_vsi_ctrl_rx_rings
- ice_vsi_alloc_arrays
- ice_vsi_set_num_desc
- ice_vsi_set_num_qs
- ice_get_free_slot
- ice_vsi_delete
- ice_vsi_free_arrays
- ice_vsi_clear
- ice_msix_clean_rings
- ice_vsi_alloc
- __ice_vsi_get_qs_contig
- __ice_vsi_get_qs_sc
- __ice_vsi_get_qs
- ice_vsi_get_qs
- ice_vsi_put_qs
- ice_is_safe_mode
- ice_rss_clean
- ice_vsi_set_rss_params
- ice_set_dflt_vsi_ctx
- ice_vsi_setup_q_map
- ice_set_rss_vsi_ctx
- ice_vsi_init
- ice_free_q_vector
- ice_vsi_free_q_vectors
- ice_vsi_alloc_q_vector
- ice_vsi_alloc_q_vectors
- ice_vsi_setup_vector_base
- ice_vsi_clear_rings
- ice_vsi_alloc_rings
- ice_vsi_map_rings_to_vectors
- ice_vsi_manage_rss_lut
- ice_vsi_cfg_rss_lut_key
- ice_add_mac_to_list
- ice_update_eth_stats
- ice_free_fltr_list
- ice_vsi_add_vlan
- ice_vsi_kill_vlan
- ice_vsi_cfg_rxqs
- ice_vsi_cfg_txq
- ice_vsi_cfg_txqs
- ice_vsi_cfg_lan_txqs
- ice_intrl_usec_to_reg
- ice_cfg_itr_gran
- ice_cfg_itr
- ice_cfg_txq_interrupt
- ice_cfg_rxq_interrupt
- ice_vsi_cfg_msix
- ice_vsi_manage_vlan_insertion
- ice_vsi_manage_vlan_stripping
- ice_vsi_start_rx_rings
- ice_vsi_stop_rx_rings
- ice_trigger_sw_intr
- ice_vsi_stop_tx_ring
- ice_fill_txq_meta
- ice_vsi_stop_tx_rings
- ice_vsi_stop_lan_tx_rings
- ice_cfg_vlan_pruning
- ice_vsi_set_tc_cfg
- ice_vsi_set_q_vectors_reg_idx
- ice_vsi_add_rem_eth_mac
- ice_cfg_sw_lldp
- ice_vsi_setup
- ice_vsi_release_msix
- ice_vsi_free_irq
- ice_vsi_free_tx_rings
- ice_vsi_free_rx_rings
- ice_vsi_close
- ice_free_res
- ice_search_res
- ice_get_res
- ice_vsi_dis_irq
- ice_napi_del
- ice_vsi_release
- ice_vsi_rebuild
- ice_is_reset_in_progress
- ice_vsi_update_q_map
- ice_vsi_cfg_tc
- ice_nvm_version_str
- ice_vsi_cfg_mac_fltr
1
2
3
4 #include "ice.h"
5 #include "ice_lib.h"
6 #include "ice_dcb_lib.h"
7
8
9
10
11
12
13
14 static int ice_setup_rx_ctx(struct ice_ring *ring)
15 {
16 struct ice_vsi *vsi = ring->vsi;
17 struct ice_hw *hw = &vsi->back->hw;
18 u32 rxdid = ICE_RXDID_FLEX_NIC;
19 struct ice_rlan_ctx rlan_ctx;
20 u32 regval;
21 u16 pf_q;
22 int err;
23
24
25 pf_q = vsi->rxq_map[ring->q_index];
26
27
28 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
29
30 rlan_ctx.base = ring->dma >> 7;
31
32 rlan_ctx.qlen = ring->count;
33
34
35
36
37 rlan_ctx.dbuf = vsi->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
38
39
40 rlan_ctx.dsize = 1;
41
42
43
44
45 rlan_ctx.crcstrip = 1;
46
47
48 rlan_ctx.l2tsel = 1;
49
50 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
51 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
52 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
53
54
55
56
57
58 rlan_ctx.showiv = 0;
59
60
61
62
63 rlan_ctx.rxmax = min_t(u16, vsi->max_frame,
64 ICE_MAX_CHAINED_RX_BUFS * vsi->rx_buf_len);
65
66
67 rlan_ctx.lrxqthresh = 1;
68
69
70
71
72 if (vsi->type != ICE_VSI_VF) {
73 regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
74 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
75 QRXFLXP_CNTXT_RXDID_IDX_M;
76
77
78
79
80
81 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
82 QRXFLXP_CNTXT_RXDID_PRIO_M;
83
84 wr32(hw, QRXFLXP_CNTXT(pf_q), regval);
85 }
86
87
88 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
89 if (err) {
90 dev_err(&vsi->back->pdev->dev,
91 "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
92 pf_q, err);
93 return -EIO;
94 }
95
96 if (vsi->type == ICE_VSI_VF)
97 return 0;
98
99
100 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
101 writel(0, ring->tail);
102 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring));
103
104 return 0;
105 }
106
107
108
109
110
111
112
113
114
115 static void
116 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
117 {
118 struct ice_vsi *vsi = ring->vsi;
119 struct ice_hw *hw = &vsi->back->hw;
120
121 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
122
123 tlan_ctx->port_num = vsi->port_info->lport;
124
125
126 tlan_ctx->qlen = ring->count;
127
128 ice_set_cgd_num(tlan_ctx, ring);
129
130
131 tlan_ctx->pf_num = hw->pf_id;
132
133
134
135
136
137
138
139 switch (vsi->type) {
140 case ICE_VSI_LB:
141
142 case ICE_VSI_PF:
143 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
144 break;
145 case ICE_VSI_VF:
146
147 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;
148 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
149 break;
150 default:
151 return;
152 }
153
154
155 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
156
157 tlan_ctx->tso_ena = ICE_TX_LEGACY;
158 tlan_ctx->tso_qnum = pf_q;
159
160
161
162
163
164 tlan_ctx->legacy_int = ICE_TX_LEGACY;
165 }
166
167
168
169
170
171
172
173
174
175
176
177
178 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
179 {
180 int i;
181
182 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
183 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
184 QRX_CTRL_QENA_STAT_M))
185 return 0;
186
187 usleep_range(20, 40);
188 }
189
190 return -ETIMEDOUT;
191 }
192
193
194
195
196
197
198
199 #ifndef CONFIG_PCI_IOV
200 static
201 #endif
202 int ice_vsi_ctrl_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
203 {
204 int pf_q = vsi->rxq_map[rxq_idx];
205 struct ice_pf *pf = vsi->back;
206 struct ice_hw *hw = &pf->hw;
207 int ret = 0;
208 u32 rx_reg;
209
210 rx_reg = rd32(hw, QRX_CTRL(pf_q));
211
212
213 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
214 return 0;
215
216
217 if (ena)
218 rx_reg |= QRX_CTRL_QENA_REQ_M;
219 else
220 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
221 wr32(hw, QRX_CTRL(pf_q), rx_reg);
222
223
224 ret = ice_pf_rxq_wait(pf, pf_q, ena);
225 if (ret)
226 dev_err(&pf->pdev->dev,
227 "VSI idx %d Rx ring %d %sable timeout\n",
228 vsi->idx, pf_q, (ena ? "en" : "dis"));
229
230 return ret;
231 }
232
233
234
235
236
237
238 static int ice_vsi_ctrl_rx_rings(struct ice_vsi *vsi, bool ena)
239 {
240 int i, ret = 0;
241
242 for (i = 0; i < vsi->num_rxq; i++) {
243 ret = ice_vsi_ctrl_rx_ring(vsi, ena, i);
244 if (ret)
245 break;
246 }
247
248 return ret;
249 }
250
251
252
253
254
255
256
257
258 static int ice_vsi_alloc_arrays(struct ice_vsi *vsi)
259 {
260 struct ice_pf *pf = vsi->back;
261
262
263 vsi->tx_rings = devm_kcalloc(&pf->pdev->dev, vsi->alloc_txq,
264 sizeof(*vsi->tx_rings), GFP_KERNEL);
265 if (!vsi->tx_rings)
266 return -ENOMEM;
267
268 vsi->rx_rings = devm_kcalloc(&pf->pdev->dev, vsi->alloc_rxq,
269 sizeof(*vsi->rx_rings), GFP_KERNEL);
270 if (!vsi->rx_rings)
271 goto err_rings;
272
273 vsi->txq_map = devm_kcalloc(&pf->pdev->dev, vsi->alloc_txq,
274 sizeof(*vsi->txq_map), GFP_KERNEL);
275
276 if (!vsi->txq_map)
277 goto err_txq_map;
278
279 vsi->rxq_map = devm_kcalloc(&pf->pdev->dev, vsi->alloc_rxq,
280 sizeof(*vsi->rxq_map), GFP_KERNEL);
281 if (!vsi->rxq_map)
282 goto err_rxq_map;
283
284
285
286 if (vsi->type == ICE_VSI_LB)
287 return 0;
288
289
290 vsi->q_vectors = devm_kcalloc(&pf->pdev->dev, vsi->num_q_vectors,
291 sizeof(*vsi->q_vectors), GFP_KERNEL);
292 if (!vsi->q_vectors)
293 goto err_vectors;
294
295 return 0;
296
297 err_vectors:
298 devm_kfree(&pf->pdev->dev, vsi->rxq_map);
299 err_rxq_map:
300 devm_kfree(&pf->pdev->dev, vsi->txq_map);
301 err_txq_map:
302 devm_kfree(&pf->pdev->dev, vsi->rx_rings);
303 err_rings:
304 devm_kfree(&pf->pdev->dev, vsi->tx_rings);
305 return -ENOMEM;
306 }
307
308
309
310
311
312 static void ice_vsi_set_num_desc(struct ice_vsi *vsi)
313 {
314 switch (vsi->type) {
315 case ICE_VSI_PF:
316
317 case ICE_VSI_LB:
318 vsi->num_rx_desc = ICE_DFLT_NUM_RX_DESC;
319 vsi->num_tx_desc = ICE_DFLT_NUM_TX_DESC;
320 break;
321 default:
322 dev_dbg(&vsi->back->pdev->dev,
323 "Not setting number of Tx/Rx descriptors for VSI type %d\n",
324 vsi->type);
325 break;
326 }
327 }
328
329
330
331
332
333
334
335
336 static void ice_vsi_set_num_qs(struct ice_vsi *vsi, u16 vf_id)
337 {
338 struct ice_pf *pf = vsi->back;
339 struct ice_vf *vf = NULL;
340
341 if (vsi->type == ICE_VSI_VF)
342 vsi->vf_id = vf_id;
343
344 switch (vsi->type) {
345 case ICE_VSI_PF:
346 vsi->alloc_txq = min_t(int, ice_get_avail_txq_count(pf),
347 num_online_cpus());
348
349 pf->num_lan_tx = vsi->alloc_txq;
350
351
352 if (!test_bit(ICE_FLAG_RSS_ENA, pf->flags))
353 vsi->alloc_rxq = 1;
354 else
355 vsi->alloc_rxq = min_t(int, ice_get_avail_rxq_count(pf),
356 num_online_cpus());
357
358 pf->num_lan_rx = vsi->alloc_rxq;
359
360 vsi->num_q_vectors = max_t(int, vsi->alloc_rxq, vsi->alloc_txq);
361 break;
362 case ICE_VSI_VF:
363 vf = &pf->vf[vsi->vf_id];
364 vsi->alloc_txq = vf->num_vf_qs;
365 vsi->alloc_rxq = vf->num_vf_qs;
366
367
368
369
370
371 vsi->num_q_vectors = pf->num_vf_msix - ICE_NONQ_VECS_VF;
372 break;
373 case ICE_VSI_LB:
374 vsi->alloc_txq = 1;
375 vsi->alloc_rxq = 1;
376 break;
377 default:
378 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
379 break;
380 }
381
382 ice_vsi_set_num_desc(vsi);
383 }
384
385
386
387
388
389
390
391
392
393
394 static int ice_get_free_slot(void *array, int size, int curr)
395 {
396 int **tmp_array = (int **)array;
397 int next;
398
399 if (curr < (size - 1) && !tmp_array[curr + 1]) {
400 next = curr + 1;
401 } else {
402 int i = 0;
403
404 while ((i < size) && (tmp_array[i]))
405 i++;
406 if (i == size)
407 next = ICE_NO_VSI;
408 else
409 next = i;
410 }
411 return next;
412 }
413
414
415
416
417
418 void ice_vsi_delete(struct ice_vsi *vsi)
419 {
420 struct ice_pf *pf = vsi->back;
421 struct ice_vsi_ctx *ctxt;
422 enum ice_status status;
423
424 ctxt = devm_kzalloc(&pf->pdev->dev, sizeof(*ctxt), GFP_KERNEL);
425 if (!ctxt)
426 return;
427
428 if (vsi->type == ICE_VSI_VF)
429 ctxt->vf_num = vsi->vf_id;
430 ctxt->vsi_num = vsi->vsi_num;
431
432 memcpy(&ctxt->info, &vsi->info, sizeof(ctxt->info));
433
434 status = ice_free_vsi(&pf->hw, vsi->idx, ctxt, false, NULL);
435 if (status)
436 dev_err(&pf->pdev->dev, "Failed to delete VSI %i in FW\n",
437 vsi->vsi_num);
438
439 devm_kfree(&pf->pdev->dev, ctxt);
440 }
441
442
443
444
445
446 static void ice_vsi_free_arrays(struct ice_vsi *vsi)
447 {
448 struct ice_pf *pf = vsi->back;
449
450
451 if (vsi->q_vectors) {
452 devm_kfree(&pf->pdev->dev, vsi->q_vectors);
453 vsi->q_vectors = NULL;
454 }
455 if (vsi->tx_rings) {
456 devm_kfree(&pf->pdev->dev, vsi->tx_rings);
457 vsi->tx_rings = NULL;
458 }
459 if (vsi->rx_rings) {
460 devm_kfree(&pf->pdev->dev, vsi->rx_rings);
461 vsi->rx_rings = NULL;
462 }
463 if (vsi->txq_map) {
464 devm_kfree(&pf->pdev->dev, vsi->txq_map);
465 vsi->txq_map = NULL;
466 }
467 if (vsi->rxq_map) {
468 devm_kfree(&pf->pdev->dev, vsi->rxq_map);
469 vsi->rxq_map = NULL;
470 }
471 }
472
473
474
475
476
477
478
479
480
481
482 int ice_vsi_clear(struct ice_vsi *vsi)
483 {
484 struct ice_pf *pf = NULL;
485
486 if (!vsi)
487 return 0;
488
489 if (!vsi->back)
490 return -EINVAL;
491
492 pf = vsi->back;
493
494 if (!pf->vsi[vsi->idx] || pf->vsi[vsi->idx] != vsi) {
495 dev_dbg(&pf->pdev->dev, "vsi does not exist at pf->vsi[%d]\n",
496 vsi->idx);
497 return -EINVAL;
498 }
499
500 mutex_lock(&pf->sw_mutex);
501
502
503 pf->vsi[vsi->idx] = NULL;
504 if (vsi->idx < pf->next_vsi)
505 pf->next_vsi = vsi->idx;
506
507 ice_vsi_free_arrays(vsi);
508 mutex_unlock(&pf->sw_mutex);
509 devm_kfree(&pf->pdev->dev, vsi);
510
511 return 0;
512 }
513
514
515
516
517
518
519 static irqreturn_t ice_msix_clean_rings(int __always_unused irq, void *data)
520 {
521 struct ice_q_vector *q_vector = (struct ice_q_vector *)data;
522
523 if (!q_vector->tx.ring && !q_vector->rx.ring)
524 return IRQ_HANDLED;
525
526 napi_schedule(&q_vector->napi);
527
528 return IRQ_HANDLED;
529 }
530
531
532
533
534
535
536
537
538
539 static struct ice_vsi *
540 ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type type, u16 vf_id)
541 {
542 struct ice_vsi *vsi = NULL;
543
544
545 mutex_lock(&pf->sw_mutex);
546
547
548
549
550
551 if (pf->next_vsi == ICE_NO_VSI) {
552 dev_dbg(&pf->pdev->dev, "out of VSI slots!\n");
553 goto unlock_pf;
554 }
555
556 vsi = devm_kzalloc(&pf->pdev->dev, sizeof(*vsi), GFP_KERNEL);
557 if (!vsi)
558 goto unlock_pf;
559
560 vsi->type = type;
561 vsi->back = pf;
562 set_bit(__ICE_DOWN, vsi->state);
563
564 vsi->idx = pf->next_vsi;
565
566 if (type == ICE_VSI_VF)
567 ice_vsi_set_num_qs(vsi, vf_id);
568 else
569 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
570
571 switch (vsi->type) {
572 case ICE_VSI_PF:
573 if (ice_vsi_alloc_arrays(vsi))
574 goto err_rings;
575
576
577 vsi->irq_handler = ice_msix_clean_rings;
578 break;
579 case ICE_VSI_VF:
580 if (ice_vsi_alloc_arrays(vsi))
581 goto err_rings;
582 break;
583 case ICE_VSI_LB:
584 if (ice_vsi_alloc_arrays(vsi))
585 goto err_rings;
586 break;
587 default:
588 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
589 goto unlock_pf;
590 }
591
592
593 pf->vsi[pf->next_vsi] = vsi;
594
595
596 pf->next_vsi = ice_get_free_slot(pf->vsi, pf->num_alloc_vsi,
597 pf->next_vsi);
598 goto unlock_pf;
599
600 err_rings:
601 devm_kfree(&pf->pdev->dev, vsi);
602 vsi = NULL;
603 unlock_pf:
604 mutex_unlock(&pf->sw_mutex);
605 return vsi;
606 }
607
608
609
610
611
612
613
614 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
615 {
616 int offset, i;
617
618 mutex_lock(qs_cfg->qs_mutex);
619 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
620 0, qs_cfg->q_count, 0);
621 if (offset >= qs_cfg->pf_map_size) {
622 mutex_unlock(qs_cfg->qs_mutex);
623 return -ENOMEM;
624 }
625
626 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
627 for (i = 0; i < qs_cfg->q_count; i++)
628 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset;
629 mutex_unlock(qs_cfg->qs_mutex);
630
631 return 0;
632 }
633
634
635
636
637
638
639
640 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
641 {
642 int i, index = 0;
643
644 mutex_lock(qs_cfg->qs_mutex);
645 for (i = 0; i < qs_cfg->q_count; i++) {
646 index = find_next_zero_bit(qs_cfg->pf_map,
647 qs_cfg->pf_map_size, index);
648 if (index >= qs_cfg->pf_map_size)
649 goto err_scatter;
650 set_bit(index, qs_cfg->pf_map);
651 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index;
652 }
653 mutex_unlock(qs_cfg->qs_mutex);
654
655 return 0;
656 err_scatter:
657 for (index = 0; index < i; index++) {
658 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
659 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
660 }
661 mutex_unlock(qs_cfg->qs_mutex);
662
663 return -ENOMEM;
664 }
665
666
667
668
669
670
671
672
673
674
675 static int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
676 {
677 int ret = 0;
678
679 ret = __ice_vsi_get_qs_contig(qs_cfg);
680 if (ret) {
681
682 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
683 qs_cfg->q_count = min_t(u16, qs_cfg->q_count,
684 qs_cfg->scatter_count);
685 ret = __ice_vsi_get_qs_sc(qs_cfg);
686 }
687 return ret;
688 }
689
690
691
692
693
694
695
696 static int ice_vsi_get_qs(struct ice_vsi *vsi)
697 {
698 struct ice_pf *pf = vsi->back;
699 struct ice_qs_cfg tx_qs_cfg = {
700 .qs_mutex = &pf->avail_q_mutex,
701 .pf_map = pf->avail_txqs,
702 .pf_map_size = pf->max_pf_txqs,
703 .q_count = vsi->alloc_txq,
704 .scatter_count = ICE_MAX_SCATTER_TXQS,
705 .vsi_map = vsi->txq_map,
706 .vsi_map_offset = 0,
707 .mapping_mode = vsi->tx_mapping_mode
708 };
709 struct ice_qs_cfg rx_qs_cfg = {
710 .qs_mutex = &pf->avail_q_mutex,
711 .pf_map = pf->avail_rxqs,
712 .pf_map_size = pf->max_pf_rxqs,
713 .q_count = vsi->alloc_rxq,
714 .scatter_count = ICE_MAX_SCATTER_RXQS,
715 .vsi_map = vsi->rxq_map,
716 .vsi_map_offset = 0,
717 .mapping_mode = vsi->rx_mapping_mode
718 };
719 int ret = 0;
720
721 vsi->tx_mapping_mode = ICE_VSI_MAP_CONTIG;
722 vsi->rx_mapping_mode = ICE_VSI_MAP_CONTIG;
723
724 ret = __ice_vsi_get_qs(&tx_qs_cfg);
725 if (!ret)
726 ret = __ice_vsi_get_qs(&rx_qs_cfg);
727
728 return ret;
729 }
730
731
732
733
734
735 void ice_vsi_put_qs(struct ice_vsi *vsi)
736 {
737 struct ice_pf *pf = vsi->back;
738 int i;
739
740 mutex_lock(&pf->avail_q_mutex);
741
742 for (i = 0; i < vsi->alloc_txq; i++) {
743 clear_bit(vsi->txq_map[i], pf->avail_txqs);
744 vsi->txq_map[i] = ICE_INVAL_Q_INDEX;
745 }
746
747 for (i = 0; i < vsi->alloc_rxq; i++) {
748 clear_bit(vsi->rxq_map[i], pf->avail_rxqs);
749 vsi->rxq_map[i] = ICE_INVAL_Q_INDEX;
750 }
751
752 mutex_unlock(&pf->avail_q_mutex);
753 }
754
755
756
757
758
759
760
761 bool ice_is_safe_mode(struct ice_pf *pf)
762 {
763 return !test_bit(ICE_FLAG_ADV_FEATURES, pf->flags);
764 }
765
766
767
768
769
770 static void ice_rss_clean(struct ice_vsi *vsi)
771 {
772 struct ice_pf *pf;
773
774 pf = vsi->back;
775
776 if (vsi->rss_hkey_user)
777 devm_kfree(&pf->pdev->dev, vsi->rss_hkey_user);
778 if (vsi->rss_lut_user)
779 devm_kfree(&pf->pdev->dev, vsi->rss_lut_user);
780 }
781
782
783
784
785
786 static void ice_vsi_set_rss_params(struct ice_vsi *vsi)
787 {
788 struct ice_hw_common_caps *cap;
789 struct ice_pf *pf = vsi->back;
790
791 if (!test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
792 vsi->rss_size = 1;
793 return;
794 }
795
796 cap = &pf->hw.func_caps.common_cap;
797 switch (vsi->type) {
798 case ICE_VSI_PF:
799
800 vsi->rss_table_size = cap->rss_table_size;
801 vsi->rss_size = min_t(int, num_online_cpus(),
802 BIT(cap->rss_table_entry_width));
803 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
804 break;
805 case ICE_VSI_VF:
806
807
808
809 vsi->rss_table_size = ICE_VSIQF_HLUT_ARRAY_SIZE;
810 vsi->rss_size = min_t(int, num_online_cpus(),
811 BIT(cap->rss_table_entry_width));
812 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI;
813 break;
814 case ICE_VSI_LB:
815 break;
816 default:
817 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n",
818 vsi->type);
819 break;
820 }
821 }
822
823
824
825
826
827
828
829 static void ice_set_dflt_vsi_ctx(struct ice_vsi_ctx *ctxt)
830 {
831 u32 table = 0;
832
833 memset(&ctxt->info, 0, sizeof(ctxt->info));
834
835 ctxt->alloc_from_pool = true;
836
837 ctxt->info.sw_flags = ICE_AQ_VSI_SW_FLAG_SRC_PRUNE;
838
839 ctxt->info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
840
841
842
843
844 ctxt->info.vlan_flags = ((ICE_AQ_VSI_VLAN_MODE_ALL &
845 ICE_AQ_VSI_VLAN_MODE_M) >>
846 ICE_AQ_VSI_VLAN_MODE_S);
847
848 table |= ICE_UP_TABLE_TRANSLATE(0, 0);
849 table |= ICE_UP_TABLE_TRANSLATE(1, 1);
850 table |= ICE_UP_TABLE_TRANSLATE(2, 2);
851 table |= ICE_UP_TABLE_TRANSLATE(3, 3);
852 table |= ICE_UP_TABLE_TRANSLATE(4, 4);
853 table |= ICE_UP_TABLE_TRANSLATE(5, 5);
854 table |= ICE_UP_TABLE_TRANSLATE(6, 6);
855 table |= ICE_UP_TABLE_TRANSLATE(7, 7);
856 ctxt->info.ingress_table = cpu_to_le32(table);
857 ctxt->info.egress_table = cpu_to_le32(table);
858
859 ctxt->info.outer_up_table = cpu_to_le32(table);
860
861 }
862
863
864
865
866
867
868 static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
869 {
870 u16 offset = 0, qmap = 0, tx_count = 0;
871 u16 qcount_tx = vsi->alloc_txq;
872 u16 qcount_rx = vsi->alloc_rxq;
873 u16 tx_numq_tc, rx_numq_tc;
874 u16 pow = 0, max_rss = 0;
875 bool ena_tc0 = false;
876 u8 netdev_tc = 0;
877 int i;
878
879
880 if (vsi->tc_cfg.numtc) {
881 if (!(vsi->tc_cfg.ena_tc & BIT(0)))
882 ena_tc0 = true;
883 } else {
884 ena_tc0 = true;
885 }
886
887 if (ena_tc0) {
888 vsi->tc_cfg.numtc++;
889 vsi->tc_cfg.ena_tc |= 1;
890 }
891
892 rx_numq_tc = qcount_rx / vsi->tc_cfg.numtc;
893 if (!rx_numq_tc)
894 rx_numq_tc = 1;
895 tx_numq_tc = qcount_tx / vsi->tc_cfg.numtc;
896 if (!tx_numq_tc)
897 tx_numq_tc = 1;
898
899
900
901
902
903
904
905
906
907
908
909
910
911 qcount_rx = rx_numq_tc;
912
913
914 if (test_bit(ICE_FLAG_RSS_ENA, vsi->back->flags)) {
915 if (vsi->type == ICE_VSI_PF || vsi->type == ICE_VSI_VF) {
916 if (vsi->type == ICE_VSI_PF)
917 max_rss = ICE_MAX_LG_RSS_QS;
918 else
919 max_rss = ICE_MAX_SMALL_RSS_QS;
920 qcount_rx = min_t(int, rx_numq_tc, max_rss);
921 qcount_rx = min_t(int, qcount_rx, vsi->rss_size);
922 }
923 }
924
925
926 pow = order_base_2(qcount_rx);
927
928 ice_for_each_traffic_class(i) {
929 if (!(vsi->tc_cfg.ena_tc & BIT(i))) {
930
931 vsi->tc_cfg.tc_info[i].qoffset = 0;
932 vsi->tc_cfg.tc_info[i].qcount_rx = 1;
933 vsi->tc_cfg.tc_info[i].qcount_tx = 1;
934 vsi->tc_cfg.tc_info[i].netdev_tc = 0;
935 ctxt->info.tc_mapping[i] = 0;
936 continue;
937 }
938
939
940 vsi->tc_cfg.tc_info[i].qoffset = offset;
941 vsi->tc_cfg.tc_info[i].qcount_rx = qcount_rx;
942 vsi->tc_cfg.tc_info[i].qcount_tx = tx_numq_tc;
943 vsi->tc_cfg.tc_info[i].netdev_tc = netdev_tc++;
944
945 qmap = ((offset << ICE_AQ_VSI_TC_Q_OFFSET_S) &
946 ICE_AQ_VSI_TC_Q_OFFSET_M) |
947 ((pow << ICE_AQ_VSI_TC_Q_NUM_S) &
948 ICE_AQ_VSI_TC_Q_NUM_M);
949 offset += qcount_rx;
950 tx_count += tx_numq_tc;
951 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
952 }
953
954
955
956
957
958
959
960 if (offset)
961 vsi->num_rxq = offset;
962 else
963 vsi->num_rxq = qcount_rx;
964
965 vsi->num_txq = tx_count;
966
967 if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {
968 dev_dbg(&vsi->back->pdev->dev, "VF VSI should have same number of Tx and Rx queues. Hence making them equal\n");
969
970
971
972 vsi->num_txq = vsi->num_rxq;
973 }
974
975
976 ctxt->info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG);
977
978
979
980
981 ctxt->info.q_mapping[0] = cpu_to_le16(vsi->rxq_map[0]);
982 ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq);
983 }
984
985
986
987
988
989
990 static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
991 {
992 u8 lut_type, hash_type;
993 struct ice_pf *pf;
994
995 pf = vsi->back;
996
997 switch (vsi->type) {
998 case ICE_VSI_PF:
999
1000 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF;
1001 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1002 break;
1003 case ICE_VSI_VF:
1004
1005 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;
1006 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1007 break;
1008 case ICE_VSI_LB:
1009 dev_dbg(&pf->pdev->dev, "Unsupported VSI type %d\n", vsi->type);
1010 return;
1011 default:
1012 dev_warn(&pf->pdev->dev, "Unknown VSI type %d\n", vsi->type);
1013 return;
1014 }
1015
1016 ctxt->info.q_opt_rss = ((lut_type << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &
1017 ICE_AQ_VSI_Q_OPT_RSS_LUT_M) |
1018 ((hash_type << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) &
1019 ICE_AQ_VSI_Q_OPT_RSS_HASH_M);
1020 }
1021
1022
1023
1024
1025
1026
1027
1028
1029 static int ice_vsi_init(struct ice_vsi *vsi)
1030 {
1031 struct ice_pf *pf = vsi->back;
1032 struct ice_hw *hw = &pf->hw;
1033 struct ice_vsi_ctx *ctxt;
1034 int ret = 0;
1035
1036 ctxt = devm_kzalloc(&pf->pdev->dev, sizeof(*ctxt), GFP_KERNEL);
1037 if (!ctxt)
1038 return -ENOMEM;
1039
1040 ctxt->info = vsi->info;
1041 switch (vsi->type) {
1042 case ICE_VSI_LB:
1043
1044 case ICE_VSI_PF:
1045 ctxt->flags = ICE_AQ_VSI_TYPE_PF;
1046 break;
1047 case ICE_VSI_VF:
1048 ctxt->flags = ICE_AQ_VSI_TYPE_VF;
1049
1050 ctxt->vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
1051 break;
1052 default:
1053 return -ENODEV;
1054 }
1055
1056 ice_set_dflt_vsi_ctx(ctxt);
1057
1058 if (vsi->vsw->bridge_mode == BRIDGE_MODE_VEB)
1059 ctxt->info.sw_flags |= ICE_AQ_VSI_SW_FLAG_ALLOW_LB;
1060
1061
1062 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
1063 ice_set_rss_vsi_ctx(ctxt, vsi);
1064
1065 ctxt->info.sw_id = vsi->port_info->sw_id;
1066 ice_vsi_setup_q_map(vsi, ctxt);
1067
1068
1069 if (vsi->type == ICE_VSI_VF && pf->vf[vsi->vf_id].spoofchk) {
1070 ctxt->info.valid_sections |=
1071 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID);
1072 ctxt->info.sec_flags |=
1073 ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF;
1074 }
1075
1076
1077 if (vsi->type == ICE_VSI_PF) {
1078 ctxt->info.sec_flags |= ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD;
1079 ctxt->info.valid_sections |=
1080 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID);
1081 }
1082
1083 ret = ice_add_vsi(hw, vsi->idx, ctxt, NULL);
1084 if (ret) {
1085 dev_err(&pf->pdev->dev,
1086 "Add VSI failed, err %d\n", ret);
1087 return -EIO;
1088 }
1089
1090
1091 vsi->info = ctxt->info;
1092
1093
1094 vsi->vsi_num = ctxt->vsi_num;
1095
1096 devm_kfree(&pf->pdev->dev, ctxt);
1097 return ret;
1098 }
1099
1100
1101
1102
1103
1104
1105 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
1106 {
1107 struct ice_q_vector *q_vector;
1108 struct ice_pf *pf = vsi->back;
1109 struct ice_ring *ring;
1110
1111 if (!vsi->q_vectors[v_idx]) {
1112 dev_dbg(&pf->pdev->dev, "Queue vector at index %d not found\n",
1113 v_idx);
1114 return;
1115 }
1116 q_vector = vsi->q_vectors[v_idx];
1117
1118 ice_for_each_ring(ring, q_vector->tx)
1119 ring->q_vector = NULL;
1120 ice_for_each_ring(ring, q_vector->rx)
1121 ring->q_vector = NULL;
1122
1123
1124 if (vsi->netdev)
1125 netif_napi_del(&q_vector->napi);
1126
1127 devm_kfree(&pf->pdev->dev, q_vector);
1128 vsi->q_vectors[v_idx] = NULL;
1129 }
1130
1131
1132
1133
1134
1135 void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
1136 {
1137 int v_idx;
1138
1139 ice_for_each_q_vector(vsi, v_idx)
1140 ice_free_q_vector(vsi, v_idx);
1141 }
1142
1143
1144
1145
1146
1147
1148
1149
1150 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)
1151 {
1152 struct ice_pf *pf = vsi->back;
1153 struct ice_q_vector *q_vector;
1154
1155
1156 q_vector = devm_kzalloc(&pf->pdev->dev, sizeof(*q_vector), GFP_KERNEL);
1157 if (!q_vector)
1158 return -ENOMEM;
1159
1160 q_vector->vsi = vsi;
1161 q_vector->v_idx = v_idx;
1162 if (vsi->type == ICE_VSI_VF)
1163 goto out;
1164
1165 if (cpu_online(v_idx))
1166 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
1167
1168
1169
1170
1171
1172 if (vsi->netdev)
1173 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,
1174 NAPI_POLL_WEIGHT);
1175
1176 out:
1177
1178 vsi->q_vectors[v_idx] = q_vector;
1179
1180 return 0;
1181 }
1182
1183
1184
1185
1186
1187
1188
1189
1190 static int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
1191 {
1192 struct ice_pf *pf = vsi->back;
1193 int v_idx = 0, num_q_vectors;
1194 int err;
1195
1196 if (vsi->q_vectors[0]) {
1197 dev_dbg(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
1198 vsi->vsi_num);
1199 return -EEXIST;
1200 }
1201
1202 num_q_vectors = vsi->num_q_vectors;
1203
1204 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1205 err = ice_vsi_alloc_q_vector(vsi, v_idx);
1206 if (err)
1207 goto err_out;
1208 }
1209
1210 return 0;
1211
1212 err_out:
1213 while (v_idx--)
1214 ice_free_q_vector(vsi, v_idx);
1215
1216 dev_err(&pf->pdev->dev,
1217 "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
1218 vsi->num_q_vectors, vsi->vsi_num, err);
1219 vsi->num_q_vectors = 0;
1220 return err;
1221 }
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233 static int ice_vsi_setup_vector_base(struct ice_vsi *vsi)
1234 {
1235 struct ice_pf *pf = vsi->back;
1236 u16 num_q_vectors;
1237
1238
1239 if (vsi->type == ICE_VSI_VF)
1240 return 0;
1241
1242 if (vsi->base_vector) {
1243 dev_dbg(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
1244 vsi->vsi_num, vsi->base_vector);
1245 return -EEXIST;
1246 }
1247
1248 num_q_vectors = vsi->num_q_vectors;
1249
1250 vsi->base_vector = ice_get_res(pf, pf->irq_tracker, num_q_vectors,
1251 vsi->idx);
1252 if (vsi->base_vector < 0) {
1253 dev_err(&pf->pdev->dev,
1254 "Failed to get tracking for %d vectors for VSI %d, err=%d\n",
1255 num_q_vectors, vsi->vsi_num, vsi->base_vector);
1256 return -ENOENT;
1257 }
1258 pf->num_avail_sw_msix -= num_q_vectors;
1259
1260 return 0;
1261 }
1262
1263
1264
1265
1266
1267 static void ice_vsi_clear_rings(struct ice_vsi *vsi)
1268 {
1269 int i;
1270
1271 if (vsi->tx_rings) {
1272 for (i = 0; i < vsi->alloc_txq; i++) {
1273 if (vsi->tx_rings[i]) {
1274 kfree_rcu(vsi->tx_rings[i], rcu);
1275 vsi->tx_rings[i] = NULL;
1276 }
1277 }
1278 }
1279 if (vsi->rx_rings) {
1280 for (i = 0; i < vsi->alloc_rxq; i++) {
1281 if (vsi->rx_rings[i]) {
1282 kfree_rcu(vsi->rx_rings[i], rcu);
1283 vsi->rx_rings[i] = NULL;
1284 }
1285 }
1286 }
1287 }
1288
1289
1290
1291
1292
1293 static int ice_vsi_alloc_rings(struct ice_vsi *vsi)
1294 {
1295 struct ice_pf *pf = vsi->back;
1296 int i;
1297
1298
1299 for (i = 0; i < vsi->alloc_txq; i++) {
1300 struct ice_ring *ring;
1301
1302
1303 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1304
1305 if (!ring)
1306 goto err_out;
1307
1308 ring->q_index = i;
1309 ring->reg_idx = vsi->txq_map[i];
1310 ring->ring_active = false;
1311 ring->vsi = vsi;
1312 ring->dev = &pf->pdev->dev;
1313 ring->count = vsi->num_tx_desc;
1314 vsi->tx_rings[i] = ring;
1315 }
1316
1317
1318 for (i = 0; i < vsi->alloc_rxq; i++) {
1319 struct ice_ring *ring;
1320
1321
1322 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1323 if (!ring)
1324 goto err_out;
1325
1326 ring->q_index = i;
1327 ring->reg_idx = vsi->rxq_map[i];
1328 ring->ring_active = false;
1329 ring->vsi = vsi;
1330 ring->netdev = vsi->netdev;
1331 ring->dev = &pf->pdev->dev;
1332 ring->count = vsi->num_rx_desc;
1333 vsi->rx_rings[i] = ring;
1334 }
1335
1336 return 0;
1337
1338 err_out:
1339 ice_vsi_clear_rings(vsi);
1340 return -ENOMEM;
1341 }
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351 #ifdef CONFIG_DCB
1352 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
1353 #else
1354 static void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
1355 #endif
1356 {
1357 int q_vectors = vsi->num_q_vectors;
1358 int tx_rings_rem, rx_rings_rem;
1359 int v_id;
1360
1361
1362 tx_rings_rem = vsi->num_txq;
1363 rx_rings_rem = vsi->num_rxq;
1364
1365 for (v_id = 0; v_id < q_vectors; v_id++) {
1366 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
1367 int tx_rings_per_v, rx_rings_per_v, q_id, q_base;
1368
1369
1370 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id);
1371 q_vector->num_ring_tx = tx_rings_per_v;
1372 q_vector->tx.ring = NULL;
1373 q_vector->tx.itr_idx = ICE_TX_ITR;
1374 q_base = vsi->num_txq - tx_rings_rem;
1375
1376 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
1377 struct ice_ring *tx_ring = vsi->tx_rings[q_id];
1378
1379 tx_ring->q_vector = q_vector;
1380 tx_ring->next = q_vector->tx.ring;
1381 q_vector->tx.ring = tx_ring;
1382 }
1383 tx_rings_rem -= tx_rings_per_v;
1384
1385
1386 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id);
1387 q_vector->num_ring_rx = rx_rings_per_v;
1388 q_vector->rx.ring = NULL;
1389 q_vector->rx.itr_idx = ICE_RX_ITR;
1390 q_base = vsi->num_rxq - rx_rings_rem;
1391
1392 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
1393 struct ice_ring *rx_ring = vsi->rx_rings[q_id];
1394
1395 rx_ring->q_vector = q_vector;
1396 rx_ring->next = q_vector->rx.ring;
1397 q_vector->rx.ring = rx_ring;
1398 }
1399 rx_rings_rem -= rx_rings_per_v;
1400 }
1401 }
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412 int ice_vsi_manage_rss_lut(struct ice_vsi *vsi, bool ena)
1413 {
1414 int err = 0;
1415 u8 *lut;
1416
1417 lut = devm_kzalloc(&vsi->back->pdev->dev, vsi->rss_table_size,
1418 GFP_KERNEL);
1419 if (!lut)
1420 return -ENOMEM;
1421
1422 if (ena) {
1423 if (vsi->rss_lut_user)
1424 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1425 else
1426 ice_fill_rss_lut(lut, vsi->rss_table_size,
1427 vsi->rss_size);
1428 }
1429
1430 err = ice_set_rss(vsi, NULL, lut, vsi->rss_table_size);
1431 devm_kfree(&vsi->back->pdev->dev, lut);
1432 return err;
1433 }
1434
1435
1436
1437
1438
1439 static int ice_vsi_cfg_rss_lut_key(struct ice_vsi *vsi)
1440 {
1441 struct ice_aqc_get_set_rss_keys *key;
1442 struct ice_pf *pf = vsi->back;
1443 enum ice_status status;
1444 int err = 0;
1445 u8 *lut;
1446
1447 vsi->rss_size = min_t(int, vsi->rss_size, vsi->num_rxq);
1448
1449 lut = devm_kzalloc(&pf->pdev->dev, vsi->rss_table_size, GFP_KERNEL);
1450 if (!lut)
1451 return -ENOMEM;
1452
1453 if (vsi->rss_lut_user)
1454 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1455 else
1456 ice_fill_rss_lut(lut, vsi->rss_table_size, vsi->rss_size);
1457
1458 status = ice_aq_set_rss_lut(&pf->hw, vsi->idx, vsi->rss_lut_type, lut,
1459 vsi->rss_table_size);
1460
1461 if (status) {
1462 dev_err(&pf->pdev->dev,
1463 "set_rss_lut failed, error %d\n", status);
1464 err = -EIO;
1465 goto ice_vsi_cfg_rss_exit;
1466 }
1467
1468 key = devm_kzalloc(&pf->pdev->dev, sizeof(*key), GFP_KERNEL);
1469 if (!key) {
1470 err = -ENOMEM;
1471 goto ice_vsi_cfg_rss_exit;
1472 }
1473
1474 if (vsi->rss_hkey_user)
1475 memcpy(key,
1476 (struct ice_aqc_get_set_rss_keys *)vsi->rss_hkey_user,
1477 ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1478 else
1479 netdev_rss_key_fill((void *)key,
1480 ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1481
1482 status = ice_aq_set_rss_key(&pf->hw, vsi->idx, key);
1483
1484 if (status) {
1485 dev_err(&pf->pdev->dev, "set_rss_key failed, error %d\n",
1486 status);
1487 err = -EIO;
1488 }
1489
1490 devm_kfree(&pf->pdev->dev, key);
1491 ice_vsi_cfg_rss_exit:
1492 devm_kfree(&pf->pdev->dev, lut);
1493 return err;
1494 }
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506 int ice_add_mac_to_list(struct ice_vsi *vsi, struct list_head *add_list,
1507 const u8 *macaddr)
1508 {
1509 struct ice_fltr_list_entry *tmp;
1510 struct ice_pf *pf = vsi->back;
1511
1512 tmp = devm_kzalloc(&pf->pdev->dev, sizeof(*tmp), GFP_ATOMIC);
1513 if (!tmp)
1514 return -ENOMEM;
1515
1516 tmp->fltr_info.flag = ICE_FLTR_TX;
1517 tmp->fltr_info.src_id = ICE_SRC_ID_VSI;
1518 tmp->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
1519 tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1520 tmp->fltr_info.vsi_handle = vsi->idx;
1521 ether_addr_copy(tmp->fltr_info.l_data.mac.mac_addr, macaddr);
1522
1523 INIT_LIST_HEAD(&tmp->list_entry);
1524 list_add(&tmp->list_entry, add_list);
1525
1526 return 0;
1527 }
1528
1529
1530
1531
1532
1533 void ice_update_eth_stats(struct ice_vsi *vsi)
1534 {
1535 struct ice_eth_stats *prev_es, *cur_es;
1536 struct ice_hw *hw = &vsi->back->hw;
1537 u16 vsi_num = vsi->vsi_num;
1538
1539 prev_es = &vsi->eth_stats_prev;
1540 cur_es = &vsi->eth_stats;
1541
1542 ice_stat_update40(hw, GLV_GORCL(vsi_num), vsi->stat_offsets_loaded,
1543 &prev_es->rx_bytes, &cur_es->rx_bytes);
1544
1545 ice_stat_update40(hw, GLV_UPRCL(vsi_num), vsi->stat_offsets_loaded,
1546 &prev_es->rx_unicast, &cur_es->rx_unicast);
1547
1548 ice_stat_update40(hw, GLV_MPRCL(vsi_num), vsi->stat_offsets_loaded,
1549 &prev_es->rx_multicast, &cur_es->rx_multicast);
1550
1551 ice_stat_update40(hw, GLV_BPRCL(vsi_num), vsi->stat_offsets_loaded,
1552 &prev_es->rx_broadcast, &cur_es->rx_broadcast);
1553
1554 ice_stat_update32(hw, GLV_RDPC(vsi_num), vsi->stat_offsets_loaded,
1555 &prev_es->rx_discards, &cur_es->rx_discards);
1556
1557 ice_stat_update40(hw, GLV_GOTCL(vsi_num), vsi->stat_offsets_loaded,
1558 &prev_es->tx_bytes, &cur_es->tx_bytes);
1559
1560 ice_stat_update40(hw, GLV_UPTCL(vsi_num), vsi->stat_offsets_loaded,
1561 &prev_es->tx_unicast, &cur_es->tx_unicast);
1562
1563 ice_stat_update40(hw, GLV_MPTCL(vsi_num), vsi->stat_offsets_loaded,
1564 &prev_es->tx_multicast, &cur_es->tx_multicast);
1565
1566 ice_stat_update40(hw, GLV_BPTCL(vsi_num), vsi->stat_offsets_loaded,
1567 &prev_es->tx_broadcast, &cur_es->tx_broadcast);
1568
1569 ice_stat_update32(hw, GLV_TEPC(vsi_num), vsi->stat_offsets_loaded,
1570 &prev_es->tx_errors, &cur_es->tx_errors);
1571
1572 vsi->stat_offsets_loaded = true;
1573 }
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583 void ice_free_fltr_list(struct device *dev, struct list_head *h)
1584 {
1585 struct ice_fltr_list_entry *e, *tmp;
1586
1587 list_for_each_entry_safe(e, tmp, h, list_entry) {
1588 list_del(&e->list_entry);
1589 devm_kfree(dev, e);
1590 }
1591 }
1592
1593
1594
1595
1596
1597
1598 int ice_vsi_add_vlan(struct ice_vsi *vsi, u16 vid)
1599 {
1600 struct ice_fltr_list_entry *tmp;
1601 struct ice_pf *pf = vsi->back;
1602 LIST_HEAD(tmp_add_list);
1603 enum ice_status status;
1604 int err = 0;
1605
1606 tmp = devm_kzalloc(&pf->pdev->dev, sizeof(*tmp), GFP_KERNEL);
1607 if (!tmp)
1608 return -ENOMEM;
1609
1610 tmp->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1611 tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1612 tmp->fltr_info.flag = ICE_FLTR_TX;
1613 tmp->fltr_info.src_id = ICE_SRC_ID_VSI;
1614 tmp->fltr_info.vsi_handle = vsi->idx;
1615 tmp->fltr_info.l_data.vlan.vlan_id = vid;
1616
1617 INIT_LIST_HEAD(&tmp->list_entry);
1618 list_add(&tmp->list_entry, &tmp_add_list);
1619
1620 status = ice_add_vlan(&pf->hw, &tmp_add_list);
1621 if (status) {
1622 err = -ENODEV;
1623 dev_err(&pf->pdev->dev, "Failure Adding VLAN %d on VSI %i\n",
1624 vid, vsi->vsi_num);
1625 }
1626
1627 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
1628 return err;
1629 }
1630
1631
1632
1633
1634
1635
1636
1637
1638 int ice_vsi_kill_vlan(struct ice_vsi *vsi, u16 vid)
1639 {
1640 struct ice_fltr_list_entry *list;
1641 struct ice_pf *pf = vsi->back;
1642 LIST_HEAD(tmp_add_list);
1643 enum ice_status status;
1644 int err = 0;
1645
1646 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
1647 if (!list)
1648 return -ENOMEM;
1649
1650 list->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1651 list->fltr_info.vsi_handle = vsi->idx;
1652 list->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1653 list->fltr_info.l_data.vlan.vlan_id = vid;
1654 list->fltr_info.flag = ICE_FLTR_TX;
1655 list->fltr_info.src_id = ICE_SRC_ID_VSI;
1656
1657 INIT_LIST_HEAD(&list->list_entry);
1658 list_add(&list->list_entry, &tmp_add_list);
1659
1660 status = ice_remove_vlan(&pf->hw, &tmp_add_list);
1661 if (status == ICE_ERR_DOES_NOT_EXIST) {
1662 dev_dbg(&pf->pdev->dev,
1663 "Failed to remove VLAN %d on VSI %i, it does not exist, status: %d\n",
1664 vid, vsi->vsi_num, status);
1665 } else if (status) {
1666 dev_err(&pf->pdev->dev,
1667 "Error removing VLAN %d on vsi %i error: %d\n",
1668 vid, vsi->vsi_num, status);
1669 err = -EIO;
1670 }
1671
1672 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
1673 return err;
1674 }
1675
1676
1677
1678
1679
1680
1681
1682
1683 int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)
1684 {
1685 u16 i;
1686
1687 if (vsi->type == ICE_VSI_VF)
1688 goto setup_rings;
1689
1690 if (vsi->netdev && vsi->netdev->mtu > ETH_DATA_LEN)
1691 vsi->max_frame = vsi->netdev->mtu +
1692 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
1693 else
1694 vsi->max_frame = ICE_RXBUF_2048;
1695
1696 vsi->rx_buf_len = ICE_RXBUF_2048;
1697 setup_rings:
1698
1699 for (i = 0; i < vsi->num_rxq; i++) {
1700 int err;
1701
1702 err = ice_setup_rx_ctx(vsi->rx_rings[i]);
1703 if (err) {
1704 dev_err(&vsi->back->pdev->dev,
1705 "ice_setup_rx_ctx failed for RxQ %d, err %d\n",
1706 i, err);
1707 return err;
1708 }
1709 }
1710
1711 return 0;
1712 }
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722 static int
1723 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring, u16 tc_q_idx,
1724 struct ice_aqc_add_tx_qgrp *qg_buf, u8 tc)
1725 {
1726 struct ice_tlan_ctx tlan_ctx = { 0 };
1727 struct ice_aqc_add_txqs_perq *txq;
1728 struct ice_pf *pf = vsi->back;
1729 u8 buf_len = sizeof(*qg_buf);
1730 enum ice_status status;
1731 u16 pf_q;
1732
1733 pf_q = ring->reg_idx;
1734 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
1735
1736 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
1737 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
1738 ice_tlan_ctx_info);
1739
1740
1741
1742
1743 ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q);
1744
1745
1746
1747
1748 ring->q_handle = tc_q_idx;
1749
1750 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle,
1751 1, qg_buf, buf_len, NULL);
1752 if (status) {
1753 dev_err(&pf->pdev->dev,
1754 "Failed to set LAN Tx queue context, error: %d\n",
1755 status);
1756 return -ENODEV;
1757 }
1758
1759
1760
1761
1762
1763 txq = &qg_buf->txqs[0];
1764 if (pf_q == le16_to_cpu(txq->txq_id))
1765 ring->txq_teid = le32_to_cpu(txq->q_teid);
1766
1767 return 0;
1768 }
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 static int
1780 ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_ring **rings, int offset)
1781 {
1782 struct ice_aqc_add_tx_qgrp *qg_buf;
1783 struct ice_pf *pf = vsi->back;
1784 u16 q_idx = 0, i;
1785 int err = 0;
1786 u8 tc;
1787
1788 qg_buf = devm_kzalloc(&pf->pdev->dev, sizeof(*qg_buf), GFP_KERNEL);
1789 if (!qg_buf)
1790 return -ENOMEM;
1791
1792 qg_buf->num_txqs = 1;
1793
1794
1795 ice_for_each_traffic_class(tc) {
1796 if (!(vsi->tc_cfg.ena_tc & BIT(tc)))
1797 break;
1798
1799 for (i = 0; i < vsi->tc_cfg.tc_info[tc].qcount_tx; i++) {
1800 err = ice_vsi_cfg_txq(vsi, rings[q_idx], i + offset,
1801 qg_buf, tc);
1802 if (err)
1803 goto err_cfg_txqs;
1804
1805 q_idx++;
1806 }
1807 }
1808 err_cfg_txqs:
1809 devm_kfree(&pf->pdev->dev, qg_buf);
1810 return err;
1811 }
1812
1813
1814
1815
1816
1817
1818
1819
1820 int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)
1821 {
1822 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, 0);
1823 }
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833 u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)
1834 {
1835 u32 val = intrl / gran;
1836
1837 if (val)
1838 return val | GLINT_RATE_INTRL_ENA_M;
1839 return 0;
1840 }
1841
1842
1843
1844
1845
1846 static void ice_cfg_itr_gran(struct ice_hw *hw)
1847 {
1848 u32 regval = rd32(hw, GLINT_CTL);
1849
1850
1851 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
1852 (((regval & GLINT_CTL_ITR_GRAN_200_M) >>
1853 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&
1854 (((regval & GLINT_CTL_ITR_GRAN_100_M) >>
1855 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&
1856 (((regval & GLINT_CTL_ITR_GRAN_50_M) >>
1857 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&
1858 (((regval & GLINT_CTL_ITR_GRAN_25_M) >>
1859 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))
1860 return;
1861
1862 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &
1863 GLINT_CTL_ITR_GRAN_200_M) |
1864 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &
1865 GLINT_CTL_ITR_GRAN_100_M) |
1866 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &
1867 GLINT_CTL_ITR_GRAN_50_M) |
1868 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &
1869 GLINT_CTL_ITR_GRAN_25_M);
1870 wr32(hw, GLINT_CTL, regval);
1871 }
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881 static void
1882 ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
1883 {
1884 ice_cfg_itr_gran(hw);
1885
1886 if (q_vector->num_ring_rx) {
1887 struct ice_ring_container *rc = &q_vector->rx;
1888
1889
1890 if (!rc->itr_setting)
1891 rc->itr_setting = ICE_DFLT_RX_ITR;
1892
1893 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1894 rc->next_update = jiffies + 1;
1895 rc->current_itr = rc->target_itr;
1896 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
1897 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1898 }
1899
1900 if (q_vector->num_ring_tx) {
1901 struct ice_ring_container *rc = &q_vector->tx;
1902
1903
1904 if (!rc->itr_setting)
1905 rc->itr_setting = ICE_DFLT_TX_ITR;
1906
1907 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1908 rc->next_update = jiffies + 1;
1909 rc->current_itr = rc->target_itr;
1910 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
1911 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1912 }
1913 }
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925 #ifdef CONFIG_PCI_IOV
1926 void
1927 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1928 #else
1929 static void
1930 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1931 #endif
1932 {
1933 struct ice_pf *pf = vsi->back;
1934 struct ice_hw *hw = &pf->hw;
1935 u32 val;
1936
1937 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;
1938
1939 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
1940 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);
1941
1942 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
1943 }
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955 #ifdef CONFIG_PCI_IOV
1956 void
1957 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1958 #else
1959 static void
1960 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1961 #endif
1962 {
1963 struct ice_pf *pf = vsi->back;
1964 struct ice_hw *hw = &pf->hw;
1965 u32 val;
1966
1967 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;
1968
1969 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
1970 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);
1971
1972 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
1973
1974 ice_flush(hw);
1975 }
1976
1977
1978
1979
1980
1981
1982
1983
1984 void ice_vsi_cfg_msix(struct ice_vsi *vsi)
1985 {
1986 struct ice_pf *pf = vsi->back;
1987 struct ice_hw *hw = &pf->hw;
1988 u32 txq = 0, rxq = 0;
1989 int i, q;
1990
1991 for (i = 0; i < vsi->num_q_vectors; i++) {
1992 struct ice_q_vector *q_vector = vsi->q_vectors[i];
1993 u16 reg_idx = q_vector->reg_idx;
1994
1995 ice_cfg_itr(hw, q_vector);
1996
1997 wr32(hw, GLINT_RATE(reg_idx),
1998 ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011 for (q = 0; q < q_vector->num_ring_tx; q++) {
2012 ice_cfg_txq_interrupt(vsi, txq, reg_idx,
2013 q_vector->tx.itr_idx);
2014 txq++;
2015 }
2016
2017 for (q = 0; q < q_vector->num_ring_rx; q++) {
2018 ice_cfg_rxq_interrupt(vsi, rxq, reg_idx,
2019 q_vector->rx.itr_idx);
2020 rxq++;
2021 }
2022 }
2023 }
2024
2025
2026
2027
2028
2029 int ice_vsi_manage_vlan_insertion(struct ice_vsi *vsi)
2030 {
2031 struct device *dev = &vsi->back->pdev->dev;
2032 struct ice_hw *hw = &vsi->back->hw;
2033 struct ice_vsi_ctx *ctxt;
2034 enum ice_status status;
2035 int ret = 0;
2036
2037 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
2038 if (!ctxt)
2039 return -ENOMEM;
2040
2041
2042
2043
2044
2045 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
2046
2047
2048 ctxt->info.vlan_flags |= (vsi->info.vlan_flags &
2049 ICE_AQ_VSI_VLAN_EMOD_M);
2050
2051 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
2052
2053 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
2054 if (status) {
2055 dev_err(dev, "update VSI for VLAN insert failed, err %d aq_err %d\n",
2056 status, hw->adminq.sq_last_status);
2057 ret = -EIO;
2058 goto out;
2059 }
2060
2061 vsi->info.vlan_flags = ctxt->info.vlan_flags;
2062 out:
2063 devm_kfree(dev, ctxt);
2064 return ret;
2065 }
2066
2067
2068
2069
2070
2071
2072 int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
2073 {
2074 struct device *dev = &vsi->back->pdev->dev;
2075 struct ice_hw *hw = &vsi->back->hw;
2076 struct ice_vsi_ctx *ctxt;
2077 enum ice_status status;
2078 int ret = 0;
2079
2080 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
2081 if (!ctxt)
2082 return -ENOMEM;
2083
2084
2085
2086
2087
2088 if (ena)
2089
2090 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2091 else
2092
2093 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2094
2095
2096 ctxt->info.vlan_flags |= ICE_AQ_VSI_VLAN_MODE_ALL;
2097
2098 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
2099
2100 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
2101 if (status) {
2102 dev_err(dev, "update VSI for VLAN strip failed, ena = %d err %d aq_err %d\n",
2103 ena, status, hw->adminq.sq_last_status);
2104 ret = -EIO;
2105 goto out;
2106 }
2107
2108 vsi->info.vlan_flags = ctxt->info.vlan_flags;
2109 out:
2110 devm_kfree(dev, ctxt);
2111 return ret;
2112 }
2113
2114
2115
2116
2117
2118
2119
2120 int ice_vsi_start_rx_rings(struct ice_vsi *vsi)
2121 {
2122 return ice_vsi_ctrl_rx_rings(vsi, true);
2123 }
2124
2125
2126
2127
2128
2129
2130
2131 int ice_vsi_stop_rx_rings(struct ice_vsi *vsi)
2132 {
2133 return ice_vsi_ctrl_rx_rings(vsi, false);
2134 }
2135
2136
2137
2138
2139
2140
2141 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)
2142 {
2143 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
2144 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
2145 GLINT_DYN_CTL_SWINT_TRIG_M |
2146 GLINT_DYN_CTL_INTENA_M);
2147 }
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157 #ifndef CONFIG_PCI_IOV
2158 static
2159 #endif
2160 int
2161 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2162 u16 rel_vmvf_num, struct ice_ring *ring,
2163 struct ice_txq_meta *txq_meta)
2164 {
2165 struct ice_pf *pf = vsi->back;
2166 struct ice_q_vector *q_vector;
2167 struct ice_hw *hw = &pf->hw;
2168 enum ice_status status;
2169 u32 val;
2170
2171
2172 val = rd32(hw, QINT_TQCTL(ring->reg_idx));
2173 val &= ~QINT_TQCTL_CAUSE_ENA_M;
2174 wr32(hw, QINT_TQCTL(ring->reg_idx), val);
2175
2176
2177 ndelay(100);
2178
2179
2180
2181
2182 q_vector = ring->q_vector;
2183 if (q_vector)
2184 ice_trigger_sw_intr(hw, q_vector);
2185
2186 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
2187 txq_meta->tc, 1, &txq_meta->q_handle,
2188 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
2189 rel_vmvf_num, NULL);
2190
2191
2192
2193
2194
2195
2196 if (status == ICE_ERR_RESET_ONGOING) {
2197 dev_dbg(&vsi->back->pdev->dev,
2198 "Reset in progress. LAN Tx queues already disabled\n");
2199 } else if (status == ICE_ERR_DOES_NOT_EXIST) {
2200 dev_dbg(&vsi->back->pdev->dev,
2201 "LAN Tx queues do not exist, nothing to disable\n");
2202 } else if (status) {
2203 dev_err(&vsi->back->pdev->dev,
2204 "Failed to disable LAN Tx queues, error: %d\n", status);
2205 return -ENODEV;
2206 }
2207
2208 return 0;
2209 }
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220 #ifndef CONFIG_PCI_IOV
2221 static
2222 #endif
2223 void
2224 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring,
2225 struct ice_txq_meta *txq_meta)
2226 {
2227 u8 tc = 0;
2228
2229 #ifdef CONFIG_DCB
2230 tc = ring->dcb_tc;
2231 #endif
2232 txq_meta->q_id = ring->reg_idx;
2233 txq_meta->q_teid = ring->txq_teid;
2234 txq_meta->q_handle = ring->q_handle;
2235 txq_meta->vsi_idx = vsi->idx;
2236 txq_meta->tc = tc;
2237 }
2238
2239
2240
2241
2242
2243
2244
2245
2246 static int
2247 ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2248 u16 rel_vmvf_num, struct ice_ring **rings)
2249 {
2250 u16 i, q_idx = 0;
2251 int status;
2252 u8 tc;
2253
2254 if (vsi->num_txq > ICE_LAN_TXQ_MAX_QDIS)
2255 return -EINVAL;
2256
2257
2258 ice_for_each_traffic_class(tc) {
2259 if (!(vsi->tc_cfg.ena_tc & BIT(tc)))
2260 break;
2261
2262 for (i = 0; i < vsi->tc_cfg.tc_info[tc].qcount_tx; i++) {
2263 struct ice_txq_meta txq_meta = { };
2264
2265 if (!rings || !rings[q_idx])
2266 return -EINVAL;
2267
2268 ice_fill_txq_meta(vsi, rings[q_idx], &txq_meta);
2269 status = ice_vsi_stop_tx_ring(vsi, rst_src,
2270 rel_vmvf_num,
2271 rings[q_idx], &txq_meta);
2272
2273 if (status)
2274 return status;
2275
2276 q_idx++;
2277 }
2278 }
2279
2280 return 0;
2281 }
2282
2283
2284
2285
2286
2287
2288
2289 int
2290 ice_vsi_stop_lan_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2291 u16 rel_vmvf_num)
2292 {
2293 return ice_vsi_stop_tx_rings(vsi, rst_src, rel_vmvf_num, vsi->tx_rings);
2294 }
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304 int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena, bool vlan_promisc)
2305 {
2306 struct ice_vsi_ctx *ctxt;
2307 struct device *dev;
2308 struct ice_pf *pf;
2309 int status;
2310
2311 if (!vsi)
2312 return -EINVAL;
2313
2314 pf = vsi->back;
2315 dev = &pf->pdev->dev;
2316 ctxt = devm_kzalloc(dev, sizeof(*ctxt), GFP_KERNEL);
2317 if (!ctxt)
2318 return -ENOMEM;
2319
2320 ctxt->info = vsi->info;
2321
2322 if (ena) {
2323 ctxt->info.sec_flags |=
2324 ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2325 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2326 ctxt->info.sw_flags2 |= ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2327 } else {
2328 ctxt->info.sec_flags &=
2329 ~(ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2330 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S);
2331 ctxt->info.sw_flags2 &= ~ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2332 }
2333
2334 if (!vlan_promisc)
2335 ctxt->info.valid_sections =
2336 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID |
2337 ICE_AQ_VSI_PROP_SW_VALID);
2338
2339 status = ice_update_vsi(&pf->hw, vsi->idx, ctxt, NULL);
2340 if (status) {
2341 netdev_err(vsi->netdev, "%sabling VLAN pruning on VSI handle: %d, VSI HW ID: %d failed, err = %d, aq_err = %d\n",
2342 ena ? "En" : "Dis", vsi->idx, vsi->vsi_num, status,
2343 pf->hw.adminq.sq_last_status);
2344 goto err_out;
2345 }
2346
2347 vsi->info.sec_flags = ctxt->info.sec_flags;
2348 vsi->info.sw_flags2 = ctxt->info.sw_flags2;
2349
2350 devm_kfree(dev, ctxt);
2351 return 0;
2352
2353 err_out:
2354 devm_kfree(dev, ctxt);
2355 return -EIO;
2356 }
2357
2358 static void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
2359 {
2360 struct ice_dcbx_cfg *cfg = &vsi->port_info->local_dcbx_cfg;
2361
2362 vsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg);
2363 vsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);
2364 }
2365
2366
2367
2368
2369
2370 static int
2371 ice_vsi_set_q_vectors_reg_idx(struct ice_vsi *vsi)
2372 {
2373 u16 i;
2374
2375 if (!vsi || !vsi->q_vectors)
2376 return -EINVAL;
2377
2378 ice_for_each_q_vector(vsi, i) {
2379 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2380
2381 if (!q_vector) {
2382 dev_err(&vsi->back->pdev->dev,
2383 "Failed to set reg_idx on q_vector %d VSI %d\n",
2384 i, vsi->vsi_num);
2385 goto clear_reg_idx;
2386 }
2387
2388 if (vsi->type == ICE_VSI_VF) {
2389 struct ice_vf *vf = &vsi->back->vf[vsi->vf_id];
2390
2391 q_vector->reg_idx = ice_calc_vf_reg_idx(vf, q_vector);
2392 } else {
2393 q_vector->reg_idx =
2394 q_vector->v_idx + vsi->base_vector;
2395 }
2396 }
2397
2398 return 0;
2399
2400 clear_reg_idx:
2401 ice_for_each_q_vector(vsi, i) {
2402 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2403
2404 if (q_vector)
2405 q_vector->reg_idx = 0;
2406 }
2407
2408 return -EINVAL;
2409 }
2410
2411
2412
2413
2414
2415
2416 static void
2417 ice_vsi_add_rem_eth_mac(struct ice_vsi *vsi, bool add_rule)
2418 {
2419 struct ice_fltr_list_entry *list;
2420 struct ice_pf *pf = vsi->back;
2421 LIST_HEAD(tmp_add_list);
2422 enum ice_status status;
2423
2424 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
2425 if (!list)
2426 return;
2427
2428 list->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2429 list->fltr_info.fltr_act = ICE_DROP_PACKET;
2430 list->fltr_info.flag = ICE_FLTR_TX;
2431 list->fltr_info.src_id = ICE_SRC_ID_VSI;
2432 list->fltr_info.vsi_handle = vsi->idx;
2433 list->fltr_info.l_data.ethertype_mac.ethertype = vsi->ethtype;
2434
2435 INIT_LIST_HEAD(&list->list_entry);
2436 list_add(&list->list_entry, &tmp_add_list);
2437
2438 if (add_rule)
2439 status = ice_add_eth_mac(&pf->hw, &tmp_add_list);
2440 else
2441 status = ice_remove_eth_mac(&pf->hw, &tmp_add_list);
2442
2443 if (status)
2444 dev_err(&pf->pdev->dev,
2445 "Failure Adding or Removing Ethertype on VSI %i error: %d\n",
2446 vsi->vsi_num, status);
2447
2448 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
2449 }
2450
2451
2452
2453
2454
2455
2456
2457 void ice_cfg_sw_lldp(struct ice_vsi *vsi, bool tx, bool create)
2458 {
2459 struct ice_fltr_list_entry *list;
2460 struct ice_pf *pf = vsi->back;
2461 LIST_HEAD(tmp_add_list);
2462 enum ice_status status;
2463
2464 list = devm_kzalloc(&pf->pdev->dev, sizeof(*list), GFP_KERNEL);
2465 if (!list)
2466 return;
2467
2468 list->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2469 list->fltr_info.vsi_handle = vsi->idx;
2470 list->fltr_info.l_data.ethertype_mac.ethertype = ETH_P_LLDP;
2471
2472 if (tx) {
2473 list->fltr_info.fltr_act = ICE_DROP_PACKET;
2474 list->fltr_info.flag = ICE_FLTR_TX;
2475 list->fltr_info.src_id = ICE_SRC_ID_VSI;
2476 } else {
2477 list->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2478 list->fltr_info.flag = ICE_FLTR_RX;
2479 list->fltr_info.src_id = ICE_SRC_ID_LPORT;
2480 }
2481
2482 INIT_LIST_HEAD(&list->list_entry);
2483 list_add(&list->list_entry, &tmp_add_list);
2484
2485 if (create)
2486 status = ice_add_eth_mac(&pf->hw, &tmp_add_list);
2487 else
2488 status = ice_remove_eth_mac(&pf->hw, &tmp_add_list);
2489
2490 if (status)
2491 dev_err(&pf->pdev->dev,
2492 "Fail %s %s LLDP rule on VSI %i error: %d\n",
2493 create ? "adding" : "removing", tx ? "TX" : "RX",
2494 vsi->vsi_num, status);
2495
2496 ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
2497 }
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513 struct ice_vsi *
2514 ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
2515 enum ice_vsi_type type, u16 vf_id)
2516 {
2517 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2518 struct device *dev = &pf->pdev->dev;
2519 enum ice_status status;
2520 struct ice_vsi *vsi;
2521 int ret, i;
2522
2523 if (type == ICE_VSI_VF)
2524 vsi = ice_vsi_alloc(pf, type, vf_id);
2525 else
2526 vsi = ice_vsi_alloc(pf, type, ICE_INVAL_VFID);
2527
2528 if (!vsi) {
2529 dev_err(dev, "could not allocate VSI\n");
2530 return NULL;
2531 }
2532
2533 vsi->port_info = pi;
2534 vsi->vsw = pf->first_sw;
2535 if (vsi->type == ICE_VSI_PF)
2536 vsi->ethtype = ETH_P_PAUSE;
2537
2538 if (vsi->type == ICE_VSI_VF)
2539 vsi->vf_id = vf_id;
2540
2541 if (ice_vsi_get_qs(vsi)) {
2542 dev_err(dev, "Failed to allocate queues. vsi->idx = %d\n",
2543 vsi->idx);
2544 goto unroll_get_qs;
2545 }
2546
2547
2548 ice_vsi_set_rss_params(vsi);
2549
2550
2551 ice_vsi_set_tc_cfg(vsi);
2552
2553
2554 ret = ice_vsi_init(vsi);
2555 if (ret)
2556 goto unroll_get_qs;
2557
2558 switch (vsi->type) {
2559 case ICE_VSI_PF:
2560 ret = ice_vsi_alloc_q_vectors(vsi);
2561 if (ret)
2562 goto unroll_vsi_init;
2563
2564 ret = ice_vsi_setup_vector_base(vsi);
2565 if (ret)
2566 goto unroll_alloc_q_vector;
2567
2568 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2569 if (ret)
2570 goto unroll_vector_base;
2571
2572 ret = ice_vsi_alloc_rings(vsi);
2573 if (ret)
2574 goto unroll_vector_base;
2575
2576 ice_vsi_map_rings_to_vectors(vsi);
2577
2578
2579
2580
2581
2582 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2583 ice_vsi_cfg_rss_lut_key(vsi);
2584 break;
2585 case ICE_VSI_VF:
2586
2587
2588
2589
2590
2591 ret = ice_vsi_alloc_q_vectors(vsi);
2592 if (ret)
2593 goto unroll_vsi_init;
2594
2595 ret = ice_vsi_alloc_rings(vsi);
2596 if (ret)
2597 goto unroll_alloc_q_vector;
2598
2599 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2600 if (ret)
2601 goto unroll_vector_base;
2602
2603
2604
2605
2606
2607 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2608 ice_vsi_cfg_rss_lut_key(vsi);
2609 break;
2610 case ICE_VSI_LB:
2611 ret = ice_vsi_alloc_rings(vsi);
2612 if (ret)
2613 goto unroll_vsi_init;
2614 break;
2615 default:
2616
2617 goto unroll_vsi_init;
2618 }
2619
2620
2621 for (i = 0; i < vsi->tc_cfg.numtc; i++)
2622 max_txqs[i] = vsi->alloc_txq;
2623
2624 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
2625 max_txqs);
2626 if (status) {
2627 dev_err(&pf->pdev->dev,
2628 "VSI %d failed lan queue config, error %d\n",
2629 vsi->vsi_num, status);
2630 goto unroll_vector_base;
2631 }
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643 if (!ice_is_safe_mode(pf)) {
2644 if (vsi->type == ICE_VSI_PF) {
2645 ice_vsi_add_rem_eth_mac(vsi, true);
2646
2647
2648 ice_cfg_sw_lldp(vsi, true, true);
2649
2650
2651 if (!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2652 ice_cfg_sw_lldp(vsi, false, true);
2653 }
2654 }
2655
2656 return vsi;
2657
2658 unroll_vector_base:
2659
2660 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2661 pf->num_avail_sw_msix += vsi->num_q_vectors;
2662 unroll_alloc_q_vector:
2663 ice_vsi_free_q_vectors(vsi);
2664 unroll_vsi_init:
2665 ice_vsi_delete(vsi);
2666 unroll_get_qs:
2667 ice_vsi_put_qs(vsi);
2668 ice_vsi_clear(vsi);
2669
2670 return NULL;
2671 }
2672
2673
2674
2675
2676
2677 static void ice_vsi_release_msix(struct ice_vsi *vsi)
2678 {
2679 struct ice_pf *pf = vsi->back;
2680 struct ice_hw *hw = &pf->hw;
2681 u32 txq = 0;
2682 u32 rxq = 0;
2683 int i, q;
2684
2685 for (i = 0; i < vsi->num_q_vectors; i++) {
2686 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2687 u16 reg_idx = q_vector->reg_idx;
2688
2689 wr32(hw, GLINT_ITR(ICE_IDX_ITR0, reg_idx), 0);
2690 wr32(hw, GLINT_ITR(ICE_IDX_ITR1, reg_idx), 0);
2691 for (q = 0; q < q_vector->num_ring_tx; q++) {
2692 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), 0);
2693 txq++;
2694 }
2695
2696 for (q = 0; q < q_vector->num_ring_rx; q++) {
2697 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), 0);
2698 rxq++;
2699 }
2700 }
2701
2702 ice_flush(hw);
2703 }
2704
2705
2706
2707
2708
2709 void ice_vsi_free_irq(struct ice_vsi *vsi)
2710 {
2711 struct ice_pf *pf = vsi->back;
2712 int base = vsi->base_vector;
2713 int i;
2714
2715 if (!vsi->q_vectors || !vsi->irqs_ready)
2716 return;
2717
2718 ice_vsi_release_msix(vsi);
2719 if (vsi->type == ICE_VSI_VF)
2720 return;
2721
2722 vsi->irqs_ready = false;
2723 ice_for_each_q_vector(vsi, i) {
2724 u16 vector = i + base;
2725 int irq_num;
2726
2727 irq_num = pf->msix_entries[vector].vector;
2728
2729
2730 if (!vsi->q_vectors[i] ||
2731 !(vsi->q_vectors[i]->num_ring_tx ||
2732 vsi->q_vectors[i]->num_ring_rx))
2733 continue;
2734
2735
2736 irq_set_affinity_notifier(irq_num, NULL);
2737
2738
2739 irq_set_affinity_hint(irq_num, NULL);
2740 synchronize_irq(irq_num);
2741 devm_free_irq(&pf->pdev->dev, irq_num,
2742 vsi->q_vectors[i]);
2743 }
2744 }
2745
2746
2747
2748
2749
2750 void ice_vsi_free_tx_rings(struct ice_vsi *vsi)
2751 {
2752 int i;
2753
2754 if (!vsi->tx_rings)
2755 return;
2756
2757 ice_for_each_txq(vsi, i)
2758 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
2759 ice_free_tx_ring(vsi->tx_rings[i]);
2760 }
2761
2762
2763
2764
2765
2766 void ice_vsi_free_rx_rings(struct ice_vsi *vsi)
2767 {
2768 int i;
2769
2770 if (!vsi->rx_rings)
2771 return;
2772
2773 ice_for_each_rxq(vsi, i)
2774 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
2775 ice_free_rx_ring(vsi->rx_rings[i]);
2776 }
2777
2778
2779
2780
2781
2782 void ice_vsi_close(struct ice_vsi *vsi)
2783 {
2784 if (!test_and_set_bit(__ICE_DOWN, vsi->state))
2785 ice_down(vsi);
2786
2787 ice_vsi_free_irq(vsi);
2788 ice_vsi_free_tx_rings(vsi);
2789 ice_vsi_free_rx_rings(vsi);
2790 }
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800 int ice_free_res(struct ice_res_tracker *res, u16 index, u16 id)
2801 {
2802 int count = 0;
2803 int i;
2804
2805 if (!res || index >= res->end)
2806 return -EINVAL;
2807
2808 id |= ICE_RES_VALID_BIT;
2809 for (i = index; i < res->end && res->list[i] == id; i++) {
2810 res->list[i] = 0;
2811 count++;
2812 }
2813
2814 return count;
2815 }
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825 static int ice_search_res(struct ice_res_tracker *res, u16 needed, u16 id)
2826 {
2827 int start = 0, end = 0;
2828
2829 if (needed > res->end)
2830 return -ENOMEM;
2831
2832 id |= ICE_RES_VALID_BIT;
2833
2834 do {
2835
2836 if (res->list[end++] & ICE_RES_VALID_BIT) {
2837 start = end;
2838 if ((start + needed) > res->end)
2839 break;
2840 }
2841
2842 if (end == (start + needed)) {
2843 int i = start;
2844
2845
2846 while (i != end)
2847 res->list[i++] = id;
2848
2849 return start;
2850 }
2851 } while (end < res->end);
2852
2853 return -ENOMEM;
2854 }
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865 int
2866 ice_get_res(struct ice_pf *pf, struct ice_res_tracker *res, u16 needed, u16 id)
2867 {
2868 if (!res || !pf)
2869 return -EINVAL;
2870
2871 if (!needed || needed > res->num_entries || id >= ICE_RES_VALID_BIT) {
2872 dev_err(&pf->pdev->dev,
2873 "param err: needed=%d, num_entries = %d id=0x%04x\n",
2874 needed, res->num_entries, id);
2875 return -EINVAL;
2876 }
2877
2878 return ice_search_res(res, needed, id);
2879 }
2880
2881
2882
2883
2884
2885 void ice_vsi_dis_irq(struct ice_vsi *vsi)
2886 {
2887 int base = vsi->base_vector;
2888 struct ice_pf *pf = vsi->back;
2889 struct ice_hw *hw = &pf->hw;
2890 u32 val;
2891 int i;
2892
2893
2894 if (vsi->tx_rings) {
2895 ice_for_each_txq(vsi, i) {
2896 if (vsi->tx_rings[i]) {
2897 u16 reg;
2898
2899 reg = vsi->tx_rings[i]->reg_idx;
2900 val = rd32(hw, QINT_TQCTL(reg));
2901 val &= ~QINT_TQCTL_CAUSE_ENA_M;
2902 wr32(hw, QINT_TQCTL(reg), val);
2903 }
2904 }
2905 }
2906
2907 if (vsi->rx_rings) {
2908 ice_for_each_rxq(vsi, i) {
2909 if (vsi->rx_rings[i]) {
2910 u16 reg;
2911
2912 reg = vsi->rx_rings[i]->reg_idx;
2913 val = rd32(hw, QINT_RQCTL(reg));
2914 val &= ~QINT_RQCTL_CAUSE_ENA_M;
2915 wr32(hw, QINT_RQCTL(reg), val);
2916 }
2917 }
2918 }
2919
2920
2921 ice_for_each_q_vector(vsi, i) {
2922 if (!vsi->q_vectors[i])
2923 continue;
2924 wr32(hw, GLINT_DYN_CTL(vsi->q_vectors[i]->reg_idx), 0);
2925 }
2926
2927 ice_flush(hw);
2928
2929
2930 if (vsi->type == ICE_VSI_VF)
2931 return;
2932
2933 ice_for_each_q_vector(vsi, i)
2934 synchronize_irq(pf->msix_entries[i + base].vector);
2935 }
2936
2937
2938
2939
2940
2941 void ice_napi_del(struct ice_vsi *vsi)
2942 {
2943 int v_idx;
2944
2945 if (!vsi->netdev)
2946 return;
2947
2948 ice_for_each_q_vector(vsi, v_idx)
2949 netif_napi_del(&vsi->q_vectors[v_idx]->napi);
2950 }
2951
2952
2953
2954
2955
2956
2957
2958 int ice_vsi_release(struct ice_vsi *vsi)
2959 {
2960 struct ice_pf *pf;
2961
2962 if (!vsi->back)
2963 return -ENODEV;
2964 pf = vsi->back;
2965
2966
2967
2968
2969
2970
2971
2972 if (vsi->netdev && !ice_is_reset_in_progress(pf->state))
2973 unregister_netdev(vsi->netdev);
2974
2975 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2976 ice_rss_clean(vsi);
2977
2978
2979 if (vsi->type != ICE_VSI_LB)
2980 ice_vsi_dis_irq(vsi);
2981 ice_vsi_close(vsi);
2982
2983
2984
2985
2986
2987
2988 if (vsi->type != ICE_VSI_VF) {
2989
2990 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2991 pf->num_avail_sw_msix += vsi->num_q_vectors;
2992 }
2993
2994 if (!ice_is_safe_mode(pf)) {
2995 if (vsi->type == ICE_VSI_PF) {
2996 ice_vsi_add_rem_eth_mac(vsi, false);
2997 ice_cfg_sw_lldp(vsi, true, false);
2998
2999
3000
3001 if (!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
3002 ice_cfg_sw_lldp(vsi, false, false);
3003 }
3004 }
3005
3006 ice_remove_vsi_fltr(&pf->hw, vsi->idx);
3007 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
3008 ice_vsi_delete(vsi);
3009 ice_vsi_free_q_vectors(vsi);
3010
3011
3012 if (vsi->netdev && test_bit(__ICE_DOWN, vsi->state)) {
3013 free_netdev(vsi->netdev);
3014 vsi->netdev = NULL;
3015 }
3016
3017 ice_vsi_clear_rings(vsi);
3018
3019 ice_vsi_put_qs(vsi);
3020
3021
3022
3023
3024
3025 if (!ice_is_reset_in_progress(pf->state))
3026 ice_vsi_clear(vsi);
3027
3028 return 0;
3029 }
3030
3031
3032
3033
3034
3035
3036
3037 int ice_vsi_rebuild(struct ice_vsi *vsi)
3038 {
3039 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
3040 struct ice_vf *vf = NULL;
3041 enum ice_status status;
3042 struct ice_pf *pf;
3043 int ret, i;
3044
3045 if (!vsi)
3046 return -EINVAL;
3047
3048 pf = vsi->back;
3049 if (vsi->type == ICE_VSI_VF)
3050 vf = &pf->vf[vsi->vf_id];
3051
3052 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
3053 ice_vsi_free_q_vectors(vsi);
3054
3055
3056
3057
3058
3059
3060 if (vsi->type != ICE_VSI_VF) {
3061
3062 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
3063 pf->num_avail_sw_msix += vsi->num_q_vectors;
3064 vsi->base_vector = 0;
3065 }
3066
3067 ice_vsi_put_qs(vsi);
3068 ice_vsi_clear_rings(vsi);
3069 ice_vsi_free_arrays(vsi);
3070 ice_dev_onetime_setup(&pf->hw);
3071 if (vsi->type == ICE_VSI_VF)
3072 ice_vsi_set_num_qs(vsi, vf->vf_id);
3073 else
3074 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
3075
3076 ret = ice_vsi_alloc_arrays(vsi);
3077 if (ret < 0)
3078 goto err_vsi;
3079
3080 ice_vsi_get_qs(vsi);
3081 ice_vsi_set_tc_cfg(vsi);
3082
3083
3084 ret = ice_vsi_init(vsi);
3085 if (ret < 0)
3086 goto err_vsi;
3087
3088
3089 switch (vsi->type) {
3090 case ICE_VSI_PF:
3091 ret = ice_vsi_alloc_q_vectors(vsi);
3092 if (ret)
3093 goto err_rings;
3094
3095 ret = ice_vsi_setup_vector_base(vsi);
3096 if (ret)
3097 goto err_vectors;
3098
3099 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
3100 if (ret)
3101 goto err_vectors;
3102
3103 ret = ice_vsi_alloc_rings(vsi);
3104 if (ret)
3105 goto err_vectors;
3106
3107 ice_vsi_map_rings_to_vectors(vsi);
3108
3109
3110
3111
3112 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
3113 ice_vsi_cfg_rss_lut_key(vsi);
3114 break;
3115 case ICE_VSI_VF:
3116 ret = ice_vsi_alloc_q_vectors(vsi);
3117 if (ret)
3118 goto err_rings;
3119
3120 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
3121 if (ret)
3122 goto err_vectors;
3123
3124 ret = ice_vsi_alloc_rings(vsi);
3125 if (ret)
3126 goto err_vectors;
3127
3128 break;
3129 default:
3130 break;
3131 }
3132
3133
3134 for (i = 0; i < vsi->tc_cfg.numtc; i++)
3135 max_txqs[i] = vsi->alloc_txq;
3136
3137 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3138 max_txqs);
3139 if (status) {
3140 dev_err(&pf->pdev->dev,
3141 "VSI %d failed lan queue config, error %d\n",
3142 vsi->vsi_num, status);
3143 goto err_vectors;
3144 }
3145 return 0;
3146
3147 err_vectors:
3148 ice_vsi_free_q_vectors(vsi);
3149 err_rings:
3150 if (vsi->netdev) {
3151 vsi->current_netdev_flags = 0;
3152 unregister_netdev(vsi->netdev);
3153 free_netdev(vsi->netdev);
3154 vsi->netdev = NULL;
3155 }
3156 err_vsi:
3157 ice_vsi_clear(vsi);
3158 set_bit(__ICE_RESET_FAILED, pf->state);
3159 return ret;
3160 }
3161
3162
3163
3164
3165
3166 bool ice_is_reset_in_progress(unsigned long *state)
3167 {
3168 return test_bit(__ICE_RESET_OICR_RECV, state) ||
3169 test_bit(__ICE_PFR_REQ, state) ||
3170 test_bit(__ICE_CORER_REQ, state) ||
3171 test_bit(__ICE_GLOBR_REQ, state);
3172 }
3173
3174 #ifdef CONFIG_DCB
3175
3176
3177
3178
3179
3180 static void ice_vsi_update_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctx)
3181 {
3182 vsi->info.mapping_flags = ctx->info.mapping_flags;
3183 memcpy(&vsi->info.q_mapping, &ctx->info.q_mapping,
3184 sizeof(vsi->info.q_mapping));
3185 memcpy(&vsi->info.tc_mapping, ctx->info.tc_mapping,
3186 sizeof(vsi->info.tc_mapping));
3187 }
3188
3189
3190
3191
3192
3193
3194
3195
3196 int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc)
3197 {
3198 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
3199 struct ice_vsi_ctx *ctx;
3200 struct ice_pf *pf = vsi->back;
3201 enum ice_status status;
3202 int i, ret = 0;
3203 u8 num_tc = 0;
3204
3205 ice_for_each_traffic_class(i) {
3206
3207 if (ena_tc & BIT(i))
3208 num_tc++;
3209
3210 max_txqs[i] = vsi->alloc_txq;
3211 }
3212
3213 vsi->tc_cfg.ena_tc = ena_tc;
3214 vsi->tc_cfg.numtc = num_tc;
3215
3216 ctx = devm_kzalloc(&pf->pdev->dev, sizeof(*ctx), GFP_KERNEL);
3217 if (!ctx)
3218 return -ENOMEM;
3219
3220 ctx->vf_num = 0;
3221 ctx->info = vsi->info;
3222
3223 ice_vsi_setup_q_map(vsi, ctx);
3224
3225
3226 ctx->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
3227 status = ice_update_vsi(&pf->hw, vsi->idx, ctx, NULL);
3228 if (status) {
3229 dev_info(&pf->pdev->dev, "Failed VSI Update\n");
3230 ret = -EIO;
3231 goto out;
3232 }
3233
3234 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3235 max_txqs);
3236
3237 if (status) {
3238 dev_err(&pf->pdev->dev,
3239 "VSI %d failed TC config, error %d\n",
3240 vsi->vsi_num, status);
3241 ret = -EIO;
3242 goto out;
3243 }
3244 ice_vsi_update_q_map(vsi, ctx);
3245 vsi->info.valid_sections = 0;
3246
3247 ice_vsi_cfg_netdev_tc(vsi, ena_tc);
3248 out:
3249 devm_kfree(&pf->pdev->dev, ctx);
3250 return ret;
3251 }
3252 #endif
3253
3254
3255
3256
3257
3258 char *ice_nvm_version_str(struct ice_hw *hw)
3259 {
3260 u8 oem_ver, oem_patch, ver_hi, ver_lo;
3261 static char buf[ICE_NVM_VER_LEN];
3262 u16 oem_build;
3263
3264 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
3265 &ver_lo);
3266
3267 snprintf(buf, sizeof(buf), "%x.%02x 0x%x %d.%d.%d", ver_hi, ver_lo,
3268 hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
3269
3270 return buf;
3271 }
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281 enum ice_status
3282 ice_vsi_cfg_mac_fltr(struct ice_vsi *vsi, const u8 *macaddr, bool set)
3283 {
3284 LIST_HEAD(tmp_add_list);
3285 enum ice_status status;
3286
3287
3288 if (ice_add_mac_to_list(vsi, &tmp_add_list, macaddr)) {
3289 status = ICE_ERR_NO_MEMORY;
3290 goto cfg_mac_fltr_exit;
3291 }
3292
3293 if (set)
3294 status = ice_add_mac(&vsi->back->hw, &tmp_add_list);
3295 else
3296 status = ice_remove_mac(&vsi->back->hw, &tmp_add_list);
3297
3298 cfg_mac_fltr_exit:
3299 ice_free_fltr_list(&vsi->back->pdev->dev, &tmp_add_list);
3300 return status;
3301 }