drivers/net/ethernet/intel/ice/ice

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This source file includes following definitions.
ice_set_mac_type
ice_dev_onetime_setup
ice_clear_pf_cfg
ice_aq_manage_mac_read
ice_aq_get_phy_caps
ice_get_media_type
ice_aq_get_link_info
ice_init_flex_flags
ice_init_flex_flds
ice_init_fltr_mgmt_struct
ice_cleanup_fltr_mgmt_struct
ice_get_fw_log_cfg
ice_cfg_fw_log
ice_output_fw_log
ice_get_itr_intrl_gran
ice_get_nvm_version
ice_init_hw
ice_deinit_hw
ice_check_reset
ice_pf_reset
ice_reset
ice_copy_rxq_ctx_to_hw
ice_write_rxq_ctx
ice_debug_cq
ice_aq_send_cmd
ice_aq_get_fw_ver
ice_aq_send_driver_ver
ice_aq_q_shutdown
ice_aq_req_res
ice_aq_release_res
ice_acquire_res
ice_release_res
ice_get_num_per_func
ice_parse_caps
ice_aq_discover_caps
ice_discover_caps
ice_set_safe_mode_caps
ice_get_caps
ice_aq_manage_mac_write
ice_aq_clear_pxe_mode
ice_clear_pxe_mode
ice_get_link_speed_based_on_phy_type
ice_update_phy_type
ice_aq_set_phy_cfg
ice_update_link_info
ice_set_fc
ice_copy_phy_caps_to_cfg
ice_cfg_phy_fec
ice_get_link_status
ice_aq_set_link_restart_an
ice_aq_set_event_mask
ice_aq_set_mac_loopback
ice_aq_set_port_id_led
__ice_aq_get_set_rss_lut
ice_aq_get_rss_lut
ice_aq_set_rss_lut
__ice_aq_get_set_rss_key
ice_aq_get_rss_key
ice_aq_set_rss_key
ice_aq_add_lan_txq
ice_aq_dis_lan_txq
ice_write_byte
ice_write_word
ice_write_dword
ice_write_qword
ice_set_ctx
ice_get_lan_q_ctx
ice_ena_vsi_txq
ice_dis_vsi_txq
ice_cfg_vsi_qs
ice_cfg_vsi_lan
ice_replay_pre_init
ice_replay_vsi
ice_replay_post
ice_stat_update40
ice_stat_update32
ice_sched_query_elem
   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Intel Corporation. */
   3 
   4 #include "ice_common.h"
   5 #include "ice_sched.h"
   6 #include "ice_adminq_cmd.h"
   7 
   8 #define ICE_PF_RESET_WAIT_COUNT 200
   9 
  10 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
  11         wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
  12              ((ICE_RX_OPC_MDID << \
  13                GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
  14               GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
  15              (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
  16               GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
  17 
  18 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
  19         wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
  20              (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
  21               GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
  22              (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
  23               GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
  24              (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
  25               GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
  26              (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
  27               GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
  28 
  29 /**
  30  * ice_set_mac_type - Sets MAC type
  31  * @hw: pointer to the HW structure
  32  *
  33  * This function sets the MAC type of the adapter based on the
  34  * vendor ID and device ID stored in the HW structure.
  35  */
  36 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
  37 {
  38         if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
  39                 return ICE_ERR_DEVICE_NOT_SUPPORTED;
  40 
  41         hw->mac_type = ICE_MAC_GENERIC;
  42         return 0;
  43 }
  44 
  45 /**
  46  * ice_dev_onetime_setup - Temporary HW/FW workarounds
  47  * @hw: pointer to the HW structure
  48  *
  49  * This function provides temporary workarounds for certain issues
  50  * that are expected to be fixed in the HW/FW.
  51  */
  52 void ice_dev_onetime_setup(struct ice_hw *hw)
  53 {
  54 #define MBX_PF_VT_PFALLOC       0x00231E80
  55         /* set VFs per PF */
  56         wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF));
  57 }
  58 
  59 /**
  60  * ice_clear_pf_cfg - Clear PF configuration
  61  * @hw: pointer to the hardware structure
  62  *
  63  * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
  64  * configuration, flow director filters, etc.).
  65  */
  66 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
  67 {
  68         struct ice_aq_desc desc;
  69 
  70         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
  71 
  72         return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
  73 }
  74 
  75 /**
  76  * ice_aq_manage_mac_read - manage MAC address read command
  77  * @hw: pointer to the HW struct
  78  * @buf: a virtual buffer to hold the manage MAC read response
  79  * @buf_size: Size of the virtual buffer
  80  * @cd: pointer to command details structure or NULL
  81  *
  82  * This function is used to return per PF station MAC address (0x0107).
  83  * NOTE: Upon successful completion of this command, MAC address information
  84  * is returned in user specified buffer. Please interpret user specified
  85  * buffer as "manage_mac_read" response.
  86  * Response such as various MAC addresses are stored in HW struct (port.mac)
  87  * ice_aq_discover_caps is expected to be called before this function is called.
  88  */
  89 static enum ice_status
  90 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
  91                        struct ice_sq_cd *cd)
  92 {
  93         struct ice_aqc_manage_mac_read_resp *resp;
  94         struct ice_aqc_manage_mac_read *cmd;
  95         struct ice_aq_desc desc;
  96         enum ice_status status;
  97         u16 flags;
  98         u8 i;
  99 
 100         cmd = &desc.params.mac_read;
 101 
 102         if (buf_size < sizeof(*resp))
 103                 return ICE_ERR_BUF_TOO_SHORT;
 104 
 105         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
 106 
 107         status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
 108         if (status)
 109                 return status;
 110 
 111         resp = (struct ice_aqc_manage_mac_read_resp *)buf;
 112         flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
 113 
 114         if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
 115                 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
 116                 return ICE_ERR_CFG;
 117         }
 118 
 119         /* A single port can report up to two (LAN and WoL) addresses */
 120         for (i = 0; i < cmd->num_addr; i++)
 121                 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
 122                         ether_addr_copy(hw->port_info->mac.lan_addr,
 123                                         resp[i].mac_addr);
 124                         ether_addr_copy(hw->port_info->mac.perm_addr,
 125                                         resp[i].mac_addr);
 126                         break;
 127                 }
 128 
 129         return 0;
 130 }
 131 
 132 /**
 133  * ice_aq_get_phy_caps - returns PHY capabilities
 134  * @pi: port information structure
 135  * @qual_mods: report qualified modules
 136  * @report_mode: report mode capabilities
 137  * @pcaps: structure for PHY capabilities to be filled
 138  * @cd: pointer to command details structure or NULL
 139  *
 140  * Returns the various PHY capabilities supported on the Port (0x0600)
 141  */
 142 enum ice_status
 143 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
 144                     struct ice_aqc_get_phy_caps_data *pcaps,
 145                     struct ice_sq_cd *cd)
 146 {
 147         struct ice_aqc_get_phy_caps *cmd;
 148         u16 pcaps_size = sizeof(*pcaps);
 149         struct ice_aq_desc desc;
 150         enum ice_status status;
 151 
 152         cmd = &desc.params.get_phy;
 153 
 154         if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
 155                 return ICE_ERR_PARAM;
 156 
 157         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
 158 
 159         if (qual_mods)
 160                 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
 161 
 162         cmd->param0 |= cpu_to_le16(report_mode);
 163         status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
 164 
 165         if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
 166                 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
 167                 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
 168         }
 169 
 170         return status;
 171 }
 172 
 173 /**
 174  * ice_get_media_type - Gets media type
 175  * @pi: port information structure
 176  */
 177 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
 178 {
 179         struct ice_link_status *hw_link_info;
 180 
 181         if (!pi)
 182                 return ICE_MEDIA_UNKNOWN;
 183 
 184         hw_link_info = &pi->phy.link_info;
 185         if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
 186                 /* If more than one media type is selected, report unknown */
 187                 return ICE_MEDIA_UNKNOWN;
 188 
 189         if (hw_link_info->phy_type_low) {
 190                 switch (hw_link_info->phy_type_low) {
 191                 case ICE_PHY_TYPE_LOW_1000BASE_SX:
 192                 case ICE_PHY_TYPE_LOW_1000BASE_LX:
 193                 case ICE_PHY_TYPE_LOW_10GBASE_SR:
 194                 case ICE_PHY_TYPE_LOW_10GBASE_LR:
 195                 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
 196                 case ICE_PHY_TYPE_LOW_25GBASE_SR:
 197                 case ICE_PHY_TYPE_LOW_25GBASE_LR:
 198                 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
 199                 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
 200                 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
 201                 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
 202                 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
 203                 case ICE_PHY_TYPE_LOW_50GBASE_SR:
 204                 case ICE_PHY_TYPE_LOW_50GBASE_FR:
 205                 case ICE_PHY_TYPE_LOW_50GBASE_LR:
 206                 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
 207                 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
 208                 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
 209                 case ICE_PHY_TYPE_LOW_100GBASE_DR:
 210                         return ICE_MEDIA_FIBER;
 211                 case ICE_PHY_TYPE_LOW_100BASE_TX:
 212                 case ICE_PHY_TYPE_LOW_1000BASE_T:
 213                 case ICE_PHY_TYPE_LOW_2500BASE_T:
 214                 case ICE_PHY_TYPE_LOW_5GBASE_T:
 215                 case ICE_PHY_TYPE_LOW_10GBASE_T:
 216                 case ICE_PHY_TYPE_LOW_25GBASE_T:
 217                         return ICE_MEDIA_BASET;
 218                 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
 219                 case ICE_PHY_TYPE_LOW_25GBASE_CR:
 220                 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
 221                 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
 222                 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
 223                 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
 224                 case ICE_PHY_TYPE_LOW_50GBASE_CP:
 225                 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
 226                 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
 227                 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
 228                         return ICE_MEDIA_DA;
 229                 case ICE_PHY_TYPE_LOW_1000BASE_KX:
 230                 case ICE_PHY_TYPE_LOW_2500BASE_KX:
 231                 case ICE_PHY_TYPE_LOW_2500BASE_X:
 232                 case ICE_PHY_TYPE_LOW_5GBASE_KR:
 233                 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
 234                 case ICE_PHY_TYPE_LOW_25GBASE_KR:
 235                 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
 236                 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
 237                 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
 238                 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
 239                 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
 240                 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
 241                 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
 242                         return ICE_MEDIA_BACKPLANE;
 243                 }
 244         } else {
 245                 switch (hw_link_info->phy_type_high) {
 246                 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
 247                         return ICE_MEDIA_BACKPLANE;
 248                 }
 249         }
 250         return ICE_MEDIA_UNKNOWN;
 251 }
 252 
 253 /**
 254  * ice_aq_get_link_info
 255  * @pi: port information structure
 256  * @ena_lse: enable/disable LinkStatusEvent reporting
 257  * @link: pointer to link status structure - optional
 258  * @cd: pointer to command details structure or NULL
 259  *
 260  * Get Link Status (0x607). Returns the link status of the adapter.
 261  */
 262 enum ice_status
 263 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
 264                      struct ice_link_status *link, struct ice_sq_cd *cd)
 265 {
 266         struct ice_aqc_get_link_status_data link_data = { 0 };
 267         struct ice_aqc_get_link_status *resp;
 268         struct ice_link_status *li_old, *li;
 269         enum ice_media_type *hw_media_type;
 270         struct ice_fc_info *hw_fc_info;
 271         bool tx_pause, rx_pause;
 272         struct ice_aq_desc desc;
 273         enum ice_status status;
 274         struct ice_hw *hw;
 275         u16 cmd_flags;
 276 
 277         if (!pi)
 278                 return ICE_ERR_PARAM;
 279         hw = pi->hw;
 280         li_old = &pi->phy.link_info_old;
 281         hw_media_type = &pi->phy.media_type;
 282         li = &pi->phy.link_info;
 283         hw_fc_info = &pi->fc;
 284 
 285         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
 286         cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
 287         resp = &desc.params.get_link_status;
 288         resp->cmd_flags = cpu_to_le16(cmd_flags);
 289         resp->lport_num = pi->lport;
 290 
 291         status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
 292 
 293         if (status)
 294                 return status;
 295 
 296         /* save off old link status information */
 297         *li_old = *li;
 298 
 299         /* update current link status information */
 300         li->link_speed = le16_to_cpu(link_data.link_speed);
 301         li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
 302         li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
 303         *hw_media_type = ice_get_media_type(pi);
 304         li->link_info = link_data.link_info;
 305         li->an_info = link_data.an_info;
 306         li->ext_info = link_data.ext_info;
 307         li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
 308         li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
 309         li->topo_media_conflict = link_data.topo_media_conflict;
 310         li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
 311                                       ICE_AQ_CFG_PACING_TYPE_M);
 312 
 313         /* update fc info */
 314         tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
 315         rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
 316         if (tx_pause && rx_pause)
 317                 hw_fc_info->current_mode = ICE_FC_FULL;
 318         else if (tx_pause)
 319                 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
 320         else if (rx_pause)
 321                 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
 322         else
 323                 hw_fc_info->current_mode = ICE_FC_NONE;
 324 
 325         li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
 326 
 327         ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
 328         ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
 329                   (unsigned long long)li->phy_type_low);
 330         ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
 331                   (unsigned long long)li->phy_type_high);
 332         ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
 333         ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
 334         ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
 335         ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
 336         ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
 337         ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
 338         ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
 339 
 340         /* save link status information */
 341         if (link)
 342                 *link = *li;
 343 
 344         /* flag cleared so calling functions don't call AQ again */
 345         pi->phy.get_link_info = false;
 346 
 347         return 0;
 348 }
 349 
 350 /**
 351  * ice_init_flex_flags
 352  * @hw: pointer to the hardware structure
 353  * @prof_id: Rx Descriptor Builder profile ID
 354  *
 355  * Function to initialize Rx flex flags
 356  */
 357 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
 358 {
 359         u8 idx = 0;
 360 
 361         /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
 362          * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
 363          * flexiflags1[3:0] - Not used for flag programming
 364          * flexiflags2[7:0] - Tunnel and VLAN types
 365          * 2 invalid fields in last index
 366          */
 367         switch (prof_id) {
 368         /* Rx flex flags are currently programmed for the NIC profiles only.
 369          * Different flag bit programming configurations can be added per
 370          * profile as needed.
 371          */
 372         case ICE_RXDID_FLEX_NIC:
 373         case ICE_RXDID_FLEX_NIC_2:
 374                 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
 375                                    ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
 376                                    ICE_FLG_FIN, idx++);
 377                 /* flex flag 1 is not used for flexi-flag programming, skipping
 378                  * these four FLG64 bits.
 379                  */
 380                 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
 381                                    ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
 382                 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
 383                                    ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
 384                                    ICE_FLG_EVLAN_x9100, idx++);
 385                 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
 386                                    ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
 387                                    ICE_FLG_TNL0, idx++);
 388                 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
 389                                    ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
 390                 break;
 391 
 392         default:
 393                 ice_debug(hw, ICE_DBG_INIT,
 394                           "Flag programming for profile ID %d not supported\n",
 395                           prof_id);
 396         }
 397 }
 398 
 399 /**
 400  * ice_init_flex_flds
 401  * @hw: pointer to the hardware structure
 402  * @prof_id: Rx Descriptor Builder profile ID
 403  *
 404  * Function to initialize flex descriptors
 405  */
 406 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
 407 {
 408         enum ice_flex_rx_mdid mdid;
 409 
 410         switch (prof_id) {
 411         case ICE_RXDID_FLEX_NIC:
 412         case ICE_RXDID_FLEX_NIC_2:
 413                 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);
 414                 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);
 415                 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);
 416 
 417                 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
 418                         ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;
 419 
 420                 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
 421 
 422                 ice_init_flex_flags(hw, prof_id);
 423                 break;
 424 
 425         default:
 426                 ice_debug(hw, ICE_DBG_INIT,
 427                           "Field init for profile ID %d not supported\n",
 428                           prof_id);
 429         }
 430 }
 431 
 432 /**
 433  * ice_init_fltr_mgmt_struct - initializes filter management list and locks
 434  * @hw: pointer to the HW struct
 435  */
 436 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
 437 {
 438         struct ice_switch_info *sw;
 439 
 440         hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
 441                                        sizeof(*hw->switch_info), GFP_KERNEL);
 442         sw = hw->switch_info;
 443 
 444         if (!sw)
 445                 return ICE_ERR_NO_MEMORY;
 446 
 447         INIT_LIST_HEAD(&sw->vsi_list_map_head);
 448 
 449         return ice_init_def_sw_recp(hw);
 450 }
 451 
 452 /**
 453  * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
 454  * @hw: pointer to the HW struct
 455  */
 456 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
 457 {
 458         struct ice_switch_info *sw = hw->switch_info;
 459         struct ice_vsi_list_map_info *v_pos_map;
 460         struct ice_vsi_list_map_info *v_tmp_map;
 461         struct ice_sw_recipe *recps;
 462         u8 i;
 463 
 464         list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
 465                                  list_entry) {
 466                 list_del(&v_pos_map->list_entry);
 467                 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
 468         }
 469         recps = hw->switch_info->recp_list;
 470         for (i = 0; i < ICE_SW_LKUP_LAST; i++) {
 471                 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
 472 
 473                 recps[i].root_rid = i;
 474                 mutex_destroy(&recps[i].filt_rule_lock);
 475                 list_for_each_entry_safe(lst_itr, tmp_entry,
 476                                          &recps[i].filt_rules, list_entry) {
 477                         list_del(&lst_itr->list_entry);
 478                         devm_kfree(ice_hw_to_dev(hw), lst_itr);
 479                 }
 480         }
 481         ice_rm_all_sw_replay_rule_info(hw);
 482         devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
 483         devm_kfree(ice_hw_to_dev(hw), sw);
 484 }
 485 
 486 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
 487         (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
 488 #define ICE_FW_LOG_DESC_SIZE_MAX        \
 489         ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
 490 
 491 /**
 492  * ice_get_fw_log_cfg - get FW logging configuration
 493  * @hw: pointer to the HW struct
 494  */
 495 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
 496 {
 497         struct ice_aqc_fw_logging_data *config;
 498         struct ice_aq_desc desc;
 499         enum ice_status status;
 500         u16 size;
 501 
 502         size = ICE_FW_LOG_DESC_SIZE_MAX;
 503         config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL);
 504         if (!config)
 505                 return ICE_ERR_NO_MEMORY;
 506 
 507         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
 508 
 509         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF);
 510         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
 511 
 512         status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
 513         if (!status) {
 514                 u16 i;
 515 
 516                 /* Save FW logging information into the HW structure */
 517                 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
 518                         u16 v, m, flgs;
 519 
 520                         v = le16_to_cpu(config->entry[i]);
 521                         m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
 522                         flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
 523 
 524                         if (m < ICE_AQC_FW_LOG_ID_MAX)
 525                                 hw->fw_log.evnts[m].cur = flgs;
 526                 }
 527         }
 528 
 529         devm_kfree(ice_hw_to_dev(hw), config);
 530 
 531         return status;
 532 }
 533 
 534 /**
 535  * ice_cfg_fw_log - configure FW logging
 536  * @hw: pointer to the HW struct
 537  * @enable: enable certain FW logging events if true, disable all if false
 538  *
 539  * This function enables/disables the FW logging via Rx CQ events and a UART
 540  * port based on predetermined configurations. FW logging via the Rx CQ can be
 541  * enabled/disabled for individual PF's. However, FW logging via the UART can
 542  * only be enabled/disabled for all PFs on the same device.
 543  *
 544  * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
 545  * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
 546  * before initializing the device.
 547  *
 548  * When re/configuring FW logging, callers need to update the "cfg" elements of
 549  * the hw->fw_log.evnts array with the desired logging event configurations for
 550  * modules of interest. When disabling FW logging completely, the callers can
 551  * just pass false in the "enable" parameter. On completion, the function will
 552  * update the "cur" element of the hw->fw_log.evnts array with the resulting
 553  * logging event configurations of the modules that are being re/configured. FW
 554  * logging modules that are not part of a reconfiguration operation retain their
 555  * previous states.
 556  *
 557  * Before resetting the device, it is recommended that the driver disables FW
 558  * logging before shutting down the control queue. When disabling FW logging
 559  * ("enable" = false), the latest configurations of FW logging events stored in
 560  * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
 561  * a device reset.
 562  *
 563  * When enabling FW logging to emit log messages via the Rx CQ during the
 564  * device's initialization phase, a mechanism alternative to interrupt handlers
 565  * needs to be used to extract FW log messages from the Rx CQ periodically and
 566  * to prevent the Rx CQ from being full and stalling other types of control
 567  * messages from FW to SW. Interrupts are typically disabled during the device's
 568  * initialization phase.
 569  */
 570 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
 571 {
 572         struct ice_aqc_fw_logging_data *data = NULL;
 573         struct ice_aqc_fw_logging *cmd;
 574         enum ice_status status = 0;
 575         u16 i, chgs = 0, len = 0;
 576         struct ice_aq_desc desc;
 577         u8 actv_evnts = 0;
 578         void *buf = NULL;
 579 
 580         if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
 581                 return 0;
 582 
 583         /* Disable FW logging only when the control queue is still responsive */
 584         if (!enable &&
 585             (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
 586                 return 0;
 587 
 588         /* Get current FW log settings */
 589         status = ice_get_fw_log_cfg(hw);
 590         if (status)
 591                 return status;
 592 
 593         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
 594         cmd = &desc.params.fw_logging;
 595 
 596         /* Indicate which controls are valid */
 597         if (hw->fw_log.cq_en)
 598                 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
 599 
 600         if (hw->fw_log.uart_en)
 601                 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
 602 
 603         if (enable) {
 604                 /* Fill in an array of entries with FW logging modules and
 605                  * logging events being reconfigured.
 606                  */
 607                 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
 608                         u16 val;
 609 
 610                         /* Keep track of enabled event types */
 611                         actv_evnts |= hw->fw_log.evnts[i].cfg;
 612 
 613                         if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
 614                                 continue;
 615 
 616                         if (!data) {
 617                                 data = devm_kzalloc(ice_hw_to_dev(hw),
 618                                                     ICE_FW_LOG_DESC_SIZE_MAX,
 619                                                     GFP_KERNEL);
 620                                 if (!data)
 621                                         return ICE_ERR_NO_MEMORY;
 622                         }
 623 
 624                         val = i << ICE_AQC_FW_LOG_ID_S;
 625                         val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
 626                         data->entry[chgs++] = cpu_to_le16(val);
 627                 }
 628 
 629                 /* Only enable FW logging if at least one module is specified.
 630                  * If FW logging is currently enabled but all modules are not
 631                  * enabled to emit log messages, disable FW logging altogether.
 632                  */
 633                 if (actv_evnts) {
 634                         /* Leave if there is effectively no change */
 635                         if (!chgs)
 636                                 goto out;
 637 
 638                         if (hw->fw_log.cq_en)
 639                                 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
 640 
 641                         if (hw->fw_log.uart_en)
 642                                 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
 643 
 644                         buf = data;
 645                         len = ICE_FW_LOG_DESC_SIZE(chgs);
 646                         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
 647                 }
 648         }
 649 
 650         status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
 651         if (!status) {
 652                 /* Update the current configuration to reflect events enabled.
 653                  * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
 654                  * logging mode is enabled for the device. They do not reflect
 655                  * actual modules being enabled to emit log messages. So, their
 656                  * values remain unchanged even when all modules are disabled.
 657                  */
 658                 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
 659 
 660                 hw->fw_log.actv_evnts = actv_evnts;
 661                 for (i = 0; i < cnt; i++) {
 662                         u16 v, m;
 663 
 664                         if (!enable) {
 665                                 /* When disabling all FW logging events as part
 666                                  * of device's de-initialization, the original
 667                                  * configurations are retained, and can be used
 668                                  * to reconfigure FW logging later if the device
 669                                  * is re-initialized.
 670                                  */
 671                                 hw->fw_log.evnts[i].cur = 0;
 672                                 continue;
 673                         }
 674 
 675                         v = le16_to_cpu(data->entry[i]);
 676                         m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
 677                         hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
 678                 }
 679         }
 680 
 681 out:
 682         if (data)
 683                 devm_kfree(ice_hw_to_dev(hw), data);
 684 
 685         return status;
 686 }
 687 
 688 /**
 689  * ice_output_fw_log
 690  * @hw: pointer to the HW struct
 691  * @desc: pointer to the AQ message descriptor
 692  * @buf: pointer to the buffer accompanying the AQ message
 693  *
 694  * Formats a FW Log message and outputs it via the standard driver logs.
 695  */
 696 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
 697 {
 698         ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
 699         ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
 700                         le16_to_cpu(desc->datalen));
 701         ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
 702 }
 703 
 704 /**
 705  * ice_get_itr_intrl_gran - determine int/intrl granularity
 706  * @hw: pointer to the HW struct
 707  *
 708  * Determines the ITR/intrl granularities based on the maximum aggregate
 709  * bandwidth according to the device's configuration during power-on.
 710  */
 711 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
 712 {
 713         u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
 714                          GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
 715                         GL_PWR_MODE_CTL_CAR_MAX_BW_S;
 716 
 717         switch (max_agg_bw) {
 718         case ICE_MAX_AGG_BW_200G:
 719         case ICE_MAX_AGG_BW_100G:
 720         case ICE_MAX_AGG_BW_50G:
 721                 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
 722                 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
 723                 break;
 724         case ICE_MAX_AGG_BW_25G:
 725                 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
 726                 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
 727                 break;
 728         }
 729 }
 730 
 731 /**
 732  * ice_get_nvm_version - get cached NVM version data
 733  * @hw: pointer to the hardware structure
 734  * @oem_ver: 8 bit NVM version
 735  * @oem_build: 16 bit NVM build number
 736  * @oem_patch: 8 NVM patch number
 737  * @ver_hi: high 16 bits of the NVM version
 738  * @ver_lo: low 16 bits of the NVM version
 739  */
 740 void
 741 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
 742                     u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
 743 {
 744         struct ice_nvm_info *nvm = &hw->nvm;
 745 
 746         *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
 747         *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
 748         *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
 749                            ICE_OEM_VER_BUILD_SHIFT);
 750         *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
 751         *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
 752 }
 753 
 754 /**
 755  * ice_init_hw - main hardware initialization routine
 756  * @hw: pointer to the hardware structure
 757  */
 758 enum ice_status ice_init_hw(struct ice_hw *hw)
 759 {
 760         struct ice_aqc_get_phy_caps_data *pcaps;
 761         enum ice_status status;
 762         u16 mac_buf_len;
 763         void *mac_buf;
 764 
 765         /* Set MAC type based on DeviceID */
 766         status = ice_set_mac_type(hw);
 767         if (status)
 768                 return status;
 769 
 770         hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
 771                          PF_FUNC_RID_FUNC_NUM_M) >>
 772                 PF_FUNC_RID_FUNC_NUM_S;
 773 
 774         status = ice_reset(hw, ICE_RESET_PFR);
 775         if (status)
 776                 return status;
 777 
 778         ice_get_itr_intrl_gran(hw);
 779 
 780         status = ice_create_all_ctrlq(hw);
 781         if (status)
 782                 goto err_unroll_cqinit;
 783 
 784         /* Enable FW logging. Not fatal if this fails. */
 785         status = ice_cfg_fw_log(hw, true);
 786         if (status)
 787                 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
 788 
 789         status = ice_clear_pf_cfg(hw);
 790         if (status)
 791                 goto err_unroll_cqinit;
 792 
 793         ice_clear_pxe_mode(hw);
 794 
 795         status = ice_init_nvm(hw);
 796         if (status)
 797                 goto err_unroll_cqinit;
 798 
 799         status = ice_get_caps(hw);
 800         if (status)
 801                 goto err_unroll_cqinit;
 802 
 803         hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
 804                                      sizeof(*hw->port_info), GFP_KERNEL);
 805         if (!hw->port_info) {
 806                 status = ICE_ERR_NO_MEMORY;
 807                 goto err_unroll_cqinit;
 808         }
 809 
 810         /* set the back pointer to HW */
 811         hw->port_info->hw = hw;
 812 
 813         /* Initialize port_info struct with switch configuration data */
 814         status = ice_get_initial_sw_cfg(hw);
 815         if (status)
 816                 goto err_unroll_alloc;
 817 
 818         hw->evb_veb = true;
 819 
 820         /* Query the allocated resources for Tx scheduler */
 821         status = ice_sched_query_res_alloc(hw);
 822         if (status) {
 823                 ice_debug(hw, ICE_DBG_SCHED,
 824                           "Failed to get scheduler allocated resources\n");
 825                 goto err_unroll_alloc;
 826         }
 827 
 828         /* Initialize port_info struct with scheduler data */
 829         status = ice_sched_init_port(hw->port_info);
 830         if (status)
 831                 goto err_unroll_sched;
 832 
 833         pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
 834         if (!pcaps) {
 835                 status = ICE_ERR_NO_MEMORY;
 836                 goto err_unroll_sched;
 837         }
 838 
 839         /* Initialize port_info struct with PHY capabilities */
 840         status = ice_aq_get_phy_caps(hw->port_info, false,
 841                                      ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
 842         devm_kfree(ice_hw_to_dev(hw), pcaps);
 843         if (status)
 844                 goto err_unroll_sched;
 845 
 846         /* Initialize port_info struct with link information */
 847         status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
 848         if (status)
 849                 goto err_unroll_sched;
 850 
 851         /* need a valid SW entry point to build a Tx tree */
 852         if (!hw->sw_entry_point_layer) {
 853                 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
 854                 status = ICE_ERR_CFG;
 855                 goto err_unroll_sched;
 856         }
 857         INIT_LIST_HEAD(&hw->agg_list);
 858 
 859         status = ice_init_fltr_mgmt_struct(hw);
 860         if (status)
 861                 goto err_unroll_sched;
 862 
 863         ice_dev_onetime_setup(hw);
 864 
 865         /* Get MAC information */
 866         /* A single port can report up to two (LAN and WoL) addresses */
 867         mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
 868                                sizeof(struct ice_aqc_manage_mac_read_resp),
 869                                GFP_KERNEL);
 870         mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
 871 
 872         if (!mac_buf) {
 873                 status = ICE_ERR_NO_MEMORY;
 874                 goto err_unroll_fltr_mgmt_struct;
 875         }
 876 
 877         status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
 878         devm_kfree(ice_hw_to_dev(hw), mac_buf);
 879 
 880         if (status)
 881                 goto err_unroll_fltr_mgmt_struct;
 882 
 883         ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
 884         ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
 885         status = ice_init_hw_tbls(hw);
 886         if (status)
 887                 goto err_unroll_fltr_mgmt_struct;
 888         return 0;
 889 
 890 err_unroll_fltr_mgmt_struct:
 891         ice_cleanup_fltr_mgmt_struct(hw);
 892 err_unroll_sched:
 893         ice_sched_cleanup_all(hw);
 894 err_unroll_alloc:
 895         devm_kfree(ice_hw_to_dev(hw), hw->port_info);
 896 err_unroll_cqinit:
 897         ice_destroy_all_ctrlq(hw);
 898         return status;
 899 }
 900 
 901 /**
 902  * ice_deinit_hw - unroll initialization operations done by ice_init_hw
 903  * @hw: pointer to the hardware structure
 904  *
 905  * This should be called only during nominal operation, not as a result of
 906  * ice_init_hw() failing since ice_init_hw() will take care of unrolling
 907  * applicable initializations if it fails for any reason.
 908  */
 909 void ice_deinit_hw(struct ice_hw *hw)
 910 {
 911         ice_cleanup_fltr_mgmt_struct(hw);
 912 
 913         ice_sched_cleanup_all(hw);
 914         ice_sched_clear_agg(hw);
 915         ice_free_seg(hw);
 916         ice_free_hw_tbls(hw);
 917 
 918         if (hw->port_info) {
 919                 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
 920                 hw->port_info = NULL;
 921         }
 922 
 923         /* Attempt to disable FW logging before shutting down control queues */
 924         ice_cfg_fw_log(hw, false);
 925         ice_destroy_all_ctrlq(hw);
 926 
 927         /* Clear VSI contexts if not already cleared */
 928         ice_clear_all_vsi_ctx(hw);
 929 }
 930 
 931 /**
 932  * ice_check_reset - Check to see if a global reset is complete
 933  * @hw: pointer to the hardware structure
 934  */
 935 enum ice_status ice_check_reset(struct ice_hw *hw)
 936 {
 937         u32 cnt, reg = 0, grst_delay, uld_mask;
 938 
 939         /* Poll for Device Active state in case a recent CORER, GLOBR,
 940          * or EMPR has occurred. The grst delay value is in 100ms units.
 941          * Add 1sec for outstanding AQ commands that can take a long time.
 942          */
 943         grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
 944                       GLGEN_RSTCTL_GRSTDEL_S) + 10;
 945 
 946         for (cnt = 0; cnt < grst_delay; cnt++) {
 947                 mdelay(100);
 948                 reg = rd32(hw, GLGEN_RSTAT);
 949                 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
 950                         break;
 951         }
 952 
 953         if (cnt == grst_delay) {
 954                 ice_debug(hw, ICE_DBG_INIT,
 955                           "Global reset polling failed to complete.\n");
 956                 return ICE_ERR_RESET_FAILED;
 957         }
 958 
 959 #define ICE_RESET_DONE_MASK     (GLNVM_ULD_PCIER_DONE_M |\
 960                                  GLNVM_ULD_PCIER_DONE_1_M |\
 961                                  GLNVM_ULD_CORER_DONE_M |\
 962                                  GLNVM_ULD_GLOBR_DONE_M |\
 963                                  GLNVM_ULD_POR_DONE_M |\
 964                                  GLNVM_ULD_POR_DONE_1_M |\
 965                                  GLNVM_ULD_PCIER_DONE_2_M)
 966 
 967         uld_mask = ICE_RESET_DONE_MASK;
 968 
 969         /* Device is Active; check Global Reset processes are done */
 970         for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
 971                 reg = rd32(hw, GLNVM_ULD) & uld_mask;
 972                 if (reg == uld_mask) {
 973                         ice_debug(hw, ICE_DBG_INIT,
 974                                   "Global reset processes done. %d\n", cnt);
 975                         break;
 976                 }
 977                 mdelay(10);
 978         }
 979 
 980         if (cnt == ICE_PF_RESET_WAIT_COUNT) {
 981                 ice_debug(hw, ICE_DBG_INIT,
 982                           "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
 983                           reg);
 984                 return ICE_ERR_RESET_FAILED;
 985         }
 986 
 987         return 0;
 988 }
 989 
 990 /**
 991  * ice_pf_reset - Reset the PF
 992  * @hw: pointer to the hardware structure
 993  *
 994  * If a global reset has been triggered, this function checks
 995  * for its completion and then issues the PF reset
 996  */
 997 static enum ice_status ice_pf_reset(struct ice_hw *hw)
 998 {
 999         u32 cnt, reg;
1000 
1001         /* If at function entry a global reset was already in progress, i.e.
1002          * state is not 'device active' or any of the reset done bits are not
1003          * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1004          * global reset is done.
1005          */
1006         if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1007             (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1008                 /* poll on global reset currently in progress until done */
1009                 if (ice_check_reset(hw))
1010                         return ICE_ERR_RESET_FAILED;
1011 
1012                 return 0;
1013         }
1014 
1015         /* Reset the PF */
1016         reg = rd32(hw, PFGEN_CTRL);
1017 
1018         wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1019 
1020         for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1021                 reg = rd32(hw, PFGEN_CTRL);
1022                 if (!(reg & PFGEN_CTRL_PFSWR_M))
1023                         break;
1024 
1025                 mdelay(1);
1026         }
1027 
1028         if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1029                 ice_debug(hw, ICE_DBG_INIT,
1030                           "PF reset polling failed to complete.\n");
1031                 return ICE_ERR_RESET_FAILED;
1032         }
1033 
1034         return 0;
1035 }
1036 
1037 /**
1038  * ice_reset - Perform different types of reset
1039  * @hw: pointer to the hardware structure
1040  * @req: reset request
1041  *
1042  * This function triggers a reset as specified by the req parameter.
1043  *
1044  * Note:
1045  * If anything other than a PF reset is triggered, PXE mode is restored.
1046  * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1047  * interface has been restored in the rebuild flow.
1048  */
1049 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1050 {
1051         u32 val = 0;
1052 
1053         switch (req) {
1054         case ICE_RESET_PFR:
1055                 return ice_pf_reset(hw);
1056         case ICE_RESET_CORER:
1057                 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1058                 val = GLGEN_RTRIG_CORER_M;
1059                 break;
1060         case ICE_RESET_GLOBR:
1061                 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1062                 val = GLGEN_RTRIG_GLOBR_M;
1063                 break;
1064         default:
1065                 return ICE_ERR_PARAM;
1066         }
1067 
1068         val |= rd32(hw, GLGEN_RTRIG);
1069         wr32(hw, GLGEN_RTRIG, val);
1070         ice_flush(hw);
1071 
1072         /* wait for the FW to be ready */
1073         return ice_check_reset(hw);
1074 }
1075 
1076 /**
1077  * ice_copy_rxq_ctx_to_hw
1078  * @hw: pointer to the hardware structure
1079  * @ice_rxq_ctx: pointer to the rxq context
1080  * @rxq_index: the index of the Rx queue
1081  *
1082  * Copies rxq context from dense structure to HW register space
1083  */
1084 static enum ice_status
1085 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1086 {
1087         u8 i;
1088 
1089         if (!ice_rxq_ctx)
1090                 return ICE_ERR_BAD_PTR;
1091 
1092         if (rxq_index > QRX_CTRL_MAX_INDEX)
1093                 return ICE_ERR_PARAM;
1094 
1095         /* Copy each dword separately to HW */
1096         for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1097                 wr32(hw, QRX_CONTEXT(i, rxq_index),
1098                      *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1099 
1100                 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1101                           *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1102         }
1103 
1104         return 0;
1105 }
1106 
1107 /* LAN Rx Queue Context */
1108 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1109         /* Field                Width   LSB */
1110         ICE_CTX_STORE(ice_rlan_ctx, head,               13,     0),
1111         ICE_CTX_STORE(ice_rlan_ctx, cpuid,              8,      13),
1112         ICE_CTX_STORE(ice_rlan_ctx, base,               57,     32),
1113         ICE_CTX_STORE(ice_rlan_ctx, qlen,               13,     89),
1114         ICE_CTX_STORE(ice_rlan_ctx, dbuf,               7,      102),
1115         ICE_CTX_STORE(ice_rlan_ctx, hbuf,               5,      109),
1116         ICE_CTX_STORE(ice_rlan_ctx, dtype,              2,      114),
1117         ICE_CTX_STORE(ice_rlan_ctx, dsize,              1,      116),
1118         ICE_CTX_STORE(ice_rlan_ctx, crcstrip,           1,      117),
1119         ICE_CTX_STORE(ice_rlan_ctx, l2tsel,             1,      119),
1120         ICE_CTX_STORE(ice_rlan_ctx, hsplit_0,           4,      120),
1121         ICE_CTX_STORE(ice_rlan_ctx, hsplit_1,           2,      124),
1122         ICE_CTX_STORE(ice_rlan_ctx, showiv,             1,      127),
1123         ICE_CTX_STORE(ice_rlan_ctx, rxmax,              14,     174),
1124         ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena,       1,      193),
1125         ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena,       1,      194),
1126         ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena,        1,      195),
1127         ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena,        1,      196),
1128         ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh,         3,      198),
1129         ICE_CTX_STORE(ice_rlan_ctx, prefena,            1,      201),
1130         { 0 }
1131 };
1132 
1133 /**
1134  * ice_write_rxq_ctx
1135  * @hw: pointer to the hardware structure
1136  * @rlan_ctx: pointer to the rxq context
1137  * @rxq_index: the index of the Rx queue
1138  *
1139  * Converts rxq context from sparse to dense structure and then writes
1140  * it to HW register space and enables the hardware to prefetch descriptors
1141  * instead of only fetching them on demand
1142  */
1143 enum ice_status
1144 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1145                   u32 rxq_index)
1146 {
1147         u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1148 
1149         if (!rlan_ctx)
1150                 return ICE_ERR_BAD_PTR;
1151 
1152         rlan_ctx->prefena = 1;
1153 
1154         ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1155         return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1156 }
1157 
1158 /* LAN Tx Queue Context */
1159 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1160                                     /* Field                    Width   LSB */
1161         ICE_CTX_STORE(ice_tlan_ctx, base,                       57,     0),
1162         ICE_CTX_STORE(ice_tlan_ctx, port_num,                   3,      57),
1163         ICE_CTX_STORE(ice_tlan_ctx, cgd_num,                    5,      60),
1164         ICE_CTX_STORE(ice_tlan_ctx, pf_num,                     3,      65),
1165         ICE_CTX_STORE(ice_tlan_ctx, vmvf_num,                   10,     68),
1166         ICE_CTX_STORE(ice_tlan_ctx, vmvf_type,                  2,      78),
1167         ICE_CTX_STORE(ice_tlan_ctx, src_vsi,                    10,     80),
1168         ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena,                   1,      90),
1169         ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag,        1,      91),
1170         ICE_CTX_STORE(ice_tlan_ctx, alt_vlan,                   1,      92),
1171         ICE_CTX_STORE(ice_tlan_ctx, cpuid,                      8,      93),
1172         ICE_CTX_STORE(ice_tlan_ctx, wb_mode,                    1,      101),
1173         ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc,                 1,      102),
1174         ICE_CTX_STORE(ice_tlan_ctx, tphrd,                      1,      103),
1175         ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc,                 1,      104),
1176         ICE_CTX_STORE(ice_tlan_ctx, cmpq_id,                    9,      105),
1177         ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func,               14,     114),
1178         ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode,      1,      128),
1179         ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id,             6,      129),
1180         ICE_CTX_STORE(ice_tlan_ctx, qlen,                       13,     135),
1181         ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx,            4,      148),
1182         ICE_CTX_STORE(ice_tlan_ctx, tso_ena,                    1,      152),
1183         ICE_CTX_STORE(ice_tlan_ctx, tso_qnum,                   11,     153),
1184         ICE_CTX_STORE(ice_tlan_ctx, legacy_int,                 1,      164),
1185         ICE_CTX_STORE(ice_tlan_ctx, drop_ena,                   1,      165),
1186         ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx,             2,      166),
1187         ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx,        3,      168),
1188         ICE_CTX_STORE(ice_tlan_ctx, int_q_state,                122,    171),
1189         { 0 }
1190 };
1191 
1192 /**
1193  * ice_debug_cq
1194  * @hw: pointer to the hardware structure
1195  * @mask: debug mask
1196  * @desc: pointer to control queue descriptor
1197  * @buf: pointer to command buffer
1198  * @buf_len: max length of buf
1199  *
1200  * Dumps debug log about control command with descriptor contents.
1201  */
1202 void
1203 ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf,
1204              u16 buf_len)
1205 {
1206         struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1207         u16 len;
1208 
1209 #ifndef CONFIG_DYNAMIC_DEBUG
1210         if (!(mask & hw->debug_mask))
1211                 return;
1212 #endif
1213 
1214         if (!desc)
1215                 return;
1216 
1217         len = le16_to_cpu(cq_desc->datalen);
1218 
1219         ice_debug(hw, mask,
1220                   "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1221                   le16_to_cpu(cq_desc->opcode),
1222                   le16_to_cpu(cq_desc->flags),
1223                   le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
1224         ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1225                   le32_to_cpu(cq_desc->cookie_high),
1226                   le32_to_cpu(cq_desc->cookie_low));
1227         ice_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
1228                   le32_to_cpu(cq_desc->params.generic.param0),
1229                   le32_to_cpu(cq_desc->params.generic.param1));
1230         ice_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
1231                   le32_to_cpu(cq_desc->params.generic.addr_high),
1232                   le32_to_cpu(cq_desc->params.generic.addr_low));
1233         if (buf && cq_desc->datalen != 0) {
1234                 ice_debug(hw, mask, "Buffer:\n");
1235                 if (buf_len < len)
1236                         len = buf_len;
1237 
1238                 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1239         }
1240 }
1241 
1242 /* FW Admin Queue command wrappers */
1243 
1244 /* Software lock/mutex that is meant to be held while the Global Config Lock
1245  * in firmware is acquired by the software to prevent most (but not all) types
1246  * of AQ commands from being sent to FW
1247  */
1248 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1249 
1250 /**
1251  * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1252  * @hw: pointer to the HW struct
1253  * @desc: descriptor describing the command
1254  * @buf: buffer to use for indirect commands (NULL for direct commands)
1255  * @buf_size: size of buffer for indirect commands (0 for direct commands)
1256  * @cd: pointer to command details structure
1257  *
1258  * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1259  */
1260 enum ice_status
1261 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1262                 u16 buf_size, struct ice_sq_cd *cd)
1263 {
1264         struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1265         bool lock_acquired = false;
1266         enum ice_status status;
1267 
1268         /* When a package download is in process (i.e. when the firmware's
1269          * Global Configuration Lock resource is held), only the Download
1270          * Package, Get Version, Get Package Info List and Release Resource
1271          * (with resource ID set to Global Config Lock) AdminQ commands are
1272          * allowed; all others must block until the package download completes
1273          * and the Global Config Lock is released.  See also
1274          * ice_acquire_global_cfg_lock().
1275          */
1276         switch (le16_to_cpu(desc->opcode)) {
1277         case ice_aqc_opc_download_pkg:
1278         case ice_aqc_opc_get_pkg_info_list:
1279         case ice_aqc_opc_get_ver:
1280                 break;
1281         case ice_aqc_opc_release_res:
1282                 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1283                         break;
1284                 /* fall-through */
1285         default:
1286                 mutex_lock(&ice_global_cfg_lock_sw);
1287                 lock_acquired = true;
1288                 break;
1289         }
1290 
1291         status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1292         if (lock_acquired)
1293                 mutex_unlock(&ice_global_cfg_lock_sw);
1294 
1295         return status;
1296 }
1297 
1298 /**
1299  * ice_aq_get_fw_ver
1300  * @hw: pointer to the HW struct
1301  * @cd: pointer to command details structure or NULL
1302  *
1303  * Get the firmware version (0x0001) from the admin queue commands
1304  */
1305 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1306 {
1307         struct ice_aqc_get_ver *resp;
1308         struct ice_aq_desc desc;
1309         enum ice_status status;
1310 
1311         resp = &desc.params.get_ver;
1312 
1313         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1314 
1315         status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1316 
1317         if (!status) {
1318                 hw->fw_branch = resp->fw_branch;
1319                 hw->fw_maj_ver = resp->fw_major;
1320                 hw->fw_min_ver = resp->fw_minor;
1321                 hw->fw_patch = resp->fw_patch;
1322                 hw->fw_build = le32_to_cpu(resp->fw_build);
1323                 hw->api_branch = resp->api_branch;
1324                 hw->api_maj_ver = resp->api_major;
1325                 hw->api_min_ver = resp->api_minor;
1326                 hw->api_patch = resp->api_patch;
1327         }
1328 
1329         return status;
1330 }
1331 
1332 /**
1333  * ice_aq_send_driver_ver
1334  * @hw: pointer to the HW struct
1335  * @dv: driver's major, minor version
1336  * @cd: pointer to command details structure or NULL
1337  *
1338  * Send the driver version (0x0002) to the firmware
1339  */
1340 enum ice_status
1341 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1342                        struct ice_sq_cd *cd)
1343 {
1344         struct ice_aqc_driver_ver *cmd;
1345         struct ice_aq_desc desc;
1346         u16 len;
1347 
1348         cmd = &desc.params.driver_ver;
1349 
1350         if (!dv)
1351                 return ICE_ERR_PARAM;
1352 
1353         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1354 
1355         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1356         cmd->major_ver = dv->major_ver;
1357         cmd->minor_ver = dv->minor_ver;
1358         cmd->build_ver = dv->build_ver;
1359         cmd->subbuild_ver = dv->subbuild_ver;
1360 
1361         len = 0;
1362         while (len < sizeof(dv->driver_string) &&
1363                isascii(dv->driver_string[len]) && dv->driver_string[len])
1364                 len++;
1365 
1366         return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1367 }
1368 
1369 /**
1370  * ice_aq_q_shutdown
1371  * @hw: pointer to the HW struct
1372  * @unloading: is the driver unloading itself
1373  *
1374  * Tell the Firmware that we're shutting down the AdminQ and whether
1375  * or not the driver is unloading as well (0x0003).
1376  */
1377 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1378 {
1379         struct ice_aqc_q_shutdown *cmd;
1380         struct ice_aq_desc desc;
1381 
1382         cmd = &desc.params.q_shutdown;
1383 
1384         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1385 
1386         if (unloading)
1387                 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1388 
1389         return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1390 }
1391 
1392 /**
1393  * ice_aq_req_res
1394  * @hw: pointer to the HW struct
1395  * @res: resource ID
1396  * @access: access type
1397  * @sdp_number: resource number
1398  * @timeout: the maximum time in ms that the driver may hold the resource
1399  * @cd: pointer to command details structure or NULL
1400  *
1401  * Requests common resource using the admin queue commands (0x0008).
1402  * When attempting to acquire the Global Config Lock, the driver can
1403  * learn of three states:
1404  *  1) ICE_SUCCESS -        acquired lock, and can perform download package
1405  *  2) ICE_ERR_AQ_ERROR -   did not get lock, driver should fail to load
1406  *  3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1407  *                          successfully downloaded the package; the driver does
1408  *                          not have to download the package and can continue
1409  *                          loading
1410  *
1411  * Note that if the caller is in an acquire lock, perform action, release lock
1412  * phase of operation, it is possible that the FW may detect a timeout and issue
1413  * a CORER. In this case, the driver will receive a CORER interrupt and will
1414  * have to determine its cause. The calling thread that is handling this flow
1415  * will likely get an error propagated back to it indicating the Download
1416  * Package, Update Package or the Release Resource AQ commands timed out.
1417  */
1418 static enum ice_status
1419 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1420                enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1421                struct ice_sq_cd *cd)
1422 {
1423         struct ice_aqc_req_res *cmd_resp;
1424         struct ice_aq_desc desc;
1425         enum ice_status status;
1426 
1427         cmd_resp = &desc.params.res_owner;
1428 
1429         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1430 
1431         cmd_resp->res_id = cpu_to_le16(res);
1432         cmd_resp->access_type = cpu_to_le16(access);
1433         cmd_resp->res_number = cpu_to_le32(sdp_number);
1434         cmd_resp->timeout = cpu_to_le32(*timeout);
1435         *timeout = 0;
1436 
1437         status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1438 
1439         /* The completion specifies the maximum time in ms that the driver
1440          * may hold the resource in the Timeout field.
1441          */
1442 
1443         /* Global config lock response utilizes an additional status field.
1444          *
1445          * If the Global config lock resource is held by some other driver, the
1446          * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1447          * and the timeout field indicates the maximum time the current owner
1448          * of the resource has to free it.
1449          */
1450         if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1451                 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1452                         *timeout = le32_to_cpu(cmd_resp->timeout);
1453                         return 0;
1454                 } else if (le16_to_cpu(cmd_resp->status) ==
1455                            ICE_AQ_RES_GLBL_IN_PROG) {
1456                         *timeout = le32_to_cpu(cmd_resp->timeout);
1457                         return ICE_ERR_AQ_ERROR;
1458                 } else if (le16_to_cpu(cmd_resp->status) ==
1459                            ICE_AQ_RES_GLBL_DONE) {
1460                         return ICE_ERR_AQ_NO_WORK;
1461                 }
1462 
1463                 /* invalid FW response, force a timeout immediately */
1464                 *timeout = 0;
1465                 return ICE_ERR_AQ_ERROR;
1466         }
1467 
1468         /* If the resource is held by some other driver, the command completes
1469          * with a busy return value and the timeout field indicates the maximum
1470          * time the current owner of the resource has to free it.
1471          */
1472         if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1473                 *timeout = le32_to_cpu(cmd_resp->timeout);
1474 
1475         return status;
1476 }
1477 
1478 /**
1479  * ice_aq_release_res
1480  * @hw: pointer to the HW struct
1481  * @res: resource ID
1482  * @sdp_number: resource number
1483  * @cd: pointer to command details structure or NULL
1484  *
1485  * release common resource using the admin queue commands (0x0009)
1486  */
1487 static enum ice_status
1488 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1489                    struct ice_sq_cd *cd)
1490 {
1491         struct ice_aqc_req_res *cmd;
1492         struct ice_aq_desc desc;
1493 
1494         cmd = &desc.params.res_owner;
1495 
1496         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1497 
1498         cmd->res_id = cpu_to_le16(res);
1499         cmd->res_number = cpu_to_le32(sdp_number);
1500 
1501         return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1502 }
1503 
1504 /**
1505  * ice_acquire_res
1506  * @hw: pointer to the HW structure
1507  * @res: resource ID
1508  * @access: access type (read or write)
1509  * @timeout: timeout in milliseconds
1510  *
1511  * This function will attempt to acquire the ownership of a resource.
1512  */
1513 enum ice_status
1514 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1515                 enum ice_aq_res_access_type access, u32 timeout)
1516 {
1517 #define ICE_RES_POLLING_DELAY_MS        10
1518         u32 delay = ICE_RES_POLLING_DELAY_MS;
1519         u32 time_left = timeout;
1520         enum ice_status status;
1521 
1522         status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1523 
1524         /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1525          * previously acquired the resource and performed any necessary updates;
1526          * in this case the caller does not obtain the resource and has no
1527          * further work to do.
1528          */
1529         if (status == ICE_ERR_AQ_NO_WORK)
1530                 goto ice_acquire_res_exit;
1531 
1532         if (status)
1533                 ice_debug(hw, ICE_DBG_RES,
1534                           "resource %d acquire type %d failed.\n", res, access);
1535 
1536         /* If necessary, poll until the current lock owner timeouts */
1537         timeout = time_left;
1538         while (status && timeout && time_left) {
1539                 mdelay(delay);
1540                 timeout = (timeout > delay) ? timeout - delay : 0;
1541                 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1542 
1543                 if (status == ICE_ERR_AQ_NO_WORK)
1544                         /* lock free, but no work to do */
1545                         break;
1546 
1547                 if (!status)
1548                         /* lock acquired */
1549                         break;
1550         }
1551         if (status && status != ICE_ERR_AQ_NO_WORK)
1552                 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1553 
1554 ice_acquire_res_exit:
1555         if (status == ICE_ERR_AQ_NO_WORK) {
1556                 if (access == ICE_RES_WRITE)
1557                         ice_debug(hw, ICE_DBG_RES,
1558                                   "resource indicates no work to do.\n");
1559                 else
1560                         ice_debug(hw, ICE_DBG_RES,
1561                                   "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1562         }
1563         return status;
1564 }
1565 
1566 /**
1567  * ice_release_res
1568  * @hw: pointer to the HW structure
1569  * @res: resource ID
1570  *
1571  * This function will release a resource using the proper Admin Command.
1572  */
1573 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1574 {
1575         enum ice_status status;
1576         u32 total_delay = 0;
1577 
1578         status = ice_aq_release_res(hw, res, 0, NULL);
1579 
1580         /* there are some rare cases when trying to release the resource
1581          * results in an admin queue timeout, so handle them correctly
1582          */
1583         while ((status == ICE_ERR_AQ_TIMEOUT) &&
1584                (total_delay < hw->adminq.sq_cmd_timeout)) {
1585                 mdelay(1);
1586                 status = ice_aq_release_res(hw, res, 0, NULL);
1587                 total_delay++;
1588         }
1589 }
1590 
1591 /**
1592  * ice_get_num_per_func - determine number of resources per PF
1593  * @hw: pointer to the HW structure
1594  * @max: value to be evenly split between each PF
1595  *
1596  * Determine the number of valid functions by going through the bitmap returned
1597  * from parsing capabilities and use this to calculate the number of resources
1598  * per PF based on the max value passed in.
1599  */
1600 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1601 {
1602         u8 funcs;
1603 
1604 #define ICE_CAPS_VALID_FUNCS_M  0xFF
1605         funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
1606                          ICE_CAPS_VALID_FUNCS_M);
1607 
1608         if (!funcs)
1609                 return 0;
1610 
1611         return max / funcs;
1612 }
1613 
1614 /**
1615  * ice_parse_caps - parse function/device capabilities
1616  * @hw: pointer to the HW struct
1617  * @buf: pointer to a buffer containing function/device capability records
1618  * @cap_count: number of capability records in the list
1619  * @opc: type of capabilities list to parse
1620  *
1621  * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1622  */
1623 static void
1624 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1625                enum ice_adminq_opc opc)
1626 {
1627         struct ice_aqc_list_caps_elem *cap_resp;
1628         struct ice_hw_func_caps *func_p = NULL;
1629         struct ice_hw_dev_caps *dev_p = NULL;
1630         struct ice_hw_common_caps *caps;
1631         char const *prefix;
1632         u32 i;
1633 
1634         if (!buf)
1635                 return;
1636 
1637         cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1638 
1639         if (opc == ice_aqc_opc_list_dev_caps) {
1640                 dev_p = &hw->dev_caps;
1641                 caps = &dev_p->common_cap;
1642                 prefix = "dev cap";
1643         } else if (opc == ice_aqc_opc_list_func_caps) {
1644                 func_p = &hw->func_caps;
1645                 caps = &func_p->common_cap;
1646                 prefix = "func cap";
1647         } else {
1648                 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1649                 return;
1650         }
1651 
1652         for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1653                 u32 logical_id = le32_to_cpu(cap_resp->logical_id);
1654                 u32 phys_id = le32_to_cpu(cap_resp->phys_id);
1655                 u32 number = le32_to_cpu(cap_resp->number);
1656                 u16 cap = le16_to_cpu(cap_resp->cap);
1657 
1658                 switch (cap) {
1659                 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1660                         caps->valid_functions = number;
1661                         ice_debug(hw, ICE_DBG_INIT,
1662                                   "%s: valid_functions (bitmap) = %d\n", prefix,
1663                                   caps->valid_functions);
1664                         break;
1665                 case ICE_AQC_CAPS_SRIOV:
1666                         caps->sr_iov_1_1 = (number == 1);
1667                         ice_debug(hw, ICE_DBG_INIT,
1668                                   "%s: sr_iov_1_1 = %d\n", prefix,
1669                                   caps->sr_iov_1_1);
1670                         break;
1671                 case ICE_AQC_CAPS_VF:
1672                         if (dev_p) {
1673                                 dev_p->num_vfs_exposed = number;
1674                                 ice_debug(hw, ICE_DBG_INIT,
1675                                           "%s: num_vfs_exposed = %d\n", prefix,
1676                                           dev_p->num_vfs_exposed);
1677                         } else if (func_p) {
1678                                 func_p->num_allocd_vfs = number;
1679                                 func_p->vf_base_id = logical_id;
1680                                 ice_debug(hw, ICE_DBG_INIT,
1681                                           "%s: num_allocd_vfs = %d\n", prefix,
1682                                           func_p->num_allocd_vfs);
1683                                 ice_debug(hw, ICE_DBG_INIT,
1684                                           "%s: vf_base_id = %d\n", prefix,
1685                                           func_p->vf_base_id);
1686                         }
1687                         break;
1688                 case ICE_AQC_CAPS_VSI:
1689                         if (dev_p) {
1690                                 dev_p->num_vsi_allocd_to_host = number;
1691                                 ice_debug(hw, ICE_DBG_INIT,
1692                                           "%s: num_vsi_allocd_to_host = %d\n",
1693                                           prefix,
1694                                           dev_p->num_vsi_allocd_to_host);
1695                         } else if (func_p) {
1696                                 func_p->guar_num_vsi =
1697                                         ice_get_num_per_func(hw, ICE_MAX_VSI);
1698                                 ice_debug(hw, ICE_DBG_INIT,
1699                                           "%s: guar_num_vsi (fw) = %d\n",
1700                                           prefix, number);
1701                                 ice_debug(hw, ICE_DBG_INIT,
1702                                           "%s: guar_num_vsi = %d\n",
1703                                           prefix, func_p->guar_num_vsi);
1704                         }
1705                         break;
1706                 case ICE_AQC_CAPS_DCB:
1707                         caps->dcb = (number == 1);
1708                         caps->active_tc_bitmap = logical_id;
1709                         caps->maxtc = phys_id;
1710                         ice_debug(hw, ICE_DBG_INIT,
1711                                   "%s: dcb = %d\n", prefix, caps->dcb);
1712                         ice_debug(hw, ICE_DBG_INIT,
1713                                   "%s: active_tc_bitmap = %d\n", prefix,
1714                                   caps->active_tc_bitmap);
1715                         ice_debug(hw, ICE_DBG_INIT,
1716                                   "%s: maxtc = %d\n", prefix, caps->maxtc);
1717                         break;
1718                 case ICE_AQC_CAPS_RSS:
1719                         caps->rss_table_size = number;
1720                         caps->rss_table_entry_width = logical_id;
1721                         ice_debug(hw, ICE_DBG_INIT,
1722                                   "%s: rss_table_size = %d\n", prefix,
1723                                   caps->rss_table_size);
1724                         ice_debug(hw, ICE_DBG_INIT,
1725                                   "%s: rss_table_entry_width = %d\n", prefix,
1726                                   caps->rss_table_entry_width);
1727                         break;
1728                 case ICE_AQC_CAPS_RXQS:
1729                         caps->num_rxq = number;
1730                         caps->rxq_first_id = phys_id;
1731                         ice_debug(hw, ICE_DBG_INIT,
1732                                   "%s: num_rxq = %d\n", prefix,
1733                                   caps->num_rxq);
1734                         ice_debug(hw, ICE_DBG_INIT,
1735                                   "%s: rxq_first_id = %d\n", prefix,
1736                                   caps->rxq_first_id);
1737                         break;
1738                 case ICE_AQC_CAPS_TXQS:
1739                         caps->num_txq = number;
1740                         caps->txq_first_id = phys_id;
1741                         ice_debug(hw, ICE_DBG_INIT,
1742                                   "%s: num_txq = %d\n", prefix,
1743                                   caps->num_txq);
1744                         ice_debug(hw, ICE_DBG_INIT,
1745                                   "%s: txq_first_id = %d\n", prefix,
1746                                   caps->txq_first_id);
1747                         break;
1748                 case ICE_AQC_CAPS_MSIX:
1749                         caps->num_msix_vectors = number;
1750                         caps->msix_vector_first_id = phys_id;
1751                         ice_debug(hw, ICE_DBG_INIT,
1752                                   "%s: num_msix_vectors = %d\n", prefix,
1753                                   caps->num_msix_vectors);
1754                         ice_debug(hw, ICE_DBG_INIT,
1755                                   "%s: msix_vector_first_id = %d\n", prefix,
1756                                   caps->msix_vector_first_id);
1757                         break;
1758                 case ICE_AQC_CAPS_MAX_MTU:
1759                         caps->max_mtu = number;
1760                         ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1761                                   prefix, caps->max_mtu);
1762                         break;
1763                 default:
1764                         ice_debug(hw, ICE_DBG_INIT,
1765                                   "%s: unknown capability[%d]: 0x%x\n", prefix,
1766                                   i, cap);
1767                         break;
1768                 }
1769         }
1770 }
1771 
1772 /**
1773  * ice_aq_discover_caps - query function/device capabilities
1774  * @hw: pointer to the HW struct
1775  * @buf: a virtual buffer to hold the capabilities
1776  * @buf_size: Size of the virtual buffer
1777  * @cap_count: cap count needed if AQ err==ENOMEM
1778  * @opc: capabilities type to discover - pass in the command opcode
1779  * @cd: pointer to command details structure or NULL
1780  *
1781  * Get the function(0x000a)/device(0x000b) capabilities description from
1782  * the firmware.
1783  */
1784 static enum ice_status
1785 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1786                      enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1787 {
1788         struct ice_aqc_list_caps *cmd;
1789         struct ice_aq_desc desc;
1790         enum ice_status status;
1791 
1792         cmd = &desc.params.get_cap;
1793 
1794         if (opc != ice_aqc_opc_list_func_caps &&
1795             opc != ice_aqc_opc_list_dev_caps)
1796                 return ICE_ERR_PARAM;
1797 
1798         ice_fill_dflt_direct_cmd_desc(&desc, opc);
1799 
1800         status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1801         if (!status)
1802                 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc);
1803         else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1804                 *cap_count = le32_to_cpu(cmd->count);
1805         return status;
1806 }
1807 
1808 /**
1809  * ice_discover_caps - get info about the HW
1810  * @hw: pointer to the hardware structure
1811  * @opc: capabilities type to discover - pass in the command opcode
1812  */
1813 static enum ice_status
1814 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1815 {
1816         enum ice_status status;
1817         u32 cap_count;
1818         u16 cbuf_len;
1819         u8 retries;
1820 
1821         /* The driver doesn't know how many capabilities the device will return
1822          * so the buffer size required isn't known ahead of time. The driver
1823          * starts with cbuf_len and if this turns out to be insufficient, the
1824          * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1825          * The driver then allocates the buffer based on the count and retries
1826          * the operation. So it follows that the retry count is 2.
1827          */
1828 #define ICE_GET_CAP_BUF_COUNT   40
1829 #define ICE_GET_CAP_RETRY_COUNT 2
1830 
1831         cap_count = ICE_GET_CAP_BUF_COUNT;
1832         retries = ICE_GET_CAP_RETRY_COUNT;
1833 
1834         do {
1835                 void *cbuf;
1836 
1837                 cbuf_len = (u16)(cap_count *
1838                                  sizeof(struct ice_aqc_list_caps_elem));
1839                 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL);
1840                 if (!cbuf)
1841                         return ICE_ERR_NO_MEMORY;
1842 
1843                 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1844                                               opc, NULL);
1845                 devm_kfree(ice_hw_to_dev(hw), cbuf);
1846 
1847                 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1848                         break;
1849 
1850                 /* If ENOMEM is returned, try again with bigger buffer */
1851         } while (--retries);
1852 
1853         return status;
1854 }
1855 
1856 /**
1857  * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
1858  * @hw: pointer to the hardware structure
1859  */
1860 void ice_set_safe_mode_caps(struct ice_hw *hw)
1861 {
1862         struct ice_hw_func_caps *func_caps = &hw->func_caps;
1863         struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
1864         u32 valid_func, rxq_first_id, txq_first_id;
1865         u32 msix_vector_first_id, max_mtu;
1866         u32 num_func = 0;
1867         u8 i;
1868 
1869         /* cache some func_caps values that should be restored after memset */
1870         valid_func = func_caps->common_cap.valid_functions;
1871         txq_first_id = func_caps->common_cap.txq_first_id;
1872         rxq_first_id = func_caps->common_cap.rxq_first_id;
1873         msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
1874         max_mtu = func_caps->common_cap.max_mtu;
1875 
1876         /* unset func capabilities */
1877         memset(func_caps, 0, sizeof(*func_caps));
1878 
1879         /* restore cached values */
1880         func_caps->common_cap.valid_functions = valid_func;
1881         func_caps->common_cap.txq_first_id = txq_first_id;
1882         func_caps->common_cap.rxq_first_id = rxq_first_id;
1883         func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
1884         func_caps->common_cap.max_mtu = max_mtu;
1885 
1886         /* one Tx and one Rx queue in safe mode */
1887         func_caps->common_cap.num_rxq = 1;
1888         func_caps->common_cap.num_txq = 1;
1889 
1890         /* two MSIX vectors, one for traffic and one for misc causes */
1891         func_caps->common_cap.num_msix_vectors = 2;
1892         func_caps->guar_num_vsi = 1;
1893 
1894         /* cache some dev_caps values that should be restored after memset */
1895         valid_func = dev_caps->common_cap.valid_functions;
1896         txq_first_id = dev_caps->common_cap.txq_first_id;
1897         rxq_first_id = dev_caps->common_cap.rxq_first_id;
1898         msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
1899         max_mtu = dev_caps->common_cap.max_mtu;
1900 
1901         /* unset dev capabilities */
1902         memset(dev_caps, 0, sizeof(*dev_caps));
1903 
1904         /* restore cached values */
1905         dev_caps->common_cap.valid_functions = valid_func;
1906         dev_caps->common_cap.txq_first_id = txq_first_id;
1907         dev_caps->common_cap.rxq_first_id = rxq_first_id;
1908         dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
1909         dev_caps->common_cap.max_mtu = max_mtu;
1910 
1911         /* valid_func is a bitmap. get number of functions */
1912 #define ICE_MAX_FUNCS 8
1913         for (i = 0; i < ICE_MAX_FUNCS; i++)
1914                 if (valid_func & BIT(i))
1915                         num_func++;
1916 
1917         /* one Tx and one Rx queue per function in safe mode */
1918         dev_caps->common_cap.num_rxq = num_func;
1919         dev_caps->common_cap.num_txq = num_func;
1920 
1921         /* two MSIX vectors per function */
1922         dev_caps->common_cap.num_msix_vectors = 2 * num_func;
1923 }
1924 
1925 /**
1926  * ice_get_caps - get info about the HW
1927  * @hw: pointer to the hardware structure
1928  */
1929 enum ice_status ice_get_caps(struct ice_hw *hw)
1930 {
1931         enum ice_status status;
1932 
1933         status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
1934         if (!status)
1935                 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
1936 
1937         return status;
1938 }
1939 
1940 /**
1941  * ice_aq_manage_mac_write - manage MAC address write command
1942  * @hw: pointer to the HW struct
1943  * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
1944  * @flags: flags to control write behavior
1945  * @cd: pointer to command details structure or NULL
1946  *
1947  * This function is used to write MAC address to the NVM (0x0108).
1948  */
1949 enum ice_status
1950 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
1951                         struct ice_sq_cd *cd)
1952 {
1953         struct ice_aqc_manage_mac_write *cmd;
1954         struct ice_aq_desc desc;
1955 
1956         cmd = &desc.params.mac_write;
1957         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
1958 
1959         cmd->flags = flags;
1960 
1961         /* Prep values for flags, sah, sal */
1962         cmd->sah = htons(*((const u16 *)mac_addr));
1963         cmd->sal = htonl(*((const u32 *)(mac_addr + 2)));
1964 
1965         return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1966 }
1967 
1968 /**
1969  * ice_aq_clear_pxe_mode
1970  * @hw: pointer to the HW struct
1971  *
1972  * Tell the firmware that the driver is taking over from PXE (0x0110).
1973  */
1974 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
1975 {
1976         struct ice_aq_desc desc;
1977 
1978         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
1979         desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
1980 
1981         return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1982 }
1983 
1984 /**
1985  * ice_clear_pxe_mode - clear pxe operations mode
1986  * @hw: pointer to the HW struct
1987  *
1988  * Make sure all PXE mode settings are cleared, including things
1989  * like descriptor fetch/write-back mode.
1990  */
1991 void ice_clear_pxe_mode(struct ice_hw *hw)
1992 {
1993         if (ice_check_sq_alive(hw, &hw->adminq))
1994                 ice_aq_clear_pxe_mode(hw);
1995 }
1996 
1997 /**
1998  * ice_get_link_speed_based_on_phy_type - returns link speed
1999  * @phy_type_low: lower part of phy_type
2000  * @phy_type_high: higher part of phy_type
2001  *
2002  * This helper function will convert an entry in PHY type structure
2003  * [phy_type_low, phy_type_high] to its corresponding link speed.
2004  * Note: In the structure of [phy_type_low, phy_type_high], there should
2005  * be one bit set, as this function will convert one PHY type to its
2006  * speed.
2007  * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2008  * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2009  */
2010 static u16
2011 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2012 {
2013         u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2014         u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2015 
2016         switch (phy_type_low) {
2017         case ICE_PHY_TYPE_LOW_100BASE_TX:
2018         case ICE_PHY_TYPE_LOW_100M_SGMII:
2019                 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2020                 break;
2021         case ICE_PHY_TYPE_LOW_1000BASE_T:
2022         case ICE_PHY_TYPE_LOW_1000BASE_SX:
2023         case ICE_PHY_TYPE_LOW_1000BASE_LX:
2024         case ICE_PHY_TYPE_LOW_1000BASE_KX:
2025         case ICE_PHY_TYPE_LOW_1G_SGMII:
2026                 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2027                 break;
2028         case ICE_PHY_TYPE_LOW_2500BASE_T:
2029         case ICE_PHY_TYPE_LOW_2500BASE_X:
2030         case ICE_PHY_TYPE_LOW_2500BASE_KX:
2031                 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2032                 break;
2033         case ICE_PHY_TYPE_LOW_5GBASE_T:
2034         case ICE_PHY_TYPE_LOW_5GBASE_KR:
2035                 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2036                 break;
2037         case ICE_PHY_TYPE_LOW_10GBASE_T:
2038         case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2039         case ICE_PHY_TYPE_LOW_10GBASE_SR:
2040         case ICE_PHY_TYPE_LOW_10GBASE_LR:
2041         case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2042         case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2043         case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2044                 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2045                 break;
2046         case ICE_PHY_TYPE_LOW_25GBASE_T:
2047         case ICE_PHY_TYPE_LOW_25GBASE_CR:
2048         case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2049         case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2050         case ICE_PHY_TYPE_LOW_25GBASE_SR:
2051         case ICE_PHY_TYPE_LOW_25GBASE_LR:
2052         case ICE_PHY_TYPE_LOW_25GBASE_KR:
2053         case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2054         case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2055         case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2056         case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2057                 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2058                 break;
2059         case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2060         case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2061         case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2062         case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2063         case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2064         case ICE_PHY_TYPE_LOW_40G_XLAUI:
2065                 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2066                 break;
2067         case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2068         case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2069         case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2070         case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2071         case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2072         case ICE_PHY_TYPE_LOW_50G_LAUI2:
2073         case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2074         case ICE_PHY_TYPE_LOW_50G_AUI2:
2075         case ICE_PHY_TYPE_LOW_50GBASE_CP:
2076         case ICE_PHY_TYPE_LOW_50GBASE_SR:
2077         case ICE_PHY_TYPE_LOW_50GBASE_FR:
2078         case ICE_PHY_TYPE_LOW_50GBASE_LR:
2079         case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2080         case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2081         case ICE_PHY_TYPE_LOW_50G_AUI1:
2082                 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2083                 break;
2084         case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2085         case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2086         case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2087         case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2088         case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2089         case ICE_PHY_TYPE_LOW_100G_CAUI4:
2090         case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2091         case ICE_PHY_TYPE_LOW_100G_AUI4:
2092         case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2093         case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2094         case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2095         case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2096         case ICE_PHY_TYPE_LOW_100GBASE_DR:
2097                 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2098                 break;
2099         default:
2100                 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2101                 break;
2102         }
2103 
2104         switch (phy_type_high) {
2105         case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2106         case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2107         case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2108         case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2109         case ICE_PHY_TYPE_HIGH_100G_AUI2:
2110                 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2111                 break;
2112         default:
2113                 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2114                 break;
2115         }
2116 
2117         if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2118             speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2119                 return ICE_AQ_LINK_SPEED_UNKNOWN;
2120         else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2121                  speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2122                 return ICE_AQ_LINK_SPEED_UNKNOWN;
2123         else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2124                  speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2125                 return speed_phy_type_low;
2126         else
2127                 return speed_phy_type_high;
2128 }
2129 
2130 /**
2131  * ice_update_phy_type
2132  * @phy_type_low: pointer to the lower part of phy_type
2133  * @phy_type_high: pointer to the higher part of phy_type
2134  * @link_speeds_bitmap: targeted link speeds bitmap
2135  *
2136  * Note: For the link_speeds_bitmap structure, you can check it at
2137  * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2138  * link_speeds_bitmap include multiple speeds.
2139  *
2140  * Each entry in this [phy_type_low, phy_type_high] structure will
2141  * present a certain link speed. This helper function will turn on bits
2142  * in [phy_type_low, phy_type_high] structure based on the value of
2143  * link_speeds_bitmap input parameter.
2144  */
2145 void
2146 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2147                     u16 link_speeds_bitmap)
2148 {
2149         u64 pt_high;
2150         u64 pt_low;
2151         int index;
2152         u16 speed;
2153 
2154         /* We first check with low part of phy_type */
2155         for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2156                 pt_low = BIT_ULL(index);
2157                 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2158 
2159                 if (link_speeds_bitmap & speed)
2160                         *phy_type_low |= BIT_ULL(index);
2161         }
2162 
2163         /* We then check with high part of phy_type */
2164         for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2165                 pt_high = BIT_ULL(index);
2166                 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2167 
2168                 if (link_speeds_bitmap & speed)
2169                         *phy_type_high |= BIT_ULL(index);
2170         }
2171 }
2172 
2173 /**
2174  * ice_aq_set_phy_cfg
2175  * @hw: pointer to the HW struct
2176  * @lport: logical port number
2177  * @cfg: structure with PHY configuration data to be set
2178  * @cd: pointer to command details structure or NULL
2179  *
2180  * Set the various PHY configuration parameters supported on the Port.
2181  * One or more of the Set PHY config parameters may be ignored in an MFP
2182  * mode as the PF may not have the privilege to set some of the PHY Config
2183  * parameters. This status will be indicated by the command response (0x0601).
2184  */
2185 enum ice_status
2186 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
2187                    struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2188 {
2189         struct ice_aq_desc desc;
2190 
2191         if (!cfg)
2192                 return ICE_ERR_PARAM;
2193 
2194         /* Ensure that only valid bits of cfg->caps can be turned on. */
2195         if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2196                 ice_debug(hw, ICE_DBG_PHY,
2197                           "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2198                           cfg->caps);
2199 
2200                 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2201         }
2202 
2203         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2204         desc.params.set_phy.lport_num = lport;
2205         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2206 
2207         ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2208                   (unsigned long long)le64_to_cpu(cfg->phy_type_low));
2209         ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2210                   (unsigned long long)le64_to_cpu(cfg->phy_type_high));
2211         ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2212         ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2213                   cfg->low_power_ctrl);
2214         ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2215         ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2216         ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2217 
2218         return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2219 }
2220 
2221 /**
2222  * ice_update_link_info - update status of the HW network link
2223  * @pi: port info structure of the interested logical port
2224  */
2225 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2226 {
2227         struct ice_link_status *li;
2228         enum ice_status status;
2229 
2230         if (!pi)
2231                 return ICE_ERR_PARAM;
2232 
2233         li = &pi->phy.link_info;
2234 
2235         status = ice_aq_get_link_info(pi, true, NULL, NULL);
2236         if (status)
2237                 return status;
2238 
2239         if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2240                 struct ice_aqc_get_phy_caps_data *pcaps;
2241                 struct ice_hw *hw;
2242 
2243                 hw = pi->hw;
2244                 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
2245                                      GFP_KERNEL);
2246                 if (!pcaps)
2247                         return ICE_ERR_NO_MEMORY;
2248 
2249                 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2250                                              pcaps, NULL);
2251                 if (!status)
2252                         memcpy(li->module_type, &pcaps->module_type,
2253                                sizeof(li->module_type));
2254 
2255                 devm_kfree(ice_hw_to_dev(hw), pcaps);
2256         }
2257 
2258         return status;
2259 }
2260 
2261 /**
2262  * ice_set_fc
2263  * @pi: port information structure
2264  * @aq_failures: pointer to status code, specific to ice_set_fc routine
2265  * @ena_auto_link_update: enable automatic link update
2266  *
2267  * Set the requested flow control mode.
2268  */
2269 enum ice_status
2270 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2271 {
2272         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2273         struct ice_aqc_get_phy_caps_data *pcaps;
2274         enum ice_status status;
2275         u8 pause_mask = 0x0;
2276         struct ice_hw *hw;
2277 
2278         if (!pi)
2279                 return ICE_ERR_PARAM;
2280         hw = pi->hw;
2281         *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2282 
2283         switch (pi->fc.req_mode) {
2284         case ICE_FC_FULL:
2285                 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2286                 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2287                 break;
2288         case ICE_FC_RX_PAUSE:
2289                 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2290                 break;
2291         case ICE_FC_TX_PAUSE:
2292                 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2293                 break;
2294         default:
2295                 break;
2296         }
2297 
2298         pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
2299         if (!pcaps)
2300                 return ICE_ERR_NO_MEMORY;
2301 
2302         /* Get the current PHY config */
2303         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2304                                      NULL);
2305         if (status) {
2306                 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2307                 goto out;
2308         }
2309 
2310         /* clear the old pause settings */
2311         cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2312                                    ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2313 
2314         /* set the new capabilities */
2315         cfg.caps |= pause_mask;
2316 
2317         /* If the capabilities have changed, then set the new config */
2318         if (cfg.caps != pcaps->caps) {
2319                 int retry_count, retry_max = 10;
2320 
2321                 /* Auto restart link so settings take effect */
2322                 if (ena_auto_link_update)
2323                         cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2324                 /* Copy over all the old settings */
2325                 cfg.phy_type_high = pcaps->phy_type_high;
2326                 cfg.phy_type_low = pcaps->phy_type_low;
2327                 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2328                 cfg.eee_cap = pcaps->eee_cap;
2329                 cfg.eeer_value = pcaps->eeer_value;
2330                 cfg.link_fec_opt = pcaps->link_fec_options;
2331 
2332                 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2333                 if (status) {
2334                         *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2335                         goto out;
2336                 }
2337 
2338                 /* Update the link info
2339                  * It sometimes takes a really long time for link to
2340                  * come back from the atomic reset. Thus, we wait a
2341                  * little bit.
2342                  */
2343                 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2344                         status = ice_update_link_info(pi);
2345 
2346                         if (!status)
2347                                 break;
2348 
2349                         mdelay(100);
2350                 }
2351 
2352                 if (status)
2353                         *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2354         }
2355 
2356 out:
2357         devm_kfree(ice_hw_to_dev(hw), pcaps);
2358         return status;
2359 }
2360 
2361 /**
2362  * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2363  * @caps: PHY ability structure to copy date from
2364  * @cfg: PHY configuration structure to copy data to
2365  *
2366  * Helper function to copy AQC PHY get ability data to PHY set configuration
2367  * data structure
2368  */
2369 void
2370 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2371                          struct ice_aqc_set_phy_cfg_data *cfg)
2372 {
2373         if (!caps || !cfg)
2374                 return;
2375 
2376         cfg->phy_type_low = caps->phy_type_low;
2377         cfg->phy_type_high = caps->phy_type_high;
2378         cfg->caps = caps->caps;
2379         cfg->low_power_ctrl = caps->low_power_ctrl;
2380         cfg->eee_cap = caps->eee_cap;
2381         cfg->eeer_value = caps->eeer_value;
2382         cfg->link_fec_opt = caps->link_fec_options;
2383 }
2384 
2385 /**
2386  * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2387  * @cfg: PHY configuration data to set FEC mode
2388  * @fec: FEC mode to configure
2389  *
2390  * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2391  * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2392  * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2393  */
2394 void
2395 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2396 {
2397         switch (fec) {
2398         case ICE_FEC_BASER:
2399                 /* Clear RS bits, and AND BASE-R ability
2400                  * bits and OR request bits.
2401                  */
2402                 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2403                                      ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2404                 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2405                                      ICE_AQC_PHY_FEC_25G_KR_REQ;
2406                 break;
2407         case ICE_FEC_RS:
2408                 /* Clear BASE-R bits, and AND RS ability
2409                  * bits and OR request bits.
2410                  */
2411                 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2412                 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2413                                      ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2414                 break;
2415         case ICE_FEC_NONE:
2416                 /* Clear all FEC option bits. */
2417                 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2418                 break;
2419         case ICE_FEC_AUTO:
2420                 /* AND auto FEC bit, and all caps bits. */
2421                 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2422                 break;
2423         }
2424 }
2425 
2426 /**
2427  * ice_get_link_status - get status of the HW network link
2428  * @pi: port information structure
2429  * @link_up: pointer to bool (true/false = linkup/linkdown)
2430  *
2431  * Variable link_up is true if link is up, false if link is down.
2432  * The variable link_up is invalid if status is non zero. As a
2433  * result of this call, link status reporting becomes enabled
2434  */
2435 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2436 {
2437         struct ice_phy_info *phy_info;
2438         enum ice_status status = 0;
2439 
2440         if (!pi || !link_up)
2441                 return ICE_ERR_PARAM;
2442 
2443         phy_info = &pi->phy;
2444 
2445         if (phy_info->get_link_info) {
2446                 status = ice_update_link_info(pi);
2447 
2448                 if (status)
2449                         ice_debug(pi->hw, ICE_DBG_LINK,
2450                                   "get link status error, status = %d\n",
2451                                   status);
2452         }
2453 
2454         *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2455 
2456         return status;
2457 }
2458 
2459 /**
2460  * ice_aq_set_link_restart_an
2461  * @pi: pointer to the port information structure
2462  * @ena_link: if true: enable link, if false: disable link
2463  * @cd: pointer to command details structure or NULL
2464  *
2465  * Sets up the link and restarts the Auto-Negotiation over the link.
2466  */
2467 enum ice_status
2468 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2469                            struct ice_sq_cd *cd)
2470 {
2471         struct ice_aqc_restart_an *cmd;
2472         struct ice_aq_desc desc;
2473 
2474         cmd = &desc.params.restart_an;
2475 
2476         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2477 
2478         cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2479         cmd->lport_num = pi->lport;
2480         if (ena_link)
2481                 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2482         else
2483                 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2484 
2485         return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2486 }
2487 
2488 /**
2489  * ice_aq_set_event_mask
2490  * @hw: pointer to the HW struct
2491  * @port_num: port number of the physical function
2492  * @mask: event mask to be set
2493  * @cd: pointer to command details structure or NULL
2494  *
2495  * Set event mask (0x0613)
2496  */
2497 enum ice_status
2498 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2499                       struct ice_sq_cd *cd)
2500 {
2501         struct ice_aqc_set_event_mask *cmd;
2502         struct ice_aq_desc desc;
2503 
2504         cmd = &desc.params.set_event_mask;
2505 
2506         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2507 
2508         cmd->lport_num = port_num;
2509 
2510         cmd->event_mask = cpu_to_le16(mask);
2511         return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2512 }
2513 
2514 /**
2515  * ice_aq_set_mac_loopback
2516  * @hw: pointer to the HW struct
2517  * @ena_lpbk: Enable or Disable loopback
2518  * @cd: pointer to command details structure or NULL
2519  *
2520  * Enable/disable loopback on a given port
2521  */
2522 enum ice_status
2523 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2524 {
2525         struct ice_aqc_set_mac_lb *cmd;
2526         struct ice_aq_desc desc;
2527 
2528         cmd = &desc.params.set_mac_lb;
2529 
2530         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2531         if (ena_lpbk)
2532                 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2533 
2534         return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2535 }
2536 
2537 /**
2538  * ice_aq_set_port_id_led
2539  * @pi: pointer to the port information
2540  * @is_orig_mode: is this LED set to original mode (by the net-list)
2541  * @cd: pointer to command details structure or NULL
2542  *
2543  * Set LED value for the given port (0x06e9)
2544  */
2545 enum ice_status
2546 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2547                        struct ice_sq_cd *cd)
2548 {
2549         struct ice_aqc_set_port_id_led *cmd;
2550         struct ice_hw *hw = pi->hw;
2551         struct ice_aq_desc desc;
2552 
2553         cmd = &desc.params.set_port_id_led;
2554 
2555         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2556 
2557         if (is_orig_mode)
2558                 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2559         else
2560                 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2561 
2562         return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2563 }
2564 
2565 /**
2566  * __ice_aq_get_set_rss_lut
2567  * @hw: pointer to the hardware structure
2568  * @vsi_id: VSI FW index
2569  * @lut_type: LUT table type
2570  * @lut: pointer to the LUT buffer provided by the caller
2571  * @lut_size: size of the LUT buffer
2572  * @glob_lut_idx: global LUT index
2573  * @set: set true to set the table, false to get the table
2574  *
2575  * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2576  */
2577 static enum ice_status
2578 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2579                          u16 lut_size, u8 glob_lut_idx, bool set)
2580 {
2581         struct ice_aqc_get_set_rss_lut *cmd_resp;
2582         struct ice_aq_desc desc;
2583         enum ice_status status;
2584         u16 flags = 0;
2585 
2586         cmd_resp = &desc.params.get_set_rss_lut;
2587 
2588         if (set) {
2589                 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2590                 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2591         } else {
2592                 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2593         }
2594 
2595         cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2596                                          ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2597                                         ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2598                                        ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2599 
2600         switch (lut_type) {
2601         case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2602         case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2603         case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2604                 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2605                           ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2606                 break;
2607         default:
2608                 status = ICE_ERR_PARAM;
2609                 goto ice_aq_get_set_rss_lut_exit;
2610         }
2611 
2612         if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2613                 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2614                           ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2615 
2616                 if (!set)
2617                         goto ice_aq_get_set_rss_lut_send;
2618         } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2619                 if (!set)
2620                         goto ice_aq_get_set_rss_lut_send;
2621         } else {
2622                 goto ice_aq_get_set_rss_lut_send;
2623         }
2624 
2625         /* LUT size is only valid for Global and PF table types */
2626         switch (lut_size) {
2627         case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2628                 break;
2629         case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2630                 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2631                           ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2632                          ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2633                 break;
2634         case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2635                 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2636                         flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2637                                   ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2638                                  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2639                         break;
2640                 }
2641                 /* fall-through */
2642         default:
2643                 status = ICE_ERR_PARAM;
2644                 goto ice_aq_get_set_rss_lut_exit;
2645         }
2646 
2647 ice_aq_get_set_rss_lut_send:
2648         cmd_resp->flags = cpu_to_le16(flags);
2649         status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2650 
2651 ice_aq_get_set_rss_lut_exit:
2652         return status;
2653 }
2654 
2655 /**
2656  * ice_aq_get_rss_lut
2657  * @hw: pointer to the hardware structure
2658  * @vsi_handle: software VSI handle
2659  * @lut_type: LUT table type
2660  * @lut: pointer to the LUT buffer provided by the caller
2661  * @lut_size: size of the LUT buffer
2662  *
2663  * get the RSS lookup table, PF or VSI type
2664  */
2665 enum ice_status
2666 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2667                    u8 *lut, u16 lut_size)
2668 {
2669         if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2670                 return ICE_ERR_PARAM;
2671 
2672         return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2673                                         lut_type, lut, lut_size, 0, false);
2674 }
2675 
2676 /**
2677  * ice_aq_set_rss_lut
2678  * @hw: pointer to the hardware structure
2679  * @vsi_handle: software VSI handle
2680  * @lut_type: LUT table type
2681  * @lut: pointer to the LUT buffer provided by the caller
2682  * @lut_size: size of the LUT buffer
2683  *
2684  * set the RSS lookup table, PF or VSI type
2685  */
2686 enum ice_status
2687 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2688                    u8 *lut, u16 lut_size)
2689 {
2690         if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2691                 return ICE_ERR_PARAM;
2692 
2693         return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2694                                         lut_type, lut, lut_size, 0, true);
2695 }
2696 
2697 /**
2698  * __ice_aq_get_set_rss_key
2699  * @hw: pointer to the HW struct
2700  * @vsi_id: VSI FW index
2701  * @key: pointer to key info struct
2702  * @set: set true to set the key, false to get the key
2703  *
2704  * get (0x0B04) or set (0x0B02) the RSS key per VSI
2705  */
2706 static enum
2707 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2708                                     struct ice_aqc_get_set_rss_keys *key,
2709                                     bool set)
2710 {
2711         struct ice_aqc_get_set_rss_key *cmd_resp;
2712         u16 key_size = sizeof(*key);
2713         struct ice_aq_desc desc;
2714 
2715         cmd_resp = &desc.params.get_set_rss_key;
2716 
2717         if (set) {
2718                 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2719                 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2720         } else {
2721                 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2722         }
2723 
2724         cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2725                                          ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2726                                         ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2727                                        ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2728 
2729         return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2730 }
2731 
2732 /**
2733  * ice_aq_get_rss_key
2734  * @hw: pointer to the HW struct
2735  * @vsi_handle: software VSI handle
2736  * @key: pointer to key info struct
2737  *
2738  * get the RSS key per VSI
2739  */
2740 enum ice_status
2741 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
2742                    struct ice_aqc_get_set_rss_keys *key)
2743 {
2744         if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2745                 return ICE_ERR_PARAM;
2746 
2747         return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2748                                         key, false);
2749 }
2750 
2751 /**
2752  * ice_aq_set_rss_key
2753  * @hw: pointer to the HW struct
2754  * @vsi_handle: software VSI handle
2755  * @keys: pointer to key info struct
2756  *
2757  * set the RSS key per VSI
2758  */
2759 enum ice_status
2760 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
2761                    struct ice_aqc_get_set_rss_keys *keys)
2762 {
2763         if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2764                 return ICE_ERR_PARAM;
2765 
2766         return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2767                                         keys, true);
2768 }
2769 
2770 /**
2771  * ice_aq_add_lan_txq
2772  * @hw: pointer to the hardware structure
2773  * @num_qgrps: Number of added queue groups
2774  * @qg_list: list of queue groups to be added
2775  * @buf_size: size of buffer for indirect command
2776  * @cd: pointer to command details structure or NULL
2777  *
2778  * Add Tx LAN queue (0x0C30)
2779  *
2780  * NOTE:
2781  * Prior to calling add Tx LAN queue:
2782  * Initialize the following as part of the Tx queue context:
2783  * Completion queue ID if the queue uses Completion queue, Quanta profile,
2784  * Cache profile and Packet shaper profile.
2785  *
2786  * After add Tx LAN queue AQ command is completed:
2787  * Interrupts should be associated with specific queues,
2788  * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2789  * flow.
2790  */
2791 static enum ice_status
2792 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2793                    struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2794                    struct ice_sq_cd *cd)
2795 {
2796         u16 i, sum_header_size, sum_q_size = 0;
2797         struct ice_aqc_add_tx_qgrp *list;
2798         struct ice_aqc_add_txqs *cmd;
2799         struct ice_aq_desc desc;
2800 
2801         cmd = &desc.params.add_txqs;
2802 
2803         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
2804 
2805         if (!qg_list)
2806                 return ICE_ERR_PARAM;
2807 
2808         if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2809                 return ICE_ERR_PARAM;
2810 
2811         sum_header_size = num_qgrps *
2812                 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
2813 
2814         list = qg_list;
2815         for (i = 0; i < num_qgrps; i++) {
2816                 struct ice_aqc_add_txqs_perq *q = list->txqs;
2817 
2818                 sum_q_size += list->num_txqs * sizeof(*q);
2819                 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
2820         }
2821 
2822         if (buf_size != (sum_header_size + sum_q_size))
2823                 return ICE_ERR_PARAM;
2824 
2825         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2826 
2827         cmd->num_qgrps = num_qgrps;
2828 
2829         return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2830 }
2831 
2832 /**
2833  * ice_aq_dis_lan_txq
2834  * @hw: pointer to the hardware structure
2835  * @num_qgrps: number of groups in the list
2836  * @qg_list: the list of groups to disable
2837  * @buf_size: the total size of the qg_list buffer in bytes
2838  * @rst_src: if called due to reset, specifies the reset source
2839  * @vmvf_num: the relative VM or VF number that is undergoing the reset
2840  * @cd: pointer to command details structure or NULL
2841  *
2842  * Disable LAN Tx queue (0x0C31)
2843  */
2844 static enum ice_status
2845 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2846                    struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
2847                    enum ice_disq_rst_src rst_src, u16 vmvf_num,
2848                    struct ice_sq_cd *cd)
2849 {
2850         struct ice_aqc_dis_txqs *cmd;
2851         struct ice_aq_desc desc;
2852         enum ice_status status;
2853         u16 i, sz = 0;
2854 
2855         cmd = &desc.params.dis_txqs;
2856         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
2857 
2858         /* qg_list can be NULL only in VM/VF reset flow */
2859         if (!qg_list && !rst_src)
2860                 return ICE_ERR_PARAM;
2861 
2862         if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2863                 return ICE_ERR_PARAM;
2864 
2865         cmd->num_entries = num_qgrps;
2866 
2867         cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
2868                                             ICE_AQC_Q_DIS_TIMEOUT_M);
2869 
2870         switch (rst_src) {
2871         case ICE_VM_RESET:
2872                 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
2873                 cmd->vmvf_and_timeout |=
2874                         cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
2875                 break;
2876         case ICE_VF_RESET:
2877                 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
2878                 /* In this case, FW expects vmvf_num to be absolute VF ID */
2879                 cmd->vmvf_and_timeout |=
2880                         cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
2881                                     ICE_AQC_Q_DIS_VMVF_NUM_M);
2882                 break;
2883         case ICE_NO_RESET:
2884         default:
2885                 break;
2886         }
2887 
2888         /* flush pipe on time out */
2889         cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
2890         /* If no queue group info, we are in a reset flow. Issue the AQ */
2891         if (!qg_list)
2892                 goto do_aq;
2893 
2894         /* set RD bit to indicate that command buffer is provided by the driver
2895          * and it needs to be read by the firmware
2896          */
2897         desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2898 
2899         for (i = 0; i < num_qgrps; ++i) {
2900                 /* Calculate the size taken up by the queue IDs in this group */
2901                 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
2902 
2903                 /* Add the size of the group header */
2904                 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
2905 
2906                 /* If the num of queues is even, add 2 bytes of padding */
2907                 if ((qg_list[i].num_qs % 2) == 0)
2908                         sz += 2;
2909         }
2910 
2911         if (buf_size != sz)
2912                 return ICE_ERR_PARAM;
2913 
2914 do_aq:
2915         status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2916         if (status) {
2917                 if (!qg_list)
2918                         ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
2919                                   vmvf_num, hw->adminq.sq_last_status);
2920                 else
2921                         ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
2922                                   le16_to_cpu(qg_list[0].q_id[0]),
2923                                   hw->adminq.sq_last_status);
2924         }
2925         return status;
2926 }
2927 
2928 /* End of FW Admin Queue command wrappers */
2929 
2930 /**
2931  * ice_write_byte - write a byte to a packed context structure
2932  * @src_ctx:  the context structure to read from
2933  * @dest_ctx: the context to be written to
2934  * @ce_info:  a description of the struct to be filled
2935  */
2936 static void
2937 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2938 {
2939         u8 src_byte, dest_byte, mask;
2940         u8 *from, *dest;
2941         u16 shift_width;
2942 
2943         /* copy from the next struct field */
2944         from = src_ctx + ce_info->offset;
2945 
2946         /* prepare the bits and mask */
2947         shift_width = ce_info->lsb % 8;
2948         mask = (u8)(BIT(ce_info->width) - 1);
2949 
2950         src_byte = *from;
2951         src_byte &= mask;
2952 
2953         /* shift to correct alignment */
2954         mask <<= shift_width;
2955         src_byte <<= shift_width;
2956 
2957         /* get the current bits from the target bit string */
2958         dest = dest_ctx + (ce_info->lsb / 8);
2959 
2960         memcpy(&dest_byte, dest, sizeof(dest_byte));
2961 
2962         dest_byte &= ~mask;     /* get the bits not changing */
2963         dest_byte |= src_byte;  /* add in the new bits */
2964 
2965         /* put it all back */
2966         memcpy(dest, &dest_byte, sizeof(dest_byte));
2967 }
2968 
2969 /**
2970  * ice_write_word - write a word to a packed context structure
2971  * @src_ctx:  the context structure to read from
2972  * @dest_ctx: the context to be written to
2973  * @ce_info:  a description of the struct to be filled
2974  */
2975 static void
2976 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2977 {
2978         u16 src_word, mask;
2979         __le16 dest_word;
2980         u8 *from, *dest;
2981         u16 shift_width;
2982 
2983         /* copy from the next struct field */
2984         from = src_ctx + ce_info->offset;
2985 
2986         /* prepare the bits and mask */
2987         shift_width = ce_info->lsb % 8;
2988         mask = BIT(ce_info->width) - 1;
2989 
2990         /* don't swizzle the bits until after the mask because the mask bits
2991          * will be in a different bit position on big endian machines
2992          */
2993         src_word = *(u16 *)from;
2994         src_word &= mask;
2995 
2996         /* shift to correct alignment */
2997         mask <<= shift_width;
2998         src_word <<= shift_width;
2999 
3000         /* get the current bits from the target bit string */
3001         dest = dest_ctx + (ce_info->lsb / 8);
3002 
3003         memcpy(&dest_word, dest, sizeof(dest_word));
3004 
3005         dest_word &= ~(cpu_to_le16(mask));      /* get the bits not changing */
3006         dest_word |= cpu_to_le16(src_word);     /* add in the new bits */
3007 
3008         /* put it all back */
3009         memcpy(dest, &dest_word, sizeof(dest_word));
3010 }
3011 
3012 /**
3013  * ice_write_dword - write a dword to a packed context structure
3014  * @src_ctx:  the context structure to read from
3015  * @dest_ctx: the context to be written to
3016  * @ce_info:  a description of the struct to be filled
3017  */
3018 static void
3019 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3020 {
3021         u32 src_dword, mask;
3022         __le32 dest_dword;
3023         u8 *from, *dest;
3024         u16 shift_width;
3025 
3026         /* copy from the next struct field */
3027         from = src_ctx + ce_info->offset;
3028 
3029         /* prepare the bits and mask */
3030         shift_width = ce_info->lsb % 8;
3031 
3032         /* if the field width is exactly 32 on an x86 machine, then the shift
3033          * operation will not work because the SHL instructions count is masked
3034          * to 5 bits so the shift will do nothing
3035          */
3036         if (ce_info->width < 32)
3037                 mask = BIT(ce_info->width) - 1;
3038         else
3039                 mask = (u32)~0;
3040 
3041         /* don't swizzle the bits until after the mask because the mask bits
3042          * will be in a different bit position on big endian machines
3043          */
3044         src_dword = *(u32 *)from;
3045         src_dword &= mask;
3046 
3047         /* shift to correct alignment */
3048         mask <<= shift_width;
3049         src_dword <<= shift_width;
3050 
3051         /* get the current bits from the target bit string */
3052         dest = dest_ctx + (ce_info->lsb / 8);
3053 
3054         memcpy(&dest_dword, dest, sizeof(dest_dword));
3055 
3056         dest_dword &= ~(cpu_to_le32(mask));     /* get the bits not changing */
3057         dest_dword |= cpu_to_le32(src_dword);   /* add in the new bits */
3058 
3059         /* put it all back */
3060         memcpy(dest, &dest_dword, sizeof(dest_dword));
3061 }
3062 
3063 /**
3064  * ice_write_qword - write a qword to a packed context structure
3065  * @src_ctx:  the context structure to read from
3066  * @dest_ctx: the context to be written to
3067  * @ce_info:  a description of the struct to be filled
3068  */
3069 static void
3070 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3071 {
3072         u64 src_qword, mask;
3073         __le64 dest_qword;
3074         u8 *from, *dest;
3075         u16 shift_width;
3076 
3077         /* copy from the next struct field */
3078         from = src_ctx + ce_info->offset;
3079 
3080         /* prepare the bits and mask */
3081         shift_width = ce_info->lsb % 8;
3082 
3083         /* if the field width is exactly 64 on an x86 machine, then the shift
3084          * operation will not work because the SHL instructions count is masked
3085          * to 6 bits so the shift will do nothing
3086          */
3087         if (ce_info->width < 64)
3088                 mask = BIT_ULL(ce_info->width) - 1;
3089         else
3090                 mask = (u64)~0;
3091 
3092         /* don't swizzle the bits until after the mask because the mask bits
3093          * will be in a different bit position on big endian machines
3094          */
3095         src_qword = *(u64 *)from;
3096         src_qword &= mask;
3097 
3098         /* shift to correct alignment */
3099         mask <<= shift_width;
3100         src_qword <<= shift_width;
3101 
3102         /* get the current bits from the target bit string */
3103         dest = dest_ctx + (ce_info->lsb / 8);
3104 
3105         memcpy(&dest_qword, dest, sizeof(dest_qword));
3106 
3107         dest_qword &= ~(cpu_to_le64(mask));     /* get the bits not changing */
3108         dest_qword |= cpu_to_le64(src_qword);   /* add in the new bits */
3109 
3110         /* put it all back */
3111         memcpy(dest, &dest_qword, sizeof(dest_qword));
3112 }
3113 
3114 /**
3115  * ice_set_ctx - set context bits in packed structure
3116  * @src_ctx:  pointer to a generic non-packed context structure
3117  * @dest_ctx: pointer to memory for the packed structure
3118  * @ce_info:  a description of the structure to be transformed
3119  */
3120 enum ice_status
3121 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3122 {
3123         int f;
3124 
3125         for (f = 0; ce_info[f].width; f++) {
3126                 /* We have to deal with each element of the FW response
3127                  * using the correct size so that we are correct regardless
3128                  * of the endianness of the machine.
3129                  */
3130                 switch (ce_info[f].size_of) {
3131                 case sizeof(u8):
3132                         ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3133                         break;
3134                 case sizeof(u16):
3135                         ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3136                         break;
3137                 case sizeof(u32):
3138                         ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3139                         break;
3140                 case sizeof(u64):
3141                         ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3142                         break;
3143                 default:
3144                         return ICE_ERR_INVAL_SIZE;
3145                 }
3146         }
3147 
3148         return 0;
3149 }
3150 
3151 /**
3152  * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3153  * @hw: pointer to the HW struct
3154  * @vsi_handle: software VSI handle
3155  * @tc: TC number
3156  * @q_handle: software queue handle
3157  */
3158 static struct ice_q_ctx *
3159 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3160 {
3161         struct ice_vsi_ctx *vsi;
3162         struct ice_q_ctx *q_ctx;
3163 
3164         vsi = ice_get_vsi_ctx(hw, vsi_handle);
3165         if (!vsi)
3166                 return NULL;
3167         if (q_handle >= vsi->num_lan_q_entries[tc])
3168                 return NULL;
3169         if (!vsi->lan_q_ctx[tc])
3170                 return NULL;
3171         q_ctx = vsi->lan_q_ctx[tc];
3172         return &q_ctx[q_handle];
3173 }
3174 
3175 /**
3176  * ice_ena_vsi_txq
3177  * @pi: port information structure
3178  * @vsi_handle: software VSI handle
3179  * @tc: TC number
3180  * @q_handle: software queue handle
3181  * @num_qgrps: Number of added queue groups
3182  * @buf: list of queue groups to be added
3183  * @buf_size: size of buffer for indirect command
3184  * @cd: pointer to command details structure or NULL
3185  *
3186  * This function adds one LAN queue
3187  */
3188 enum ice_status
3189 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3190                 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3191                 struct ice_sq_cd *cd)
3192 {
3193         struct ice_aqc_txsched_elem_data node = { 0 };
3194         struct ice_sched_node *parent;
3195         struct ice_q_ctx *q_ctx;
3196         enum ice_status status;
3197         struct ice_hw *hw;
3198 
3199         if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3200                 return ICE_ERR_CFG;
3201 
3202         if (num_qgrps > 1 || buf->num_txqs > 1)
3203                 return ICE_ERR_MAX_LIMIT;
3204 
3205         hw = pi->hw;
3206 
3207         if (!ice_is_vsi_valid(hw, vsi_handle))
3208                 return ICE_ERR_PARAM;
3209 
3210         mutex_lock(&pi->sched_lock);
3211 
3212         q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3213         if (!q_ctx) {
3214                 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3215                           q_handle);
3216                 status = ICE_ERR_PARAM;
3217                 goto ena_txq_exit;
3218         }
3219 
3220         /* find a parent node */
3221         parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3222                                             ICE_SCHED_NODE_OWNER_LAN);
3223         if (!parent) {
3224                 status = ICE_ERR_PARAM;
3225                 goto ena_txq_exit;
3226         }
3227 
3228         buf->parent_teid = parent->info.node_teid;
3229         node.parent_teid = parent->info.node_teid;
3230         /* Mark that the values in the "generic" section as valid. The default
3231          * value in the "generic" section is zero. This means that :
3232          * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3233          * - 0 priority among siblings, indicated by Bit 1-3.
3234          * - WFQ, indicated by Bit 4.
3235          * - 0 Adjustment value is used in PSM credit update flow, indicated by
3236          * Bit 5-6.
3237          * - Bit 7 is reserved.
3238          * Without setting the generic section as valid in valid_sections, the
3239          * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3240          */
3241         buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3242 
3243         /* add the LAN queue */
3244         status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3245         if (status) {
3246                 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3247                           le16_to_cpu(buf->txqs[0].txq_id),
3248                           hw->adminq.sq_last_status);
3249                 goto ena_txq_exit;
3250         }
3251 
3252         node.node_teid = buf->txqs[0].q_teid;
3253         node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3254         q_ctx->q_handle = q_handle;
3255 
3256         /* add a leaf node into schduler tree queue layer */
3257         status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3258 
3259 ena_txq_exit:
3260         mutex_unlock(&pi->sched_lock);
3261         return status;
3262 }
3263 
3264 /**
3265  * ice_dis_vsi_txq
3266  * @pi: port information structure
3267  * @vsi_handle: software VSI handle
3268  * @tc: TC number
3269  * @num_queues: number of queues
3270  * @q_handles: pointer to software queue handle array
3271  * @q_ids: pointer to the q_id array
3272  * @q_teids: pointer to queue node teids
3273  * @rst_src: if called due to reset, specifies the reset source
3274  * @vmvf_num: the relative VM or VF number that is undergoing the reset
3275  * @cd: pointer to command details structure or NULL
3276  *
3277  * This function removes queues and their corresponding nodes in SW DB
3278  */
3279 enum ice_status
3280 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3281                 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3282                 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3283                 struct ice_sq_cd *cd)
3284 {
3285         enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3286         struct ice_aqc_dis_txq_item qg_list;
3287         struct ice_q_ctx *q_ctx;
3288         u16 i;
3289 
3290         if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3291                 return ICE_ERR_CFG;
3292 
3293         if (!num_queues) {
3294                 /* if queue is disabled already yet the disable queue command
3295                  * has to be sent to complete the VF reset, then call
3296                  * ice_aq_dis_lan_txq without any queue information
3297                  */
3298                 if (rst_src)
3299                         return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3300                                                   vmvf_num, NULL);
3301                 return ICE_ERR_CFG;
3302         }
3303 
3304         mutex_lock(&pi->sched_lock);
3305 
3306         for (i = 0; i < num_queues; i++) {
3307                 struct ice_sched_node *node;
3308 
3309                 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3310                 if (!node)
3311                         continue;
3312                 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3313                 if (!q_ctx) {
3314                         ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3315                                   q_handles[i]);
3316                         continue;
3317                 }
3318                 if (q_ctx->q_handle != q_handles[i]) {
3319                         ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3320                                   q_ctx->q_handle, q_handles[i]);
3321                         continue;
3322                 }
3323                 qg_list.parent_teid = node->info.parent_teid;
3324                 qg_list.num_qs = 1;
3325                 qg_list.q_id[0] = cpu_to_le16(q_ids[i]);
3326                 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3327                                             sizeof(qg_list), rst_src, vmvf_num,
3328                                             cd);
3329 
3330                 if (status)
3331                         break;
3332                 ice_free_sched_node(pi, node);
3333                 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3334         }
3335         mutex_unlock(&pi->sched_lock);
3336         return status;
3337 }
3338 
3339 /**
3340  * ice_cfg_vsi_qs - configure the new/existing VSI queues
3341  * @pi: port information structure
3342  * @vsi_handle: software VSI handle
3343  * @tc_bitmap: TC bitmap
3344  * @maxqs: max queues array per TC
3345  * @owner: LAN or RDMA
3346  *
3347  * This function adds/updates the VSI queues per TC.
3348  */
3349 static enum ice_status
3350 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3351                u16 *maxqs, u8 owner)
3352 {
3353         enum ice_status status = 0;
3354         u8 i;
3355 
3356         if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3357                 return ICE_ERR_CFG;
3358 
3359         if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3360                 return ICE_ERR_PARAM;
3361 
3362         mutex_lock(&pi->sched_lock);
3363 
3364         ice_for_each_traffic_class(i) {
3365                 /* configuration is possible only if TC node is present */
3366                 if (!ice_sched_get_tc_node(pi, i))
3367                         continue;
3368 
3369                 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3370                                            ice_is_tc_ena(tc_bitmap, i));
3371                 if (status)
3372                         break;
3373         }
3374 
3375         mutex_unlock(&pi->sched_lock);
3376         return status;
3377 }
3378 
3379 /**
3380  * ice_cfg_vsi_lan - configure VSI LAN queues
3381  * @pi: port information structure
3382  * @vsi_handle: software VSI handle
3383  * @tc_bitmap: TC bitmap
3384  * @max_lanqs: max LAN queues array per TC
3385  *
3386  * This function adds/updates the VSI LAN queues per TC.
3387  */
3388 enum ice_status
3389 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3390                 u16 *max_lanqs)
3391 {
3392         return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3393                               ICE_SCHED_NODE_OWNER_LAN);
3394 }
3395 
3396 /**
3397  * ice_replay_pre_init - replay pre initialization
3398  * @hw: pointer to the HW struct
3399  *
3400  * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3401  */
3402 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3403 {
3404         struct ice_switch_info *sw = hw->switch_info;
3405         u8 i;
3406 
3407         /* Delete old entries from replay filter list head if there is any */
3408         ice_rm_all_sw_replay_rule_info(hw);
3409         /* In start of replay, move entries into replay_rules list, it
3410          * will allow adding rules entries back to filt_rules list,
3411          * which is operational list.
3412          */
3413         for (i = 0; i < ICE_SW_LKUP_LAST; i++)
3414                 list_replace_init(&sw->recp_list[i].filt_rules,
3415                                   &sw->recp_list[i].filt_replay_rules);
3416 
3417         return 0;
3418 }
3419 
3420 /**
3421  * ice_replay_vsi - replay VSI configuration
3422  * @hw: pointer to the HW struct
3423  * @vsi_handle: driver VSI handle
3424  *
3425  * Restore all VSI configuration after reset. It is required to call this
3426  * function with main VSI first.
3427  */
3428 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3429 {
3430         enum ice_status status;
3431 
3432         if (!ice_is_vsi_valid(hw, vsi_handle))
3433                 return ICE_ERR_PARAM;
3434 
3435         /* Replay pre-initialization if there is any */
3436         if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3437                 status = ice_replay_pre_init(hw);
3438                 if (status)
3439                         return status;
3440         }
3441 
3442         /* Replay per VSI all filters */
3443         status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3444         return status;
3445 }
3446 
3447 /**
3448  * ice_replay_post - post replay configuration cleanup
3449  * @hw: pointer to the HW struct
3450  *
3451  * Post replay cleanup.
3452  */
3453 void ice_replay_post(struct ice_hw *hw)
3454 {
3455         /* Delete old entries from replay filter list head */
3456         ice_rm_all_sw_replay_rule_info(hw);
3457 }
3458 
3459 /**
3460  * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3461  * @hw: ptr to the hardware info
3462  * @reg: offset of 64 bit HW register to read from
3463  * @prev_stat_loaded: bool to specify if previous stats are loaded
3464  * @prev_stat: ptr to previous loaded stat value
3465  * @cur_stat: ptr to current stat value
3466  */
3467 void
3468 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3469                   u64 *prev_stat, u64 *cur_stat)
3470 {
3471         u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
3472 
3473         /* device stats are not reset at PFR, they likely will not be zeroed
3474          * when the driver starts. Thus, save the value from the first read
3475          * without adding to the statistic value so that we report stats which
3476          * count up from zero.
3477          */
3478         if (!prev_stat_loaded) {
3479                 *prev_stat = new_data;
3480                 return;
3481         }
3482 
3483         /* Calculate the difference between the new and old values, and then
3484          * add it to the software stat value.
3485          */
3486         if (new_data >= *prev_stat)
3487                 *cur_stat += new_data - *prev_stat;
3488         else
3489                 /* to manage the potential roll-over */
3490                 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
3491 
3492         /* Update the previously stored value to prepare for next read */
3493         *prev_stat = new_data;
3494 }
3495 
3496 /**
3497  * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3498  * @hw: ptr to the hardware info
3499  * @reg: offset of HW register to read from
3500  * @prev_stat_loaded: bool to specify if previous stats are loaded
3501  * @prev_stat: ptr to previous loaded stat value
3502  * @cur_stat: ptr to current stat value
3503  */
3504 void
3505 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3506                   u64 *prev_stat, u64 *cur_stat)
3507 {
3508         u32 new_data;
3509 
3510         new_data = rd32(hw, reg);
3511 
3512         /* device stats are not reset at PFR, they likely will not be zeroed
3513          * when the driver starts. Thus, save the value from the first read
3514          * without adding to the statistic value so that we report stats which
3515          * count up from zero.
3516          */
3517         if (!prev_stat_loaded) {
3518                 *prev_stat = new_data;
3519                 return;
3520         }
3521 
3522         /* Calculate the difference between the new and old values, and then
3523          * add it to the software stat value.
3524          */
3525         if (new_data >= *prev_stat)
3526                 *cur_stat += new_data - *prev_stat;
3527         else
3528                 /* to manage the potential roll-over */
3529                 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
3530 
3531         /* Update the previously stored value to prepare for next read */
3532         *prev_stat = new_data;
3533 }
3534 
3535 /**
3536  * ice_sched_query_elem - query element information from HW
3537  * @hw: pointer to the HW struct
3538  * @node_teid: node TEID to be queried
3539  * @buf: buffer to element information
3540  *
3541  * This function queries HW element information
3542  */
3543 enum ice_status
3544 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3545                      struct ice_aqc_get_elem *buf)
3546 {
3547         u16 buf_size, num_elem_ret = 0;
3548         enum ice_status status;
3549 
3550         buf_size = sizeof(*buf);
3551         memset(buf, 0, buf_size);
3552         buf->generic[0].node_teid = cpu_to_le32(node_teid);
3553         status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3554                                           NULL);
3555         if (status || num_elem_ret != 1)
3556                 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
3557         return status;
3558 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/intel/ice/ice_common.c

DEFINITIONS
