1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_CONTROLQ_H_
5 #define _ICE_CONTROLQ_H_
6
7 #include "ice_adminq_cmd.h"
8
9 /* Maximum buffer lengths for all control queue types */
10 #define ICE_AQ_MAX_BUF_LEN 4096
11 #define ICE_MBXQ_MAX_BUF_LEN 4096
12
13 #define ICE_CTL_Q_DESC(R, i) \
14 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
15
16 #define ICE_CTL_Q_DESC_UNUSED(R) \
17 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
18 (R)->next_to_clean - (R)->next_to_use - 1)
19
20 /* Defines that help manage the driver vs FW API checks.
21 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
22 */
23 #define EXP_FW_API_VER_BRANCH 0x00
24 #define EXP_FW_API_VER_MAJOR 0x01
25 #define EXP_FW_API_VER_MINOR 0x03
26
27 /* Different control queue types: These are mainly for SW consumption. */
28 enum ice_ctl_q {
29 ICE_CTL_Q_UNKNOWN = 0,
30 ICE_CTL_Q_ADMIN,
31 ICE_CTL_Q_MAILBOX,
32 };
33
34 /* Control Queue timeout settings - max delay 250ms */
35 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */
36 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
37
38 struct ice_ctl_q_ring {
39 void *dma_head; /* Virtual address to DMA head */
40 struct ice_dma_mem desc_buf; /* descriptor ring memory */
41 void *cmd_buf; /* command buffer memory */
42
43 union {
44 struct ice_dma_mem *sq_bi;
45 struct ice_dma_mem *rq_bi;
46 } r;
47
48 u16 count; /* Number of descriptors */
49
50 /* used for interrupt processing */
51 u16 next_to_use;
52 u16 next_to_clean;
53
54 /* used for queue tracking */
55 u32 head;
56 u32 tail;
57 u32 len;
58 u32 bah;
59 u32 bal;
60 u32 len_mask;
61 u32 len_ena_mask;
62 u32 head_mask;
63 };
64
65 /* sq transaction details */
66 struct ice_sq_cd {
67 struct ice_aq_desc *wb_desc;
68 };
69
70 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
71
72 /* rq event information */
73 struct ice_rq_event_info {
74 struct ice_aq_desc desc;
75 u16 msg_len;
76 u16 buf_len;
77 u8 *msg_buf;
78 };
79
80 /* Control Queue information */
81 struct ice_ctl_q_info {
82 enum ice_ctl_q qtype;
83 enum ice_aq_err rq_last_status; /* last status on receive queue */
84 struct ice_ctl_q_ring rq; /* receive queue */
85 struct ice_ctl_q_ring sq; /* send queue */
86 u32 sq_cmd_timeout; /* send queue cmd write back timeout */
87 u16 num_rq_entries; /* receive queue depth */
88 u16 num_sq_entries; /* send queue depth */
89 u16 rq_buf_size; /* receive queue buffer size */
90 u16 sq_buf_size; /* send queue buffer size */
91 enum ice_aq_err sq_last_status; /* last status on send queue */
92 struct mutex sq_lock; /* Send queue lock */
93 struct mutex rq_lock; /* Receive queue lock */
94 };
95
96 #endif /* _ICE_CONTROLQ_H_ */